./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:03:12,156 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:03:12,157 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:03:12,178 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:03:12,179 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:03:12,179 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:03:12,182 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:03:12,185 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:03:12,188 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:03:12,190 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:03:12,190 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:03:12,191 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:03:12,191 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:03:12,192 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:03:12,192 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:03:12,193 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:03:12,194 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:03:12,194 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:03:12,195 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:03:12,197 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:03:12,200 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:03:12,201 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:03:12,202 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:03:12,203 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:03:12,204 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:03:12,206 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:03:12,210 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:03:12,211 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:03:12,211 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:03:12,212 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:03:12,212 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:03:12,213 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:03:12,214 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:03:12,214 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:03:12,215 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:03:12,216 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:03:12,216 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:03:12,216 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:03:12,216 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:03:12,217 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:03:12,217 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:03:12,218 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:03:12,220 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:03:12,247 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:03:12,250 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:03:12,250 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:03:12,250 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:03:12,251 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:03:12,251 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:03:12,251 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:03:12,252 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:03:12,252 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:03:12,252 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:03:12,253 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:03:12,253 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:03:12,253 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:03:12,253 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:03:12,253 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:03:12,253 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:03:12,254 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:03:12,254 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:03:12,255 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:03:12,255 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:03:12,255 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:03:12,255 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:03:12,255 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:03:12,255 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:03:12,256 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:03:12,256 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:03:12,256 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:03:12,256 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:03:12,257 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:03:12,257 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:03:12,257 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:03:12,257 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:03:12,258 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 [2022-07-14 16:03:12,452 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:03:12,466 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:03:12,468 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:03:12,468 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:03:12,469 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:03:12,470 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2022-07-14 16:03:12,507 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3e9b8fbd/83f17b2f2bf44086bd98bf42945f9076/FLAGab6cbbd9e [2022-07-14 16:03:12,843 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:03:12,844 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2022-07-14 16:03:12,864 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3e9b8fbd/83f17b2f2bf44086bd98bf42945f9076/FLAGab6cbbd9e [2022-07-14 16:03:13,251 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3e9b8fbd/83f17b2f2bf44086bd98bf42945f9076 [2022-07-14 16:03:13,252 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:03:13,253 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:03:13,254 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:13,254 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:03:13,257 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:03:13,257 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,258 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d6a19a3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13, skipping insertion in model container [2022-07-14 16:03:13,258 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,263 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:03:13,287 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:03:13,385 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2022-07-14 16:03:13,519 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:13,532 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:03:13,541 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2022-07-14 16:03:13,604 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:13,619 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:03:13,620 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13 WrapperNode [2022-07-14 16:03:13,620 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:13,621 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:13,621 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:03:13,621 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:03:13,626 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,642 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,726 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4146 [2022-07-14 16:03:13,727 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:13,728 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:03:13,729 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:03:13,729 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:03:13,734 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,735 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,745 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,746 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,776 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,806 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,814 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,825 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:03:13,826 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:03:13,826 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:03:13,826 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:03:13,832 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (1/1) ... [2022-07-14 16:03:13,838 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:03:13,847 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:03:13,859 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:03:13,867 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:03:13,888 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:03:13,889 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:03:13,889 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:03:13,889 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:03:14,000 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:03:14,001 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:03:15,378 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:03:15,391 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:03:15,391 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2022-07-14 16:03:15,394 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:15 BoogieIcfgContainer [2022-07-14 16:03:15,394 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:03:15,395 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:03:15,395 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:03:15,397 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:03:15,398 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:15,398 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:03:13" (1/3) ... [2022-07-14 16:03:15,399 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75f76481 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:15, skipping insertion in model container [2022-07-14 16:03:15,399 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:15,399 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:13" (2/3) ... [2022-07-14 16:03:15,399 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75f76481 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:15, skipping insertion in model container [2022-07-14 16:03:15,399 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:15,399 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:15" (3/3) ... [2022-07-14 16:03:15,400 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2022-07-14 16:03:15,454 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:03:15,455 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:03:15,455 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:03:15,455 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:03:15,455 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:03:15,455 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:03:15,455 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:03:15,455 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:03:15,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:15,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2022-07-14 16:03:15,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:15,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:15,541 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:15,542 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:15,542 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:03:15,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:15,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2022-07-14 16:03:15,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:15,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:15,570 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:15,570 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:15,614 INFO L752 eck$LassoCheckResult]: Stem: 436#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1724#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 124#L1778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112#L846true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1177#L853true assume !(1 == ~m_i~0);~m_st~0 := 2; 978#L853-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 270#L858-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2#L863-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 757#L868-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 884#L873-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1653#L878-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1612#L883-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1684#L888-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 383#L893-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 785#L898-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1786#L903-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 714#L908-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1403#L913-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 845#L1206true assume !(0 == ~M_E~0); 372#L1206-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1171#L1211-1true assume !(0 == ~T2_E~0); 1333#L1216-1true assume !(0 == ~T3_E~0); 260#L1221-1true assume !(0 == ~T4_E~0); 1254#L1226-1true assume !(0 == ~T5_E~0); 91#L1231-1true assume !(0 == ~T6_E~0); 1408#L1236-1true assume !(0 == ~T7_E~0); 1237#L1241-1true assume !(0 == ~T8_E~0); 295#L1246-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 416#L1251-1true assume !(0 == ~T10_E~0); 929#L1256-1true assume !(0 == ~T11_E~0); 7#L1261-1true assume !(0 == ~T12_E~0); 1623#L1266-1true assume !(0 == ~E_M~0); 1565#L1271-1true assume !(0 == ~E_1~0); 873#L1276-1true assume !(0 == ~E_2~0); 1555#L1281-1true assume !(0 == ~E_3~0); 806#L1286-1true assume 0 == ~E_4~0;~E_4~0 := 1; 211#L1291-1true assume !(0 == ~E_5~0); 1650#L1296-1true assume !(0 == ~E_6~0); 649#L1301-1true assume !(0 == ~E_7~0); 1115#L1306-1true assume !(0 == ~E_8~0); 1074#L1311-1true assume !(0 == ~E_9~0); 194#L1316-1true assume !(0 == ~E_10~0); 1489#L1321-1true assume !(0 == ~E_11~0); 661#L1326-1true assume 0 == ~E_12~0;~E_12~0 := 1; 120#L1331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1781#L598true assume 1 == ~m_pc~0; 150#L599true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1206#L609true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1740#L610true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1431#L1497true assume !(0 != activate_threads_~tmp~1#1); 1685#L1497-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1294#L617true assume !(1 == ~t1_pc~0); 306#L617-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1730#L628true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233#L629true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1478#L1505true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 725#L1505-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1324#L636true assume 1 == ~t2_pc~0; 291#L637true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 559#L647true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203#L648true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1468#L1513true assume !(0 != activate_threads_~tmp___1~0#1); 756#L1513-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 491#L655true assume !(1 == ~t3_pc~0); 1438#L655-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1704#L666true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135#L667true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1788#L1521true assume !(0 != activate_threads_~tmp___2~0#1); 1567#L1521-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1593#L674true assume 1 == ~t4_pc~0; 50#L675true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1662#L685true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 877#L686true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 204#L1529true assume !(0 != activate_threads_~tmp___3~0#1); 489#L1529-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1345#L693true assume !(1 == ~t5_pc~0); 615#L693-2true is_transmit5_triggered_~__retres1~5#1 := 0; 373#L704true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1114#L705true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1079#L1537true assume !(0 != activate_threads_~tmp___4~0#1); 424#L1537-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 386#L712true assume 1 == ~t6_pc~0; 906#L713true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 684#L723true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 951#L724true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1672#L1545true assume !(0 != activate_threads_~tmp___5~0#1); 773#L1545-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 768#L731true assume 1 == ~t7_pc~0; 122#L732true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 225#L742true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 867#L743true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1088#L1553true assume !(0 != activate_threads_~tmp___6~0#1); 994#L1553-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 181#L750true assume !(1 == ~t8_pc~0); 859#L750-2true is_transmit8_triggered_~__retres1~8#1 := 0; 276#L761true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1762#L762true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1101#L1561true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 347#L1561-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 723#L769true assume 1 == ~t9_pc~0; 1731#L770true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 102#L780true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 538#L781true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 925#L1569true assume !(0 != activate_threads_~tmp___8~0#1); 1364#L1569-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1018#L788true assume !(1 == ~t10_pc~0); 625#L788-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1240#L799true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 821#L800true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1140#L1577true assume !(0 != activate_threads_~tmp___9~0#1); 179#L1577-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1025#L807true assume 1 == ~t11_pc~0; 1217#L808true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 758#L818true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1277#L819true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1798#L1585true assume !(0 != activate_threads_~tmp___10~0#1); 1782#L1585-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1181#L826true assume !(1 == ~t12_pc~0); 387#L826-2true is_transmit12_triggered_~__retres1~12#1 := 0; 781#L837true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1609#L838true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1368#L1593true assume !(0 != activate_threads_~tmp___11~0#1); 485#L1593-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 429#L1344true assume !(1 == ~M_E~0); 520#L1344-2true assume !(1 == ~T1_E~0); 1746#L1349-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 654#L1354-1true assume !(1 == ~T3_E~0); 1006#L1359-1true assume !(1 == ~T4_E~0); 1586#L1364-1true assume !(1 == ~T5_E~0); 234#L1369-1true assume !(1 == ~T6_E~0); 982#L1374-1true assume !(1 == ~T7_E~0); 659#L1379-1true assume !(1 == ~T8_E~0); 712#L1384-1true assume !(1 == ~T9_E~0); 1768#L1389-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1245#L1394-1true assume !(1 == ~T11_E~0); 1673#L1399-1true assume !(1 == ~T12_E~0); 1469#L1404-1true assume !(1 == ~E_M~0); 297#L1409-1true assume !(1 == ~E_1~0); 1427#L1414-1true assume !(1 == ~E_2~0); 907#L1419-1true assume !(1 == ~E_3~0); 108#L1424-1true assume !(1 == ~E_4~0); 665#L1429-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1272#L1434-1true assume !(1 == ~E_6~0); 1657#L1439-1true assume !(1 == ~E_7~0); 133#L1444-1true assume !(1 == ~E_8~0); 853#L1449-1true assume !(1 == ~E_9~0); 350#L1454-1true assume !(1 == ~E_10~0); 1326#L1459-1true assume !(1 == ~E_11~0); 739#L1464-1true assume !(1 == ~E_12~0); 786#L1469-1true assume { :end_inline_reset_delta_events } true; 1520#L1815-2true [2022-07-14 16:03:15,616 INFO L754 eck$LassoCheckResult]: Loop: 1520#L1815-2true assume !false; 927#L1816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 688#L1181true assume false; 1758#L1196true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105#L846-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1652#L1206-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1669#L1206-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 738#L1211-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 172#L1216-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 499#L1221-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1031#L1226-3true assume !(0 == ~T5_E~0); 206#L1231-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 370#L1236-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1783#L1241-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1361#L1246-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1155#L1251-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 834#L1256-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 184#L1261-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 544#L1266-3true assume !(0 == ~E_M~0); 205#L1271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 519#L1276-3true assume 0 == ~E_2~0;~E_2~0 := 1; 466#L1281-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1215#L1286-3true assume 0 == ~E_4~0;~E_4~0 := 1; 901#L1291-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1665#L1296-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1583#L1301-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1447#L1306-3true assume !(0 == ~E_8~0); 554#L1311-3true assume 0 == ~E_9~0;~E_9~0 := 1; 142#L1316-3true assume 0 == ~E_10~0;~E_10~0 := 1; 185#L1321-3true assume 0 == ~E_11~0;~E_11~0 := 1; 631#L1326-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1417#L1331-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L598-42true assume 1 == ~m_pc~0; 1343#L599-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1190#L609-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226#L610-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1448#L1497-42true assume !(0 != activate_threads_~tmp~1#1); 1703#L1497-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 671#L617-42true assume !(1 == ~t1_pc~0); 1109#L617-44true is_transmit1_triggered_~__retres1~1#1 := 0; 414#L628-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 717#L629-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1439#L1505-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 257#L1505-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1423#L636-42true assume 1 == ~t2_pc~0; 1373#L637-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1744#L647-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 819#L648-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1100#L1513-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1002#L1513-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 855#L655-42true assume 1 == ~t3_pc~0; 1602#L656-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1063#L666-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 296#L667-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1757#L1521-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1213#L1521-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1111#L674-42true assume !(1 == ~t4_pc~0); 840#L674-44true is_transmit4_triggered_~__retres1~4#1 := 0; 774#L685-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83#L686-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 969#L1529-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 614#L1529-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1196#L693-42true assume 1 == ~t5_pc~0; 827#L694-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 880#L704-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1465#L705-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 876#L1537-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1158#L1537-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 354#L712-42true assume 1 == ~t6_pc~0; 570#L713-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 996#L723-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 734#L724-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1787#L1545-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 419#L1545-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1378#L731-42true assume 1 == ~t7_pc~0; 338#L732-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1382#L742-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1094#L743-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 365#L1553-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1060#L1553-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 209#L750-42true assume !(1 == ~t8_pc~0); 1167#L750-44true is_transmit8_triggered_~__retres1~8#1 := 0; 1561#L761-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 895#L762-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 151#L1561-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1695#L1561-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 613#L769-42true assume 1 == ~t9_pc~0; 479#L770-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1118#L780-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1238#L781-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1595#L1569-42true assume !(0 != activate_threads_~tmp___8~0#1); 258#L1569-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 619#L788-42true assume 1 == ~t10_pc~0; 795#L789-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1698#L799-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 577#L800-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1676#L1577-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1625#L1577-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1541#L807-42true assume !(1 == ~t11_pc~0); 59#L807-44true is_transmit11_triggered_~__retres1~11#1 := 0; 543#L818-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 125#L819-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 126#L1585-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1154#L1585-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 256#L826-42true assume 1 == ~t12_pc~0; 1742#L827-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 985#L837-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1339#L838-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 252#L1593-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1486#L1593-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 837#L1344-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1224#L1344-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 775#L1349-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 333#L1354-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 789#L1359-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1661#L1364-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1552#L1369-3true assume !(1 == ~T6_E~0); 1271#L1374-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 212#L1379-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1161#L1384-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 332#L1389-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 513#L1394-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1726#L1399-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1292#L1404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1231#L1409-3true assume !(1 == ~E_1~0); 1360#L1414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1385#L1419-3true assume 1 == ~E_3~0;~E_3~0 := 2; 975#L1424-3true assume 1 == ~E_4~0;~E_4~0 := 2; 160#L1429-3true assume 1 == ~E_5~0;~E_5~0 := 2; 788#L1434-3true assume 1 == ~E_6~0;~E_6~0 := 2; 961#L1439-3true assume 1 == ~E_7~0;~E_7~0 := 2; 129#L1444-3true assume 1 == ~E_8~0;~E_8~0 := 2; 190#L1449-3true assume !(1 == ~E_9~0); 1446#L1454-3true assume 1 == ~E_10~0;~E_10~0 := 2; 784#L1459-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1774#L1464-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1267#L1469-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 675#L926-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82#L993-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 402#L994-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1591#L1834true assume !(0 == start_simulation_~tmp~3#1); 1107#L1834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 909#L926-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 583#L993-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 744#L994-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1251#L1789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1596#L1796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75#L1797true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 976#L1847true assume !(0 != start_simulation_~tmp___0~1#1); 1520#L1815-2true [2022-07-14 16:03:15,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:15,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-07-14 16:03:15,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:15,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947031501] [2022-07-14 16:03:15,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:15,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:15,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:15,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:15,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:15,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947031501] [2022-07-14 16:03:15,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947031501] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:15,872 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:15,872 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:15,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953606564] [2022-07-14 16:03:15,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:15,876 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:15,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:15,877 INFO L85 PathProgramCache]: Analyzing trace with hash -1055723210, now seen corresponding path program 1 times [2022-07-14 16:03:15,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:15,878 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438831003] [2022-07-14 16:03:15,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:15,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:15,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:15,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:15,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:15,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438831003] [2022-07-14 16:03:15,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438831003] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:15,906 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:15,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:15,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545679027] [2022-07-14 16:03:15,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:15,908 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:15,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:15,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-14 16:03:15,942 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-14 16:03:15,946 INFO L87 Difference]: Start difference. First operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:15,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:15,995 INFO L93 Difference]: Finished difference Result 1796 states and 2661 transitions. [2022-07-14 16:03:15,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-14 16:03:16,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1796 states and 2661 transitions. [2022-07-14 16:03:16,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1796 states to 1790 states and 2655 transitions. [2022-07-14 16:03:16,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:16,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:16,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2655 transitions. [2022-07-14 16:03:16,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:16,037 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-07-14 16:03:16,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2655 transitions. [2022-07-14 16:03:16,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:16,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2655 transitions. [2022-07-14 16:03:16,105 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-07-14 16:03:16,105 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-07-14 16:03:16,105 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:03:16,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2655 transitions. [2022-07-14 16:03:16,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:16,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:16,115 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,115 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,115 INFO L752 eck$LassoCheckResult]: Stem: 4447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3871#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3841#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3842#L853 assume !(1 == ~m_i~0);~m_st~0 := 2; 5103#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4150#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3603#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3604#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4875#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5014#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5380#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5381#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4360#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4361#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4901#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4821#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4822#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4974#L1206 assume !(0 == ~M_E~0); 4339#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4340#L1211-1 assume !(0 == ~T2_E~0); 5233#L1216-1 assume !(0 == ~T3_E~0); 4132#L1221-1 assume !(0 == ~T4_E~0); 4133#L1226-1 assume !(0 == ~T5_E~0); 3795#L1231-1 assume !(0 == ~T6_E~0); 3796#L1236-1 assume !(0 == ~T7_E~0); 5264#L1241-1 assume !(0 == ~T8_E~0); 4194#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4195#L1251-1 assume !(0 == ~T10_E~0); 4415#L1256-1 assume !(0 == ~T11_E~0); 3615#L1261-1 assume !(0 == ~T12_E~0); 3616#L1266-1 assume !(0 == ~E_M~0); 5367#L1271-1 assume !(0 == ~E_1~0); 5002#L1276-1 assume !(0 == ~E_2~0); 5003#L1281-1 assume !(0 == ~E_3~0); 4928#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4036#L1291-1 assume !(0 == ~E_5~0); 4037#L1296-1 assume !(0 == ~E_6~0); 4743#L1301-1 assume !(0 == ~E_7~0); 4744#L1306-1 assume !(0 == ~E_8~0); 5176#L1311-1 assume !(0 == ~E_9~0); 3997#L1316-1 assume !(0 == ~E_10~0); 3998#L1321-1 assume !(0 == ~E_11~0); 4760#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3861#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3862#L598 assume 1 == ~m_pc~0; 3921#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3922#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5246#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5338#L1497 assume !(0 != activate_threads_~tmp~1#1); 5339#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5295#L617 assume !(1 == ~t1_pc~0); 4217#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4218#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4078#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4838#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4839#L636 assume 1 == ~t2_pc~0; 4186#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4187#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4017#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4018#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 4874#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4537#L655 assume !(1 == ~t3_pc~0); 4538#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5251#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3891#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3892#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 5368#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369#L674 assume 1 == ~t4_pc~0; 3711#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3712#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5009#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4019#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 4020#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4534#L693 assume !(1 == ~t5_pc~0); 4697#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4341#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4342#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5178#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 4427#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4364#L712 assume 1 == ~t6_pc~0; 4365#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4792#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4793#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5079#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 4890#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4888#L731 assume 1 == ~t7_pc~0; 3865#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3866#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4060#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4997#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 5116#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3975#L750 assume !(1 == ~t8_pc~0); 3646#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3645#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4161#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5191#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4298#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4299#L769 assume 1 == ~t9_pc~0; 4834#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3819#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3820#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4603#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 5055#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5136#L788 assume !(1 == ~t10_pc~0); 4711#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4712#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4943#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4944#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3971#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3972#L807 assume 1 == ~t11_pc~0; 5145#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4723#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4876#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5287#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 5392#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5235#L826 assume !(1 == ~t12_pc~0); 4367#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4368#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4896#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5327#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 4527#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4436#L1344 assume !(1 == ~M_E~0); 4437#L1344-2 assume !(1 == ~T1_E~0); 4578#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4750#L1354-1 assume !(1 == ~T3_E~0); 4751#L1359-1 assume !(1 == ~T4_E~0); 5125#L1364-1 assume !(1 == ~T5_E~0); 4079#L1369-1 assume !(1 == ~T6_E~0); 4080#L1374-1 assume !(1 == ~T7_E~0); 4756#L1379-1 assume !(1 == ~T8_E~0); 4757#L1384-1 assume !(1 == ~T9_E~0); 4820#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5266#L1394-1 assume !(1 == ~T11_E~0); 5267#L1399-1 assume !(1 == ~T12_E~0); 5346#L1404-1 assume !(1 == ~E_M~0); 4198#L1409-1 assume !(1 == ~E_1~0); 4199#L1414-1 assume !(1 == ~E_2~0); 5036#L1419-1 assume !(1 == ~E_3~0); 3832#L1424-1 assume !(1 == ~E_4~0); 3833#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4767#L1434-1 assume !(1 == ~E_6~0); 5285#L1439-1 assume !(1 == ~E_7~0); 3887#L1444-1 assume !(1 == ~E_8~0); 3888#L1449-1 assume !(1 == ~E_9~0); 4303#L1454-1 assume !(1 == ~E_10~0); 4304#L1459-1 assume !(1 == ~E_11~0); 4854#L1464-1 assume !(1 == ~E_12~0); 4855#L1469-1 assume { :end_inline_reset_delta_events } true; 4902#L1815-2 [2022-07-14 16:03:16,116 INFO L754 eck$LassoCheckResult]: Loop: 4902#L1815-2 assume !false; 5056#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4725#L1181 assume !false; 4796#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4748#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3606#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4335#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4886#L1008 assume !(0 != eval_~tmp~0#1); 4887#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3825#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3826#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5386#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4853#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3959#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3960#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4550#L1226-3 assume !(0 == ~T5_E~0); 4023#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4024#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4336#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5323#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5226#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4962#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3981#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3982#L1266-3 assume !(0 == ~E_M~0); 4021#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4022#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4494#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4495#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5032#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5033#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5375#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5343#L1306-3 assume !(0 == ~E_8~0); 4619#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3905#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3906#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3983#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4718#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5043#L598-42 assume !(1 == ~m_pc~0); 5044#L598-44 is_master_triggered_~__retres1~0#1 := 0; 5158#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4061#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4062#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 5344#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4774#L617-42 assume 1 == ~t1_pc~0; 4546#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4411#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4826#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4126#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4127#L636-42 assume 1 == ~t2_pc~0; 5328#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4591#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4941#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4942#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5121#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L655-42 assume !(1 == ~t3_pc~0); 4563#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4196#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4197#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5250#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5195#L674-42 assume !(1 == ~t4_pc~0); 4969#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4891#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3780#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3781#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4695#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4696#L693-42 assume 1 == ~t5_pc~0; 4951#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4952#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5012#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5007#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5008#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4310#L712-42 assume !(1 == ~t6_pc~0); 4311#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4637#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4845#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4846#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4419#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4420#L731-42 assume !(1 == ~t7_pc~0); 4118#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4119#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5186#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4327#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4328#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4031#L750-42 assume 1 == ~t8_pc~0; 4032#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4606#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5029#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3924#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3925#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4694#L769-42 assume 1 == ~t9_pc~0; 4516#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4517#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5200#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5265#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 4128#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4129#L788-42 assume 1 == ~t10_pc~0; 4702#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4916#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4646#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4647#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5384#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5362#L807-42 assume !(1 == ~t11_pc~0); 3732#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3733#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3872#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3873#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3874#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4123#L826-42 assume 1 == ~t12_pc~0; 4124#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4316#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5108#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4113#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4114#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4965#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4966#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4892#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4273#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4274#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4906#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5364#L1369-3 assume !(1 == ~T6_E~0); 5284#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4038#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4039#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4271#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4272#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4570#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5293#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5256#L1409-3 assume !(1 == ~E_1~0); 5257#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5322#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5102#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3939#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3940#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4905#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3879#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3880#L1449-3 assume !(1 == ~E_9~0); 3989#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4899#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4900#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5281#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4779#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3778#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3779#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4395#L1834 assume !(0 == start_simulation_~tmp~3#1); 5015#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5038#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4472#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4651#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4863#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5271#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3764#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3765#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 4902#L1815-2 [2022-07-14 16:03:16,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-07-14 16:03:16,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692532928] [2022-07-14 16:03:16,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,160 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692532928] [2022-07-14 16:03:16,160 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692532928] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,160 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,160 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545223150] [2022-07-14 16:03:16,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,161 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:16,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,163 INFO L85 PathProgramCache]: Analyzing trace with hash 1784148501, now seen corresponding path program 1 times [2022-07-14 16:03:16,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152235182] [2022-07-14 16:03:16,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152235182] [2022-07-14 16:03:16,305 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152235182] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,305 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,305 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254149777] [2022-07-14 16:03:16,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,306 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:16,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:16,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:16,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:16,328 INFO L87 Difference]: Start difference. First operand 1790 states and 2655 transitions. cyclomatic complexity: 866 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:16,365 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2022-07-14 16:03:16,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:16,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2654 transitions. [2022-07-14 16:03:16,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2654 transitions. [2022-07-14 16:03:16,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:16,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:16,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2654 transitions. [2022-07-14 16:03:16,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:16,385 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-07-14 16:03:16,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2654 transitions. [2022-07-14 16:03:16,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:16,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2654 transitions. [2022-07-14 16:03:16,410 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-07-14 16:03:16,410 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-07-14 16:03:16,410 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:03:16,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2654 transitions. [2022-07-14 16:03:16,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:16,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:16,418 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,418 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,419 INFO L752 eck$LassoCheckResult]: Stem: 8034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 8035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7458#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7428#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7429#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 8690#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7737#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7190#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7191#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8462#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8601#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8967#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8968#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7947#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7948#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8488#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8408#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8409#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8561#L1206 assume !(0 == ~M_E~0); 7926#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7927#L1211-1 assume !(0 == ~T2_E~0); 8820#L1216-1 assume !(0 == ~T3_E~0); 7719#L1221-1 assume !(0 == ~T4_E~0); 7720#L1226-1 assume !(0 == ~T5_E~0); 7382#L1231-1 assume !(0 == ~T6_E~0); 7383#L1236-1 assume !(0 == ~T7_E~0); 8851#L1241-1 assume !(0 == ~T8_E~0); 7781#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7782#L1251-1 assume !(0 == ~T10_E~0); 8002#L1256-1 assume !(0 == ~T11_E~0); 7202#L1261-1 assume !(0 == ~T12_E~0); 7203#L1266-1 assume !(0 == ~E_M~0); 8954#L1271-1 assume !(0 == ~E_1~0); 8589#L1276-1 assume !(0 == ~E_2~0); 8590#L1281-1 assume !(0 == ~E_3~0); 8515#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7623#L1291-1 assume !(0 == ~E_5~0); 7624#L1296-1 assume !(0 == ~E_6~0); 8330#L1301-1 assume !(0 == ~E_7~0); 8331#L1306-1 assume !(0 == ~E_8~0); 8763#L1311-1 assume !(0 == ~E_9~0); 7584#L1316-1 assume !(0 == ~E_10~0); 7585#L1321-1 assume !(0 == ~E_11~0); 8347#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7448#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7449#L598 assume 1 == ~m_pc~0; 7508#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7509#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8833#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8925#L1497 assume !(0 != activate_threads_~tmp~1#1); 8926#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8882#L617 assume !(1 == ~t1_pc~0); 7804#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7805#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7664#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7665#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8425#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8426#L636 assume 1 == ~t2_pc~0; 7773#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7774#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7604#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7605#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 8461#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8124#L655 assume !(1 == ~t3_pc~0); 8125#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8838#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7478#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7479#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 8955#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8956#L674 assume 1 == ~t4_pc~0; 7298#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7299#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8596#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7606#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 7607#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8121#L693 assume !(1 == ~t5_pc~0); 8284#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7928#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7929#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8765#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 8014#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7951#L712 assume 1 == ~t6_pc~0; 7952#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8379#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8380#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8666#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 8477#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8475#L731 assume 1 == ~t7_pc~0; 7452#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7453#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7647#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8584#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 8703#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7562#L750 assume !(1 == ~t8_pc~0); 7233#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7232#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7748#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8778#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7885#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7886#L769 assume 1 == ~t9_pc~0; 8421#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7406#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7407#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8190#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 8642#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8723#L788 assume !(1 == ~t10_pc~0); 8298#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8299#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8530#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8531#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 7558#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7559#L807 assume 1 == ~t11_pc~0; 8732#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8310#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8463#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8874#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 8979#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8822#L826 assume !(1 == ~t12_pc~0); 7954#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 7955#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8483#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8914#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 8114#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8023#L1344 assume !(1 == ~M_E~0); 8024#L1344-2 assume !(1 == ~T1_E~0); 8165#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8337#L1354-1 assume !(1 == ~T3_E~0); 8338#L1359-1 assume !(1 == ~T4_E~0); 8712#L1364-1 assume !(1 == ~T5_E~0); 7666#L1369-1 assume !(1 == ~T6_E~0); 7667#L1374-1 assume !(1 == ~T7_E~0); 8343#L1379-1 assume !(1 == ~T8_E~0); 8344#L1384-1 assume !(1 == ~T9_E~0); 8407#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8853#L1394-1 assume !(1 == ~T11_E~0); 8854#L1399-1 assume !(1 == ~T12_E~0); 8933#L1404-1 assume !(1 == ~E_M~0); 7785#L1409-1 assume !(1 == ~E_1~0); 7786#L1414-1 assume !(1 == ~E_2~0); 8623#L1419-1 assume !(1 == ~E_3~0); 7419#L1424-1 assume !(1 == ~E_4~0); 7420#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8354#L1434-1 assume !(1 == ~E_6~0); 8872#L1439-1 assume !(1 == ~E_7~0); 7474#L1444-1 assume !(1 == ~E_8~0); 7475#L1449-1 assume !(1 == ~E_9~0); 7890#L1454-1 assume !(1 == ~E_10~0); 7891#L1459-1 assume !(1 == ~E_11~0); 8441#L1464-1 assume !(1 == ~E_12~0); 8442#L1469-1 assume { :end_inline_reset_delta_events } true; 8489#L1815-2 [2022-07-14 16:03:16,420 INFO L754 eck$LassoCheckResult]: Loop: 8489#L1815-2 assume !false; 8643#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8312#L1181 assume !false; 8383#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8335#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7193#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7922#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8473#L1008 assume !(0 != eval_~tmp~0#1); 8474#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7412#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7413#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8973#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8440#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7546#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7547#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8137#L1226-3 assume !(0 == ~T5_E~0); 7610#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7611#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7923#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8910#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8813#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8549#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7569#L1266-3 assume !(0 == ~E_M~0); 7608#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7609#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8081#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8082#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8619#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8620#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8962#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8930#L1306-3 assume !(0 == ~E_8~0); 8206#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7492#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7493#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7570#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8305#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8630#L598-42 assume !(1 == ~m_pc~0); 8631#L598-44 is_master_triggered_~__retres1~0#1 := 0; 8745#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7648#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7649#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 8931#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8361#L617-42 assume 1 == ~t1_pc~0; 8133#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7998#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7999#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8413#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7713#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7714#L636-42 assume !(1 == ~t2_pc~0); 8177#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8178#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8528#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8529#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8708#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8570#L655-42 assume !(1 == ~t3_pc~0); 8150#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8151#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7783#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7784#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8837#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8782#L674-42 assume !(1 == ~t4_pc~0); 8556#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8478#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7367#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7368#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8282#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8283#L693-42 assume 1 == ~t5_pc~0; 8538#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8539#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8599#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8594#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8595#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7897#L712-42 assume !(1 == ~t6_pc~0); 7898#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8224#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8432#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8433#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8006#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8007#L731-42 assume !(1 == ~t7_pc~0); 7705#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7706#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8773#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7914#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7915#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7618#L750-42 assume 1 == ~t8_pc~0; 7619#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8193#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8616#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7511#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7512#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8281#L769-42 assume 1 == ~t9_pc~0; 8103#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8104#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8787#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8852#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 7715#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7716#L788-42 assume 1 == ~t10_pc~0; 8289#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8503#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8233#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8234#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8971#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8949#L807-42 assume !(1 == ~t11_pc~0); 7319#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7320#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7459#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7460#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7461#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7710#L826-42 assume !(1 == ~t12_pc~0); 7712#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7903#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8695#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7700#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7701#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8552#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8553#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8479#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7860#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7861#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8493#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8951#L1369-3 assume !(1 == ~T6_E~0); 8871#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7625#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7626#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7858#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7859#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8157#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8880#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8843#L1409-3 assume !(1 == ~E_1~0); 8844#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8909#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8689#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7526#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7527#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8492#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7466#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7467#L1449-3 assume !(1 == ~E_9~0); 7576#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8486#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8487#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8868#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8366#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7365#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7366#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7982#L1834 assume !(0 == start_simulation_~tmp~3#1); 8602#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8625#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8059#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8238#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8450#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8858#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7351#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7352#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 8489#L1815-2 [2022-07-14 16:03:16,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,421 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-07-14 16:03:16,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669596391] [2022-07-14 16:03:16,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669596391] [2022-07-14 16:03:16,466 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669596391] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,466 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,467 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973773941] [2022-07-14 16:03:16,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,467 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:16,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1198130711, now seen corresponding path program 1 times [2022-07-14 16:03:16,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307725581] [2022-07-14 16:03:16,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307725581] [2022-07-14 16:03:16,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307725581] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,510 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360907770] [2022-07-14 16:03:16,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,510 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:16,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:16,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:16,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:16,511 INFO L87 Difference]: Start difference. First operand 1790 states and 2654 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:16,537 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2022-07-14 16:03:16,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:16,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2653 transitions. [2022-07-14 16:03:16,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,553 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2653 transitions. [2022-07-14 16:03:16,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:16,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:16,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2653 transitions. [2022-07-14 16:03:16,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:16,557 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-07-14 16:03:16,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2653 transitions. [2022-07-14 16:03:16,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:16,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2653 transitions. [2022-07-14 16:03:16,645 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-07-14 16:03:16,645 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-07-14 16:03:16,645 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:03:16,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2653 transitions. [2022-07-14 16:03:16,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:16,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:16,655 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,655 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,656 INFO L752 eck$LassoCheckResult]: Stem: 11621#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11045#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11015#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11016#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 12277#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11324#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10777#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10778#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12049#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12188#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12554#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12555#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11534#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11535#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12075#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11995#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11996#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12148#L1206 assume !(0 == ~M_E~0); 11513#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11514#L1211-1 assume !(0 == ~T2_E~0); 12407#L1216-1 assume !(0 == ~T3_E~0); 11306#L1221-1 assume !(0 == ~T4_E~0); 11307#L1226-1 assume !(0 == ~T5_E~0); 10969#L1231-1 assume !(0 == ~T6_E~0); 10970#L1236-1 assume !(0 == ~T7_E~0); 12438#L1241-1 assume !(0 == ~T8_E~0); 11368#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11369#L1251-1 assume !(0 == ~T10_E~0); 11589#L1256-1 assume !(0 == ~T11_E~0); 10789#L1261-1 assume !(0 == ~T12_E~0); 10790#L1266-1 assume !(0 == ~E_M~0); 12541#L1271-1 assume !(0 == ~E_1~0); 12176#L1276-1 assume !(0 == ~E_2~0); 12177#L1281-1 assume !(0 == ~E_3~0); 12102#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11210#L1291-1 assume !(0 == ~E_5~0); 11211#L1296-1 assume !(0 == ~E_6~0); 11917#L1301-1 assume !(0 == ~E_7~0); 11918#L1306-1 assume !(0 == ~E_8~0); 12350#L1311-1 assume !(0 == ~E_9~0); 11171#L1316-1 assume !(0 == ~E_10~0); 11172#L1321-1 assume !(0 == ~E_11~0); 11934#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11035#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11036#L598 assume 1 == ~m_pc~0; 11095#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11096#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12420#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12512#L1497 assume !(0 != activate_threads_~tmp~1#1); 12513#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12469#L617 assume !(1 == ~t1_pc~0); 11391#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11392#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11251#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11252#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12012#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12013#L636 assume 1 == ~t2_pc~0; 11360#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11361#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11191#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11192#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 12048#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11711#L655 assume !(1 == ~t3_pc~0); 11712#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12425#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11065#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11066#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 12542#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12543#L674 assume 1 == ~t4_pc~0; 10885#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10886#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12183#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11193#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 11194#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11708#L693 assume !(1 == ~t5_pc~0); 11871#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11515#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11516#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12352#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 11601#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11538#L712 assume 1 == ~t6_pc~0; 11539#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11966#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11967#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12253#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 12064#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12062#L731 assume 1 == ~t7_pc~0; 11039#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11040#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11234#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12171#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 12290#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11149#L750 assume !(1 == ~t8_pc~0); 10820#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10819#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11335#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12365#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11472#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11473#L769 assume 1 == ~t9_pc~0; 12008#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10993#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10994#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11777#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 12229#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12310#L788 assume !(1 == ~t10_pc~0); 11885#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11886#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12117#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12118#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 11145#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11146#L807 assume 1 == ~t11_pc~0; 12319#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11897#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12050#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12461#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 12566#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12409#L826 assume !(1 == ~t12_pc~0); 11541#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11542#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12070#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12501#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 11701#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11610#L1344 assume !(1 == ~M_E~0); 11611#L1344-2 assume !(1 == ~T1_E~0); 11752#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11924#L1354-1 assume !(1 == ~T3_E~0); 11925#L1359-1 assume !(1 == ~T4_E~0); 12299#L1364-1 assume !(1 == ~T5_E~0); 11253#L1369-1 assume !(1 == ~T6_E~0); 11254#L1374-1 assume !(1 == ~T7_E~0); 11930#L1379-1 assume !(1 == ~T8_E~0); 11931#L1384-1 assume !(1 == ~T9_E~0); 11994#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12440#L1394-1 assume !(1 == ~T11_E~0); 12441#L1399-1 assume !(1 == ~T12_E~0); 12520#L1404-1 assume !(1 == ~E_M~0); 11372#L1409-1 assume !(1 == ~E_1~0); 11373#L1414-1 assume !(1 == ~E_2~0); 12210#L1419-1 assume !(1 == ~E_3~0); 11006#L1424-1 assume !(1 == ~E_4~0); 11007#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11941#L1434-1 assume !(1 == ~E_6~0); 12459#L1439-1 assume !(1 == ~E_7~0); 11061#L1444-1 assume !(1 == ~E_8~0); 11062#L1449-1 assume !(1 == ~E_9~0); 11477#L1454-1 assume !(1 == ~E_10~0); 11478#L1459-1 assume !(1 == ~E_11~0); 12028#L1464-1 assume !(1 == ~E_12~0); 12029#L1469-1 assume { :end_inline_reset_delta_events } true; 12076#L1815-2 [2022-07-14 16:03:16,656 INFO L754 eck$LassoCheckResult]: Loop: 12076#L1815-2 assume !false; 12230#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11899#L1181 assume !false; 11970#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11922#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10780#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11509#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12060#L1008 assume !(0 != eval_~tmp~0#1); 12061#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10999#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11000#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12560#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12027#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11133#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11134#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11724#L1226-3 assume !(0 == ~T5_E~0); 11197#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11198#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11510#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12497#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12400#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12136#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11155#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11156#L1266-3 assume !(0 == ~E_M~0); 11195#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11196#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11668#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11669#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12206#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12207#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12549#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12517#L1306-3 assume !(0 == ~E_8~0); 11793#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11079#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11080#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11157#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11892#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12217#L598-42 assume !(1 == ~m_pc~0); 12218#L598-44 is_master_triggered_~__retres1~0#1 := 0; 12332#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11235#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11236#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 12518#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11948#L617-42 assume 1 == ~t1_pc~0; 11720#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11585#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11586#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12000#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11300#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11301#L636-42 assume !(1 == ~t2_pc~0); 11764#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11765#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12115#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12116#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12295#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12157#L655-42 assume !(1 == ~t3_pc~0); 11737#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11738#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11370#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11371#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12424#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12369#L674-42 assume 1 == ~t4_pc~0; 12370#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12065#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10954#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10955#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11869#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11870#L693-42 assume 1 == ~t5_pc~0; 12125#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12126#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12186#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12181#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12182#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11484#L712-42 assume !(1 == ~t6_pc~0); 11485#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 11811#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12019#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12020#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11593#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11594#L731-42 assume 1 == ~t7_pc~0; 11457#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11293#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12360#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11501#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11502#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11205#L750-42 assume 1 == ~t8_pc~0; 11206#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11780#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12203#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11098#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11099#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11868#L769-42 assume 1 == ~t9_pc~0; 11690#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11691#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12374#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12439#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 11302#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11303#L788-42 assume 1 == ~t10_pc~0; 11876#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12090#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11820#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11821#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12558#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12536#L807-42 assume 1 == ~t11_pc~0; 12225#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10907#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11046#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11047#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11048#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11297#L826-42 assume 1 == ~t12_pc~0; 11298#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11490#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12282#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11287#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11288#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12139#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12140#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12066#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11447#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11448#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12080#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12538#L1369-3 assume !(1 == ~T6_E~0); 12458#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11212#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11213#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11445#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11446#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11744#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12467#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12430#L1409-3 assume !(1 == ~E_1~0); 12431#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12496#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12276#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11113#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11114#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12079#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11053#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11054#L1449-3 assume !(1 == ~E_9~0); 11163#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12073#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12074#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12455#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11953#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10952#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10953#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11569#L1834 assume !(0 == start_simulation_~tmp~3#1); 12189#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12212#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11646#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11825#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12037#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12445#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10938#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 10939#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 12076#L1815-2 [2022-07-14 16:03:16,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,657 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-07-14 16:03:16,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958069812] [2022-07-14 16:03:16,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958069812] [2022-07-14 16:03:16,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958069812] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,717 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675796255] [2022-07-14 16:03:16,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,721 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:16,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 1 times [2022-07-14 16:03:16,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490996039] [2022-07-14 16:03:16,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490996039] [2022-07-14 16:03:16,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490996039] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,788 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,788 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641380587] [2022-07-14 16:03:16,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,789 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:16,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:16,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:16,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:16,791 INFO L87 Difference]: Start difference. First operand 1790 states and 2653 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:16,818 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2022-07-14 16:03:16,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:16,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2652 transitions. [2022-07-14 16:03:16,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2652 transitions. [2022-07-14 16:03:16,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:16,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:16,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2652 transitions. [2022-07-14 16:03:16,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:16,839 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-07-14 16:03:16,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2652 transitions. [2022-07-14 16:03:16,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:16,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2652 transitions. [2022-07-14 16:03:16,865 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-07-14 16:03:16,865 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-07-14 16:03:16,866 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:03:16,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2652 transitions. [2022-07-14 16:03:16,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:16,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:16,873 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,873 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,874 INFO L752 eck$LassoCheckResult]: Stem: 15208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14632#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14602#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14603#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 15864#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14911#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14364#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14365#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15636#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15775#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16141#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16142#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15121#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15122#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15662#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15582#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15583#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15735#L1206 assume !(0 == ~M_E~0); 15100#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15101#L1211-1 assume !(0 == ~T2_E~0); 15994#L1216-1 assume !(0 == ~T3_E~0); 14893#L1221-1 assume !(0 == ~T4_E~0); 14894#L1226-1 assume !(0 == ~T5_E~0); 14556#L1231-1 assume !(0 == ~T6_E~0); 14557#L1236-1 assume !(0 == ~T7_E~0); 16025#L1241-1 assume !(0 == ~T8_E~0); 14955#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14956#L1251-1 assume !(0 == ~T10_E~0); 15176#L1256-1 assume !(0 == ~T11_E~0); 14376#L1261-1 assume !(0 == ~T12_E~0); 14377#L1266-1 assume !(0 == ~E_M~0); 16128#L1271-1 assume !(0 == ~E_1~0); 15763#L1276-1 assume !(0 == ~E_2~0); 15764#L1281-1 assume !(0 == ~E_3~0); 15689#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14797#L1291-1 assume !(0 == ~E_5~0); 14798#L1296-1 assume !(0 == ~E_6~0); 15504#L1301-1 assume !(0 == ~E_7~0); 15505#L1306-1 assume !(0 == ~E_8~0); 15937#L1311-1 assume !(0 == ~E_9~0); 14758#L1316-1 assume !(0 == ~E_10~0); 14759#L1321-1 assume !(0 == ~E_11~0); 15521#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14622#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14623#L598 assume 1 == ~m_pc~0; 14682#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14683#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16007#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16099#L1497 assume !(0 != activate_threads_~tmp~1#1); 16100#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16056#L617 assume !(1 == ~t1_pc~0); 14978#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14979#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14838#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14839#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15599#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15600#L636 assume 1 == ~t2_pc~0; 14947#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14948#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14778#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14779#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 15635#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15298#L655 assume !(1 == ~t3_pc~0); 15299#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16012#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14652#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14653#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 16129#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16130#L674 assume 1 == ~t4_pc~0; 14472#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14473#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15770#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14780#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 14781#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15295#L693 assume !(1 == ~t5_pc~0); 15458#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15102#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15103#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15939#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 15188#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15125#L712 assume 1 == ~t6_pc~0; 15126#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15553#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15554#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15840#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 15651#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15649#L731 assume 1 == ~t7_pc~0; 14626#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14627#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14821#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15758#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 15877#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14736#L750 assume !(1 == ~t8_pc~0); 14407#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14406#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14922#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15952#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15059#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15060#L769 assume 1 == ~t9_pc~0; 15595#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14580#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14581#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15364#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 15816#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15897#L788 assume !(1 == ~t10_pc~0); 15472#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15473#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15704#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15705#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 14732#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14733#L807 assume 1 == ~t11_pc~0; 15906#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15484#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15637#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16048#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 16153#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15996#L826 assume !(1 == ~t12_pc~0); 15128#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15129#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15657#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16088#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 15288#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15197#L1344 assume !(1 == ~M_E~0); 15198#L1344-2 assume !(1 == ~T1_E~0); 15339#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15511#L1354-1 assume !(1 == ~T3_E~0); 15512#L1359-1 assume !(1 == ~T4_E~0); 15886#L1364-1 assume !(1 == ~T5_E~0); 14840#L1369-1 assume !(1 == ~T6_E~0); 14841#L1374-1 assume !(1 == ~T7_E~0); 15517#L1379-1 assume !(1 == ~T8_E~0); 15518#L1384-1 assume !(1 == ~T9_E~0); 15581#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16027#L1394-1 assume !(1 == ~T11_E~0); 16028#L1399-1 assume !(1 == ~T12_E~0); 16107#L1404-1 assume !(1 == ~E_M~0); 14959#L1409-1 assume !(1 == ~E_1~0); 14960#L1414-1 assume !(1 == ~E_2~0); 15797#L1419-1 assume !(1 == ~E_3~0); 14593#L1424-1 assume !(1 == ~E_4~0); 14594#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15528#L1434-1 assume !(1 == ~E_6~0); 16046#L1439-1 assume !(1 == ~E_7~0); 14648#L1444-1 assume !(1 == ~E_8~0); 14649#L1449-1 assume !(1 == ~E_9~0); 15064#L1454-1 assume !(1 == ~E_10~0); 15065#L1459-1 assume !(1 == ~E_11~0); 15615#L1464-1 assume !(1 == ~E_12~0); 15616#L1469-1 assume { :end_inline_reset_delta_events } true; 15663#L1815-2 [2022-07-14 16:03:16,874 INFO L754 eck$LassoCheckResult]: Loop: 15663#L1815-2 assume !false; 15817#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15486#L1181 assume !false; 15557#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15509#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14367#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15096#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15647#L1008 assume !(0 != eval_~tmp~0#1); 15648#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14586#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14587#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15614#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14720#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14721#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15311#L1226-3 assume !(0 == ~T5_E~0); 14784#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14785#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15097#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16084#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15987#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15723#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14742#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14743#L1266-3 assume !(0 == ~E_M~0); 14782#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14783#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15255#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15256#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15793#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15794#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16136#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16104#L1306-3 assume !(0 == ~E_8~0); 15380#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14666#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14667#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14744#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15479#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15804#L598-42 assume !(1 == ~m_pc~0); 15805#L598-44 is_master_triggered_~__retres1~0#1 := 0; 15919#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14822#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14823#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 16105#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15535#L617-42 assume 1 == ~t1_pc~0; 15307#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15172#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15173#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15587#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14888#L636-42 assume !(1 == ~t2_pc~0); 15351#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15352#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15702#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15703#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15882#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15744#L655-42 assume 1 == ~t3_pc~0; 15745#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15325#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14958#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16011#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15956#L674-42 assume !(1 == ~t4_pc~0); 15730#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 15652#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14541#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14542#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15456#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15457#L693-42 assume 1 == ~t5_pc~0; 15712#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15713#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15773#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15768#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15769#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15071#L712-42 assume !(1 == ~t6_pc~0); 15072#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15398#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15606#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15607#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15180#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15181#L731-42 assume 1 == ~t7_pc~0; 15044#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14880#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15947#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15088#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15089#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14792#L750-42 assume 1 == ~t8_pc~0; 14793#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15367#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15790#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14685#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14686#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15455#L769-42 assume 1 == ~t9_pc~0; 15277#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15278#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15961#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16026#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 14889#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14890#L788-42 assume 1 == ~t10_pc~0; 15463#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15677#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15407#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15408#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16145#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16123#L807-42 assume 1 == ~t11_pc~0; 15812#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14494#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14633#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14634#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14635#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14884#L826-42 assume 1 == ~t12_pc~0; 14885#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15077#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15869#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14874#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14875#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15726#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15727#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15653#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15034#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15035#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15667#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16125#L1369-3 assume !(1 == ~T6_E~0); 16045#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14799#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14800#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15032#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15033#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15331#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16054#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16017#L1409-3 assume !(1 == ~E_1~0); 16018#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16083#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15863#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14700#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14701#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15666#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14640#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14641#L1449-3 assume !(1 == ~E_9~0); 14750#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15660#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15661#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16042#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15540#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14539#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14540#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15156#L1834 assume !(0 == start_simulation_~tmp~3#1); 15776#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15799#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15233#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15412#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15624#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16032#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14525#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14526#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 15663#L1815-2 [2022-07-14 16:03:16,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,875 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-07-14 16:03:16,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153428032] [2022-07-14 16:03:16,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153428032] [2022-07-14 16:03:16,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153428032] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226538085] [2022-07-14 16:03:16,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,908 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:16,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:16,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1846949459, now seen corresponding path program 1 times [2022-07-14 16:03:16,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:16,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767776104] [2022-07-14 16:03:16,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:16,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:16,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:16,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:16,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:16,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767776104] [2022-07-14 16:03:16,935 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767776104] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:16,935 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:16,935 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:16,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858472171] [2022-07-14 16:03:16,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:16,936 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:16,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:16,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:16,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:16,938 INFO L87 Difference]: Start difference. First operand 1790 states and 2652 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:16,956 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-07-14 16:03:16,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:16,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2022-07-14 16:03:16,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2651 transitions. [2022-07-14 16:03:16,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:16,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:16,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2651 transitions. [2022-07-14 16:03:16,972 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:16,972 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-07-14 16:03:16,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2651 transitions. [2022-07-14 16:03:16,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:16,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:16,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2651 transitions. [2022-07-14 16:03:16,993 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-07-14 16:03:16,993 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-07-14 16:03:16,993 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:03:16,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2651 transitions. [2022-07-14 16:03:16,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:16,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:16,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:16,999 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,999 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:16,999 INFO L752 eck$LassoCheckResult]: Stem: 18797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18221#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18194#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18195#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 19451#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18498#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17951#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17952#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19223#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19362#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19728#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19729#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18710#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18711#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19249#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19169#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19170#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19322#L1206 assume !(0 == ~M_E~0); 18687#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18688#L1211-1 assume !(0 == ~T2_E~0); 19581#L1216-1 assume !(0 == ~T3_E~0); 18480#L1221-1 assume !(0 == ~T4_E~0); 18481#L1226-1 assume !(0 == ~T5_E~0); 18145#L1231-1 assume !(0 == ~T6_E~0); 18146#L1236-1 assume !(0 == ~T7_E~0); 19612#L1241-1 assume !(0 == ~T8_E~0); 18542#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18543#L1251-1 assume !(0 == ~T10_E~0); 18763#L1256-1 assume !(0 == ~T11_E~0); 17963#L1261-1 assume !(0 == ~T12_E~0); 17964#L1266-1 assume !(0 == ~E_M~0); 19715#L1271-1 assume !(0 == ~E_1~0); 19350#L1276-1 assume !(0 == ~E_2~0); 19351#L1281-1 assume !(0 == ~E_3~0); 19278#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18384#L1291-1 assume !(0 == ~E_5~0); 18385#L1296-1 assume !(0 == ~E_6~0); 19091#L1301-1 assume !(0 == ~E_7~0); 19092#L1306-1 assume !(0 == ~E_8~0); 19524#L1311-1 assume !(0 == ~E_9~0); 18345#L1316-1 assume !(0 == ~E_10~0); 18346#L1321-1 assume !(0 == ~E_11~0); 19108#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18211#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18212#L598 assume 1 == ~m_pc~0; 18269#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18270#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19594#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19686#L1497 assume !(0 != activate_threads_~tmp~1#1); 19687#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19643#L617 assume !(1 == ~t1_pc~0); 18565#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18566#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18425#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18426#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19186#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19187#L636 assume 1 == ~t2_pc~0; 18534#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18535#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18365#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18366#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 19222#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18886#L655 assume !(1 == ~t3_pc~0); 18887#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19599#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18239#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18240#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 19716#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19717#L674 assume 1 == ~t4_pc~0; 18059#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18060#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19357#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18369#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 18370#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18882#L693 assume !(1 == ~t5_pc~0); 19045#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18692#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18693#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19526#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 18775#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18712#L712 assume 1 == ~t6_pc~0; 18713#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19140#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19141#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19427#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 19238#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19236#L731 assume 1 == ~t7_pc~0; 18213#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18214#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18410#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19346#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 19464#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18323#L750 assume !(1 == ~t8_pc~0); 17994#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17993#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18509#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19539#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18646#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18647#L769 assume 1 == ~t9_pc~0; 19184#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18167#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18168#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18951#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 19403#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19484#L788 assume !(1 == ~t10_pc~0); 19059#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19060#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19293#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19294#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 18321#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18322#L807 assume 1 == ~t11_pc~0; 19493#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19071#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19224#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19635#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 19740#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19583#L826 assume !(1 == ~t12_pc~0); 18717#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18718#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19244#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19675#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 18875#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18784#L1344 assume !(1 == ~M_E~0); 18785#L1344-2 assume !(1 == ~T1_E~0); 18926#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19099#L1354-1 assume !(1 == ~T3_E~0); 19100#L1359-1 assume !(1 == ~T4_E~0); 19473#L1364-1 assume !(1 == ~T5_E~0); 18427#L1369-1 assume !(1 == ~T6_E~0); 18428#L1374-1 assume !(1 == ~T7_E~0); 19106#L1379-1 assume !(1 == ~T8_E~0); 19107#L1384-1 assume !(1 == ~T9_E~0); 19168#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19614#L1394-1 assume !(1 == ~T11_E~0); 19615#L1399-1 assume !(1 == ~T12_E~0); 19694#L1404-1 assume !(1 == ~E_M~0); 18546#L1409-1 assume !(1 == ~E_1~0); 18547#L1414-1 assume !(1 == ~E_2~0); 19384#L1419-1 assume !(1 == ~E_3~0); 18180#L1424-1 assume !(1 == ~E_4~0); 18181#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19118#L1434-1 assume !(1 == ~E_6~0); 19633#L1439-1 assume !(1 == ~E_7~0); 18235#L1444-1 assume !(1 == ~E_8~0); 18236#L1449-1 assume !(1 == ~E_9~0); 18651#L1454-1 assume !(1 == ~E_10~0); 18652#L1459-1 assume !(1 == ~E_11~0); 19202#L1464-1 assume !(1 == ~E_12~0); 19203#L1469-1 assume { :end_inline_reset_delta_events } true; 19250#L1815-2 [2022-07-14 16:03:17,000 INFO L754 eck$LassoCheckResult]: Loop: 19250#L1815-2 assume !false; 19404#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19073#L1181 assume !false; 19144#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19096#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17954#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18684#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19234#L1008 assume !(0 != eval_~tmp~0#1); 19235#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18175#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18176#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19734#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19201#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18307#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18308#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18898#L1226-3 assume !(0 == ~T5_E~0); 18371#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18372#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18683#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19671#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19574#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19310#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18329#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18330#L1266-3 assume !(0 == ~E_M~0); 18367#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18368#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18842#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18843#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19380#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19381#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19723#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19691#L1306-3 assume !(0 == ~E_8~0); 18967#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18253#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18254#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18331#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 19065#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19391#L598-42 assume !(1 == ~m_pc~0); 19392#L598-44 is_master_triggered_~__retres1~0#1 := 0; 19506#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18408#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18409#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 19692#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19122#L617-42 assume 1 == ~t1_pc~0; 18894#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18759#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18760#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19174#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18474#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18475#L636-42 assume !(1 == ~t2_pc~0); 18938#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18939#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19289#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19290#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19469#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19331#L655-42 assume 1 == ~t3_pc~0; 19332#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18912#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18544#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18545#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19598#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19543#L674-42 assume !(1 == ~t4_pc~0); 19317#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 19239#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18128#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18129#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19043#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19044#L693-42 assume 1 == ~t5_pc~0; 19299#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19300#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19360#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19355#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19356#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18658#L712-42 assume !(1 == ~t6_pc~0); 18659#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 18985#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19193#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19194#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18767#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18768#L731-42 assume !(1 == ~t7_pc~0); 18466#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18467#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19534#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18675#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18676#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18379#L750-42 assume 1 == ~t8_pc~0; 18380#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18954#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19377#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18272#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18273#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19042#L769-42 assume 1 == ~t9_pc~0; 18864#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18865#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19548#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19613#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 18476#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18477#L788-42 assume 1 == ~t10_pc~0; 19050#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19264#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18994#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18995#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19732#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19710#L807-42 assume !(1 == ~t11_pc~0); 18080#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18081#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18219#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18220#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18222#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18471#L826-42 assume 1 == ~t12_pc~0; 18472#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18664#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19456#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18461#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18462#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19313#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19314#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19240#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18621#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18622#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19254#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19712#L1369-3 assume !(1 == ~T6_E~0); 19632#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18386#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18387#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18619#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18620#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18918#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19641#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19604#L1409-3 assume !(1 == ~E_1~0); 19605#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19670#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19450#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18287#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18288#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19253#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18227#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18228#L1449-3 assume !(1 == ~E_9~0); 18337#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19247#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19248#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19629#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19127#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18126#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18127#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18743#L1834 assume !(0 == start_simulation_~tmp~3#1); 19363#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19386#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18820#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18999#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19211#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19619#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18112#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18113#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 19250#L1815-2 [2022-07-14 16:03:17,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,001 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-07-14 16:03:17,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431164381] [2022-07-14 16:03:17,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431164381] [2022-07-14 16:03:17,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431164381] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,033 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752377028] [2022-07-14 16:03:17,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,033 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,034 INFO L85 PathProgramCache]: Analyzing trace with hash -112792235, now seen corresponding path program 1 times [2022-07-14 16:03:17,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459476624] [2022-07-14 16:03:17,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459476624] [2022-07-14 16:03:17,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459476624] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413670385] [2022-07-14 16:03:17,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,060 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,061 INFO L87 Difference]: Start difference. First operand 1790 states and 2651 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,079 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2022-07-14 16:03:17,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2650 transitions. [2022-07-14 16:03:17,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2650 transitions. [2022-07-14 16:03:17,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2650 transitions. [2022-07-14 16:03:17,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,093 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-07-14 16:03:17,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2650 transitions. [2022-07-14 16:03:17,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2650 transitions. [2022-07-14 16:03:17,113 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-07-14 16:03:17,113 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-07-14 16:03:17,113 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:03:17,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2650 transitions. [2022-07-14 16:03:17,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,118 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,118 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,119 INFO L752 eck$LassoCheckResult]: Stem: 22382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21808#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21778#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21779#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 23038#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22085#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21538#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21539#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22810#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22949#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23315#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23316#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22297#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22298#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22836#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22756#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22757#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22909#L1206 assume !(0 == ~M_E~0); 22274#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22275#L1211-1 assume !(0 == ~T2_E~0); 23168#L1216-1 assume !(0 == ~T3_E~0); 22067#L1221-1 assume !(0 == ~T4_E~0); 22068#L1226-1 assume !(0 == ~T5_E~0); 21732#L1231-1 assume !(0 == ~T6_E~0); 21733#L1236-1 assume !(0 == ~T7_E~0); 23199#L1241-1 assume !(0 == ~T8_E~0); 22129#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22130#L1251-1 assume !(0 == ~T10_E~0); 22350#L1256-1 assume !(0 == ~T11_E~0); 21550#L1261-1 assume !(0 == ~T12_E~0); 21551#L1266-1 assume !(0 == ~E_M~0); 23302#L1271-1 assume !(0 == ~E_1~0); 22937#L1276-1 assume !(0 == ~E_2~0); 22938#L1281-1 assume !(0 == ~E_3~0); 22865#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 21971#L1291-1 assume !(0 == ~E_5~0); 21972#L1296-1 assume !(0 == ~E_6~0); 22678#L1301-1 assume !(0 == ~E_7~0); 22679#L1306-1 assume !(0 == ~E_8~0); 23111#L1311-1 assume !(0 == ~E_9~0); 21932#L1316-1 assume !(0 == ~E_10~0); 21933#L1321-1 assume !(0 == ~E_11~0); 22695#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21798#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21799#L598 assume 1 == ~m_pc~0; 21856#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21857#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23181#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23273#L1497 assume !(0 != activate_threads_~tmp~1#1); 23274#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23230#L617 assume !(1 == ~t1_pc~0); 22152#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22153#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22012#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22013#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22773#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22774#L636 assume 1 == ~t2_pc~0; 22121#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22122#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21952#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21953#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 22809#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22472#L655 assume !(1 == ~t3_pc~0); 22473#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23186#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21826#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21827#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 23303#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23304#L674 assume 1 == ~t4_pc~0; 21646#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21647#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22944#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21954#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 21955#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22469#L693 assume !(1 == ~t5_pc~0); 22632#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22279#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22280#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23113#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 22362#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22299#L712 assume 1 == ~t6_pc~0; 22300#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22727#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22728#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23014#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 22825#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22823#L731 assume 1 == ~t7_pc~0; 21800#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21801#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21995#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22933#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 23051#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21910#L750 assume !(1 == ~t8_pc~0); 21581#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 21580#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22096#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23126#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22233#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22234#L769 assume 1 == ~t9_pc~0; 22771#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21754#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21755#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22538#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 22990#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23071#L788 assume !(1 == ~t10_pc~0); 22646#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22647#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22879#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22880#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 21906#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21907#L807 assume 1 == ~t11_pc~0; 23080#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22658#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22811#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23222#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 23327#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23170#L826 assume !(1 == ~t12_pc~0); 22304#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22305#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22831#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23262#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 22462#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22371#L1344 assume !(1 == ~M_E~0); 22372#L1344-2 assume !(1 == ~T1_E~0); 22513#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22686#L1354-1 assume !(1 == ~T3_E~0); 22687#L1359-1 assume !(1 == ~T4_E~0); 23060#L1364-1 assume !(1 == ~T5_E~0); 22014#L1369-1 assume !(1 == ~T6_E~0); 22015#L1374-1 assume !(1 == ~T7_E~0); 22693#L1379-1 assume !(1 == ~T8_E~0); 22694#L1384-1 assume !(1 == ~T9_E~0); 22755#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23201#L1394-1 assume !(1 == ~T11_E~0); 23202#L1399-1 assume !(1 == ~T12_E~0); 23281#L1404-1 assume !(1 == ~E_M~0); 22133#L1409-1 assume !(1 == ~E_1~0); 22134#L1414-1 assume !(1 == ~E_2~0); 22971#L1419-1 assume !(1 == ~E_3~0); 21767#L1424-1 assume !(1 == ~E_4~0); 21768#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22705#L1434-1 assume !(1 == ~E_6~0); 23220#L1439-1 assume !(1 == ~E_7~0); 21822#L1444-1 assume !(1 == ~E_8~0); 21823#L1449-1 assume !(1 == ~E_9~0); 22238#L1454-1 assume !(1 == ~E_10~0); 22239#L1459-1 assume !(1 == ~E_11~0); 22789#L1464-1 assume !(1 == ~E_12~0); 22790#L1469-1 assume { :end_inline_reset_delta_events } true; 22837#L1815-2 [2022-07-14 16:03:17,119 INFO L754 eck$LassoCheckResult]: Loop: 22837#L1815-2 assume !false; 22991#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22660#L1181 assume !false; 22731#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22683#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21541#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22270#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22821#L1008 assume !(0 != eval_~tmp~0#1); 22822#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21762#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21763#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23321#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22788#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21894#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21895#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22485#L1226-3 assume !(0 == ~T5_E~0); 21958#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21959#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22271#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23259#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23161#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22897#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21918#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21919#L1266-3 assume !(0 == ~E_M~0); 21956#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21957#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22429#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22430#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22967#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22968#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23310#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23278#L1306-3 assume !(0 == ~E_8~0); 22554#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21840#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21841#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21920#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22653#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22978#L598-42 assume !(1 == ~m_pc~0); 22979#L598-44 is_master_triggered_~__retres1~0#1 := 0; 23093#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21996#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21997#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 23279#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22709#L617-42 assume 1 == ~t1_pc~0; 22482#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22346#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22347#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22761#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22061#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22062#L636-42 assume !(1 == ~t2_pc~0); 22524#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22525#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22875#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22876#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23056#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22915#L655-42 assume !(1 == ~t3_pc~0); 22497#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22498#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22131#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22132#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23185#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23130#L674-42 assume !(1 == ~t4_pc~0); 22904#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 22826#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21715#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21716#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22630#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22631#L693-42 assume 1 == ~t5_pc~0; 22886#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22887#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22946#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22941#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22942#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22245#L712-42 assume !(1 == ~t6_pc~0); 22246#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 22572#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22780#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22781#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22354#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22355#L731-42 assume !(1 == ~t7_pc~0); 22053#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22054#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23121#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22262#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22263#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21966#L750-42 assume !(1 == ~t8_pc~0); 21968#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 22541#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22964#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21859#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21860#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22629#L769-42 assume 1 == ~t9_pc~0; 22450#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22451#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23135#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23200#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 22063#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22064#L788-42 assume 1 == ~t10_pc~0; 22637#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22851#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22581#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22582#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23319#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23296#L807-42 assume !(1 == ~t11_pc~0); 21667#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21668#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21806#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21807#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21809#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22058#L826-42 assume 1 == ~t12_pc~0; 22059#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22251#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23043#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22048#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22049#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22900#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22901#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22827#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22208#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22209#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22841#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23299#L1369-3 assume !(1 == ~T6_E~0); 23219#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21973#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21974#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22206#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22207#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22505#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23228#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23191#L1409-3 assume !(1 == ~E_1~0); 23192#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23257#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23037#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21874#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21875#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22840#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21814#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21815#L1449-3 assume !(1 == ~E_9~0); 21924#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22833#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22834#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 23216#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22714#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21713#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21714#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22330#L1834 assume !(0 == start_simulation_~tmp~3#1); 22950#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22973#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22407#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22586#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 22798#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23206#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21699#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21700#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 22837#L1815-2 [2022-07-14 16:03:17,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,120 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-07-14 16:03:17,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111595340] [2022-07-14 16:03:17,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111595340] [2022-07-14 16:03:17,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111595340] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,139 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,139 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411221680] [2022-07-14 16:03:17,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,140 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,140 INFO L85 PathProgramCache]: Analyzing trace with hash -1085730025, now seen corresponding path program 1 times [2022-07-14 16:03:17,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58760698] [2022-07-14 16:03:17,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,166 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58760698] [2022-07-14 16:03:17,166 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58760698] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,166 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,166 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689772058] [2022-07-14 16:03:17,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,167 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,168 INFO L87 Difference]: Start difference. First operand 1790 states and 2650 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,185 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2022-07-14 16:03:17,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2649 transitions. [2022-07-14 16:03:17,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2649 transitions. [2022-07-14 16:03:17,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2649 transitions. [2022-07-14 16:03:17,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,200 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-07-14 16:03:17,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2649 transitions. [2022-07-14 16:03:17,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2649 transitions. [2022-07-14 16:03:17,220 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-07-14 16:03:17,220 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-07-14 16:03:17,220 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:03:17,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2649 transitions. [2022-07-14 16:03:17,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,226 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,226 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,226 INFO L752 eck$LassoCheckResult]: Stem: 25969#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25395#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25363#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25364#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 26625#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25672#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25125#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25126#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26397#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26536#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26902#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26903#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25884#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25885#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26423#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26343#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26344#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26496#L1206 assume !(0 == ~M_E~0); 25861#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25862#L1211-1 assume !(0 == ~T2_E~0); 26755#L1216-1 assume !(0 == ~T3_E~0); 25654#L1221-1 assume !(0 == ~T4_E~0); 25655#L1226-1 assume !(0 == ~T5_E~0); 25317#L1231-1 assume !(0 == ~T6_E~0); 25318#L1236-1 assume !(0 == ~T7_E~0); 26786#L1241-1 assume !(0 == ~T8_E~0); 25716#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25717#L1251-1 assume !(0 == ~T10_E~0); 25937#L1256-1 assume !(0 == ~T11_E~0); 25137#L1261-1 assume !(0 == ~T12_E~0); 25138#L1266-1 assume !(0 == ~E_M~0); 26889#L1271-1 assume !(0 == ~E_1~0); 26524#L1276-1 assume !(0 == ~E_2~0); 26525#L1281-1 assume !(0 == ~E_3~0); 26450#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1291-1 assume !(0 == ~E_5~0); 25559#L1296-1 assume !(0 == ~E_6~0); 26265#L1301-1 assume !(0 == ~E_7~0); 26266#L1306-1 assume !(0 == ~E_8~0); 26698#L1311-1 assume !(0 == ~E_9~0); 25519#L1316-1 assume !(0 == ~E_10~0); 25520#L1321-1 assume !(0 == ~E_11~0); 26282#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25383#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25384#L598 assume 1 == ~m_pc~0; 25443#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25444#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26768#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26860#L1497 assume !(0 != activate_threads_~tmp~1#1); 26861#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26817#L617 assume !(1 == ~t1_pc~0); 25739#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25740#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25599#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25600#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26360#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26361#L636 assume 1 == ~t2_pc~0; 25708#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25709#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25539#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25540#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 26396#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26059#L655 assume !(1 == ~t3_pc~0); 26060#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26773#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25413#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25414#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 26890#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26891#L674 assume 1 == ~t4_pc~0; 25233#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25234#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26531#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25541#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 25542#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26056#L693 assume !(1 == ~t5_pc~0); 26219#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25864#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25865#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26700#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 25949#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25886#L712 assume 1 == ~t6_pc~0; 25887#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26314#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26315#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26601#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 26412#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26410#L731 assume 1 == ~t7_pc~0; 25387#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25388#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25582#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26519#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 26638#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25497#L750 assume !(1 == ~t8_pc~0); 25168#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25167#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25683#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26713#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25820#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25821#L769 assume 1 == ~t9_pc~0; 26358#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25341#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25342#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26125#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 26577#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26658#L788 assume !(1 == ~t10_pc~0); 26233#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26234#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26466#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26467#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 25493#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25494#L807 assume 1 == ~t11_pc~0; 26667#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26245#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26398#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26809#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 26914#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26757#L826 assume !(1 == ~t12_pc~0); 25889#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25890#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26418#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26849#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 26049#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25958#L1344 assume !(1 == ~M_E~0); 25959#L1344-2 assume !(1 == ~T1_E~0); 26100#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26273#L1354-1 assume !(1 == ~T3_E~0); 26274#L1359-1 assume !(1 == ~T4_E~0); 26647#L1364-1 assume !(1 == ~T5_E~0); 25601#L1369-1 assume !(1 == ~T6_E~0); 25602#L1374-1 assume !(1 == ~T7_E~0); 26280#L1379-1 assume !(1 == ~T8_E~0); 26281#L1384-1 assume !(1 == ~T9_E~0); 26342#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26788#L1394-1 assume !(1 == ~T11_E~0); 26789#L1399-1 assume !(1 == ~T12_E~0); 26868#L1404-1 assume !(1 == ~E_M~0); 25720#L1409-1 assume !(1 == ~E_1~0); 25721#L1414-1 assume !(1 == ~E_2~0); 26558#L1419-1 assume !(1 == ~E_3~0); 25354#L1424-1 assume !(1 == ~E_4~0); 25355#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26289#L1434-1 assume !(1 == ~E_6~0); 26807#L1439-1 assume !(1 == ~E_7~0); 25409#L1444-1 assume !(1 == ~E_8~0); 25410#L1449-1 assume !(1 == ~E_9~0); 25825#L1454-1 assume !(1 == ~E_10~0); 25826#L1459-1 assume !(1 == ~E_11~0); 26376#L1464-1 assume !(1 == ~E_12~0); 26377#L1469-1 assume { :end_inline_reset_delta_events } true; 26424#L1815-2 [2022-07-14 16:03:17,227 INFO L754 eck$LassoCheckResult]: Loop: 26424#L1815-2 assume !false; 26578#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26247#L1181 assume !false; 26318#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26270#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25128#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25857#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26408#L1008 assume !(0 != eval_~tmp~0#1); 26409#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25349#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25350#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26908#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26375#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25481#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25482#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26072#L1226-3 assume !(0 == ~T5_E~0); 25545#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25546#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25858#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26846#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26748#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26484#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25503#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25504#L1266-3 assume !(0 == ~E_M~0); 25543#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25544#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26016#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26017#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26554#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26555#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26897#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26865#L1306-3 assume !(0 == ~E_8~0); 26141#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25427#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25428#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25505#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26240#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26565#L598-42 assume !(1 == ~m_pc~0); 26566#L598-44 is_master_triggered_~__retres1~0#1 := 0; 26680#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25583#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25584#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 26866#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26296#L617-42 assume 1 == ~t1_pc~0; 26069#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25933#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25934#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26348#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25648#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25649#L636-42 assume !(1 == ~t2_pc~0); 26112#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26113#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26463#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26464#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26643#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26505#L655-42 assume !(1 == ~t3_pc~0); 26089#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26090#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25718#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25719#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26772#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26717#L674-42 assume !(1 == ~t4_pc~0); 26491#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 26413#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25302#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25303#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26217#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26218#L693-42 assume 1 == ~t5_pc~0; 26476#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26477#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26534#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26529#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26530#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25832#L712-42 assume !(1 == ~t6_pc~0); 25833#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26160#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26367#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26368#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25941#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25942#L731-42 assume !(1 == ~t7_pc~0); 25637#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25638#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26708#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25849#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25850#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25550#L750-42 assume !(1 == ~t8_pc~0); 25552#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 26128#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26551#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25446#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25447#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26216#L769-42 assume 1 == ~t9_pc~0; 26036#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26037#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26722#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26787#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 25650#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25651#L788-42 assume 1 == ~t10_pc~0; 26224#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26435#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26168#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26169#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26906#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26882#L807-42 assume !(1 == ~t11_pc~0); 25254#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25255#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25393#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25394#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25396#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25645#L826-42 assume 1 == ~t12_pc~0; 25646#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25838#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26630#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25635#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25636#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26487#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26488#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26414#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25795#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25796#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26428#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26886#L1369-3 assume !(1 == ~T6_E~0); 26806#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25560#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25561#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25793#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25794#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26092#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26815#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26778#L1409-3 assume !(1 == ~E_1~0); 26779#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26844#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26624#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25461#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25462#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26427#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25399#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25400#L1449-3 assume !(1 == ~E_9~0); 25511#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26420#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26421#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26803#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26301#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25300#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25301#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25917#L1834 assume !(0 == start_simulation_~tmp~3#1); 26537#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26560#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25994#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26173#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26385#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26793#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25286#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25287#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 26424#L1815-2 [2022-07-14 16:03:17,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,227 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-07-14 16:03:17,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284791825] [2022-07-14 16:03:17,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,247 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284791825] [2022-07-14 16:03:17,247 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284791825] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,247 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,247 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618108193] [2022-07-14 16:03:17,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,248 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1085730025, now seen corresponding path program 2 times [2022-07-14 16:03:17,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602459357] [2022-07-14 16:03:17,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1602459357] [2022-07-14 16:03:17,275 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1602459357] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,275 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,298 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98616543] [2022-07-14 16:03:17,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,299 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,299 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,299 INFO L87 Difference]: Start difference. First operand 1790 states and 2649 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,320 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2022-07-14 16:03:17,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2648 transitions. [2022-07-14 16:03:17,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2648 transitions. [2022-07-14 16:03:17,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2648 transitions. [2022-07-14 16:03:17,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,336 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-07-14 16:03:17,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2648 transitions. [2022-07-14 16:03:17,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2648 transitions. [2022-07-14 16:03:17,363 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-07-14 16:03:17,363 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-07-14 16:03:17,363 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:03:17,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2648 transitions. [2022-07-14 16:03:17,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,368 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,368 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,368 INFO L752 eck$LassoCheckResult]: Stem: 29556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28980#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28950#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28951#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 30212#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29259#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28712#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28713#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29984#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30123#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30489#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30490#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29469#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29470#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30010#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29930#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29931#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30083#L1206 assume !(0 == ~M_E~0); 29448#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29449#L1211-1 assume !(0 == ~T2_E~0); 30342#L1216-1 assume !(0 == ~T3_E~0); 29241#L1221-1 assume !(0 == ~T4_E~0); 29242#L1226-1 assume !(0 == ~T5_E~0); 28904#L1231-1 assume !(0 == ~T6_E~0); 28905#L1236-1 assume !(0 == ~T7_E~0); 30373#L1241-1 assume !(0 == ~T8_E~0); 29303#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29304#L1251-1 assume !(0 == ~T10_E~0); 29524#L1256-1 assume !(0 == ~T11_E~0); 28724#L1261-1 assume !(0 == ~T12_E~0); 28725#L1266-1 assume !(0 == ~E_M~0); 30476#L1271-1 assume !(0 == ~E_1~0); 30111#L1276-1 assume !(0 == ~E_2~0); 30112#L1281-1 assume !(0 == ~E_3~0); 30037#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29145#L1291-1 assume !(0 == ~E_5~0); 29146#L1296-1 assume !(0 == ~E_6~0); 29852#L1301-1 assume !(0 == ~E_7~0); 29853#L1306-1 assume !(0 == ~E_8~0); 30285#L1311-1 assume !(0 == ~E_9~0); 29106#L1316-1 assume !(0 == ~E_10~0); 29107#L1321-1 assume !(0 == ~E_11~0); 29869#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28970#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28971#L598 assume 1 == ~m_pc~0; 29030#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29031#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30355#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30447#L1497 assume !(0 != activate_threads_~tmp~1#1); 30448#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30404#L617 assume !(1 == ~t1_pc~0); 29326#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29327#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29186#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29187#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29947#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29948#L636 assume 1 == ~t2_pc~0; 29295#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29296#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29126#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29127#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 29983#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29646#L655 assume !(1 == ~t3_pc~0); 29647#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30360#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29000#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29001#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 30477#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30478#L674 assume 1 == ~t4_pc~0; 28820#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28821#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30118#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29128#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 29129#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29643#L693 assume !(1 == ~t5_pc~0); 29806#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29450#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29451#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30287#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 29536#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29473#L712 assume 1 == ~t6_pc~0; 29474#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29901#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29902#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30188#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 29999#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29997#L731 assume 1 == ~t7_pc~0; 28974#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28975#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29169#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30106#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 30225#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29084#L750 assume !(1 == ~t8_pc~0); 28755#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28754#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29270#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30300#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29407#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29408#L769 assume 1 == ~t9_pc~0; 29945#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28928#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28929#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29712#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 30164#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30245#L788 assume !(1 == ~t10_pc~0); 29820#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29821#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30052#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30053#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 29080#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29081#L807 assume 1 == ~t11_pc~0; 30254#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29832#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29985#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30396#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 30501#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30344#L826 assume !(1 == ~t12_pc~0); 29476#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29477#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30005#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30436#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 29636#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29545#L1344 assume !(1 == ~M_E~0); 29546#L1344-2 assume !(1 == ~T1_E~0); 29687#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29859#L1354-1 assume !(1 == ~T3_E~0); 29860#L1359-1 assume !(1 == ~T4_E~0); 30234#L1364-1 assume !(1 == ~T5_E~0); 29188#L1369-1 assume !(1 == ~T6_E~0); 29189#L1374-1 assume !(1 == ~T7_E~0); 29865#L1379-1 assume !(1 == ~T8_E~0); 29866#L1384-1 assume !(1 == ~T9_E~0); 29929#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30375#L1394-1 assume !(1 == ~T11_E~0); 30376#L1399-1 assume !(1 == ~T12_E~0); 30455#L1404-1 assume !(1 == ~E_M~0); 29307#L1409-1 assume !(1 == ~E_1~0); 29308#L1414-1 assume !(1 == ~E_2~0); 30145#L1419-1 assume !(1 == ~E_3~0); 28941#L1424-1 assume !(1 == ~E_4~0); 28942#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29876#L1434-1 assume !(1 == ~E_6~0); 30394#L1439-1 assume !(1 == ~E_7~0); 28996#L1444-1 assume !(1 == ~E_8~0); 28997#L1449-1 assume !(1 == ~E_9~0); 29412#L1454-1 assume !(1 == ~E_10~0); 29413#L1459-1 assume !(1 == ~E_11~0); 29963#L1464-1 assume !(1 == ~E_12~0); 29964#L1469-1 assume { :end_inline_reset_delta_events } true; 30011#L1815-2 [2022-07-14 16:03:17,369 INFO L754 eck$LassoCheckResult]: Loop: 30011#L1815-2 assume !false; 30165#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29834#L1181 assume !false; 29905#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29857#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28715#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29444#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29995#L1008 assume !(0 != eval_~tmp~0#1); 29996#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28934#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28935#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30495#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29962#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29068#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29069#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29659#L1226-3 assume !(0 == ~T5_E~0); 29132#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29133#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29445#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30432#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30335#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30071#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29090#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29091#L1266-3 assume !(0 == ~E_M~0); 29130#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29131#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29603#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29604#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30141#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30142#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30484#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30452#L1306-3 assume !(0 == ~E_8~0); 29728#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29014#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29015#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29092#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29827#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30152#L598-42 assume !(1 == ~m_pc~0); 30153#L598-44 is_master_triggered_~__retres1~0#1 := 0; 30267#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29170#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29171#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 30453#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29883#L617-42 assume 1 == ~t1_pc~0; 29655#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29520#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29521#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29935#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29235#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29236#L636-42 assume !(1 == ~t2_pc~0); 29699#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29700#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30050#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30051#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30230#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30092#L655-42 assume !(1 == ~t3_pc~0); 29672#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 29673#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29305#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29306#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30359#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30304#L674-42 assume 1 == ~t4_pc~0; 30305#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30000#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28889#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28890#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29804#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29805#L693-42 assume 1 == ~t5_pc~0; 30060#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30061#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30121#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30116#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30117#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29419#L712-42 assume !(1 == ~t6_pc~0); 29420#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29746#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29954#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29955#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29528#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29529#L731-42 assume 1 == ~t7_pc~0; 29392#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29228#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30295#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29436#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29437#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29140#L750-42 assume 1 == ~t8_pc~0; 29141#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29715#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30138#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29033#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29034#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29803#L769-42 assume 1 == ~t9_pc~0; 29625#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29626#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30309#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30374#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 29237#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29238#L788-42 assume 1 == ~t10_pc~0; 29811#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30025#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29755#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29756#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30493#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30471#L807-42 assume 1 == ~t11_pc~0; 30160#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28842#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28981#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28982#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28983#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29232#L826-42 assume 1 == ~t12_pc~0; 29233#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29425#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30217#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29222#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29223#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30074#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30075#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30001#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29382#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29383#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30015#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30473#L1369-3 assume !(1 == ~T6_E~0); 30393#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29147#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29148#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29380#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29381#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29679#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30402#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30365#L1409-3 assume !(1 == ~E_1~0); 30366#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30431#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30211#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29048#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29049#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30014#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28988#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28989#L1449-3 assume !(1 == ~E_9~0); 29098#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30008#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30009#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30390#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29888#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28887#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28888#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29504#L1834 assume !(0 == start_simulation_~tmp~3#1); 30124#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30147#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29582#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29760#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 29972#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30380#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28873#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28874#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 30011#L1815-2 [2022-07-14 16:03:17,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,369 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-07-14 16:03:17,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388797970] [2022-07-14 16:03:17,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388797970] [2022-07-14 16:03:17,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388797970] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,389 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113984307] [2022-07-14 16:03:17,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,390 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 2 times [2022-07-14 16:03:17,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891613874] [2022-07-14 16:03:17,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891613874] [2022-07-14 16:03:17,418 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891613874] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395638554] [2022-07-14 16:03:17,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,419 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,420 INFO L87 Difference]: Start difference. First operand 1790 states and 2648 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,438 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2022-07-14 16:03:17,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2647 transitions. [2022-07-14 16:03:17,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2647 transitions. [2022-07-14 16:03:17,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2647 transitions. [2022-07-14 16:03:17,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,453 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-07-14 16:03:17,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2647 transitions. [2022-07-14 16:03:17,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2647 transitions. [2022-07-14 16:03:17,473 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-07-14 16:03:17,473 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-07-14 16:03:17,473 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:03:17,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2647 transitions. [2022-07-14 16:03:17,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,478 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,478 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,478 INFO L752 eck$LassoCheckResult]: Stem: 33143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32567#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32537#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32538#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 33799#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32846#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32299#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32300#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33571#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33710#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34076#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34077#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33056#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33057#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33597#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33517#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33518#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33670#L1206 assume !(0 == ~M_E~0); 33035#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33036#L1211-1 assume !(0 == ~T2_E~0); 33929#L1216-1 assume !(0 == ~T3_E~0); 32828#L1221-1 assume !(0 == ~T4_E~0); 32829#L1226-1 assume !(0 == ~T5_E~0); 32491#L1231-1 assume !(0 == ~T6_E~0); 32492#L1236-1 assume !(0 == ~T7_E~0); 33960#L1241-1 assume !(0 == ~T8_E~0); 32890#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32891#L1251-1 assume !(0 == ~T10_E~0); 33111#L1256-1 assume !(0 == ~T11_E~0); 32311#L1261-1 assume !(0 == ~T12_E~0); 32312#L1266-1 assume !(0 == ~E_M~0); 34063#L1271-1 assume !(0 == ~E_1~0); 33698#L1276-1 assume !(0 == ~E_2~0); 33699#L1281-1 assume !(0 == ~E_3~0); 33624#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 32732#L1291-1 assume !(0 == ~E_5~0); 32733#L1296-1 assume !(0 == ~E_6~0); 33439#L1301-1 assume !(0 == ~E_7~0); 33440#L1306-1 assume !(0 == ~E_8~0); 33872#L1311-1 assume !(0 == ~E_9~0); 32693#L1316-1 assume !(0 == ~E_10~0); 32694#L1321-1 assume !(0 == ~E_11~0); 33456#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32557#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32558#L598 assume 1 == ~m_pc~0; 32617#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32618#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33942#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34034#L1497 assume !(0 != activate_threads_~tmp~1#1); 34035#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33991#L617 assume !(1 == ~t1_pc~0); 32913#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32914#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32773#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32774#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33534#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33535#L636 assume 1 == ~t2_pc~0; 32882#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32883#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32713#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32714#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 33570#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33233#L655 assume !(1 == ~t3_pc~0); 33234#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33947#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32587#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32588#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 34064#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34065#L674 assume 1 == ~t4_pc~0; 32407#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32408#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33705#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32715#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 32716#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33230#L693 assume !(1 == ~t5_pc~0); 33393#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33037#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33038#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33874#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 33123#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33060#L712 assume 1 == ~t6_pc~0; 33061#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33488#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33489#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33775#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 33586#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33584#L731 assume 1 == ~t7_pc~0; 32561#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32562#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32756#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33693#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 33812#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32671#L750 assume !(1 == ~t8_pc~0); 32342#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32341#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32857#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33887#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32994#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32995#L769 assume 1 == ~t9_pc~0; 33530#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32515#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32516#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33299#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 33751#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33832#L788 assume !(1 == ~t10_pc~0); 33407#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33408#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33639#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33640#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 32667#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32668#L807 assume 1 == ~t11_pc~0; 33841#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33419#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33572#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33983#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 34088#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33931#L826 assume !(1 == ~t12_pc~0); 33063#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33064#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33592#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34023#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 33223#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33132#L1344 assume !(1 == ~M_E~0); 33133#L1344-2 assume !(1 == ~T1_E~0); 33274#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33446#L1354-1 assume !(1 == ~T3_E~0); 33447#L1359-1 assume !(1 == ~T4_E~0); 33821#L1364-1 assume !(1 == ~T5_E~0); 32775#L1369-1 assume !(1 == ~T6_E~0); 32776#L1374-1 assume !(1 == ~T7_E~0); 33452#L1379-1 assume !(1 == ~T8_E~0); 33453#L1384-1 assume !(1 == ~T9_E~0); 33516#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33962#L1394-1 assume !(1 == ~T11_E~0); 33963#L1399-1 assume !(1 == ~T12_E~0); 34042#L1404-1 assume !(1 == ~E_M~0); 32894#L1409-1 assume !(1 == ~E_1~0); 32895#L1414-1 assume !(1 == ~E_2~0); 33732#L1419-1 assume !(1 == ~E_3~0); 32528#L1424-1 assume !(1 == ~E_4~0); 32529#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33463#L1434-1 assume !(1 == ~E_6~0); 33981#L1439-1 assume !(1 == ~E_7~0); 32583#L1444-1 assume !(1 == ~E_8~0); 32584#L1449-1 assume !(1 == ~E_9~0); 32999#L1454-1 assume !(1 == ~E_10~0); 33000#L1459-1 assume !(1 == ~E_11~0); 33550#L1464-1 assume !(1 == ~E_12~0); 33551#L1469-1 assume { :end_inline_reset_delta_events } true; 33598#L1815-2 [2022-07-14 16:03:17,478 INFO L754 eck$LassoCheckResult]: Loop: 33598#L1815-2 assume !false; 33752#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33421#L1181 assume !false; 33492#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33444#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32302#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33031#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33582#L1008 assume !(0 != eval_~tmp~0#1); 33583#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32521#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32522#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34082#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33549#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32655#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32656#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33246#L1226-3 assume !(0 == ~T5_E~0); 32719#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32720#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33032#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34019#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33922#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33658#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32677#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32678#L1266-3 assume !(0 == ~E_M~0); 32717#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32718#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33190#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33191#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33728#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33729#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34071#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34039#L1306-3 assume !(0 == ~E_8~0); 33315#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32601#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32602#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32679#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33414#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33739#L598-42 assume !(1 == ~m_pc~0); 33740#L598-44 is_master_triggered_~__retres1~0#1 := 0; 33854#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32757#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32758#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 34040#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33470#L617-42 assume 1 == ~t1_pc~0; 33242#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33107#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33108#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33522#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32822#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32823#L636-42 assume !(1 == ~t2_pc~0); 33286#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33287#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33637#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33638#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33817#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33679#L655-42 assume 1 == ~t3_pc~0; 33680#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33260#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32892#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32893#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33946#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33891#L674-42 assume !(1 == ~t4_pc~0); 33665#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 33587#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32476#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32477#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33391#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33392#L693-42 assume !(1 == ~t5_pc~0); 33649#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33648#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33708#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33703#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33704#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33006#L712-42 assume 1 == ~t6_pc~0; 33008#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33333#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33541#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33542#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33115#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33116#L731-42 assume 1 == ~t7_pc~0; 32979#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32815#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33882#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33023#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33024#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32727#L750-42 assume 1 == ~t8_pc~0; 32728#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33302#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33725#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32620#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32621#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33390#L769-42 assume 1 == ~t9_pc~0; 33212#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33213#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33896#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33961#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 32824#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32825#L788-42 assume 1 == ~t10_pc~0; 33398#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33612#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33342#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33343#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34080#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34058#L807-42 assume 1 == ~t11_pc~0; 33747#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32429#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32568#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32569#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32570#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32819#L826-42 assume 1 == ~t12_pc~0; 32820#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33012#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33804#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32809#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32810#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33661#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33662#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33588#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32969#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32970#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33602#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34060#L1369-3 assume !(1 == ~T6_E~0); 33980#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32734#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32735#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32967#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32968#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33266#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33989#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33952#L1409-3 assume !(1 == ~E_1~0); 33953#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34018#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33798#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32635#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32636#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33601#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32575#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32576#L1449-3 assume !(1 == ~E_9~0); 32685#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33595#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33596#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33977#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33475#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32474#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32475#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33091#L1834 assume !(0 == start_simulation_~tmp~3#1); 33711#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33734#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33168#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33347#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33559#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33967#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32460#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32461#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 33598#L1815-2 [2022-07-14 16:03:17,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-07-14 16:03:17,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911162897] [2022-07-14 16:03:17,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911162897] [2022-07-14 16:03:17,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911162897] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942261951] [2022-07-14 16:03:17,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,501 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1098284653, now seen corresponding path program 1 times [2022-07-14 16:03:17,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161509205] [2022-07-14 16:03:17,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161509205] [2022-07-14 16:03:17,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161509205] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,531 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498731318] [2022-07-14 16:03:17,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,531 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,532 INFO L87 Difference]: Start difference. First operand 1790 states and 2647 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,549 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2022-07-14 16:03:17,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2646 transitions. [2022-07-14 16:03:17,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2646 transitions. [2022-07-14 16:03:17,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2646 transitions. [2022-07-14 16:03:17,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,587 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-07-14 16:03:17,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2646 transitions. [2022-07-14 16:03:17,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2646 transitions. [2022-07-14 16:03:17,607 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-07-14 16:03:17,607 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-07-14 16:03:17,607 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:03:17,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2646 transitions. [2022-07-14 16:03:17,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,613 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,613 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,613 INFO L752 eck$LassoCheckResult]: Stem: 36730#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36731#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36154#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36124#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36125#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 37386#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36433#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35886#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35887#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37158#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37297#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37663#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37664#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36643#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36644#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37184#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37104#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37105#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37257#L1206 assume !(0 == ~M_E~0); 36622#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36623#L1211-1 assume !(0 == ~T2_E~0); 37516#L1216-1 assume !(0 == ~T3_E~0); 36415#L1221-1 assume !(0 == ~T4_E~0); 36416#L1226-1 assume !(0 == ~T5_E~0); 36078#L1231-1 assume !(0 == ~T6_E~0); 36079#L1236-1 assume !(0 == ~T7_E~0); 37547#L1241-1 assume !(0 == ~T8_E~0); 36477#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36478#L1251-1 assume !(0 == ~T10_E~0); 36698#L1256-1 assume !(0 == ~T11_E~0); 35898#L1261-1 assume !(0 == ~T12_E~0); 35899#L1266-1 assume !(0 == ~E_M~0); 37650#L1271-1 assume !(0 == ~E_1~0); 37285#L1276-1 assume !(0 == ~E_2~0); 37286#L1281-1 assume !(0 == ~E_3~0); 37211#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 36319#L1291-1 assume !(0 == ~E_5~0); 36320#L1296-1 assume !(0 == ~E_6~0); 37026#L1301-1 assume !(0 == ~E_7~0); 37027#L1306-1 assume !(0 == ~E_8~0); 37459#L1311-1 assume !(0 == ~E_9~0); 36280#L1316-1 assume !(0 == ~E_10~0); 36281#L1321-1 assume !(0 == ~E_11~0); 37043#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36144#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36145#L598 assume 1 == ~m_pc~0; 36204#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36205#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37529#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37621#L1497 assume !(0 != activate_threads_~tmp~1#1); 37622#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37578#L617 assume !(1 == ~t1_pc~0); 36500#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36501#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36360#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36361#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37121#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37122#L636 assume 1 == ~t2_pc~0; 36469#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36470#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36300#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36301#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 37157#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36820#L655 assume !(1 == ~t3_pc~0); 36821#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37534#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36174#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36175#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 37651#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37652#L674 assume 1 == ~t4_pc~0; 35994#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35995#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37292#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36302#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 36303#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36817#L693 assume !(1 == ~t5_pc~0); 36980#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36624#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36625#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37461#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 36710#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36647#L712 assume 1 == ~t6_pc~0; 36648#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37075#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37076#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37362#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 37173#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37171#L731 assume 1 == ~t7_pc~0; 36148#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36149#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36343#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37280#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 37399#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36258#L750 assume !(1 == ~t8_pc~0); 35929#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35928#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36444#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37474#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36581#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36582#L769 assume 1 == ~t9_pc~0; 37117#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36102#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36103#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36886#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 37338#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37419#L788 assume !(1 == ~t10_pc~0); 36994#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36995#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37226#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37227#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 36254#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36255#L807 assume 1 == ~t11_pc~0; 37428#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37006#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37159#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37570#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 37675#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37518#L826 assume !(1 == ~t12_pc~0); 36650#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36651#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37179#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37610#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 36810#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36719#L1344 assume !(1 == ~M_E~0); 36720#L1344-2 assume !(1 == ~T1_E~0); 36861#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37033#L1354-1 assume !(1 == ~T3_E~0); 37034#L1359-1 assume !(1 == ~T4_E~0); 37408#L1364-1 assume !(1 == ~T5_E~0); 36362#L1369-1 assume !(1 == ~T6_E~0); 36363#L1374-1 assume !(1 == ~T7_E~0); 37039#L1379-1 assume !(1 == ~T8_E~0); 37040#L1384-1 assume !(1 == ~T9_E~0); 37103#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37549#L1394-1 assume !(1 == ~T11_E~0); 37550#L1399-1 assume !(1 == ~T12_E~0); 37629#L1404-1 assume !(1 == ~E_M~0); 36481#L1409-1 assume !(1 == ~E_1~0); 36482#L1414-1 assume !(1 == ~E_2~0); 37319#L1419-1 assume !(1 == ~E_3~0); 36115#L1424-1 assume !(1 == ~E_4~0); 36116#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37050#L1434-1 assume !(1 == ~E_6~0); 37568#L1439-1 assume !(1 == ~E_7~0); 36170#L1444-1 assume !(1 == ~E_8~0); 36171#L1449-1 assume !(1 == ~E_9~0); 36586#L1454-1 assume !(1 == ~E_10~0); 36587#L1459-1 assume !(1 == ~E_11~0); 37137#L1464-1 assume !(1 == ~E_12~0); 37138#L1469-1 assume { :end_inline_reset_delta_events } true; 37185#L1815-2 [2022-07-14 16:03:17,614 INFO L754 eck$LassoCheckResult]: Loop: 37185#L1815-2 assume !false; 37339#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37008#L1181 assume !false; 37079#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37031#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35889#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36618#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37169#L1008 assume !(0 != eval_~tmp~0#1); 37170#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36108#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36109#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37669#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37136#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36242#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36243#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36833#L1226-3 assume !(0 == ~T5_E~0); 36306#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36307#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36619#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37606#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37509#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37245#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36264#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36265#L1266-3 assume !(0 == ~E_M~0); 36304#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36305#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36777#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36778#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37315#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37316#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37658#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37626#L1306-3 assume !(0 == ~E_8~0); 36902#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36188#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36189#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36266#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37001#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37326#L598-42 assume 1 == ~m_pc~0; 37328#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37441#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36344#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36345#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 37627#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37057#L617-42 assume 1 == ~t1_pc~0; 36829#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36694#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36695#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37109#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36409#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36410#L636-42 assume !(1 == ~t2_pc~0); 36873#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36874#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37224#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37225#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37404#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37266#L655-42 assume 1 == ~t3_pc~0; 37267#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36847#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36479#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36480#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37533#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37478#L674-42 assume !(1 == ~t4_pc~0); 37252#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 37174#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36063#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36064#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36978#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36979#L693-42 assume 1 == ~t5_pc~0; 37234#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37235#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37295#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37290#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37291#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36593#L712-42 assume !(1 == ~t6_pc~0); 36594#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 36920#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37128#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37129#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36702#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36703#L731-42 assume !(1 == ~t7_pc~0); 36401#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36402#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37469#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36610#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36611#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36314#L750-42 assume 1 == ~t8_pc~0; 36315#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36889#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37312#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36207#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36208#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36977#L769-42 assume !(1 == ~t9_pc~0); 36801#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 36800#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37483#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37548#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 36411#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36412#L788-42 assume 1 == ~t10_pc~0; 36985#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37199#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36929#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36930#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37667#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37645#L807-42 assume 1 == ~t11_pc~0; 37334#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36016#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36155#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36156#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36157#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36406#L826-42 assume 1 == ~t12_pc~0; 36407#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36599#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37391#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36396#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36397#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37248#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37249#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37175#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36556#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36557#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37189#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37647#L1369-3 assume !(1 == ~T6_E~0); 37567#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36321#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36322#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36554#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36555#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36853#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37576#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37539#L1409-3 assume !(1 == ~E_1~0); 37540#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37605#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37385#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36222#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36223#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37188#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36162#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36163#L1449-3 assume !(1 == ~E_9~0); 36272#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37182#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37183#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37564#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37062#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36061#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36062#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36678#L1834 assume !(0 == start_simulation_~tmp~3#1); 37298#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37321#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36755#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36934#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 37146#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37554#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36047#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36048#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 37185#L1815-2 [2022-07-14 16:03:17,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,614 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-07-14 16:03:17,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031090472] [2022-07-14 16:03:17,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031090472] [2022-07-14 16:03:17,634 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031090472] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,634 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,634 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132315392] [2022-07-14 16:03:17,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,635 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,635 INFO L85 PathProgramCache]: Analyzing trace with hash -1147501804, now seen corresponding path program 1 times [2022-07-14 16:03:17,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444467862] [2022-07-14 16:03:17,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444467862] [2022-07-14 16:03:17,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444467862] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,662 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715136451] [2022-07-14 16:03:17,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,662 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,663 INFO L87 Difference]: Start difference. First operand 1790 states and 2646 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,681 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2022-07-14 16:03:17,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2645 transitions. [2022-07-14 16:03:17,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2645 transitions. [2022-07-14 16:03:17,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2645 transitions. [2022-07-14 16:03:17,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,701 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-07-14 16:03:17,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2645 transitions. [2022-07-14 16:03:17,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2645 transitions. [2022-07-14 16:03:17,732 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-07-14 16:03:17,732 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-07-14 16:03:17,732 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:03:17,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2645 transitions. [2022-07-14 16:03:17,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,737 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,737 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,738 INFO L752 eck$LassoCheckResult]: Stem: 40317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39741#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39711#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39712#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 40973#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40020#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39473#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39474#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40745#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40884#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41250#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41251#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40230#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40231#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40771#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40691#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40692#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40844#L1206 assume !(0 == ~M_E~0); 40209#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40210#L1211-1 assume !(0 == ~T2_E~0); 41103#L1216-1 assume !(0 == ~T3_E~0); 40002#L1221-1 assume !(0 == ~T4_E~0); 40003#L1226-1 assume !(0 == ~T5_E~0); 39665#L1231-1 assume !(0 == ~T6_E~0); 39666#L1236-1 assume !(0 == ~T7_E~0); 41134#L1241-1 assume !(0 == ~T8_E~0); 40064#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40065#L1251-1 assume !(0 == ~T10_E~0); 40285#L1256-1 assume !(0 == ~T11_E~0); 39485#L1261-1 assume !(0 == ~T12_E~0); 39486#L1266-1 assume !(0 == ~E_M~0); 41237#L1271-1 assume !(0 == ~E_1~0); 40872#L1276-1 assume !(0 == ~E_2~0); 40873#L1281-1 assume !(0 == ~E_3~0); 40798#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 39906#L1291-1 assume !(0 == ~E_5~0); 39907#L1296-1 assume !(0 == ~E_6~0); 40613#L1301-1 assume !(0 == ~E_7~0); 40614#L1306-1 assume !(0 == ~E_8~0); 41046#L1311-1 assume !(0 == ~E_9~0); 39867#L1316-1 assume !(0 == ~E_10~0); 39868#L1321-1 assume !(0 == ~E_11~0); 40630#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39731#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39732#L598 assume 1 == ~m_pc~0; 39791#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39792#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41116#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41208#L1497 assume !(0 != activate_threads_~tmp~1#1); 41209#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41165#L617 assume !(1 == ~t1_pc~0); 40087#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40088#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39947#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39948#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40708#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40709#L636 assume 1 == ~t2_pc~0; 40056#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40057#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39887#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39888#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 40744#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40407#L655 assume !(1 == ~t3_pc~0); 40408#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41121#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39761#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39762#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 41238#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41239#L674 assume 1 == ~t4_pc~0; 39581#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39582#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40879#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39889#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 39890#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40404#L693 assume !(1 == ~t5_pc~0); 40567#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40211#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40212#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41048#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 40297#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40234#L712 assume 1 == ~t6_pc~0; 40235#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40662#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40663#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40949#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 40760#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40758#L731 assume 1 == ~t7_pc~0; 39735#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39736#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39930#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40867#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 40986#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39845#L750 assume !(1 == ~t8_pc~0); 39516#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39515#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40031#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41061#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40168#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40169#L769 assume 1 == ~t9_pc~0; 40704#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39689#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39690#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40473#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 40925#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41006#L788 assume !(1 == ~t10_pc~0); 40581#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40582#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40813#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40814#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 39841#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39842#L807 assume 1 == ~t11_pc~0; 41015#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40593#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40746#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41157#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 41262#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41105#L826 assume !(1 == ~t12_pc~0); 40237#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40238#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40766#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41197#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 40397#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40306#L1344 assume !(1 == ~M_E~0); 40307#L1344-2 assume !(1 == ~T1_E~0); 40448#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40620#L1354-1 assume !(1 == ~T3_E~0); 40621#L1359-1 assume !(1 == ~T4_E~0); 40995#L1364-1 assume !(1 == ~T5_E~0); 39949#L1369-1 assume !(1 == ~T6_E~0); 39950#L1374-1 assume !(1 == ~T7_E~0); 40626#L1379-1 assume !(1 == ~T8_E~0); 40627#L1384-1 assume !(1 == ~T9_E~0); 40690#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41136#L1394-1 assume !(1 == ~T11_E~0); 41137#L1399-1 assume !(1 == ~T12_E~0); 41216#L1404-1 assume !(1 == ~E_M~0); 40068#L1409-1 assume !(1 == ~E_1~0); 40069#L1414-1 assume !(1 == ~E_2~0); 40906#L1419-1 assume !(1 == ~E_3~0); 39702#L1424-1 assume !(1 == ~E_4~0); 39703#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40637#L1434-1 assume !(1 == ~E_6~0); 41155#L1439-1 assume !(1 == ~E_7~0); 39757#L1444-1 assume !(1 == ~E_8~0); 39758#L1449-1 assume !(1 == ~E_9~0); 40173#L1454-1 assume !(1 == ~E_10~0); 40174#L1459-1 assume !(1 == ~E_11~0); 40724#L1464-1 assume !(1 == ~E_12~0); 40725#L1469-1 assume { :end_inline_reset_delta_events } true; 40772#L1815-2 [2022-07-14 16:03:17,738 INFO L754 eck$LassoCheckResult]: Loop: 40772#L1815-2 assume !false; 40926#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40595#L1181 assume !false; 40666#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40618#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39476#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40205#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40756#L1008 assume !(0 != eval_~tmp~0#1); 40757#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39695#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39696#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41256#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40723#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39829#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39830#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40420#L1226-3 assume !(0 == ~T5_E~0); 39893#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39894#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40206#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41193#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41096#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40832#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39851#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39852#L1266-3 assume !(0 == ~E_M~0); 39891#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39892#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40364#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40365#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40902#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40903#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41245#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41213#L1306-3 assume !(0 == ~E_8~0); 40489#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39775#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39776#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39853#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40588#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40913#L598-42 assume !(1 == ~m_pc~0); 40914#L598-44 is_master_triggered_~__retres1~0#1 := 0; 41028#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39931#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39932#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 41214#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40644#L617-42 assume 1 == ~t1_pc~0; 40416#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40281#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40282#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40696#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39996#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39997#L636-42 assume !(1 == ~t2_pc~0); 40460#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40461#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40811#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40812#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40991#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40853#L655-42 assume !(1 == ~t3_pc~0); 40433#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 40434#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40066#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40067#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41120#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41065#L674-42 assume !(1 == ~t4_pc~0); 40839#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 40761#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39650#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39651#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40565#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40566#L693-42 assume 1 == ~t5_pc~0; 40821#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40822#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40882#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40877#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40878#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40180#L712-42 assume !(1 == ~t6_pc~0); 40181#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 40507#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40715#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40716#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40289#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40290#L731-42 assume !(1 == ~t7_pc~0); 39988#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39989#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41056#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40197#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40198#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39901#L750-42 assume 1 == ~t8_pc~0; 39902#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40476#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40899#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39794#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39795#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40564#L769-42 assume 1 == ~t9_pc~0; 40386#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40387#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41070#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41135#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 39998#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39999#L788-42 assume 1 == ~t10_pc~0; 40572#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40786#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40516#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40517#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41254#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41232#L807-42 assume !(1 == ~t11_pc~0); 39602#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 39603#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39742#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39743#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39744#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39993#L826-42 assume 1 == ~t12_pc~0; 39994#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40186#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40978#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39983#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39984#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40835#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40836#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40762#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40143#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40144#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40776#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41234#L1369-3 assume !(1 == ~T6_E~0); 41154#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39908#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39909#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40141#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40142#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40440#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41163#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41126#L1409-3 assume !(1 == ~E_1~0); 41127#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41192#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40972#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39809#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39810#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40775#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39749#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39750#L1449-3 assume !(1 == ~E_9~0); 39859#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40769#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40770#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41151#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40649#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39648#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39649#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40265#L1834 assume !(0 == start_simulation_~tmp~3#1); 40885#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40908#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40342#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40521#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40733#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41141#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39634#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39635#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 40772#L1815-2 [2022-07-14 16:03:17,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-07-14 16:03:17,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150421575] [2022-07-14 16:03:17,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150421575] [2022-07-14 16:03:17,765 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150421575] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,765 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,765 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260491685] [2022-07-14 16:03:17,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,766 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,766 INFO L85 PathProgramCache]: Analyzing trace with hash 2071608406, now seen corresponding path program 1 times [2022-07-14 16:03:17,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102771264] [2022-07-14 16:03:17,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102771264] [2022-07-14 16:03:17,805 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102771264] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,805 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,805 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3398097] [2022-07-14 16:03:17,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,806 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,807 INFO L87 Difference]: Start difference. First operand 1790 states and 2645 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,826 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2022-07-14 16:03:17,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:17,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2644 transitions. [2022-07-14 16:03:17,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2644 transitions. [2022-07-14 16:03:17,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:17,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:17,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2644 transitions. [2022-07-14 16:03:17,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,840 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-07-14 16:03:17,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2644 transitions. [2022-07-14 16:03:17,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:17,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2644 transitions. [2022-07-14 16:03:17,899 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-07-14 16:03:17,899 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-07-14 16:03:17,899 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:03:17,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2644 transitions. [2022-07-14 16:03:17,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:17,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,907 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,907 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,907 INFO L752 eck$LassoCheckResult]: Stem: 43904#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43328#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43298#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43299#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 44560#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43607#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43060#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43061#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44332#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44471#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44837#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44838#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43817#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43818#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44358#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44278#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44279#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44431#L1206 assume !(0 == ~M_E~0); 43796#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43797#L1211-1 assume !(0 == ~T2_E~0); 44690#L1216-1 assume !(0 == ~T3_E~0); 43589#L1221-1 assume !(0 == ~T4_E~0); 43590#L1226-1 assume !(0 == ~T5_E~0); 43252#L1231-1 assume !(0 == ~T6_E~0); 43253#L1236-1 assume !(0 == ~T7_E~0); 44721#L1241-1 assume !(0 == ~T8_E~0); 43651#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43652#L1251-1 assume !(0 == ~T10_E~0); 43872#L1256-1 assume !(0 == ~T11_E~0); 43072#L1261-1 assume !(0 == ~T12_E~0); 43073#L1266-1 assume !(0 == ~E_M~0); 44824#L1271-1 assume !(0 == ~E_1~0); 44459#L1276-1 assume !(0 == ~E_2~0); 44460#L1281-1 assume !(0 == ~E_3~0); 44385#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 43493#L1291-1 assume !(0 == ~E_5~0); 43494#L1296-1 assume !(0 == ~E_6~0); 44200#L1301-1 assume !(0 == ~E_7~0); 44201#L1306-1 assume !(0 == ~E_8~0); 44633#L1311-1 assume !(0 == ~E_9~0); 43454#L1316-1 assume !(0 == ~E_10~0); 43455#L1321-1 assume !(0 == ~E_11~0); 44217#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43318#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43319#L598 assume 1 == ~m_pc~0; 43378#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43379#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44703#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44795#L1497 assume !(0 != activate_threads_~tmp~1#1); 44796#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44752#L617 assume !(1 == ~t1_pc~0); 43674#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43675#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43534#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43535#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44295#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44296#L636 assume 1 == ~t2_pc~0; 43643#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43644#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43474#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43475#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 44331#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43994#L655 assume !(1 == ~t3_pc~0); 43995#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44708#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43348#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43349#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 44825#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44826#L674 assume 1 == ~t4_pc~0; 43168#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43169#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44466#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43476#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 43477#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43991#L693 assume !(1 == ~t5_pc~0); 44154#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43798#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43799#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44635#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 43884#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43821#L712 assume 1 == ~t6_pc~0; 43822#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44249#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44250#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44536#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 44347#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44345#L731 assume 1 == ~t7_pc~0; 43322#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43323#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43517#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44454#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 44573#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43432#L750 assume !(1 == ~t8_pc~0); 43103#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43102#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43618#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44648#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43755#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43756#L769 assume 1 == ~t9_pc~0; 44291#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43276#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43277#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44060#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 44512#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44593#L788 assume !(1 == ~t10_pc~0); 44168#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44169#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44400#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44401#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 43428#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43429#L807 assume 1 == ~t11_pc~0; 44602#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44180#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44333#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44744#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 44849#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44692#L826 assume !(1 == ~t12_pc~0); 43824#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 43825#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44353#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44784#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 43984#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43893#L1344 assume !(1 == ~M_E~0); 43894#L1344-2 assume !(1 == ~T1_E~0); 44035#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44207#L1354-1 assume !(1 == ~T3_E~0); 44208#L1359-1 assume !(1 == ~T4_E~0); 44582#L1364-1 assume !(1 == ~T5_E~0); 43536#L1369-1 assume !(1 == ~T6_E~0); 43537#L1374-1 assume !(1 == ~T7_E~0); 44213#L1379-1 assume !(1 == ~T8_E~0); 44214#L1384-1 assume !(1 == ~T9_E~0); 44277#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44723#L1394-1 assume !(1 == ~T11_E~0); 44724#L1399-1 assume !(1 == ~T12_E~0); 44803#L1404-1 assume !(1 == ~E_M~0); 43655#L1409-1 assume !(1 == ~E_1~0); 43656#L1414-1 assume !(1 == ~E_2~0); 44493#L1419-1 assume !(1 == ~E_3~0); 43289#L1424-1 assume !(1 == ~E_4~0); 43290#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44224#L1434-1 assume !(1 == ~E_6~0); 44742#L1439-1 assume !(1 == ~E_7~0); 43344#L1444-1 assume !(1 == ~E_8~0); 43345#L1449-1 assume !(1 == ~E_9~0); 43760#L1454-1 assume !(1 == ~E_10~0); 43761#L1459-1 assume !(1 == ~E_11~0); 44311#L1464-1 assume !(1 == ~E_12~0); 44312#L1469-1 assume { :end_inline_reset_delta_events } true; 44359#L1815-2 [2022-07-14 16:03:17,908 INFO L754 eck$LassoCheckResult]: Loop: 44359#L1815-2 assume !false; 44513#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44182#L1181 assume !false; 44253#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44205#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43063#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43792#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44343#L1008 assume !(0 != eval_~tmp~0#1); 44344#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43282#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43283#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44843#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44310#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43416#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43417#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44007#L1226-3 assume !(0 == ~T5_E~0); 43480#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43481#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43793#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44780#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44683#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44419#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43438#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43439#L1266-3 assume !(0 == ~E_M~0); 43478#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43479#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43951#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43952#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44489#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44490#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44832#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44800#L1306-3 assume !(0 == ~E_8~0); 44076#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43362#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43363#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43440#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44175#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44500#L598-42 assume !(1 == ~m_pc~0); 44501#L598-44 is_master_triggered_~__retres1~0#1 := 0; 44615#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43518#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43519#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 44801#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44231#L617-42 assume 1 == ~t1_pc~0; 44003#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43868#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43869#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44283#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43583#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43584#L636-42 assume 1 == ~t2_pc~0; 44785#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44048#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44398#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44399#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44578#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44440#L655-42 assume !(1 == ~t3_pc~0); 44020#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 44021#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43653#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43654#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44707#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44652#L674-42 assume !(1 == ~t4_pc~0); 44426#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 44348#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43237#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43238#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44152#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44153#L693-42 assume 1 == ~t5_pc~0; 44408#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44409#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44469#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44464#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44465#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43767#L712-42 assume !(1 == ~t6_pc~0); 43768#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44094#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44302#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44303#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43876#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43877#L731-42 assume !(1 == ~t7_pc~0); 43575#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43576#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44643#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43784#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43785#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43488#L750-42 assume 1 == ~t8_pc~0; 43489#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44063#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44486#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43381#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43382#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44151#L769-42 assume 1 == ~t9_pc~0; 43973#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43974#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44657#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44722#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 43585#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43586#L788-42 assume !(1 == ~t10_pc~0); 44160#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 44373#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44103#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44104#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44841#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44819#L807-42 assume !(1 == ~t11_pc~0); 43189#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43190#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43329#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43330#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43331#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43580#L826-42 assume 1 == ~t12_pc~0; 43581#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43773#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44565#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43570#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43571#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44422#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44423#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44349#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43730#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43731#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44363#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44821#L1369-3 assume !(1 == ~T6_E~0); 44741#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43495#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43496#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43728#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43729#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44027#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44750#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44713#L1409-3 assume !(1 == ~E_1~0); 44714#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44779#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44559#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43396#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43397#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44362#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43336#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43337#L1449-3 assume !(1 == ~E_9~0); 43446#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44356#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44357#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44738#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44236#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43235#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43236#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43852#L1834 assume !(0 == start_simulation_~tmp~3#1); 44472#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44495#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43929#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44108#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 44320#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44728#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43221#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43222#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 44359#L1815-2 [2022-07-14 16:03:17,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-07-14 16:03:17,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952834312] [2022-07-14 16:03:17,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,938 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952834312] [2022-07-14 16:03:17,938 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952834312] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,938 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,938 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:17,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508507769] [2022-07-14 16:03:17,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,940 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,941 INFO L85 PathProgramCache]: Analyzing trace with hash 2024415830, now seen corresponding path program 1 times [2022-07-14 16:03:17,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791658214] [2022-07-14 16:03:17,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791658214] [2022-07-14 16:03:17,983 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791658214] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,983 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,983 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841282221] [2022-07-14 16:03:17,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,984 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:17,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:17,985 INFO L87 Difference]: Start difference. First operand 1790 states and 2644 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,053 INFO L93 Difference]: Finished difference Result 1790 states and 2639 transitions. [2022-07-14 16:03:18,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:18,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2639 transitions. [2022-07-14 16:03:18,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:18,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2639 transitions. [2022-07-14 16:03:18,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-07-14 16:03:18,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-07-14 16:03:18,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2639 transitions. [2022-07-14 16:03:18,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,070 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-07-14 16:03:18,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2639 transitions. [2022-07-14 16:03:18,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-07-14 16:03:18,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2639 transitions. [2022-07-14 16:03:18,091 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-07-14 16:03:18,091 INFO L374 stractBuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-07-14 16:03:18,091 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:03:18,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2639 transitions. [2022-07-14 16:03:18,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-07-14 16:03:18,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,097 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,097 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,097 INFO L752 eck$LassoCheckResult]: Stem: 47493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 46917#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46890#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46891#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 48147#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47194#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46647#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46648#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47919#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48058#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48424#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48425#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47406#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47407#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47945#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47865#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47866#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48018#L1206 assume !(0 == ~M_E~0); 47383#L1206-2 assume !(0 == ~T1_E~0); 47384#L1211-1 assume !(0 == ~T2_E~0); 48277#L1216-1 assume !(0 == ~T3_E~0); 47176#L1221-1 assume !(0 == ~T4_E~0); 47177#L1226-1 assume !(0 == ~T5_E~0); 46841#L1231-1 assume !(0 == ~T6_E~0); 46842#L1236-1 assume !(0 == ~T7_E~0); 48308#L1241-1 assume !(0 == ~T8_E~0); 47238#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47239#L1251-1 assume !(0 == ~T10_E~0); 47459#L1256-1 assume !(0 == ~T11_E~0); 46659#L1261-1 assume !(0 == ~T12_E~0); 46660#L1266-1 assume !(0 == ~E_M~0); 48411#L1271-1 assume !(0 == ~E_1~0); 48046#L1276-1 assume !(0 == ~E_2~0); 48047#L1281-1 assume !(0 == ~E_3~0); 47974#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47080#L1291-1 assume !(0 == ~E_5~0); 47081#L1296-1 assume !(0 == ~E_6~0); 47787#L1301-1 assume !(0 == ~E_7~0); 47788#L1306-1 assume !(0 == ~E_8~0); 48220#L1311-1 assume !(0 == ~E_9~0); 47041#L1316-1 assume !(0 == ~E_10~0); 47042#L1321-1 assume !(0 == ~E_11~0); 47804#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 46907#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46908#L598 assume 1 == ~m_pc~0; 46965#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46966#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48290#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48382#L1497 assume !(0 != activate_threads_~tmp~1#1); 48383#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48339#L617 assume !(1 == ~t1_pc~0); 47261#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47262#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47121#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47122#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47882#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47883#L636 assume 1 == ~t2_pc~0; 47230#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47231#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47061#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47062#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 47918#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47582#L655 assume !(1 == ~t3_pc~0); 47583#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48295#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46935#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46936#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 48412#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48413#L674 assume 1 == ~t4_pc~0; 46755#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46756#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48053#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47065#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 47066#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47578#L693 assume !(1 == ~t5_pc~0); 47741#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47388#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47389#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48222#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 47471#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47408#L712 assume 1 == ~t6_pc~0; 47409#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47836#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47837#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48123#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 47934#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47932#L731 assume 1 == ~t7_pc~0; 46909#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46910#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47106#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48042#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 48160#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47019#L750 assume !(1 == ~t8_pc~0); 46690#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46689#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47205#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48235#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47342#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47343#L769 assume 1 == ~t9_pc~0; 47880#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46863#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46864#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47647#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 48099#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48180#L788 assume !(1 == ~t10_pc~0); 47755#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47756#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47989#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47990#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 47017#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47018#L807 assume 1 == ~t11_pc~0; 48189#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47767#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47920#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48331#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 48436#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48279#L826 assume !(1 == ~t12_pc~0); 47413#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47414#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47940#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48371#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 47571#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47480#L1344 assume !(1 == ~M_E~0); 47481#L1344-2 assume !(1 == ~T1_E~0); 47622#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47795#L1354-1 assume !(1 == ~T3_E~0); 47796#L1359-1 assume !(1 == ~T4_E~0); 48169#L1364-1 assume !(1 == ~T5_E~0); 47123#L1369-1 assume !(1 == ~T6_E~0); 47124#L1374-1 assume !(1 == ~T7_E~0); 47802#L1379-1 assume !(1 == ~T8_E~0); 47803#L1384-1 assume !(1 == ~T9_E~0); 47864#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48310#L1394-1 assume !(1 == ~T11_E~0); 48311#L1399-1 assume !(1 == ~T12_E~0); 48390#L1404-1 assume !(1 == ~E_M~0); 47242#L1409-1 assume !(1 == ~E_1~0); 47243#L1414-1 assume !(1 == ~E_2~0); 48080#L1419-1 assume !(1 == ~E_3~0); 46876#L1424-1 assume !(1 == ~E_4~0); 46877#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47814#L1434-1 assume !(1 == ~E_6~0); 48329#L1439-1 assume !(1 == ~E_7~0); 46931#L1444-1 assume !(1 == ~E_8~0); 46932#L1449-1 assume !(1 == ~E_9~0); 47347#L1454-1 assume !(1 == ~E_10~0); 47348#L1459-1 assume !(1 == ~E_11~0); 47898#L1464-1 assume !(1 == ~E_12~0); 47899#L1469-1 assume { :end_inline_reset_delta_events } true; 47946#L1815-2 [2022-07-14 16:03:18,098 INFO L754 eck$LassoCheckResult]: Loop: 47946#L1815-2 assume !false; 48100#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47769#L1181 assume !false; 47840#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47792#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46650#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47380#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47930#L1008 assume !(0 != eval_~tmp~0#1); 47931#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46871#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46872#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48430#L1206-5 assume !(0 == ~T1_E~0); 47897#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47003#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47004#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47594#L1226-3 assume !(0 == ~T5_E~0); 47067#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47068#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47379#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48367#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48270#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48006#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47025#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47026#L1266-3 assume !(0 == ~E_M~0); 47063#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47064#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47538#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47539#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48076#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48077#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48419#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48387#L1306-3 assume !(0 == ~E_8~0); 47663#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46949#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46950#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47027#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47761#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48087#L598-42 assume !(1 == ~m_pc~0); 48088#L598-44 is_master_triggered_~__retres1~0#1 := 0; 48202#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47104#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47105#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 48388#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47818#L617-42 assume 1 == ~t1_pc~0; 47590#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47455#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47456#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47870#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47170#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47171#L636-42 assume !(1 == ~t2_pc~0); 47634#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47635#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47985#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47986#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48165#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48027#L655-42 assume !(1 == ~t3_pc~0); 47607#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 47608#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47240#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47241#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48294#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48239#L674-42 assume 1 == ~t4_pc~0; 48240#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47935#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46824#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46825#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47739#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47740#L693-42 assume 1 == ~t5_pc~0; 47995#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47996#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48056#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48051#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48052#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47354#L712-42 assume !(1 == ~t6_pc~0); 47355#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 47681#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47889#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47890#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47463#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47464#L731-42 assume !(1 == ~t7_pc~0); 47162#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 47163#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48230#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47371#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47372#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47075#L750-42 assume 1 == ~t8_pc~0; 47076#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47650#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48073#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46968#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46969#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47738#L769-42 assume 1 == ~t9_pc~0; 47560#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47561#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48244#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48309#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 47172#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47173#L788-42 assume 1 == ~t10_pc~0; 47746#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47960#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47690#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47691#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48428#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48406#L807-42 assume !(1 == ~t11_pc~0); 46776#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 46777#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46915#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46916#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46918#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47167#L826-42 assume 1 == ~t12_pc~0; 47168#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47360#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48152#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47157#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47158#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48009#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48010#L1344-5 assume !(1 == ~T1_E~0); 47936#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47317#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47318#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47950#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48408#L1369-3 assume !(1 == ~T6_E~0); 48328#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47082#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47083#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47315#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47316#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47614#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48337#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48300#L1409-3 assume !(1 == ~E_1~0); 48301#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48366#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48146#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46983#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46984#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47949#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46923#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46924#L1449-3 assume !(1 == ~E_9~0); 47033#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47943#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47944#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48325#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47823#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46822#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46823#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47439#L1834 assume !(0 == start_simulation_~tmp~3#1); 48059#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48082#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47516#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47695#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47907#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48315#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46808#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46809#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 47946#L1815-2 [2022-07-14 16:03:18,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,098 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-07-14 16:03:18,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,099 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742041852] [2022-07-14 16:03:18,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742041852] [2022-07-14 16:03:18,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742041852] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860972480] [2022-07-14 16:03:18,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,137 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,137 INFO L85 PathProgramCache]: Analyzing trace with hash 351618645, now seen corresponding path program 1 times [2022-07-14 16:03:18,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803300511] [2022-07-14 16:03:18,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803300511] [2022-07-14 16:03:18,170 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803300511] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,171 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,171 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674062509] [2022-07-14 16:03:18,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,172 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:18,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:18,173 INFO L87 Difference]: Start difference. First operand 1790 states and 2639 transitions. cyclomatic complexity: 850 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,273 INFO L93 Difference]: Finished difference Result 3324 states and 4886 transitions. [2022-07-14 16:03:18,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:18,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3324 states and 4886 transitions. [2022-07-14 16:03:18,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2022-07-14 16:03:18,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3324 states to 3324 states and 4886 transitions. [2022-07-14 16:03:18,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3324 [2022-07-14 16:03:18,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3324 [2022-07-14 16:03:18,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3324 states and 4886 transitions. [2022-07-14 16:03:18,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,297 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-07-14 16:03:18,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3324 states and 4886 transitions. [2022-07-14 16:03:18,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3324 to 3324. [2022-07-14 16:03:18,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3324 states to 3324 states and 4886 transitions. [2022-07-14 16:03:18,341 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-07-14 16:03:18,341 INFO L374 stractBuchiCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-07-14 16:03:18,341 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:03:18,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3324 states and 4886 transitions. [2022-07-14 16:03:18,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2022-07-14 16:03:18,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,350 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,350 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,350 INFO L752 eck$LassoCheckResult]: Stem: 52619#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52041#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52011#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52012#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 53277#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52318#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51771#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51772#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53046#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53186#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53556#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53557#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52531#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52532#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53072#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52992#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52993#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53146#L1206 assume !(0 == ~M_E~0); 52508#L1206-2 assume !(0 == ~T1_E~0); 52509#L1211-1 assume !(0 == ~T2_E~0); 53408#L1216-1 assume !(0 == ~T3_E~0); 52300#L1221-1 assume !(0 == ~T4_E~0); 52301#L1226-1 assume !(0 == ~T5_E~0); 51965#L1231-1 assume !(0 == ~T6_E~0); 51966#L1236-1 assume !(0 == ~T7_E~0); 53439#L1241-1 assume !(0 == ~T8_E~0); 52362#L1246-1 assume !(0 == ~T9_E~0); 52363#L1251-1 assume !(0 == ~T10_E~0); 52584#L1256-1 assume !(0 == ~T11_E~0); 51783#L1261-1 assume !(0 == ~T12_E~0); 51784#L1266-1 assume !(0 == ~E_M~0); 53543#L1271-1 assume !(0 == ~E_1~0); 53174#L1276-1 assume !(0 == ~E_2~0); 53175#L1281-1 assume !(0 == ~E_3~0); 53102#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 52204#L1291-1 assume !(0 == ~E_5~0); 52205#L1296-1 assume !(0 == ~E_6~0); 52913#L1301-1 assume !(0 == ~E_7~0); 52914#L1306-1 assume !(0 == ~E_8~0); 53350#L1311-1 assume !(0 == ~E_9~0); 52165#L1316-1 assume !(0 == ~E_10~0); 52166#L1321-1 assume !(0 == ~E_11~0); 52930#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52031#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52032#L598 assume 1 == ~m_pc~0; 52089#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52090#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53421#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53514#L1497 assume !(0 != activate_threads_~tmp~1#1); 53515#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53471#L617 assume !(1 == ~t1_pc~0); 52385#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52386#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52245#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52246#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53009#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53010#L636 assume 1 == ~t2_pc~0; 52354#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52355#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52185#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52186#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 53045#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52707#L655 assume !(1 == ~t3_pc~0); 52708#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53426#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52059#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52060#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 53544#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53545#L674 assume 1 == ~t4_pc~0; 51879#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51880#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53181#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52187#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 52188#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52704#L693 assume !(1 == ~t5_pc~0); 52867#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52513#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52514#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53352#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 52596#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52533#L712 assume 1 == ~t6_pc~0; 52534#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52962#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52963#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53253#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 53061#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53059#L731 assume 1 == ~t7_pc~0; 52033#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52034#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52230#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53170#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 53290#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52143#L750 assume !(1 == ~t8_pc~0); 51814#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51813#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52329#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53365#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52466#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52467#L769 assume 1 == ~t9_pc~0; 53007#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51987#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51988#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52773#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 53229#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53310#L788 assume !(1 == ~t10_pc~0); 52881#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52882#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53116#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53117#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 52141#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52142#L807 assume 1 == ~t11_pc~0; 53319#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52893#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53047#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53463#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 53572#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53410#L826 assume !(1 == ~t12_pc~0); 52538#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52539#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53067#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53503#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 52697#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52605#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 52606#L1344-2 assume !(1 == ~T1_E~0); 53618#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53617#L1354-1 assume !(1 == ~T3_E~0); 53616#L1359-1 assume !(1 == ~T4_E~0); 53615#L1364-1 assume !(1 == ~T5_E~0); 53614#L1369-1 assume !(1 == ~T6_E~0); 53613#L1374-1 assume !(1 == ~T7_E~0); 53612#L1379-1 assume !(1 == ~T8_E~0); 53611#L1384-1 assume !(1 == ~T9_E~0); 52990#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53610#L1394-1 assume !(1 == ~T11_E~0); 53609#L1399-1 assume !(1 == ~T12_E~0); 53608#L1404-1 assume !(1 == ~E_M~0); 53607#L1409-1 assume !(1 == ~E_1~0); 53606#L1414-1 assume !(1 == ~E_2~0); 53605#L1419-1 assume !(1 == ~E_3~0); 53604#L1424-1 assume !(1 == ~E_4~0); 53603#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53602#L1434-1 assume !(1 == ~E_6~0); 53601#L1439-1 assume !(1 == ~E_7~0); 53600#L1444-1 assume !(1 == ~E_8~0); 53599#L1449-1 assume !(1 == ~E_9~0); 53598#L1454-1 assume !(1 == ~E_10~0); 53597#L1459-1 assume !(1 == ~E_11~0); 53596#L1464-1 assume !(1 == ~E_12~0); 53595#L1469-1 assume { :end_inline_reset_delta_events } true; 53593#L1815-2 [2022-07-14 16:03:18,351 INFO L754 eck$LassoCheckResult]: Loop: 53593#L1815-2 assume !false; 53592#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53588#L1181 assume !false; 53587#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53584#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52503#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52504#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53057#L1008 assume !(0 != eval_~tmp~0#1); 53058#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51995#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51996#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53564#L1206-5 assume !(0 == ~T1_E~0); 53024#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52127#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52128#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52720#L1226-3 assume !(0 == ~T5_E~0); 52191#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52192#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52505#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53500#L1246-3 assume !(0 == ~T9_E~0); 53402#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53134#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52152#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52153#L1266-3 assume !(0 == ~E_M~0); 52189#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52190#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52664#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52665#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53204#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53205#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53551#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53519#L1306-3 assume !(0 == ~E_8~0); 52789#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52073#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52074#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52149#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52887#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53214#L598-42 assume 1 == ~m_pc~0; 53216#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53332#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52228#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52229#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 53520#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52944#L617-42 assume 1 == ~t1_pc~0; 52716#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52580#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52581#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52997#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52294#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52295#L636-42 assume 1 == ~t2_pc~0; 53504#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52761#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53113#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53114#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53295#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53155#L655-42 assume 1 == ~t3_pc~0; 53156#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52734#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52364#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52365#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53425#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53370#L674-42 assume !(1 == ~t4_pc~0); 53141#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 53062#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51948#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51949#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52865#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52866#L693-42 assume 1 == ~t5_pc~0; 53123#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53124#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53184#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53179#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53180#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52478#L712-42 assume 1 == ~t6_pc~0; 52480#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52807#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53016#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53017#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52588#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52589#L731-42 assume 1 == ~t7_pc~0; 52451#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52287#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53360#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52495#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52496#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52199#L750-42 assume 1 == ~t8_pc~0; 52200#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52776#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53201#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52092#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52093#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52864#L769-42 assume !(1 == ~t9_pc~0); 52688#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 52687#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53375#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53440#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 52296#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52297#L788-42 assume 1 == ~t10_pc~0; 52872#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53087#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52816#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52817#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53560#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53537#L807-42 assume 1 == ~t11_pc~0; 53225#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51901#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52039#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52040#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52042#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52291#L826-42 assume 1 == ~t12_pc~0; 52292#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52484#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53282#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52281#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52282#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53137#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53138#L1344-5 assume !(1 == ~T1_E~0); 53063#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52441#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52442#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53077#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53540#L1369-3 assume !(1 == ~T6_E~0); 53460#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52206#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52207#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52439#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52440#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52740#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53469#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53431#L1409-3 assume !(1 == ~E_1~0); 53432#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53498#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53276#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52107#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52108#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53076#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52047#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52048#L1449-3 assume !(1 == ~E_9~0); 52157#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53070#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53071#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53456#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53457#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53639#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53638#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 53637#L1834 assume !(0 == start_simulation_~tmp~3#1); 53187#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53632#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53623#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53622#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 53621#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53620#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53619#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53594#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 53593#L1815-2 [2022-07-14 16:03:18,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2022-07-14 16:03:18,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593564150] [2022-07-14 16:03:18,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593564150] [2022-07-14 16:03:18,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593564150] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,375 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,375 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466592577] [2022-07-14 16:03:18,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,376 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,376 INFO L85 PathProgramCache]: Analyzing trace with hash 2055060947, now seen corresponding path program 1 times [2022-07-14 16:03:18,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939006553] [2022-07-14 16:03:18,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939006553] [2022-07-14 16:03:18,401 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939006553] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,401 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,401 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017721087] [2022-07-14 16:03:18,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,402 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:18,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:18,402 INFO L87 Difference]: Start difference. First operand 3324 states and 4886 transitions. cyclomatic complexity: 1564 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,558 INFO L93 Difference]: Finished difference Result 6182 states and 9069 transitions. [2022-07-14 16:03:18,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:18,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6182 states and 9069 transitions. [2022-07-14 16:03:18,580 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5965 [2022-07-14 16:03:18,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6182 states to 6182 states and 9069 transitions. [2022-07-14 16:03:18,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6182 [2022-07-14 16:03:18,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6182 [2022-07-14 16:03:18,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6182 states and 9069 transitions. [2022-07-14 16:03:18,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,606 INFO L369 hiAutomatonCegarLoop]: Abstraction has 6182 states and 9069 transitions. [2022-07-14 16:03:18,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6182 states and 9069 transitions. [2022-07-14 16:03:18,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6182 to 6180. [2022-07-14 16:03:18,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6180 states to 6180 states and 9067 transitions. [2022-07-14 16:03:18,700 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6180 states and 9067 transitions. [2022-07-14 16:03:18,700 INFO L374 stractBuchiCegarLoop]: Abstraction has 6180 states and 9067 transitions. [2022-07-14 16:03:18,700 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:03:18,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6180 states and 9067 transitions. [2022-07-14 16:03:18,716 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5965 [2022-07-14 16:03:18,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,718 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,719 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,719 INFO L752 eck$LassoCheckResult]: Stem: 62133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 61556#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61526#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61527#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 62800#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61835#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61287#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61288#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62566#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62708#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63109#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63110#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62045#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62046#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62592#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 62512#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62513#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62666#L1206 assume !(0 == ~M_E~0); 62024#L1206-2 assume !(0 == ~T1_E~0); 62025#L1211-1 assume !(0 == ~T2_E~0); 62940#L1216-1 assume !(0 == ~T3_E~0); 61817#L1221-1 assume !(0 == ~T4_E~0); 61818#L1226-1 assume !(0 == ~T5_E~0); 61479#L1231-1 assume !(0 == ~T6_E~0); 61480#L1236-1 assume !(0 == ~T7_E~0); 62975#L1241-1 assume !(0 == ~T8_E~0); 61879#L1246-1 assume !(0 == ~T9_E~0); 61880#L1251-1 assume !(0 == ~T10_E~0); 62100#L1256-1 assume !(0 == ~T11_E~0); 61299#L1261-1 assume !(0 == ~T12_E~0); 61300#L1266-1 assume !(0 == ~E_M~0); 63093#L1271-1 assume !(0 == ~E_1~0); 62696#L1276-1 assume !(0 == ~E_2~0); 62697#L1281-1 assume !(0 == ~E_3~0); 62619#L1286-1 assume !(0 == ~E_4~0); 61721#L1291-1 assume !(0 == ~E_5~0); 61722#L1296-1 assume !(0 == ~E_6~0); 62432#L1301-1 assume !(0 == ~E_7~0); 62433#L1306-1 assume !(0 == ~E_8~0); 62877#L1311-1 assume !(0 == ~E_9~0); 61682#L1316-1 assume !(0 == ~E_10~0); 61683#L1321-1 assume !(0 == ~E_11~0); 62449#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61546#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61547#L598 assume 1 == ~m_pc~0; 61606#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61607#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62957#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63055#L1497 assume !(0 != activate_threads_~tmp~1#1); 63056#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63007#L617 assume !(1 == ~t1_pc~0); 61902#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61903#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61762#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61763#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62529#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62530#L636 assume 1 == ~t2_pc~0; 61871#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61872#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61702#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61703#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 62565#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62224#L655 assume !(1 == ~t3_pc~0); 62225#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62962#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61576#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61577#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 63094#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63095#L674 assume 1 == ~t4_pc~0; 61395#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61396#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62703#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61704#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 61705#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62221#L693 assume !(1 == ~t5_pc~0); 62385#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62026#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62027#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62879#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 62112#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62049#L712 assume 1 == ~t6_pc~0; 62050#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62482#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62483#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62776#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 62581#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62579#L731 assume 1 == ~t7_pc~0; 61550#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61551#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61745#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62689#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 62815#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61660#L750 assume !(1 == ~t8_pc~0); 61330#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 61329#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61846#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62892#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61983#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61984#L769 assume 1 == ~t9_pc~0; 62525#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61503#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61504#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62290#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 62752#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62837#L788 assume !(1 == ~t10_pc~0); 62399#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62400#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62634#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62635#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 61656#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61657#L807 assume 1 == ~t11_pc~0; 62846#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62411#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62567#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62999#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 63127#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62943#L826 assume !(1 == ~t12_pc~0); 62052#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62053#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62587#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63039#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 62214#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62121#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 62122#L1344-2 assume !(1 == ~T1_E~0); 62265#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62439#L1354-1 assume !(1 == ~T3_E~0); 62440#L1359-1 assume !(1 == ~T4_E~0); 63102#L1364-1 assume !(1 == ~T5_E~0); 63103#L1369-1 assume !(1 == ~T6_E~0); 62805#L1374-1 assume !(1 == ~T7_E~0); 62806#L1379-1 assume !(1 == ~T8_E~0); 62510#L1384-1 assume !(1 == ~T9_E~0); 62511#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63126#L1394-1 assume !(1 == ~T11_E~0); 63116#L1399-1 assume !(1 == ~T12_E~0); 63117#L1404-1 assume !(1 == ~E_M~0); 61883#L1409-1 assume !(1 == ~E_1~0); 61884#L1414-1 assume !(1 == ~E_2~0); 62730#L1419-1 assume !(1 == ~E_3~0); 62731#L1424-1 assume !(1 == ~E_4~0); 63188#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63186#L1434-1 assume !(1 == ~E_6~0); 63184#L1439-1 assume !(1 == ~E_7~0); 63181#L1444-1 assume !(1 == ~E_8~0); 63179#L1449-1 assume !(1 == ~E_9~0); 63177#L1454-1 assume !(1 == ~E_10~0); 63175#L1459-1 assume !(1 == ~E_11~0); 63173#L1464-1 assume !(1 == ~E_12~0); 63169#L1469-1 assume { :end_inline_reset_delta_events } true; 63161#L1815-2 [2022-07-14 16:03:18,719 INFO L754 eck$LassoCheckResult]: Loop: 63161#L1815-2 assume !false; 63155#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63150#L1181 assume !false; 63149#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63146#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63135#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63134#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63132#L1008 assume !(0 != eval_~tmp~0#1); 63131#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63130#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63128#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63129#L1206-5 assume !(0 == ~T1_E~0); 64984#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64982#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64980#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64978#L1226-3 assume !(0 == ~T5_E~0); 64976#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64974#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64972#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64970#L1246-3 assume !(0 == ~T9_E~0); 64968#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64966#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 64964#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64962#L1266-3 assume !(0 == ~E_M~0); 64889#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64887#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64885#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64883#L1286-3 assume !(0 == ~E_4~0); 64882#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64880#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64878#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64876#L1306-3 assume !(0 == ~E_8~0); 64874#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64832#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64757#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64656#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64654#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64579#L598-42 assume 1 == ~m_pc~0; 64536#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64534#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64468#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64466#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 64402#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64400#L617-42 assume 1 == ~t1_pc~0; 64397#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64270#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64266#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64264#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64262#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64257#L636-42 assume !(1 == ~t2_pc~0); 64256#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 64252#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64250#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64248#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64246#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64244#L655-42 assume 1 == ~t3_pc~0; 64241#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64189#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64072#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64034#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64025#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64018#L674-42 assume !(1 == ~t4_pc~0); 64011#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 64009#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64007#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64006#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64005#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64004#L693-42 assume 1 == ~t5_pc~0; 64002#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63988#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63986#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63984#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63981#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63979#L712-42 assume !(1 == ~t6_pc~0); 63976#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 63974#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63972#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63970#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63968#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63966#L731-42 assume 1 == ~t7_pc~0; 63963#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63961#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63959#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63957#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63955#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63953#L750-42 assume !(1 == ~t8_pc~0); 63950#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 63948#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63946#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63944#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63942#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63940#L769-42 assume 1 == ~t9_pc~0; 63937#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63935#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63933#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 63931#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 63929#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63927#L788-42 assume 1 == ~t10_pc~0; 63924#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 63922#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63920#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63918#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63916#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63913#L807-42 assume !(1 == ~t11_pc~0); 63910#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 63908#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63906#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 63904#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 63902#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63899#L826-42 assume 1 == ~t12_pc~0; 63896#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 63894#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63892#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63890#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63888#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63885#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62657#L1344-5 assume !(1 == ~T1_E~0); 63882#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63880#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63878#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63876#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63656#L1369-3 assume !(1 == ~T6_E~0); 63634#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63609#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63588#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63585#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63584#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63582#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63559#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63557#L1409-3 assume !(1 == ~E_1~0); 63555#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63042#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63043#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63505#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63503#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63502#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63501#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63499#L1449-3 assume !(1 == ~E_9~0); 63498#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63431#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 63398#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63395#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63378#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63364#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63361#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63358#L1834 assume !(0 == start_simulation_~tmp~3#1); 62709#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63347#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63336#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63330#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 63323#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63317#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63312#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 63168#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 63161#L1815-2 [2022-07-14 16:03:18,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2022-07-14 16:03:18,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616925652] [2022-07-14 16:03:18,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616925652] [2022-07-14 16:03:18,746 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616925652] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,746 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,746 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910552316] [2022-07-14 16:03:18,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,747 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,747 INFO L85 PathProgramCache]: Analyzing trace with hash 1827868184, now seen corresponding path program 1 times [2022-07-14 16:03:18,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852660486] [2022-07-14 16:03:18,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,771 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852660486] [2022-07-14 16:03:18,771 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852660486] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,771 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,771 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920293822] [2022-07-14 16:03:18,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,772 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:18,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:18,773 INFO L87 Difference]: Start difference. First operand 6180 states and 9067 transitions. cyclomatic complexity: 2891 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,902 INFO L93 Difference]: Finished difference Result 11670 states and 17086 transitions. [2022-07-14 16:03:18,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:18,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11670 states and 17086 transitions. [2022-07-14 16:03:18,941 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11439 [2022-07-14 16:03:18,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11670 states to 11670 states and 17086 transitions. [2022-07-14 16:03:18,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11670 [2022-07-14 16:03:18,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11670 [2022-07-14 16:03:18,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11670 states and 17086 transitions. [2022-07-14 16:03:18,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,985 INFO L369 hiAutomatonCegarLoop]: Abstraction has 11670 states and 17086 transitions. [2022-07-14 16:03:18,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11670 states and 17086 transitions. [2022-07-14 16:03:19,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11670 to 11666. [2022-07-14 16:03:19,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11666 states to 11666 states and 17082 transitions. [2022-07-14 16:03:19,155 INFO L392 hiAutomatonCegarLoop]: Abstraction has 11666 states and 17082 transitions. [2022-07-14 16:03:19,155 INFO L374 stractBuchiCegarLoop]: Abstraction has 11666 states and 17082 transitions. [2022-07-14 16:03:19,155 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:03:19,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11666 states and 17082 transitions. [2022-07-14 16:03:19,182 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11439 [2022-07-14 16:03:19,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,184 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,185 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,185 INFO L752 eck$LassoCheckResult]: Stem: 80000#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 80001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 79417#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79387#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79388#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 80729#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79698#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79147#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79148#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80469#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 80627#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81133#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81134#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 79912#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 79913#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80500#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 80408#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 80409#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80578#L1206 assume !(0 == ~M_E~0); 79890#L1206-2 assume !(0 == ~T1_E~0); 79891#L1211-1 assume !(0 == ~T2_E~0); 80902#L1216-1 assume !(0 == ~T3_E~0); 79680#L1221-1 assume !(0 == ~T4_E~0); 79681#L1226-1 assume !(0 == ~T5_E~0); 79340#L1231-1 assume !(0 == ~T6_E~0); 79341#L1236-1 assume !(0 == ~T7_E~0); 80941#L1241-1 assume !(0 == ~T8_E~0); 79743#L1246-1 assume !(0 == ~T9_E~0); 79744#L1251-1 assume !(0 == ~T10_E~0); 79967#L1256-1 assume !(0 == ~T11_E~0); 79159#L1261-1 assume !(0 == ~T12_E~0); 79160#L1266-1 assume !(0 == ~E_M~0); 81113#L1271-1 assume !(0 == ~E_1~0); 80612#L1276-1 assume !(0 == ~E_2~0); 80613#L1281-1 assume !(0 == ~E_3~0); 80528#L1286-1 assume !(0 == ~E_4~0); 79583#L1291-1 assume !(0 == ~E_5~0); 79584#L1296-1 assume !(0 == ~E_6~0); 80326#L1301-1 assume !(0 == ~E_7~0); 80327#L1306-1 assume !(0 == ~E_8~0); 80826#L1311-1 assume !(0 == ~E_9~0); 79544#L1316-1 assume !(0 == ~E_10~0); 79545#L1321-1 assume !(0 == ~E_11~0); 80345#L1326-1 assume !(0 == ~E_12~0); 79407#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79408#L598 assume 1 == ~m_pc~0; 79467#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79468#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80919#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81058#L1497 assume !(0 != activate_threads_~tmp~1#1); 81059#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80987#L617 assume !(1 == ~t1_pc~0); 79766#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79767#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79625#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79626#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80425#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80426#L636 assume 1 == ~t2_pc~0; 79735#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79736#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79564#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79565#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 80468#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80094#L655 assume !(1 == ~t3_pc~0); 80095#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80925#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79437#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79438#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 81114#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81115#L674 assume 1 == ~t4_pc~0; 79256#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79257#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80619#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79566#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 79567#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80091#L693 assume !(1 == ~t5_pc~0); 80276#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 79892#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79893#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80829#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 79979#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79916#L712 assume 1 == ~t6_pc~0; 79917#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80377#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80378#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80703#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 80489#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80486#L731 assume 1 == ~t7_pc~0; 79411#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79412#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79608#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80607#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 80744#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79522#L750 assume !(1 == ~t8_pc~0); 79190#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 79189#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79709#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80848#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 79847#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 79848#L769 assume 1 == ~t9_pc~0; 80421#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79364#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79365#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80168#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 80675#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80772#L788 assume !(1 == ~t10_pc~0); 80290#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 80291#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80543#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80544#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 79518#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79519#L807 assume 1 == ~t11_pc~0; 80783#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80305#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80470#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80979#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 81192#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80904#L826 assume !(1 == ~t12_pc~0); 79919#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 79920#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80495#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81027#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 80084#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79988#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 79989#L1344-2 assume !(1 == ~T1_E~0); 80140#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80335#L1354-1 assume !(1 == ~T3_E~0); 80336#L1359-1 assume !(1 == ~T4_E~0); 81123#L1364-1 assume !(1 == ~T5_E~0); 81124#L1369-1 assume !(1 == ~T6_E~0); 80734#L1374-1 assume !(1 == ~T7_E~0); 80735#L1379-1 assume !(1 == ~T8_E~0); 80406#L1384-1 assume !(1 == ~T9_E~0); 80407#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 80944#L1394-1 assume !(1 == ~T11_E~0); 80945#L1399-1 assume !(1 == ~T12_E~0); 81073#L1404-1 assume !(1 == ~E_M~0); 79747#L1409-1 assume !(1 == ~E_1~0); 79748#L1414-1 assume !(1 == ~E_2~0); 81056#L1419-1 assume !(1 == ~E_3~0); 81375#L1424-1 assume !(1 == ~E_4~0); 81373#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 81371#L1434-1 assume !(1 == ~E_6~0); 81337#L1439-1 assume !(1 == ~E_7~0); 81335#L1444-1 assume !(1 == ~E_8~0); 81333#L1449-1 assume !(1 == ~E_9~0); 81301#L1454-1 assume !(1 == ~E_10~0); 81274#L1459-1 assume !(1 == ~E_11~0); 81256#L1464-1 assume !(1 == ~E_12~0); 81239#L1469-1 assume { :end_inline_reset_delta_events } true; 81231#L1815-2 [2022-07-14 16:03:19,185 INFO L754 eck$LassoCheckResult]: Loop: 81231#L1815-2 assume !false; 81225#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81220#L1181 assume !false; 81219#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81216#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81205#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81204#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 81202#L1008 assume !(0 != eval_~tmp~0#1); 81201#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81200#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81198#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 81199#L1206-5 assume !(0 == ~T1_E~0); 88696#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88693#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88691#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88689#L1226-3 assume !(0 == ~T5_E~0); 88687#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88685#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88683#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88680#L1246-3 assume !(0 == ~T9_E~0); 88678#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88676#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88674#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 88672#L1266-3 assume !(0 == ~E_M~0); 88670#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88667#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88665#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88663#L1286-3 assume !(0 == ~E_4~0); 88661#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88659#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88657#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88654#L1306-3 assume !(0 == ~E_8~0); 88652#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88650#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88648#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88646#L1326-3 assume !(0 == ~E_12~0); 88644#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88641#L598-42 assume !(1 == ~m_pc~0); 88639#L598-44 is_master_triggered_~__retres1~0#1 := 0; 88636#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88634#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88632#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 88630#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88627#L617-42 assume !(1 == ~t1_pc~0); 88625#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 88622#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88620#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88618#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88616#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88613#L636-42 assume !(1 == ~t2_pc~0); 88611#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 88608#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88606#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88604#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88602#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88599#L655-42 assume !(1 == ~t3_pc~0); 88597#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88594#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88592#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88590#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88588#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88585#L674-42 assume 1 == ~t4_pc~0; 88583#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 88580#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88578#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88576#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88574#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88571#L693-42 assume !(1 == ~t5_pc~0); 88569#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 88566#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88564#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88562#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88560#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88557#L712-42 assume 1 == ~t6_pc~0; 88555#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88552#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88550#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88548#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88546#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88544#L731-42 assume 1 == ~t7_pc~0; 88541#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88539#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88537#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88535#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 88533#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88531#L750-42 assume 1 == ~t8_pc~0; 88529#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 88527#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88526#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88525#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 88524#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88523#L769-42 assume 1 == ~t9_pc~0; 88521#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88520#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88519#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88518#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 88516#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88513#L788-42 assume !(1 == ~t10_pc~0); 88511#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 88508#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88506#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88504#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 88502#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88499#L807-42 assume 1 == ~t11_pc~0; 88497#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88494#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88492#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88490#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 88488#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88487#L826-42 assume 1 == ~t12_pc~0; 88483#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 88481#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88479#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88477#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 88475#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88473#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 80569#L1344-5 assume !(1 == ~T1_E~0); 88469#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88467#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88465#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88463#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88461#L1369-3 assume !(1 == ~T6_E~0); 88458#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88456#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 88454#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 88451#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 88449#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 88447#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 88444#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88442#L1409-3 assume !(1 == ~E_1~0); 88440#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88438#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88436#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88433#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88430#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88428#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 88426#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 88424#L1449-3 assume !(1 == ~E_9~0); 88422#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 88420#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 81369#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 81365#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81331#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81319#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81318#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81317#L1834 assume !(0 == start_simulation_~tmp~3#1); 80628#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81296#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81285#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81283#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81270#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81253#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81249#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 81238#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 81231#L1815-2 [2022-07-14 16:03:19,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,186 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2022-07-14 16:03:19,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408021878] [2022-07-14 16:03:19,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,205 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408021878] [2022-07-14 16:03:19,205 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408021878] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,206 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,206 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:19,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628387221] [2022-07-14 16:03:19,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,206 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,207 INFO L85 PathProgramCache]: Analyzing trace with hash 13748699, now seen corresponding path program 1 times [2022-07-14 16:03:19,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,207 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010625968] [2022-07-14 16:03:19,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010625968] [2022-07-14 16:03:19,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010625968] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264990660] [2022-07-14 16:03:19,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,231 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,231 INFO L87 Difference]: Start difference. First operand 11666 states and 17082 transitions. cyclomatic complexity: 5424 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,362 INFO L93 Difference]: Finished difference Result 22935 states and 33364 transitions. [2022-07-14 16:03:19,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22935 states and 33364 transitions. [2022-07-14 16:03:19,530 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22701 [2022-07-14 16:03:19,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22935 states to 22935 states and 33364 transitions. [2022-07-14 16:03:19,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22935 [2022-07-14 16:03:19,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22935 [2022-07-14 16:03:19,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22935 states and 33364 transitions. [2022-07-14 16:03:19,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,620 INFO L369 hiAutomatonCegarLoop]: Abstraction has 22935 states and 33364 transitions. [2022-07-14 16:03:19,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22935 states and 33364 transitions. [2022-07-14 16:03:19,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22935 to 22215. [2022-07-14 16:03:19,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22215 states, 22215 states have (on average 1.456133243304074) internal successors, (32348), 22214 states have internal predecessors, (32348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22215 states to 22215 states and 32348 transitions. [2022-07-14 16:03:19,905 INFO L392 hiAutomatonCegarLoop]: Abstraction has 22215 states and 32348 transitions. [2022-07-14 16:03:19,905 INFO L374 stractBuchiCegarLoop]: Abstraction has 22215 states and 32348 transitions. [2022-07-14 16:03:19,905 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:03:19,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22215 states and 32348 transitions. [2022-07-14 16:03:19,959 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21981 [2022-07-14 16:03:19,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,962 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,962 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,962 INFO L752 eck$LassoCheckResult]: Stem: 114623#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 114624#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 114026#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113999#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114000#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 115406#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114307#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113755#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113756#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115127#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115288#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115905#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 115906#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 114530#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 114531#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 115158#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 115060#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 115061#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115246#L1206 assume !(0 == ~M_E~0); 114506#L1206-2 assume !(0 == ~T1_E~0); 114507#L1211-1 assume !(0 == ~T2_E~0); 115593#L1216-1 assume !(0 == ~T3_E~0); 114288#L1221-1 assume !(0 == ~T4_E~0); 114289#L1226-1 assume !(0 == ~T5_E~0); 113949#L1231-1 assume !(0 == ~T6_E~0); 113950#L1236-1 assume !(0 == ~T7_E~0); 115635#L1241-1 assume !(0 == ~T8_E~0); 114352#L1246-1 assume !(0 == ~T9_E~0); 114353#L1251-1 assume !(0 == ~T10_E~0); 114587#L1256-1 assume !(0 == ~T11_E~0); 113767#L1261-1 assume !(0 == ~T12_E~0); 113768#L1266-1 assume !(0 == ~E_M~0); 115869#L1271-1 assume !(0 == ~E_1~0); 115274#L1276-1 assume !(0 == ~E_2~0); 115275#L1281-1 assume !(0 == ~E_3~0); 115194#L1286-1 assume !(0 == ~E_4~0); 114188#L1291-1 assume !(0 == ~E_5~0); 114189#L1296-1 assume !(0 == ~E_6~0); 114961#L1301-1 assume !(0 == ~E_7~0); 114962#L1306-1 assume !(0 == ~E_8~0); 115507#L1311-1 assume !(0 == ~E_9~0); 114150#L1316-1 assume !(0 == ~E_10~0); 114151#L1321-1 assume !(0 == ~E_11~0); 114980#L1326-1 assume !(0 == ~E_12~0); 114016#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114017#L598 assume !(1 == ~m_pc~0); 114751#L598-2 is_master_triggered_~__retres1~0#1 := 0; 114752#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115612#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115787#L1497 assume !(0 != activate_threads_~tmp~1#1); 115788#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115690#L617 assume !(1 == ~t1_pc~0); 114376#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114377#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114230#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114231#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115079#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115080#L636 assume 1 == ~t2_pc~0; 114344#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114345#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114169#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114170#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 115126#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114723#L655 assume !(1 == ~t3_pc~0); 114724#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115619#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114044#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114045#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 115871#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115872#L674 assume 1 == ~t4_pc~0; 113862#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113863#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115281#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114173#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 114174#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114717#L693 assume !(1 == ~t5_pc~0); 114908#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 114512#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114513#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 115511#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 114600#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114532#L712 assume 1 == ~t6_pc~0; 114533#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 115018#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115019#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 115373#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 115146#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115141#L731 assume 1 == ~t7_pc~0; 114018#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114019#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114215#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115270#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 115420#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114127#L750 assume !(1 == ~t8_pc~0); 113798#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 113797#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114319#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 115529#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114460#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114461#L769 assume 1 == ~t9_pc~0; 115077#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 113971#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 113972#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114797#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 115342#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 115448#L788 assume !(1 == ~t10_pc~0); 114926#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 114927#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 115210#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 115211#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 114125#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114126#L807 assume 1 == ~t11_pc~0; 115459#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 114940#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115128#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 115675#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 115983#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 115596#L826 assume !(1 == ~t12_pc~0); 114537#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 114538#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 115153#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 115746#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 114710#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114609#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 114610#L1344-2 assume !(1 == ~T1_E~0); 114771#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114970#L1354-1 assume !(1 == ~T3_E~0); 114971#L1359-1 assume !(1 == ~T4_E~0); 115434#L1364-1 assume !(1 == ~T5_E~0); 114232#L1369-1 assume !(1 == ~T6_E~0); 114233#L1374-1 assume !(1 == ~T7_E~0); 114978#L1379-1 assume !(1 == ~T8_E~0); 114979#L1384-1 assume !(1 == ~T9_E~0); 115059#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 127128#L1394-1 assume !(1 == ~T11_E~0); 127127#L1399-1 assume !(1 == ~T12_E~0); 127126#L1404-1 assume !(1 == ~E_M~0); 127125#L1409-1 assume !(1 == ~E_1~0); 127124#L1414-1 assume !(1 == ~E_2~0); 127123#L1419-1 assume !(1 == ~E_3~0); 127121#L1424-1 assume !(1 == ~E_4~0); 127119#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 127117#L1434-1 assume !(1 == ~E_6~0); 127115#L1439-1 assume !(1 == ~E_7~0); 127113#L1444-1 assume !(1 == ~E_8~0); 127111#L1449-1 assume !(1 == ~E_9~0); 127110#L1454-1 assume !(1 == ~E_10~0); 127109#L1459-1 assume !(1 == ~E_11~0); 127107#L1464-1 assume !(1 == ~E_12~0); 127100#L1469-1 assume { :end_inline_reset_delta_events } true; 127098#L1815-2 [2022-07-14 16:03:19,962 INFO L754 eck$LassoCheckResult]: Loop: 127098#L1815-2 assume !false; 127001#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 126996#L1181 assume !false; 126994#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 126904#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 126892#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 126890#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 126887#L1008 assume !(0 != eval_~tmp~0#1); 126888#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 132496#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132494#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 132492#L1206-5 assume !(0 == ~T1_E~0); 132490#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132488#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132486#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132484#L1226-3 assume !(0 == ~T5_E~0); 132482#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132480#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132478#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 132476#L1246-3 assume !(0 == ~T9_E~0); 132474#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 132472#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 132470#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 132468#L1266-3 assume !(0 == ~E_M~0); 132466#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132464#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132462#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132460#L1286-3 assume !(0 == ~E_4~0); 132458#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132456#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 132454#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 132452#L1306-3 assume !(0 == ~E_8~0); 132450#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 132447#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 132445#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 132443#L1326-3 assume !(0 == ~E_12~0); 132441#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132439#L598-42 assume !(1 == ~m_pc~0); 132437#L598-44 is_master_triggered_~__retres1~0#1 := 0; 132434#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132432#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132430#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 132428#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132426#L617-42 assume 1 == ~t1_pc~0; 132423#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 132420#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132418#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132416#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 132414#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132412#L636-42 assume !(1 == ~t2_pc~0); 132410#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 132406#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132404#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132402#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132400#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132398#L655-42 assume 1 == ~t3_pc~0; 132395#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 132392#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132390#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132388#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132386#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132384#L674-42 assume 1 == ~t4_pc~0; 132382#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 132378#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132376#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132374#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132372#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132370#L693-42 assume !(1 == ~t5_pc~0); 132368#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 132364#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132362#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132360#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 132359#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132358#L712-42 assume !(1 == ~t6_pc~0); 132356#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 132355#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132354#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132353#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 132352#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132350#L731-42 assume 1 == ~t7_pc~0; 132347#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 132345#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132343#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132341#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 132339#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132337#L750-42 assume 1 == ~t8_pc~0; 132334#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 132331#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132329#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132327#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 132326#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132325#L769-42 assume 1 == ~t9_pc~0; 132323#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132322#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132321#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 132320#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 132319#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 132318#L788-42 assume 1 == ~t10_pc~0; 132316#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 132314#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132312#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 132310#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 132308#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 132306#L807-42 assume 1 == ~t11_pc~0; 132304#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 132301#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 132298#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 132296#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 132295#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132294#L826-42 assume 1 == ~t12_pc~0; 132292#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 132291#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 132290#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 132289#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 130706#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130705#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 115235#L1344-5 assume !(1 == ~T1_E~0); 130704#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 130702#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 130700#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 130698#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 130696#L1369-3 assume !(1 == ~T6_E~0); 130693#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 130691#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 129748#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129743#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129741#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 129739#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 129737#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 129735#L1409-3 assume !(1 == ~E_1~0); 129733#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129730#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 129728#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116922#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 129725#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 129723#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 129721#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 128456#L1449-3 assume !(1 == ~E_9~0); 128453#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 128451#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 128449#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 128445#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 127352#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 127338#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 127336#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 127334#L1834 assume !(0 == start_simulation_~tmp~3#1); 115290#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 127149#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 127139#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 127137#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 127136#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 127132#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 127130#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 127099#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 127098#L1815-2 [2022-07-14 16:03:19,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,963 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2022-07-14 16:03:19,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621464475] [2022-07-14 16:03:19,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621464475] [2022-07-14 16:03:19,994 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621464475] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,994 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,994 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:19,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29169752] [2022-07-14 16:03:19,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,994 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1676004775, now seen corresponding path program 1 times [2022-07-14 16:03:19,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,995 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464434404] [2022-07-14 16:03:19,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,025 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464434404] [2022-07-14 16:03:20,025 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464434404] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,025 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26548108] [2022-07-14 16:03:20,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,026 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:20,026 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:20,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:20,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:20,026 INFO L87 Difference]: Start difference. First operand 22215 states and 32348 transitions. cyclomatic complexity: 10149 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:20,538 INFO L93 Difference]: Finished difference Result 63391 states and 92112 transitions. [2022-07-14 16:03:20,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:20,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63391 states and 92112 transitions. [2022-07-14 16:03:20,782 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62800 [2022-07-14 16:03:21,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63391 states to 63391 states and 92112 transitions. [2022-07-14 16:03:21,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63391 [2022-07-14 16:03:21,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63391 [2022-07-14 16:03:21,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63391 states and 92112 transitions. [2022-07-14 16:03:21,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:21,180 INFO L369 hiAutomatonCegarLoop]: Abstraction has 63391 states and 92112 transitions. [2022-07-14 16:03:21,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63391 states and 92112 transitions. [2022-07-14 16:03:21,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63391 to 22824. [2022-07-14 16:03:21,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22824 states, 22824 states have (on average 1.443962495618647) internal successors, (32957), 22823 states have internal predecessors, (32957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:21,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22824 states to 22824 states and 32957 transitions. [2022-07-14 16:03:21,558 INFO L392 hiAutomatonCegarLoop]: Abstraction has 22824 states and 32957 transitions. [2022-07-14 16:03:21,558 INFO L374 stractBuchiCegarLoop]: Abstraction has 22824 states and 32957 transitions. [2022-07-14 16:03:21,558 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 16:03:21,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22824 states and 32957 transitions. [2022-07-14 16:03:21,610 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22587 [2022-07-14 16:03:21,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:21,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:21,612 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:21,612 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:21,612 INFO L752 eck$LassoCheckResult]: Stem: 200234#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 200235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 199641#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 199611#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 199612#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 200982#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199924#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199374#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 199375#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 200721#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 200875#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 201400#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 201401#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 200143#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 200144#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 200750#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 200658#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 200659#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 200835#L1206 assume !(0 == ~M_E~0); 200122#L1206-2 assume !(0 == ~T1_E~0); 200123#L1211-1 assume !(0 == ~T2_E~0); 201155#L1216-1 assume !(0 == ~T3_E~0); 199906#L1221-1 assume !(0 == ~T4_E~0); 199907#L1226-1 assume !(0 == ~T5_E~0); 199565#L1231-1 assume !(0 == ~T6_E~0); 199566#L1236-1 assume !(0 == ~T7_E~0); 201195#L1241-1 assume !(0 == ~T8_E~0); 199971#L1246-1 assume !(0 == ~T9_E~0); 199972#L1251-1 assume !(0 == ~T10_E~0); 200199#L1256-1 assume !(0 == ~T11_E~0); 199386#L1261-1 assume !(0 == ~T12_E~0); 199387#L1266-1 assume !(0 == ~E_M~0); 201373#L1271-1 assume !(0 == ~E_1~0); 200863#L1276-1 assume !(0 == ~E_2~0); 200864#L1281-1 assume !(0 == ~E_3~0); 200781#L1286-1 assume !(0 == ~E_4~0); 199807#L1291-1 assume !(0 == ~E_5~0); 199808#L1296-1 assume !(0 == ~E_6~0); 200563#L1301-1 assume !(0 == ~E_7~0); 200564#L1306-1 assume !(0 == ~E_8~0); 201075#L1311-1 assume !(0 == ~E_9~0); 199767#L1316-1 assume !(0 == ~E_10~0); 199768#L1321-1 assume !(0 == ~E_11~0); 200581#L1326-1 assume !(0 == ~E_12~0); 199631#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199632#L598 assume !(1 == ~m_pc~0); 200358#L598-2 is_master_triggered_~__retres1~0#1 := 0; 200359#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201174#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 201314#L1497 assume !(0 != activate_threads_~tmp~1#1); 201315#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201238#L617 assume !(1 == ~t1_pc~0); 199994#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 199995#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201440#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 201334#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 200677#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 200678#L636 assume 1 == ~t2_pc~0; 199963#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199964#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199788#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 199789#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 200720#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200327#L655 assume !(1 == ~t3_pc~0); 200328#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 201180#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199661#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 199662#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 201374#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 201375#L674 assume 1 == ~t4_pc~0; 199481#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 199482#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 200870#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 199790#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 199791#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 200324#L693 assume !(1 == ~t5_pc~0); 200514#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 200124#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 200125#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 201078#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 200211#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 200147#L712 assume 1 == ~t6_pc~0; 200148#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 200615#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 200616#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200953#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 200738#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 200734#L731 assume 1 == ~t7_pc~0; 199635#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 199636#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 199832#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 200858#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 200997#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 199744#L750 assume !(1 == ~t8_pc~0); 199417#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 199416#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 199936#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 201094#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 200077#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200078#L769 assume 1 == ~t9_pc~0; 200673#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 199589#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 199590#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 200411#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 200923#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 201023#L788 assume !(1 == ~t10_pc~0); 200528#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 200529#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 200796#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200797#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 199740#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 199741#L807 assume 1 == ~t11_pc~0; 201032#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 200543#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200722#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 201227#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 201461#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 201159#L826 assume !(1 == ~t12_pc~0); 200150#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 200151#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 200745#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 201287#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 200317#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 200222#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 200223#L1344-2 assume !(1 == ~T1_E~0); 200382#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 201444#L1354-1 assume !(1 == ~T3_E~0); 206962#L1359-1 assume !(1 == ~T4_E~0); 201387#L1364-1 assume !(1 == ~T5_E~0); 199851#L1369-1 assume !(1 == ~T6_E~0); 199852#L1374-1 assume !(1 == ~T7_E~0); 200987#L1379-1 assume !(1 == ~T8_E~0); 200653#L1384-1 assume !(1 == ~T9_E~0); 200654#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 201198#L1394-1 assume !(1 == ~T11_E~0); 201199#L1399-1 assume !(1 == ~T12_E~0); 201329#L1404-1 assume !(1 == ~E_M~0); 199975#L1409-1 assume !(1 == ~E_1~0); 199976#L1414-1 assume !(1 == ~E_2~0); 200900#L1419-1 assume !(1 == ~E_3~0); 199602#L1424-1 assume !(1 == ~E_4~0); 199603#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 218933#L1434-1 assume !(1 == ~E_6~0); 218931#L1439-1 assume !(1 == ~E_7~0); 218929#L1444-1 assume !(1 == ~E_8~0); 218927#L1449-1 assume !(1 == ~E_9~0); 218924#L1454-1 assume !(1 == ~E_10~0); 218922#L1459-1 assume !(1 == ~E_11~0); 218920#L1464-1 assume !(1 == ~E_12~0); 200695#L1469-1 assume { :end_inline_reset_delta_events } true; 218884#L1815-2 [2022-07-14 16:03:21,613 INFO L754 eck$LassoCheckResult]: Loop: 218884#L1815-2 assume !false; 218873#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 218864#L1181 assume !false; 218859#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 218705#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 218688#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 218369#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 218351#L1008 assume !(0 != eval_~tmp~0#1); 218352#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 222197#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 222196#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 222195#L1206-5 assume !(0 == ~T1_E~0); 222194#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 222193#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 222192#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 222191#L1226-3 assume !(0 == ~T5_E~0); 222190#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 222189#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 222188#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 222187#L1246-3 assume !(0 == ~T9_E~0); 222186#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 200817#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 200818#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 200420#L1266-3 assume !(0 == ~E_M~0); 199792#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199793#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 200284#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 200285#L1286-3 assume !(0 == ~E_4~0); 222184#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 201423#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 201384#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 201324#L1306-3 assume !(0 == ~E_8~0); 200431#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 199675#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 199676#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 199752#L1326-3 assume !(0 == ~E_12~0); 202345#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 200906#L598-42 assume !(1 == ~m_pc~0); 200907#L598-44 is_master_triggered_~__retres1~0#1 := 0; 201163#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201164#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 201325#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 201326#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200597#L617-42 assume 1 == ~t1_pc~0; 200338#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 200339#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200664#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 200665#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 222171#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222170#L636-42 assume !(1 == ~t2_pc~0); 222169#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 222167#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222166#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222165#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 222164#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222163#L655-42 assume !(1 == ~t3_pc~0); 222162#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 222160#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222156#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 222155#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 222154#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222153#L674-42 assume !(1 == ~t4_pc~0); 222151#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 222150#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222149#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 222148#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 222147#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 222146#L693-42 assume !(1 == ~t5_pc~0); 222145#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 222143#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 222142#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 222141#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 222140#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 222139#L712-42 assume 1 == ~t6_pc~0; 222138#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 222136#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222135#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 222134#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 222133#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 222132#L731-42 assume !(1 == ~t7_pc~0); 222131#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 222129#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 222128#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 222127#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 222126#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 222112#L750-42 assume !(1 == ~t8_pc~0); 200416#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 200415#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 200893#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 199691#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 199692#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200511#L769-42 assume 1 == ~t9_pc~0; 200306#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 200307#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 201108#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 201196#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 199902#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 199903#L788-42 assume 1 == ~t10_pc~0; 200519#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 200767#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 200460#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200461#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 201407#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 201362#L807-42 assume 1 == ~t11_pc~0; 200916#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 199503#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 199642#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 199643#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 199644#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 221750#L826-42 assume !(1 == ~t12_pc~0); 221749#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 221677#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 201268#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 199887#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 199888#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 200822#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 200823#L1344-5 assume !(1 == ~T1_E~0); 200740#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200050#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 200051#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 200755#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 201367#L1369-3 assume !(1 == ~T6_E~0); 201223#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 199809#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 199810#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 201145#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 200369#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 200370#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 201236#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 201187#L1409-3 assume !(1 == ~E_1~0); 201188#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 201282#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 200978#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 199706#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 199707#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 200754#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 199649#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 199650#L1449-3 assume !(1 == ~E_9~0); 221657#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 221656#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 221655#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 202479#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 202408#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 202395#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 202393#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 201388#L1834 assume !(0 == start_simulation_~tmp~3#1); 200877#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 219214#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 219172#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 219164#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 219157#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 218919#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 218916#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 218895#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 218884#L1815-2 [2022-07-14 16:03:21,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:21,613 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2022-07-14 16:03:21,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:21,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638860893] [2022-07-14 16:03:21,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:21,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:21,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:21,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:21,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:21,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638860893] [2022-07-14 16:03:21,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638860893] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:21,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:21,645 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:21,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835112024] [2022-07-14 16:03:21,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:21,646 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:21,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:21,647 INFO L85 PathProgramCache]: Analyzing trace with hash 570837597, now seen corresponding path program 1 times [2022-07-14 16:03:21,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:21,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105028789] [2022-07-14 16:03:21,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:21,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:21,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:21,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:21,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:21,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105028789] [2022-07-14 16:03:21,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105028789] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:21,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:21,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:21,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531661638] [2022-07-14 16:03:21,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:21,675 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:21,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:21,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:21,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:21,676 INFO L87 Difference]: Start difference. First operand 22824 states and 32957 transitions. cyclomatic complexity: 10149 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:22,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:22,062 INFO L93 Difference]: Finished difference Result 55624 states and 79764 transitions. [2022-07-14 16:03:22,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:22,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55624 states and 79764 transitions. [2022-07-14 16:03:22,266 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54580 [2022-07-14 16:03:22,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55624 states to 55624 states and 79764 transitions. [2022-07-14 16:03:22,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55624 [2022-07-14 16:03:22,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55624 [2022-07-14 16:03:22,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55624 states and 79764 transitions. [2022-07-14 16:03:22,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:22,481 INFO L369 hiAutomatonCegarLoop]: Abstraction has 55624 states and 79764 transitions. [2022-07-14 16:03:22,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55624 states and 79764 transitions. [2022-07-14 16:03:22,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55624 to 43656. [2022-07-14 16:03:22,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43656 states, 43656 states have (on average 1.438129924867143) internal successors, (62783), 43655 states have internal predecessors, (62783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:23,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43656 states to 43656 states and 62783 transitions. [2022-07-14 16:03:23,030 INFO L392 hiAutomatonCegarLoop]: Abstraction has 43656 states and 62783 transitions. [2022-07-14 16:03:23,030 INFO L374 stractBuchiCegarLoop]: Abstraction has 43656 states and 62783 transitions. [2022-07-14 16:03:23,030 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 16:03:23,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43656 states and 62783 transitions. [2022-07-14 16:03:23,264 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43412 [2022-07-14 16:03:23,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:23,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:23,266 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:23,266 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:23,266 INFO L752 eck$LassoCheckResult]: Stem: 278673#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 278674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 278098#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 278068#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 278069#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 279376#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 278374#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 277832#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 277833#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 279132#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 279278#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 279737#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 279738#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 278585#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 278586#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 279161#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 279076#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 279077#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 279236#L1206 assume !(0 == ~M_E~0); 278562#L1206-2 assume !(0 == ~T1_E~0); 278563#L1211-1 assume !(0 == ~T2_E~0); 279545#L1216-1 assume !(0 == ~T3_E~0); 278356#L1221-1 assume !(0 == ~T4_E~0); 278357#L1226-1 assume !(0 == ~T5_E~0); 278023#L1231-1 assume !(0 == ~T6_E~0); 278024#L1236-1 assume !(0 == ~T7_E~0); 279582#L1241-1 assume !(0 == ~T8_E~0); 278415#L1246-1 assume !(0 == ~T9_E~0); 278416#L1251-1 assume !(0 == ~T10_E~0); 278640#L1256-1 assume !(0 == ~T11_E~0); 277844#L1261-1 assume !(0 == ~T12_E~0); 277845#L1266-1 assume !(0 == ~E_M~0); 279724#L1271-1 assume !(0 == ~E_1~0); 279265#L1276-1 assume !(0 == ~E_2~0); 279266#L1281-1 assume !(0 == ~E_3~0); 279190#L1286-1 assume !(0 == ~E_4~0); 278258#L1291-1 assume !(0 == ~E_5~0); 278259#L1296-1 assume !(0 == ~E_6~0); 278990#L1301-1 assume !(0 == ~E_7~0); 278991#L1306-1 assume !(0 == ~E_8~0); 279468#L1311-1 assume !(0 == ~E_9~0); 278220#L1316-1 assume !(0 == ~E_10~0); 278221#L1321-1 assume !(0 == ~E_11~0); 279007#L1326-1 assume !(0 == ~E_12~0); 278088#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278089#L598 assume !(1 == ~m_pc~0); 278792#L598-2 is_master_triggered_~__retres1~0#1 := 0; 278793#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 279561#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 279686#L1497 assume !(0 != activate_threads_~tmp~1#1); 279687#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279619#L617 assume !(1 == ~t1_pc~0); 278439#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 278440#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278300#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278301#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 279093#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 279094#L636 assume !(1 == ~t2_pc~0); 279637#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 278863#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278239#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278240#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 279131#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278764#L655 assume !(1 == ~t3_pc~0); 278765#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 279566#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278116#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 278117#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 279725#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279726#L674 assume 1 == ~t4_pc~0; 277937#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 277938#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279273#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 278241#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 278242#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278761#L693 assume !(1 == ~t5_pc~0); 278941#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 278567#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278568#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279472#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 278652#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278588#L712 assume 1 == ~t6_pc~0; 278589#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 279041#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 279042#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 279351#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 279149#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 279146#L731 assume 1 == ~t7_pc~0; 278090#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 278091#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278285#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 279261#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 279392#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 278198#L750 assume !(1 == ~t8_pc~0); 277875#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 277874#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 278385#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 279486#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 278519#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 278520#L769 assume 1 == ~t9_pc~0; 279091#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 278044#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 278045#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 278838#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 279325#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 279421#L788 assume !(1 == ~t10_pc~0); 278955#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 278956#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 279204#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 279205#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 278194#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 278195#L807 assume 1 == ~t11_pc~0; 279430#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 278970#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 279133#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 279609#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 279780#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 279549#L826 assume !(1 == ~t12_pc~0); 278593#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 278594#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 279156#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 279662#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 278754#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278661#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 278662#L1344-2 assume !(1 == ~T1_E~0); 305419#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 305418#L1354-1 assume !(1 == ~T3_E~0); 305417#L1359-1 assume !(1 == ~T4_E~0); 305416#L1364-1 assume !(1 == ~T5_E~0); 305415#L1369-1 assume !(1 == ~T6_E~0); 305414#L1374-1 assume !(1 == ~T7_E~0); 305413#L1379-1 assume !(1 == ~T8_E~0); 279074#L1384-1 assume !(1 == ~T9_E~0); 279075#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 279584#L1394-1 assume !(1 == ~T11_E~0); 279585#L1399-1 assume !(1 == ~T12_E~0); 279697#L1404-1 assume !(1 == ~E_M~0); 279698#L1409-1 assume !(1 == ~E_1~0); 279683#L1414-1 assume !(1 == ~E_2~0); 279684#L1419-1 assume !(1 == ~E_3~0); 278057#L1424-1 assume !(1 == ~E_4~0); 278058#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 279606#L1434-1 assume !(1 == ~E_6~0); 279607#L1439-1 assume !(1 == ~E_7~0); 278112#L1444-1 assume !(1 == ~E_8~0); 278113#L1449-1 assume !(1 == ~E_9~0); 278525#L1454-1 assume !(1 == ~E_10~0); 278526#L1459-1 assume !(1 == ~E_11~0); 279111#L1464-1 assume !(1 == ~E_12~0); 279112#L1469-1 assume { :end_inline_reset_delta_events } true; 319438#L1815-2 [2022-07-14 16:03:23,267 INFO L754 eck$LassoCheckResult]: Loop: 319438#L1815-2 assume !false; 319428#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 319419#L1181 assume !false; 319417#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 319267#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 319254#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 319251#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 319245#L1008 assume !(0 != eval_~tmp~0#1); 319246#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 320861#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 320859#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 320856#L1206-5 assume !(0 == ~T1_E~0); 320854#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 320852#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 320851#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 320849#L1226-3 assume !(0 == ~T5_E~0); 320847#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 320845#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 320843#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 320841#L1246-3 assume !(0 == ~T9_E~0); 320838#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 320836#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 320834#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 320832#L1266-3 assume !(0 == ~E_M~0); 320830#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 320828#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 320825#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 320823#L1286-3 assume !(0 == ~E_4~0); 320821#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 320819#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 320817#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 320815#L1306-3 assume !(0 == ~E_8~0); 320812#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 320810#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 320808#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 320806#L1326-3 assume !(0 == ~E_12~0); 320804#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 320802#L598-42 assume !(1 == ~m_pc~0); 320799#L598-44 is_master_triggered_~__retres1~0#1 := 0; 320797#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 320795#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 320793#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 320791#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 320789#L617-42 assume 1 == ~t1_pc~0; 320786#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 320784#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 320782#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 320731#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 320728#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320727#L636-42 assume !(1 == ~t2_pc~0); 297343#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 320349#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320348#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 320347#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 320346#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320345#L655-42 assume 1 == ~t3_pc~0; 320343#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 320342#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320341#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 320340#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 320339#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 320338#L674-42 assume !(1 == ~t4_pc~0); 320336#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 320335#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320334#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 320333#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 320332#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 320331#L693-42 assume 1 == ~t5_pc~0; 320328#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 320325#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 320323#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 320321#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 320319#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 320317#L712-42 assume !(1 == ~t6_pc~0); 320314#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 320313#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 320310#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 320308#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 320306#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 320304#L731-42 assume 1 == ~t7_pc~0; 320301#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 320299#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 320296#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 320294#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 320292#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 320290#L750-42 assume 1 == ~t8_pc~0; 320288#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 320285#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 320282#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 320280#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 320278#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 320276#L769-42 assume 1 == ~t9_pc~0; 320273#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 320271#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 320268#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 320266#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 320264#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 320262#L788-42 assume 1 == ~t10_pc~0; 320256#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 320254#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 320252#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 320250#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 320248#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 320246#L807-42 assume !(1 == ~t11_pc~0); 320242#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 320240#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 320238#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 320236#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 320234#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 320232#L826-42 assume 1 == ~t12_pc~0; 320228#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 320226#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 320224#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 320222#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 320220#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 320218#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 279227#L1344-5 assume !(1 == ~T1_E~0); 320214#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 320212#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 320210#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 320208#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 320204#L1369-3 assume !(1 == ~T6_E~0); 320202#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 320200#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 320199#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 315066#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 320198#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 320197#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 320196#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 320195#L1409-3 assume !(1 == ~E_1~0); 279655#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 279656#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 279375#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 278161#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 278162#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 279166#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 278102#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 278103#L1449-3 assume !(1 == ~E_9~0); 278212#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 279158#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 279159#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 279601#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 279028#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 278004#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 278005#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 278620#L1834 assume !(0 == start_simulation_~tmp~3#1); 279279#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 279488#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 319495#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 319494#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 319492#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 319490#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 319449#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 319448#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 319438#L1815-2 [2022-07-14 16:03:23,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:23,267 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2022-07-14 16:03:23,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:23,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248303665] [2022-07-14 16:03:23,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:23,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:23,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:23,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:23,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:23,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248303665] [2022-07-14 16:03:23,299 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248303665] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:23,299 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:23,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:23,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16722107] [2022-07-14 16:03:23,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:23,299 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:23,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:23,300 INFO L85 PathProgramCache]: Analyzing trace with hash -1174420838, now seen corresponding path program 1 times [2022-07-14 16:03:23,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:23,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709576932] [2022-07-14 16:03:23,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:23,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:23,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:23,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:23,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:23,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709576932] [2022-07-14 16:03:23,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709576932] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:23,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:23,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:23,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485345065] [2022-07-14 16:03:23,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:23,321 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:23,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:23,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:23,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:23,322 INFO L87 Difference]: Start difference. First operand 43656 states and 62783 transitions. cyclomatic complexity: 19143 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:23,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:23,594 INFO L93 Difference]: Finished difference Result 83655 states and 119840 transitions. [2022-07-14 16:03:23,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:23,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83655 states and 119840 transitions. [2022-07-14 16:03:24,034 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83332 [2022-07-14 16:03:24,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83655 states to 83655 states and 119840 transitions. [2022-07-14 16:03:24,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83655 [2022-07-14 16:03:24,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83655 [2022-07-14 16:03:24,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83655 states and 119840 transitions. [2022-07-14 16:03:24,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:24,385 INFO L369 hiAutomatonCegarLoop]: Abstraction has 83655 states and 119840 transitions. [2022-07-14 16:03:24,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83655 states and 119840 transitions. [2022-07-14 16:03:24,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83655 to 83591. [2022-07-14 16:03:25,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83591 states, 83591 states have (on average 1.4328815303082867) internal successors, (119776), 83590 states have internal predecessors, (119776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:25,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83591 states to 83591 states and 119776 transitions. [2022-07-14 16:03:25,369 INFO L392 hiAutomatonCegarLoop]: Abstraction has 83591 states and 119776 transitions. [2022-07-14 16:03:25,369 INFO L374 stractBuchiCegarLoop]: Abstraction has 83591 states and 119776 transitions. [2022-07-14 16:03:25,369 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 16:03:25,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83591 states and 119776 transitions. [2022-07-14 16:03:25,556 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83268 [2022-07-14 16:03:25,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:25,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:25,558 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:25,558 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:25,559 INFO L752 eck$LassoCheckResult]: Stem: 405998#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 405999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 405414#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 405384#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 405385#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 406741#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405696#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 405150#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 405151#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 406483#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 406631#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 407182#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 407183#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 405910#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 405911#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 406513#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 406419#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 406420#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 406591#L1206 assume !(0 == ~M_E~0); 405887#L1206-2 assume !(0 == ~T1_E~0); 405888#L1211-1 assume !(0 == ~T2_E~0); 406915#L1216-1 assume !(0 == ~T3_E~0); 405677#L1221-1 assume !(0 == ~T4_E~0); 405678#L1226-1 assume !(0 == ~T5_E~0); 405336#L1231-1 assume !(0 == ~T6_E~0); 405337#L1236-1 assume !(0 == ~T7_E~0); 406967#L1241-1 assume !(0 == ~T8_E~0); 405738#L1246-1 assume !(0 == ~T9_E~0); 405739#L1251-1 assume !(0 == ~T10_E~0); 405965#L1256-1 assume !(0 == ~T11_E~0); 405162#L1261-1 assume !(0 == ~T12_E~0); 405163#L1266-1 assume !(0 == ~E_M~0); 407153#L1271-1 assume !(0 == ~E_1~0); 406618#L1276-1 assume !(0 == ~E_2~0); 406619#L1281-1 assume !(0 == ~E_3~0); 406541#L1286-1 assume !(0 == ~E_4~0); 405577#L1291-1 assume !(0 == ~E_5~0); 405578#L1296-1 assume !(0 == ~E_6~0); 406330#L1301-1 assume !(0 == ~E_7~0); 406331#L1306-1 assume !(0 == ~E_8~0); 406834#L1311-1 assume !(0 == ~E_9~0); 405536#L1316-1 assume !(0 == ~E_10~0); 405537#L1321-1 assume !(0 == ~E_11~0); 406347#L1326-1 assume !(0 == ~E_12~0); 405402#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405403#L598 assume !(1 == ~m_pc~0); 406119#L598-2 is_master_triggered_~__retres1~0#1 := 0; 406120#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406940#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 407092#L1497 assume !(0 != activate_threads_~tmp~1#1); 407093#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 407013#L617 assume !(1 == ~t1_pc~0); 405762#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 405763#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 405620#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 405621#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 406437#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 406438#L636 assume !(1 == ~t2_pc~0); 407034#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 406192#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 405558#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 405559#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 406482#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 406092#L655 assume !(1 == ~t3_pc~0); 406093#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 406946#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 405432#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 405433#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 407157#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 407158#L674 assume !(1 == ~t4_pc~0); 406922#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 406923#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 406625#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 405560#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 405561#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406089#L693 assume !(1 == ~t5_pc~0); 406278#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 405892#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405893#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 406838#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 405977#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 405912#L712 assume 1 == ~t6_pc~0; 405913#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 406380#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 406381#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 406705#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 406500#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406497#L731 assume 1 == ~t7_pc~0; 405406#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 405407#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 405603#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 406613#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 406758#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 405514#L750 assume !(1 == ~t8_pc~0); 405193#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 405192#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 405708#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 406851#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 405844#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 405845#L769 assume 1 == ~t9_pc~0; 406435#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 405359#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 405360#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 406167#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 406677#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 406783#L788 assume !(1 == ~t10_pc~0); 406292#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 406293#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 406556#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 406557#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 405510#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 405511#L807 assume 1 == ~t11_pc~0; 406795#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 406307#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 406484#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 406999#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 407238#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406921#L826 assume !(1 == ~t12_pc~0); 405915#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405916#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 406508#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 407062#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 406082#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 405986#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 405987#L1344-2 assume !(1 == ~T1_E~0); 414550#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 414549#L1354-1 assume !(1 == ~T3_E~0); 414548#L1359-1 assume !(1 == ~T4_E~0); 414547#L1364-1 assume !(1 == ~T5_E~0); 414546#L1369-1 assume !(1 == ~T6_E~0); 406746#L1374-1 assume !(1 == ~T7_E~0); 406345#L1379-1 assume !(1 == ~T8_E~0); 406346#L1384-1 assume !(1 == ~T9_E~0); 406418#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 417030#L1394-1 assume !(1 == ~T11_E~0); 417026#L1399-1 assume !(1 == ~T12_E~0); 417021#L1404-1 assume !(1 == ~E_M~0); 414229#L1409-1 assume !(1 == ~E_1~0); 414215#L1414-1 assume !(1 == ~E_2~0); 414213#L1419-1 assume !(1 == ~E_3~0); 414211#L1424-1 assume !(1 == ~E_4~0); 414209#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 414207#L1434-1 assume !(1 == ~E_6~0); 414205#L1439-1 assume !(1 == ~E_7~0); 414204#L1444-1 assume !(1 == ~E_8~0); 413388#L1449-1 assume !(1 == ~E_9~0); 412635#L1454-1 assume !(1 == ~E_10~0); 412633#L1459-1 assume !(1 == ~E_11~0); 412631#L1464-1 assume !(1 == ~E_12~0); 412627#L1469-1 assume { :end_inline_reset_delta_events } true; 412624#L1815-2 [2022-07-14 16:03:25,559 INFO L754 eck$LassoCheckResult]: Loop: 412624#L1815-2 assume !false; 412622#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 412615#L1181 assume !false; 412613#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 412323#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 412312#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 412308#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 412305#L1008 assume !(0 != eval_~tmp~0#1); 412306#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 426172#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 426171#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 426170#L1206-5 assume !(0 == ~T1_E~0); 426169#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 426168#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 426167#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 426166#L1226-3 assume !(0 == ~T5_E~0); 426165#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 426164#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 426163#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 426162#L1246-3 assume !(0 == ~T9_E~0); 426161#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 426160#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 426159#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 426158#L1266-3 assume !(0 == ~E_M~0); 426157#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 426156#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 426155#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 426154#L1286-3 assume !(0 == ~E_4~0); 426153#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 426152#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 426151#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 426150#L1306-3 assume !(0 == ~E_8~0); 426149#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 426148#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 426147#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 426146#L1326-3 assume !(0 == ~E_12~0); 426145#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 426144#L598-42 assume !(1 == ~m_pc~0); 426143#L598-44 is_master_triggered_~__retres1~0#1 := 0; 426142#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 426141#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 426140#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 426139#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 426138#L617-42 assume 1 == ~t1_pc~0; 426136#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 426134#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 426132#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 426130#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 426129#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 426128#L636-42 assume !(1 == ~t2_pc~0); 416872#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 426127#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426126#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 426125#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 426124#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 426123#L655-42 assume !(1 == ~t3_pc~0); 426122#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 426120#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 426119#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 426118#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 426117#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 426116#L674-42 assume !(1 == ~t4_pc~0); 426115#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 426114#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 408015#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 408016#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 423789#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423788#L693-42 assume 1 == ~t5_pc~0; 423786#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 418999#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418996#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 418994#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 418992#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 418990#L712-42 assume 1 == ~t6_pc~0; 418988#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 418985#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418982#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 418980#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 418978#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 418976#L731-42 assume 1 == ~t7_pc~0; 418970#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 418968#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 418966#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 418964#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 418962#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 418960#L750-42 assume !(1 == ~t8_pc~0); 418956#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 418954#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 418952#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 418950#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 418948#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 418946#L769-42 assume 1 == ~t9_pc~0; 418942#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 418940#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 418938#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 418936#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 418934#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 418933#L788-42 assume !(1 == ~t10_pc~0); 418930#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 418927#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 418925#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 418923#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 418393#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 418382#L807-42 assume 1 == ~t11_pc~0; 418372#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 418363#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 414535#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 414533#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 414531#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 414529#L826-42 assume 1 == ~t12_pc~0; 414526#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 414524#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 414522#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 414520#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 414518#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414516#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 407702#L1344-5 assume !(1 == ~T1_E~0); 414514#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 414510#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 414508#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 414506#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 414504#L1369-3 assume !(1 == ~T6_E~0); 414502#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 414500#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 414498#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 414494#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 414492#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 414491#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 414489#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 414487#L1409-3 assume !(1 == ~E_1~0); 414485#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 414483#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 414481#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 411787#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 414479#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 414478#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 414476#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 414474#L1449-3 assume !(1 == ~E_9~0); 414472#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 414470#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 414468#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 414464#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 414457#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 414444#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 413399#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 413396#L1834 assume !(0 == start_simulation_~tmp~3#1); 413393#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 412655#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 412646#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 412644#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 412642#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 412640#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 412638#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 412626#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 412624#L1815-2 [2022-07-14 16:03:25,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:25,560 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2022-07-14 16:03:25,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:25,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530041639] [2022-07-14 16:03:25,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:25,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:25,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:25,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:25,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:25,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530041639] [2022-07-14 16:03:25,584 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [530041639] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:25,584 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:25,584 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:25,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901093278] [2022-07-14 16:03:25,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:25,585 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:25,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:25,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1266244005, now seen corresponding path program 1 times [2022-07-14 16:03:25,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:25,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801266584] [2022-07-14 16:03:25,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:25,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:25,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:25,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:25,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:25,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801266584] [2022-07-14 16:03:25,606 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801266584] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:25,606 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:25,606 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:25,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794706956] [2022-07-14 16:03:25,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:25,607 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:25,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:25,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:25,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:25,607 INFO L87 Difference]: Start difference. First operand 83591 states and 119776 transitions. cyclomatic complexity: 36217 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:26,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:26,721 INFO L93 Difference]: Finished difference Result 202670 states and 288625 transitions. [2022-07-14 16:03:26,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:26,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202670 states and 288625 transitions. [2022-07-14 16:03:27,531 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 199052 [2022-07-14 16:03:28,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202670 states to 202670 states and 288625 transitions. [2022-07-14 16:03:28,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202670 [2022-07-14 16:03:28,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202670 [2022-07-14 16:03:28,314 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202670 states and 288625 transitions. [2022-07-14 16:03:28,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:28,391 INFO L369 hiAutomatonCegarLoop]: Abstraction has 202670 states and 288625 transitions. [2022-07-14 16:03:28,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202670 states and 288625 transitions. [2022-07-14 16:03:29,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202670 to 160034. [2022-07-14 16:03:29,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160034 states, 160034 states have (on average 1.4280527887823837) internal successors, (228537), 160033 states have internal predecessors, (228537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:30,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160034 states to 160034 states and 228537 transitions. [2022-07-14 16:03:30,160 INFO L392 hiAutomatonCegarLoop]: Abstraction has 160034 states and 228537 transitions. [2022-07-14 16:03:30,160 INFO L374 stractBuchiCegarLoop]: Abstraction has 160034 states and 228537 transitions. [2022-07-14 16:03:30,160 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-14 16:03:30,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160034 states and 228537 transitions. [2022-07-14 16:03:30,849 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 159616 [2022-07-14 16:03:30,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:30,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:30,853 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:30,853 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:30,854 INFO L752 eck$LassoCheckResult]: Stem: 692256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 692257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 691684#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 691657#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 691658#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 692979#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 691960#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 691421#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 691422#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692727#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692876#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 693397#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 693398#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 692168#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 692169#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 692756#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 692668#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 692669#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692835#L1206 assume !(0 == ~M_E~0); 692144#L1206-2 assume !(0 == ~T1_E~0); 692145#L1211-1 assume !(0 == ~T2_E~0); 693147#L1216-1 assume !(0 == ~T3_E~0); 691942#L1221-1 assume !(0 == ~T4_E~0); 691943#L1226-1 assume !(0 == ~T5_E~0); 691609#L1231-1 assume !(0 == ~T6_E~0); 691610#L1236-1 assume !(0 == ~T7_E~0); 693199#L1241-1 assume !(0 == ~T8_E~0); 692001#L1246-1 assume !(0 == ~T9_E~0); 692002#L1251-1 assume !(0 == ~T10_E~0); 692221#L1256-1 assume !(0 == ~T11_E~0); 691433#L1261-1 assume !(0 == ~T12_E~0); 691434#L1266-1 assume !(0 == ~E_M~0); 693373#L1271-1 assume !(0 == ~E_1~0); 692863#L1276-1 assume !(0 == ~E_2~0); 692864#L1281-1 assume !(0 == ~E_3~0); 692786#L1286-1 assume !(0 == ~E_4~0); 691845#L1291-1 assume !(0 == ~E_5~0); 691846#L1296-1 assume !(0 == ~E_6~0); 692581#L1301-1 assume !(0 == ~E_7~0); 692582#L1306-1 assume !(0 == ~E_8~0); 693071#L1311-1 assume !(0 == ~E_9~0); 691807#L1316-1 assume !(0 == ~E_10~0); 691808#L1321-1 assume !(0 == ~E_11~0); 692598#L1326-1 assume !(0 == ~E_12~0); 691674#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 691675#L598 assume !(1 == ~m_pc~0); 692377#L598-2 is_master_triggered_~__retres1~0#1 := 0; 692378#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693168#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 693320#L1497 assume !(0 != activate_threads_~tmp~1#1); 693321#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 693244#L617 assume !(1 == ~t1_pc~0); 692023#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692024#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 691885#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 691886#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 692686#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692687#L636 assume !(1 == ~t2_pc~0); 693266#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692451#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 691826#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 691827#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 692726#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692350#L655 assume !(1 == ~t3_pc~0); 692351#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 693178#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691702#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 691703#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 693374#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693375#L674 assume !(1 == ~t4_pc~0); 693153#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 693154#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692870#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 691830#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 691831#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692344#L693 assume !(1 == ~t5_pc~0); 692529#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692149#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692150#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 693073#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 692233#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692170#L712 assume !(1 == ~t6_pc~0); 692171#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692633#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692634#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 692950#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 692744#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 692742#L731 assume 1 == ~t7_pc~0; 691676#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 691677#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691870#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 692859#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 692997#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 691784#L750 assume !(1 == ~t8_pc~0); 691464#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691463#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691971#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 693088#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 692103#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692104#L769 assume 1 == ~t9_pc~0; 692684#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 691630#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 691631#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 692422#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 692922#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 693021#L788 assume !(1 == ~t10_pc~0); 692545#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 692546#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 692803#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 692804#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 691782#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 691783#L807 assume 1 == ~t11_pc~0; 693030#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 692560#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 692728#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 693231#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 693445#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 693152#L826 assume !(1 == ~t12_pc~0); 692174#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 692175#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 692751#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 693290#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 692337#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692242#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 692243#L1344-2 assume !(1 == ~T1_E~0); 692396#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 692589#L1354-1 assume !(1 == ~T3_E~0); 692590#L1359-1 assume !(1 == ~T4_E~0); 693009#L1364-1 assume !(1 == ~T5_E~0); 691887#L1369-1 assume !(1 == ~T6_E~0); 691888#L1374-1 assume !(1 == ~T7_E~0); 692596#L1379-1 assume !(1 == ~T8_E~0); 692597#L1384-1 assume !(1 == ~T9_E~0); 692667#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 693203#L1394-1 assume !(1 == ~T11_E~0); 693204#L1399-1 assume !(1 == ~T12_E~0); 693333#L1404-1 assume !(1 == ~E_M~0); 693334#L1409-1 assume !(1 == ~E_1~0); 693317#L1414-1 assume !(1 == ~E_2~0); 693318#L1419-1 assume !(1 == ~E_3~0); 691643#L1424-1 assume !(1 == ~E_4~0); 691644#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 692607#L1434-1 assume !(1 == ~E_6~0); 693228#L1439-1 assume !(1 == ~E_7~0); 691698#L1444-1 assume !(1 == ~E_8~0); 691699#L1449-1 assume !(1 == ~E_9~0); 692108#L1454-1 assume !(1 == ~E_10~0); 692109#L1459-1 assume !(1 == ~E_11~0); 692705#L1464-1 assume !(1 == ~E_12~0); 692706#L1469-1 assume { :end_inline_reset_delta_events } true; 692757#L1815-2 [2022-07-14 16:03:30,855 INFO L754 eck$LassoCheckResult]: Loop: 692757#L1815-2 assume !false; 842091#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 842086#L1181 assume !false; 842085#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 842082#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 842068#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 842067#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 842065#L1008 assume !(0 != eval_~tmp~0#1); 842066#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 848136#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 848134#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 848133#L1206-5 assume !(0 == ~T1_E~0); 848132#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 848131#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 848129#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 848127#L1226-3 assume !(0 == ~T5_E~0); 848125#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 848123#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 848121#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 848119#L1246-3 assume !(0 == ~T9_E~0); 848115#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 848113#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 848111#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 848109#L1266-3 assume !(0 == ~E_M~0); 848106#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 848104#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 848103#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 848102#L1286-3 assume !(0 == ~E_4~0); 848101#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 848100#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 848099#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 848098#L1306-3 assume !(0 == ~E_8~0); 848097#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 848096#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 848095#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 848094#L1326-3 assume !(0 == ~E_12~0); 848093#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 848092#L598-42 assume !(1 == ~m_pc~0); 848091#L598-44 is_master_triggered_~__retres1~0#1 := 0; 848090#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 848089#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 848088#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 848087#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 848086#L617-42 assume !(1 == ~t1_pc~0); 848084#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 848082#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 848080#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 848079#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 846826#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 693313#L636-42 assume !(1 == ~t2_pc~0); 692408#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 692409#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 693436#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 693087#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 693003#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692841#L655-42 assume 1 == ~t3_pc~0; 692842#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 692380#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692003#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 692004#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 693175#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693094#L674-42 assume !(1 == ~t4_pc~0); 692827#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 692745#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 691592#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 691593#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 692527#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692528#L693-42 assume !(1 == ~t5_pc~0); 692811#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 692810#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692872#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 692867#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 692868#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692115#L712-42 assume !(1 == ~t6_pc~0); 692116#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 840623#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 840621#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 840618#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 840616#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 840614#L731-42 assume !(1 == ~t7_pc~0); 840612#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 840609#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 840607#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 840604#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 840602#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 840600#L750-42 assume !(1 == ~t8_pc~0); 840597#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 840595#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 840593#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 840590#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 840588#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 840586#L769-42 assume !(1 == ~t9_pc~0); 840584#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 840581#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 840579#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 840576#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 840574#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 840572#L788-42 assume 1 == ~t10_pc~0; 840569#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 840567#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 840565#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 840564#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 840562#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 840560#L807-42 assume !(1 == ~t11_pc~0); 840557#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 840555#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 840553#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 840550#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 840548#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 840546#L826-42 assume 1 == ~t12_pc~0; 840543#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 840541#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 840539#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 840536#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 840534#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 840532#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 807972#L1344-5 assume !(1 == ~T1_E~0); 840529#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 840527#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 840524#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 840522#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 840520#L1369-3 assume !(1 == ~T6_E~0); 840518#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 840516#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 840514#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 830058#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 840510#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 840508#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 840506#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 840504#L1409-3 assume !(1 == ~E_1~0); 840502#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 840499#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 840497#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 823157#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 840494#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 840492#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 840490#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 840487#L1449-3 assume !(1 == ~E_9~0); 840485#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 840483#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 840481#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 807913#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 692617#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 691590#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 691591#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 692201#L1834 assume !(0 == start_simulation_~tmp~3#1); 693389#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 842115#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 842105#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 842104#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 842101#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 842099#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 842097#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 842096#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 692757#L1815-2 [2022-07-14 16:03:30,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:30,855 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2022-07-14 16:03:30,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:30,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905993485] [2022-07-14 16:03:30,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:30,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:30,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:30,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:30,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:30,890 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905993485] [2022-07-14 16:03:30,890 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905993485] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:30,890 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:30,890 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:30,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456534810] [2022-07-14 16:03:30,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:30,891 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:30,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:30,893 INFO L85 PathProgramCache]: Analyzing trace with hash 2074182241, now seen corresponding path program 1 times [2022-07-14 16:03:30,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:30,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397812052] [2022-07-14 16:03:30,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:30,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:30,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:30,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:30,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:30,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [397812052] [2022-07-14 16:03:30,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [397812052] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:30,924 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:30,924 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:30,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109542246] [2022-07-14 16:03:30,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:30,925 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:30,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:30,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:30,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:30,925 INFO L87 Difference]: Start difference. First operand 160034 states and 228537 transitions. cyclomatic complexity: 68535 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:32,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:32,733 INFO L93 Difference]: Finished difference Result 387109 states and 549562 transitions. [2022-07-14 16:03:32,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:32,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 387109 states and 549562 transitions. [2022-07-14 16:03:34,361 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 380132 [2022-07-14 16:03:35,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 387109 states to 387109 states and 549562 transitions. [2022-07-14 16:03:35,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 387109 [2022-07-14 16:03:35,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 387109 [2022-07-14 16:03:35,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387109 states and 549562 transitions. [2022-07-14 16:03:35,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:35,544 INFO L369 hiAutomatonCegarLoop]: Abstraction has 387109 states and 549562 transitions. [2022-07-14 16:03:35,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387109 states and 549562 transitions. [2022-07-14 16:03:38,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387109 to 306129. [2022-07-14 16:03:38,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306129 states, 306129 states have (on average 1.423576335466421) internal successors, (435798), 306128 states have internal predecessors, (435798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306129 states to 306129 states and 435798 transitions. [2022-07-14 16:03:39,696 INFO L392 hiAutomatonCegarLoop]: Abstraction has 306129 states and 435798 transitions. [2022-07-14 16:03:39,696 INFO L374 stractBuchiCegarLoop]: Abstraction has 306129 states and 435798 transitions. [2022-07-14 16:03:39,696 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-14 16:03:39,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306129 states and 435798 transitions. [2022-07-14 16:03:40,383 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 305520 [2022-07-14 16:03:40,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:40,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:40,386 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:40,386 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:40,386 INFO L752 eck$LassoCheckResult]: Stem: 1239415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1239416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1238834#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1238811#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1238812#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1240167#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1239111#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1238574#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1238575#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1239901#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1240061#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1240642#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1240643#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1239324#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1239325#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1239932#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1239842#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1239843#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1240011#L1206 assume !(0 == ~M_E~0); 1239299#L1206-2 assume !(0 == ~T1_E~0); 1239300#L1211-1 assume !(0 == ~T2_E~0); 1240349#L1216-1 assume !(0 == ~T3_E~0); 1239092#L1221-1 assume !(0 == ~T4_E~0); 1239093#L1226-1 assume !(0 == ~T5_E~0); 1238763#L1231-1 assume !(0 == ~T6_E~0); 1238764#L1236-1 assume !(0 == ~T7_E~0); 1240409#L1241-1 assume !(0 == ~T8_E~0); 1239153#L1246-1 assume !(0 == ~T9_E~0); 1239154#L1251-1 assume !(0 == ~T10_E~0); 1239379#L1256-1 assume !(0 == ~T11_E~0); 1238586#L1261-1 assume !(0 == ~T12_E~0); 1238587#L1266-1 assume !(0 == ~E_M~0); 1240612#L1271-1 assume !(0 == ~E_1~0); 1240048#L1276-1 assume !(0 == ~E_2~0); 1240049#L1281-1 assume !(0 == ~E_3~0); 1239964#L1286-1 assume !(0 == ~E_4~0); 1238995#L1291-1 assume !(0 == ~E_5~0); 1238996#L1296-1 assume !(0 == ~E_6~0); 1239742#L1301-1 assume !(0 == ~E_7~0); 1239743#L1306-1 assume !(0 == ~E_8~0); 1240274#L1311-1 assume !(0 == ~E_9~0); 1238956#L1316-1 assume !(0 == ~E_10~0); 1238957#L1321-1 assume !(0 == ~E_11~0); 1239760#L1326-1 assume !(0 == ~E_12~0); 1238828#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1238829#L598 assume !(1 == ~m_pc~0); 1239537#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1239538#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1240375#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1240543#L1497 assume !(0 != activate_threads_~tmp~1#1); 1240544#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1240461#L617 assume !(1 == ~t1_pc~0); 1239175#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1239176#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1239036#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1239037#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1239859#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1239860#L636 assume !(1 == ~t2_pc~0); 1240484#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1239607#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1238976#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1238977#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1239900#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1239512#L655 assume !(1 == ~t3_pc~0); 1239513#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1240384#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1238853#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1238854#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1240613#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1240614#L674 assume !(1 == ~t4_pc~0); 1240354#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1240355#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1240055#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1238980#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1238981#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1239508#L693 assume !(1 == ~t5_pc~0); 1239689#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1239305#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1239306#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1240276#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1239392#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1239326#L712 assume !(1 == ~t6_pc~0); 1239327#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1239799#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1239800#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1240136#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1239920#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1239916#L731 assume !(1 == ~t7_pc~0); 1239917#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1239020#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1239021#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1240044#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1240191#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1238934#L750 assume !(1 == ~t8_pc~0); 1238617#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1238616#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1239123#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1240291#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1239258#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1239259#L769 assume 1 == ~t9_pc~0; 1239857#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1238784#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1238785#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1239583#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1240108#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1240217#L788 assume !(1 == ~t10_pc~0); 1239704#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1239705#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1239979#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1239980#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1238932#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1238933#L807 assume 1 == ~t11_pc~0; 1240227#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1239721#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1239902#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1240449#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1240691#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1240353#L826 assume !(1 == ~t12_pc~0); 1239330#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1239331#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1239927#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1240510#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1239501#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239401#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 1239402#L1344-2 assume !(1 == ~T1_E~0); 1240677#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1240678#L1354-1 assume !(1 == ~T3_E~0); 1240203#L1359-1 assume !(1 == ~T4_E~0); 1240204#L1364-1 assume !(1 == ~T5_E~0); 1239038#L1369-1 assume !(1 == ~T6_E~0); 1239039#L1374-1 assume !(1 == ~T7_E~0); 1239758#L1379-1 assume !(1 == ~T8_E~0); 1239759#L1384-1 assume !(1 == ~T9_E~0); 1341222#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1341217#L1394-1 assume !(1 == ~T11_E~0); 1341218#L1399-1 assume !(1 == ~T12_E~0); 1341210#L1404-1 assume !(1 == ~E_M~0); 1341211#L1409-1 assume !(1 == ~E_1~0); 1341207#L1414-1 assume !(1 == ~E_2~0); 1341208#L1419-1 assume !(1 == ~E_3~0); 1238797#L1424-1 assume !(1 == ~E_4~0); 1238798#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1240445#L1434-1 assume !(1 == ~E_6~0); 1240446#L1439-1 assume !(1 == ~E_7~0); 1238849#L1444-1 assume !(1 == ~E_8~0); 1238850#L1449-1 assume !(1 == ~E_9~0); 1239263#L1454-1 assume !(1 == ~E_10~0); 1239264#L1459-1 assume !(1 == ~E_11~0); 1239878#L1464-1 assume !(1 == ~E_12~0); 1239879#L1469-1 assume { :end_inline_reset_delta_events } true; 1379530#L1815-2 [2022-07-14 16:03:40,386 INFO L754 eck$LassoCheckResult]: Loop: 1379530#L1815-2 assume !false; 1379528#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1379523#L1181 assume !false; 1379522#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1379456#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1379444#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1379442#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1379360#L1008 assume !(0 != eval_~tmp~0#1); 1379361#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1383842#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1383840#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1383838#L1206-5 assume !(0 == ~T1_E~0); 1383829#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1383825#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1383823#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1383821#L1226-3 assume !(0 == ~T5_E~0); 1383819#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1383816#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1383814#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1383812#L1246-3 assume !(0 == ~T9_E~0); 1383811#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1383809#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1382186#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1382181#L1266-3 assume !(0 == ~E_M~0); 1382175#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1382167#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1382159#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1382151#L1286-3 assume !(0 == ~E_4~0); 1382144#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1381815#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1381813#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1381809#L1306-3 assume !(0 == ~E_8~0); 1381804#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1381799#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1381794#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1381789#L1326-3 assume !(0 == ~E_12~0); 1381784#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1381778#L598-42 assume !(1 == ~m_pc~0); 1381772#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1381767#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1381762#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1381757#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 1381752#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1381746#L617-42 assume !(1 == ~t1_pc~0); 1381741#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1381735#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1381729#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1381723#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 1381717#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1381711#L636-42 assume !(1 == ~t2_pc~0); 1376268#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1381701#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1381696#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1381691#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1381686#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1381680#L655-42 assume !(1 == ~t3_pc~0); 1381676#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1381670#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1381665#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1381660#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1381655#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1381650#L674-42 assume !(1 == ~t4_pc~0); 1381645#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1381639#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1381633#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1381627#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1381335#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1381332#L693-42 assume 1 == ~t5_pc~0; 1381329#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1381327#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1381325#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1381324#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1381323#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1381321#L712-42 assume !(1 == ~t6_pc~0); 1379647#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1381318#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1381316#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1381314#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1381312#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1381305#L731-42 assume !(1 == ~t7_pc~0); 1288815#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1381291#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1381290#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1381289#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1381288#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1381287#L750-42 assume !(1 == ~t8_pc~0); 1381285#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1381283#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1381281#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1381279#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1381277#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1381275#L769-42 assume !(1 == ~t9_pc~0); 1381273#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1381270#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1381268#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1381266#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1381264#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1381262#L788-42 assume !(1 == ~t10_pc~0); 1381260#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1381257#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1381255#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1381253#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1381251#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1381249#L807-42 assume 1 == ~t11_pc~0; 1381247#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1381238#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1381228#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1381227#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1381226#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1381225#L826-42 assume 1 == ~t12_pc~0; 1381223#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1381222#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1381221#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1381220#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1381219#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1381218#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1341784#L1344-5 assume !(1 == ~T1_E~0); 1381217#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1381216#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1381214#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1381212#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1381210#L1369-3 assume !(1 == ~T6_E~0); 1381208#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1381206#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1381204#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1371599#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1381201#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1381199#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1381197#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1381195#L1409-3 assume !(1 == ~E_1~0); 1381193#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1381191#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1381189#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1352118#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1381186#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1381184#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1381182#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1381180#L1449-3 assume !(1 == ~E_9~0); 1381178#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1381176#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1381174#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1341736#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1381168#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1380488#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1380485#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1380481#L1834 assume !(0 == start_simulation_~tmp~3#1); 1380477#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1379558#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1379547#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1379545#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1379543#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1379542#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1379537#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1379536#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1379530#L1815-2 [2022-07-14 16:03:40,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:40,387 INFO L85 PathProgramCache]: Analyzing trace with hash -1728090755, now seen corresponding path program 1 times [2022-07-14 16:03:40,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:40,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831323676] [2022-07-14 16:03:40,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:40,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:40,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:40,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:40,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:40,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831323676] [2022-07-14 16:03:40,413 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831323676] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:40,413 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:40,414 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:40,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372105863] [2022-07-14 16:03:40,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:40,414 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:40,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:40,414 INFO L85 PathProgramCache]: Analyzing trace with hash -505002975, now seen corresponding path program 1 times [2022-07-14 16:03:40,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:40,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050716697] [2022-07-14 16:03:40,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:40,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:40,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:40,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:40,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:40,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050716697] [2022-07-14 16:03:40,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050716697] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:40,434 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:40,434 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:40,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919780052] [2022-07-14 16:03:40,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:40,434 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:40,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:40,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:40,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:40,435 INFO L87 Difference]: Start difference. First operand 306129 states and 435798 transitions. cyclomatic complexity: 129701 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,304 INFO L93 Difference]: Finished difference Result 739572 states and 1059859 transitions. [2022-07-14 16:03:43,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:43,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 739572 states and 1059859 transitions. [2022-07-14 16:03:46,962 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 737952 [2022-07-14 16:03:48,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 739572 states to 739572 states and 1059859 transitions. [2022-07-14 16:03:48,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 739572 [2022-07-14 16:03:49,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 739572 [2022-07-14 16:03:49,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 739572 states and 1059859 transitions. [2022-07-14 16:03:49,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:49,233 INFO L369 hiAutomatonCegarLoop]: Abstraction has 739572 states and 1059859 transitions. [2022-07-14 16:03:49,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 739572 states and 1059859 transitions.