./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.12.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.12.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:03:13,675 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:03:13,677 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:03:13,718 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:03:13,719 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:03:13,720 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:03:13,722 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:03:13,724 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:03:13,727 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:03:13,731 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:03:13,732 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:03:13,734 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:03:13,734 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:03:13,736 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:03:13,737 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:03:13,740 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:03:13,741 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:03:13,742 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:03:13,743 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:03:13,748 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:03:13,750 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:03:13,751 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:03:13,752 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:03:13,752 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:03:13,754 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:03:13,760 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:03:13,760 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:03:13,760 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:03:13,761 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:03:13,762 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:03:13,763 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:03:13,763 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:03:13,764 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:03:13,765 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:03:13,765 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:03:13,766 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:03:13,767 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:03:13,768 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:03:13,768 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:03:13,768 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:03:13,769 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:03:13,770 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:03:13,771 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:03:13,801 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:03:13,801 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:03:13,802 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:03:13,802 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:03:13,804 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:03:13,804 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:03:13,804 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:03:13,804 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:03:13,804 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:03:13,805 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:03:13,805 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:03:13,806 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:03:13,806 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:03:13,806 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:03:13,806 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:03:13,806 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:03:13,807 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:03:13,807 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:03:13,808 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:03:13,808 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:03:13,808 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:03:13,808 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:03:13,808 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:03:13,809 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:03:13,809 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:03:13,809 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:03:13,809 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:03:13,809 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:03:13,810 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:03:13,810 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:03:13,810 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:03:13,811 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:03:13,811 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a [2022-07-14 16:03:14,035 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:03:14,053 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:03:14,055 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:03:14,056 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:03:14,057 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:03:14,058 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2022-07-14 16:03:14,116 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9bbac4cf5/cad8e21cf63845fd8372cb6ad730baf2/FLAGda25b4f3c [2022-07-14 16:03:14,521 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:03:14,522 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2022-07-14 16:03:14,536 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9bbac4cf5/cad8e21cf63845fd8372cb6ad730baf2/FLAGda25b4f3c [2022-07-14 16:03:14,551 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9bbac4cf5/cad8e21cf63845fd8372cb6ad730baf2 [2022-07-14 16:03:14,553 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:03:14,554 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:03:14,555 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:14,555 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:03:14,565 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:03:14,566 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:14,567 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@374276fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14, skipping insertion in model container [2022-07-14 16:03:14,567 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:14,574 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:03:14,620 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:03:14,751 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-2.c[671,684] [2022-07-14 16:03:14,844 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:14,853 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:03:14,863 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-2.c[671,684] [2022-07-14 16:03:14,941 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:14,961 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:03:14,962 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14 WrapperNode [2022-07-14 16:03:14,962 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:14,965 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:14,965 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:03:14,965 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:03:14,971 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:14,986 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,074 INFO L137 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 269, statements flattened = 4134 [2022-07-14 16:03:15,075 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:15,076 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:03:15,076 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:03:15,076 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:03:15,082 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,082 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,091 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,091 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,144 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,182 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,189 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,202 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:03:15,204 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:03:15,204 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:03:15,204 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:03:15,212 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (1/1) ... [2022-07-14 16:03:15,228 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:03:15,237 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:03:15,252 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:03:15,299 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:03:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:03:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:03:15,361 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:03:15,361 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:03:15,483 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:03:15,485 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:03:17,270 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:03:17,285 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:03:17,285 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2022-07-14 16:03:17,288 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:17 BoogieIcfgContainer [2022-07-14 16:03:17,289 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:03:17,290 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:03:17,290 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:03:17,293 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:03:17,293 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:17,293 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:03:14" (1/3) ... [2022-07-14 16:03:17,294 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7177647f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:17, skipping insertion in model container [2022-07-14 16:03:17,294 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:17,295 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:14" (2/3) ... [2022-07-14 16:03:17,295 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7177647f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:17, skipping insertion in model container [2022-07-14 16:03:17,295 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:17,295 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:17" (3/3) ... [2022-07-14 16:03:17,296 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-2.c [2022-07-14 16:03:17,363 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:03:17,363 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:03:17,363 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:03:17,363 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:03:17,363 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:03:17,364 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:03:17,364 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:03:17,364 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:03:17,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1624 [2022-07-14 16:03:17,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,456 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,459 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,459 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:03:17,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1624 [2022-07-14 16:03:17,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:17,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:17,523 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,526 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:17,538 INFO L752 eck$LassoCheckResult]: Stem: 422#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1706#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1157#L1766true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1467#L834true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 156#L841true assume !(1 == ~m_i~0);~m_st~0 := 2; 548#L841-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 108#L846-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1721#L851-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1025#L856-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 449#L861-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 483#L866-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 391#L871-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 751#L876-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 743#L881-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1315#L886-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 250#L891-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1302#L896-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 508#L901-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1190#L1194true assume !(0 == ~M_E~0); 607#L1194-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 878#L1199-1true assume !(0 == ~T2_E~0); 1067#L1204-1true assume !(0 == ~T3_E~0); 796#L1209-1true assume !(0 == ~T4_E~0); 1354#L1214-1true assume !(0 == ~T5_E~0); 1734#L1219-1true assume !(0 == ~T6_E~0); 1656#L1224-1true assume !(0 == ~T7_E~0); 290#L1229-1true assume !(0 == ~T8_E~0); 68#L1234-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 495#L1239-1true assume !(0 == ~T10_E~0); 87#L1244-1true assume !(0 == ~T11_E~0); 1451#L1249-1true assume !(0 == ~T12_E~0); 472#L1254-1true assume !(0 == ~E_M~0); 42#L1259-1true assume !(0 == ~E_1~0); 25#L1264-1true assume !(0 == ~E_2~0); 1781#L1269-1true assume !(0 == ~E_3~0); 1709#L1274-1true assume 0 == ~E_4~0;~E_4~0 := 1; 1441#L1279-1true assume !(0 == ~E_5~0); 125#L1284-1true assume !(0 == ~E_6~0); 1567#L1289-1true assume !(0 == ~E_7~0); 514#L1294-1true assume !(0 == ~E_8~0); 521#L1299-1true assume !(0 == ~E_9~0); 1628#L1304-1true assume !(0 == ~E_10~0); 1670#L1309-1true assume !(0 == ~E_11~0); 1646#L1314-1true assume 0 == ~E_12~0;~E_12~0 := 1; 103#L1319-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67#L586true assume 1 == ~m_pc~0; 1223#L587true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 769#L597true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1774#L598true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 203#L1485true assume !(0 != activate_threads_~tmp~1#1); 1035#L1485-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1726#L605true assume !(1 == ~t1_pc~0); 1180#L605-2true is_transmit1_triggered_~__retres1~1#1 := 0; 407#L616true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1279#L617true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1346#L1493true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 848#L1493-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357#L624true assume 1 == ~t2_pc~0; 90#L625true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 455#L635true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1327#L636true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1430#L1501true assume !(0 != activate_threads_~tmp___1~0#1); 1090#L1501-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 924#L643true assume !(1 == ~t3_pc~0); 765#L643-2true is_transmit3_triggered_~__retres1~3#1 := 0; 531#L654true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 469#L655true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 256#L1509true assume !(0 != activate_threads_~tmp___2~0#1); 1269#L1509-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135#L662true assume 1 == ~t4_pc~0; 444#L663true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 116#L673true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1574#L674true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 552#L1517true assume !(0 != activate_threads_~tmp___3~0#1); 61#L1517-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375#L681true assume !(1 == ~t5_pc~0); 2#L681-2true is_transmit5_triggered_~__retres1~5#1 := 0; 588#L692true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1360#L693true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1267#L1525true assume !(0 != activate_threads_~tmp___4~0#1); 263#L1525-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 722#L700true assume 1 == ~t6_pc~0; 1780#L701true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 130#L711true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376#L712true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 157#L1533true assume !(0 != activate_threads_~tmp___5~0#1); 1160#L1533-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1292#L719true assume 1 == ~t7_pc~0; 1582#L720true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1601#L730true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 754#L731true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1403#L1541true assume !(0 != activate_threads_~tmp___6~0#1); 8#L1541-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1602#L738true assume !(1 == ~t8_pc~0); 885#L738-2true is_transmit8_triggered_~__retres1~8#1 := 0; 789#L749true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 186#L750true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 605#L1549true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1199#L1549-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 944#L757true assume 1 == ~t9_pc~0; 1639#L758true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6#L768true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 708#L769true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1061#L1557true assume !(0 != activate_threads_~tmp___8~0#1); 582#L1557-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1583#L776true assume !(1 == ~t10_pc~0); 1101#L776-2true is_transmit10_triggered_~__retres1~10#1 := 0; 205#L787true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1002#L788true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126#L1565true assume !(0 != activate_threads_~tmp___9~0#1); 759#L1565-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 104#L795true assume 1 == ~t11_pc~0; 273#L796true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1058#L806true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1013#L807true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1324#L1573true assume !(0 != activate_threads_~tmp___10~0#1); 761#L1573-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 746#L814true assume !(1 == ~t12_pc~0); 907#L814-2true is_transmit12_triggered_~__retres1~12#1 := 0; 993#L825true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1150#L826true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1314#L1581true assume !(0 != activate_threads_~tmp___11~0#1); 230#L1581-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1107#L1332true assume !(1 == ~M_E~0); 1497#L1332-2true assume !(1 == ~T1_E~0); 1521#L1337-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 684#L1342-1true assume !(1 == ~T3_E~0); 1435#L1347-1true assume !(1 == ~T4_E~0); 1140#L1352-1true assume !(1 == ~T5_E~0); 949#L1357-1true assume !(1 == ~T6_E~0); 389#L1362-1true assume !(1 == ~T7_E~0); 1209#L1367-1true assume !(1 == ~T8_E~0); 173#L1372-1true assume !(1 == ~T9_E~0); 487#L1377-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 343#L1382-1true assume !(1 == ~T11_E~0); 846#L1387-1true assume !(1 == ~T12_E~0); 1383#L1392-1true assume !(1 == ~E_M~0); 358#L1397-1true assume !(1 == ~E_1~0); 1501#L1402-1true assume !(1 == ~E_2~0); 179#L1407-1true assume !(1 == ~E_3~0); 1620#L1412-1true assume !(1 == ~E_4~0); 1057#L1417-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1792#L1422-1true assume !(1 == ~E_6~0); 1500#L1427-1true assume !(1 == ~E_7~0); 274#L1432-1true assume !(1 == ~E_8~0); 1388#L1437-1true assume !(1 == ~E_9~0); 985#L1442-1true assume !(1 == ~E_10~0); 1297#L1447-1true assume !(1 == ~E_11~0); 834#L1452-1true assume !(1 == ~E_12~0); 75#L1457-1true assume { :end_inline_reset_delta_events } true; 1436#L1803-2true [2022-07-14 16:03:17,545 INFO L754 eck$LassoCheckResult]: Loop: 1436#L1803-2true assume !false; 241#L1804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 315#L1169true assume false; 630#L1184true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1610#L834-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 608#L1194-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1638#L1194-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 161#L1199-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 884#L1204-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 287#L1209-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L1214-3true assume !(0 == ~T5_E~0); 671#L1219-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 406#L1224-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1787#L1229-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 423#L1234-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 92#L1239-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 321#L1244-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 702#L1249-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1542#L1254-3true assume !(0 == ~E_M~0); 1347#L1259-3true assume 0 == ~E_1~0;~E_1~0 := 1; 818#L1264-3true assume 0 == ~E_2~0;~E_2~0 := 1; 95#L1269-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1607#L1274-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1434#L1279-3true assume 0 == ~E_5~0;~E_5~0 := 1; 405#L1284-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1493#L1289-3true assume 0 == ~E_7~0;~E_7~0 := 1; 394#L1294-3true assume !(0 == ~E_8~0); 1659#L1299-3true assume 0 == ~E_9~0;~E_9~0 := 1; 650#L1304-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1011#L1309-3true assume 0 == ~E_11~0;~E_11~0 := 1; 344#L1314-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1735#L1319-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 348#L586-42true assume 1 == ~m_pc~0; 1039#L587-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 129#L597-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1361#L598-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1426#L1485-42true assume !(0 != activate_threads_~tmp~1#1); 418#L1485-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 893#L605-42true assume 1 == ~t1_pc~0; 960#L606-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 623#L616-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984#L617-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 419#L1493-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 470#L1493-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 425#L624-42true assume !(1 == ~t2_pc~0); 520#L624-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1446#L635-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54#L636-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1688#L1501-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 319#L1501-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1284#L643-42true assume 1 == ~t3_pc~0; 532#L644-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 507#L654-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 673#L655-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 402#L1509-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 994#L1509-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1309#L662-42true assume !(1 == ~t4_pc~0); 1370#L662-44true is_transmit4_triggered_~__retres1~4#1 := 0; 140#L673-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 460#L674-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1473#L1517-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1413#L1517-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1326#L681-42true assume !(1 == ~t5_pc~0); 73#L681-44true is_transmit5_triggered_~__retres1~5#1 := 0; 744#L692-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252#L693-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1621#L1525-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1066#L1525-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336#L700-42true assume 1 == ~t6_pc~0; 512#L701-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 951#L711-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1771#L712-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1081#L1533-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1693#L1533-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1458#L719-42true assume 1 == ~t7_pc~0; 740#L720-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 370#L730-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 193#L731-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 530#L1541-42true assume !(0 != activate_threads_~tmp___6~0#1); 379#L1541-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1440#L738-42true assume 1 == ~t8_pc~0; 501#L739-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 353#L749-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114#L750-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94#L1549-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 372#L1549-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1241#L757-42true assume 1 == ~t9_pc~0; 593#L758-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 185#L768-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 258#L769-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 632#L1557-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 245#L1557-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1038#L776-42true assume 1 == ~t10_pc~0; 981#L777-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1026#L787-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1660#L788-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1598#L1565-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1785#L1565-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 788#L795-42true assume 1 == ~t11_pc~0; 1461#L796-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 166#L806-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1561#L807-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 212#L1573-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 385#L1573-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1118#L814-42true assume !(1 == ~t12_pc~0); 310#L814-44true is_transmit12_triggered_~__retres1~12#1 := 0; 121#L825-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1593#L826-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30#L1581-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1736#L1581-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102#L1332-3true assume 1 == ~M_E~0;~M_E~0 := 2; 698#L1332-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 89#L1337-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 553#L1342-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1033#L1347-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 675#L1352-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1192#L1357-3true assume !(1 == ~T6_E~0); 1778#L1362-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1643#L1367-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1611#L1372-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 21#L1377-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 428#L1382-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 332#L1387-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 991#L1392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1700#L1397-3true assume !(1 == ~E_1~0); 1492#L1402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 635#L1407-3true assume 1 == ~E_3~0;~E_3~0 := 2; 145#L1412-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1227#L1417-3true assume 1 == ~E_5~0;~E_5~0 := 2; 566#L1422-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1187#L1427-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1390#L1432-3true assume 1 == ~E_8~0;~E_8~0 := 2; 874#L1437-3true assume !(1 == ~E_9~0); 652#L1442-3true assume 1 == ~E_10~0;~E_10~0 := 2; 887#L1447-3true assume 1 == ~E_11~0;~E_11~0 := 2; 47#L1452-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1748#L1457-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 364#L914-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1401#L981-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 858#L982-1true start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 138#L1822true assume !(0 == start_simulation_~tmp~3#1); 735#L1822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 760#L914-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 270#L981-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 603#L982-2true stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 690#L1777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 791#L1784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 649#L1785true start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1234#L1835true assume !(0 != start_simulation_~tmp___0~1#1); 1436#L1803-2true [2022-07-14 16:03:17,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-07-14 16:03:17,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143834838] [2022-07-14 16:03:17,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,749 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,749 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143834838] [2022-07-14 16:03:17,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143834838] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,750 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,750 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:17,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429321983] [2022-07-14 16:03:17,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,756 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:17,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:17,757 INFO L85 PathProgramCache]: Analyzing trace with hash -754553770, now seen corresponding path program 1 times [2022-07-14 16:03:17,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:17,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159730931] [2022-07-14 16:03:17,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:17,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:17,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:17,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:17,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:17,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159730931] [2022-07-14 16:03:17,801 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159730931] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:17,801 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:17,801 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:17,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392146161] [2022-07-14 16:03:17,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:17,803 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:17,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:17,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-14 16:03:17,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-14 16:03:17,833 INFO L87 Difference]: Start difference. First operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:17,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:17,891 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-07-14 16:03:17,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-14 16:03:17,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2022-07-14 16:03:17,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:17,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1785 states and 2646 transitions. [2022-07-14 16:03:17,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:17,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:17,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2646 transitions. [2022-07-14 16:03:17,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:17,940 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2022-07-14 16:03:17,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2646 transitions. [2022-07-14 16:03:18,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:18,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4823529411764707) internal successors, (2646), 1784 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2646 transitions. [2022-07-14 16:03:18,020 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2022-07-14 16:03:18,020 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2022-07-14 16:03:18,020 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:03:18,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2646 transitions. [2022-07-14 16:03:18,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,031 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,031 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,032 INFO L752 eck$LassoCheckResult]: Stem: 4391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5173#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5174#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3911#L841 assume !(1 == ~m_i~0);~m_st~0 := 2; 3912#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3814#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3815#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5093#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4433#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4434#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4338#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4339#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4841#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4842#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4100#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4101#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4524#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4525#L1194 assume !(0 == ~M_E~0); 4673#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4674#L1199-1 assume !(0 == ~T2_E~0); 4971#L1204-1 assume !(0 == ~T3_E~0); 4895#L1209-1 assume !(0 == ~T4_E~0); 4896#L1214-1 assume !(0 == ~T5_E~0); 5281#L1219-1 assume !(0 == ~T6_E~0); 5369#L1224-1 assume !(0 == ~T7_E~0); 4174#L1229-1 assume !(0 == ~T8_E~0); 3731#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3732#L1239-1 assume !(0 == ~T10_E~0); 3774#L1244-1 assume !(0 == ~T11_E~0); 3775#L1249-1 assume !(0 == ~T12_E~0); 4468#L1254-1 assume !(0 == ~E_M~0); 3678#L1259-1 assume !(0 == ~E_1~0); 3642#L1264-1 assume !(0 == ~E_2~0); 3643#L1269-1 assume !(0 == ~E_3~0); 5372#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5311#L1279-1 assume !(0 == ~E_5~0); 3852#L1284-1 assume !(0 == ~E_6~0); 3853#L1289-1 assume !(0 == ~E_7~0); 4531#L1294-1 assume !(0 == ~E_8~0); 4532#L1299-1 assume !(0 == ~E_9~0); 4542#L1304-1 assume !(0 == ~E_10~0); 5363#L1309-1 assume !(0 == ~E_11~0); 5367#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3806#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3728#L586 assume 1 == ~m_pc~0; 3729#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3800#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4865#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4008#L1485 assume !(0 != activate_threads_~tmp~1#1); 4009#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5096#L605 assume !(1 == ~t1_pc~0); 4612#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4363#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4364#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5246#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4942#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4281#L624 assume 1 == ~t2_pc~0; 3780#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3781#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4441#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5270#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 5133#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5011#L643 assume !(1 == ~t3_pc~0); 4858#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4554#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4467#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4110#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 4111#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3872#L662 assume 1 == ~t4_pc~0; 3873#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3831#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3832#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4586#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 3715#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3716#L681 assume !(1 == ~t5_pc~0); 3590#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3591#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4638#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5240#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 4122#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4123#L700 assume 1 == ~t6_pc~0; 4822#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3863#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3864#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3913#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 3914#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5177#L719 assume 1 == ~t7_pc~0; 5251#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4080#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4850#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4851#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 3604#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3605#L738 assume !(1 == ~t8_pc~0); 4977#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4887#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3973#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3974#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4670#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5034#L757 assume 1 == ~t9_pc~0; 5035#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3599#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3600#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4802#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 4630#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4631#L776 assume !(1 == ~t10_pc~0); 3624#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3623#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4012#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3854#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 3855#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3807#L795 assume 1 == ~t11_pc~0; 3808#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4141#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5085#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5086#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 4856#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4844#L814 assume !(1 == ~t12_pc~0); 4699#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4700#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5070#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5170#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 4065#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4066#L1332 assume !(1 == ~M_E~0); 5144#L1332-2 assume !(1 == ~T1_E~0); 5327#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4769#L1342-1 assume !(1 == ~T3_E~0); 4770#L1347-1 assume !(1 == ~T4_E~0); 5165#L1352-1 assume !(1 == ~T5_E~0); 5040#L1357-1 assume !(1 == ~T6_E~0); 4334#L1362-1 assume !(1 == ~T7_E~0); 4335#L1367-1 assume !(1 == ~T8_E~0); 3948#L1372-1 assume !(1 == ~T9_E~0); 3949#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4254#L1382-1 assume !(1 == ~T11_E~0); 4255#L1387-1 assume !(1 == ~T12_E~0); 4940#L1392-1 assume !(1 == ~E_M~0); 4282#L1397-1 assume !(1 == ~E_1~0); 4283#L1402-1 assume !(1 == ~E_2~0); 3959#L1407-1 assume !(1 == ~E_3~0); 3960#L1412-1 assume !(1 == ~E_4~0); 5111#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5112#L1422-1 assume !(1 == ~E_6~0); 5328#L1427-1 assume !(1 == ~E_7~0); 4142#L1432-1 assume !(1 == ~E_8~0); 4143#L1437-1 assume !(1 == ~E_9~0); 5061#L1442-1 assume !(1 == ~E_10~0); 5062#L1447-1 assume !(1 == ~E_11~0); 4930#L1452-1 assume !(1 == ~E_12~0); 3748#L1457-1 assume { :end_inline_reset_delta_events } true; 3749#L1803-2 [2022-07-14 16:03:18,032 INFO L754 eck$LassoCheckResult]: Loop: 3749#L1803-2 assume !false; 4085#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3621#L1169 assume !false; 4210#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4315#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3816#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3817#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4592#L996 assume !(0 != eval_~tmp~0#1); 4704#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4705#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4675#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4676#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3920#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3921#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4169#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3613#L1214-3 assume !(0 == ~T5_E~0); 3614#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4361#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4362#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4393#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3786#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3787#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4218#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4795#L1254-3 assume !(0 == ~E_M~0); 5275#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4910#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3792#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3793#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5307#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4359#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4360#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4343#L1294-3 assume !(0 == ~E_8~0); 4344#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4726#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4727#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4256#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4257#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4265#L586-42 assume !(1 == ~m_pc~0); 4266#L586-44 is_master_triggered_~__retres1~0#1 := 0; 3861#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3862#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5286#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 4383#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4384#L605-42 assume 1 == ~t1_pc~0; 4981#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4689#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4690#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4385#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4386#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4397#L624-42 assume !(1 == ~t2_pc~0); 4398#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4541#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3701#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3702#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4215#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4216#L643-42 assume 1 == ~t3_pc~0; 4557#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4522#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4523#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4355#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4356#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5071#L662-42 assume !(1 == ~t4_pc~0); 5264#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3884#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3885#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4451#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5303#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5269#L681-42 assume !(1 == ~t5_pc~0); 3744#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 3745#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4104#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4105#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5119#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4241#L700-42 assume 1 == ~t6_pc~0; 4242#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4052#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5041#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5127#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5128#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5317#L719-42 assume !(1 == ~t7_pc~0); 3936#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3937#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3987#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3988#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 4318#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4319#L738-42 assume !(1 == ~t8_pc~0); 4512#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4274#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3827#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3790#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3791#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4311#L757-42 assume 1 == ~t9_pc~0; 4647#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3971#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3972#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4115#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4089#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4090#L776-42 assume 1 == ~t10_pc~0; 5060#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5047#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5094#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5356#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5357#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4884#L795-42 assume !(1 == ~t11_pc~0); 4885#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3931#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3932#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4027#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4028#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4328#L814-42 assume 1 == ~t12_pc~0; 5099#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3843#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3844#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3652#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3653#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3804#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3805#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3778#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3779#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4587#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4758#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4759#L1357-3 assume !(1 == ~T6_E~0); 5197#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5365#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5361#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3633#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3634#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4237#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4238#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5068#L1397-3 assume !(1 == ~E_1~0); 5326#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4709#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3889#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3890#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4606#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4607#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5196#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4965#L1437-3 assume !(1 == ~E_9~0); 4728#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4729#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3687#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3688#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4293#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4139#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4951#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 3880#L1822 assume !(0 == start_simulation_~tmp~3#1); 3881#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4830#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4135#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4136#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 4667#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4779#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4724#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4725#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 3749#L1803-2 [2022-07-14 16:03:18,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-07-14 16:03:18,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215466444] [2022-07-14 16:03:18,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215466444] [2022-07-14 16:03:18,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215466444] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,106 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,106 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116925419] [2022-07-14 16:03:18,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,107 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,108 INFO L85 PathProgramCache]: Analyzing trace with hash 213897014, now seen corresponding path program 1 times [2022-07-14 16:03:18,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161400353] [2022-07-14 16:03:18,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161400353] [2022-07-14 16:03:18,297 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161400353] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,297 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,297 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701719732] [2022-07-14 16:03:18,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,298 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:18,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:18,300 INFO L87 Difference]: Start difference. First operand 1785 states and 2646 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,374 INFO L93 Difference]: Finished difference Result 1785 states and 2645 transitions. [2022-07-14 16:03:18,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:18,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2645 transitions. [2022-07-14 16:03:18,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2645 transitions. [2022-07-14 16:03:18,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:18,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:18,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2645 transitions. [2022-07-14 16:03:18,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,399 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2022-07-14 16:03:18,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2645 transitions. [2022-07-14 16:03:18,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:18,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4817927170868348) internal successors, (2645), 1784 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2645 transitions. [2022-07-14 16:03:18,427 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2022-07-14 16:03:18,428 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2022-07-14 16:03:18,428 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:03:18,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2645 transitions. [2022-07-14 16:03:18,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,439 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,439 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,441 INFO L752 eck$LassoCheckResult]: Stem: 7968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8750#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8751#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7488#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 7489#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7391#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7392#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8670#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8010#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8011#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7915#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7916#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8418#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8419#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7677#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7678#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8101#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8102#L1194 assume !(0 == ~M_E~0); 8250#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8251#L1199-1 assume !(0 == ~T2_E~0); 8548#L1204-1 assume !(0 == ~T3_E~0); 8472#L1209-1 assume !(0 == ~T4_E~0); 8473#L1214-1 assume !(0 == ~T5_E~0); 8858#L1219-1 assume !(0 == ~T6_E~0); 8946#L1224-1 assume !(0 == ~T7_E~0); 7751#L1229-1 assume !(0 == ~T8_E~0); 7308#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7309#L1239-1 assume !(0 == ~T10_E~0); 7351#L1244-1 assume !(0 == ~T11_E~0); 7352#L1249-1 assume !(0 == ~T12_E~0); 8045#L1254-1 assume !(0 == ~E_M~0); 7255#L1259-1 assume !(0 == ~E_1~0); 7219#L1264-1 assume !(0 == ~E_2~0); 7220#L1269-1 assume !(0 == ~E_3~0); 8949#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8888#L1279-1 assume !(0 == ~E_5~0); 7429#L1284-1 assume !(0 == ~E_6~0); 7430#L1289-1 assume !(0 == ~E_7~0); 8108#L1294-1 assume !(0 == ~E_8~0); 8109#L1299-1 assume !(0 == ~E_9~0); 8119#L1304-1 assume !(0 == ~E_10~0); 8940#L1309-1 assume !(0 == ~E_11~0); 8944#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7383#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7305#L586 assume 1 == ~m_pc~0; 7306#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7377#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8442#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7585#L1485 assume !(0 != activate_threads_~tmp~1#1); 7586#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8673#L605 assume !(1 == ~t1_pc~0); 8189#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7940#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7941#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8823#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8519#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7858#L624 assume 1 == ~t2_pc~0; 7357#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7358#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8018#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8847#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 8710#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8588#L643 assume !(1 == ~t3_pc~0); 8435#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8131#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8044#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7687#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 7688#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7449#L662 assume 1 == ~t4_pc~0; 7450#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7408#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7409#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8163#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 7292#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7293#L681 assume !(1 == ~t5_pc~0); 7167#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7168#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8215#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8817#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 7699#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7700#L700 assume 1 == ~t6_pc~0; 8399#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7440#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7441#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7490#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 7491#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8754#L719 assume 1 == ~t7_pc~0; 8828#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7657#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8427#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8428#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 7181#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7182#L738 assume !(1 == ~t8_pc~0); 8554#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8464#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7550#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7551#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8247#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8611#L757 assume 1 == ~t9_pc~0; 8612#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7176#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7177#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8379#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 8207#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8208#L776 assume !(1 == ~t10_pc~0); 7201#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7200#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7589#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7431#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 7432#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7384#L795 assume 1 == ~t11_pc~0; 7385#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7718#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8662#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8663#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 8433#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8421#L814 assume !(1 == ~t12_pc~0); 8276#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8277#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8647#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8747#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 7642#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7643#L1332 assume !(1 == ~M_E~0); 8721#L1332-2 assume !(1 == ~T1_E~0); 8904#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8346#L1342-1 assume !(1 == ~T3_E~0); 8347#L1347-1 assume !(1 == ~T4_E~0); 8742#L1352-1 assume !(1 == ~T5_E~0); 8617#L1357-1 assume !(1 == ~T6_E~0); 7911#L1362-1 assume !(1 == ~T7_E~0); 7912#L1367-1 assume !(1 == ~T8_E~0); 7525#L1372-1 assume !(1 == ~T9_E~0); 7526#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7831#L1382-1 assume !(1 == ~T11_E~0); 7832#L1387-1 assume !(1 == ~T12_E~0); 8517#L1392-1 assume !(1 == ~E_M~0); 7859#L1397-1 assume !(1 == ~E_1~0); 7860#L1402-1 assume !(1 == ~E_2~0); 7536#L1407-1 assume !(1 == ~E_3~0); 7537#L1412-1 assume !(1 == ~E_4~0); 8688#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8689#L1422-1 assume !(1 == ~E_6~0); 8905#L1427-1 assume !(1 == ~E_7~0); 7719#L1432-1 assume !(1 == ~E_8~0); 7720#L1437-1 assume !(1 == ~E_9~0); 8638#L1442-1 assume !(1 == ~E_10~0); 8639#L1447-1 assume !(1 == ~E_11~0); 8507#L1452-1 assume !(1 == ~E_12~0); 7325#L1457-1 assume { :end_inline_reset_delta_events } true; 7326#L1803-2 [2022-07-14 16:03:18,442 INFO L754 eck$LassoCheckResult]: Loop: 7326#L1803-2 assume !false; 7662#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7198#L1169 assume !false; 7787#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7892#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7393#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7394#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8169#L996 assume !(0 != eval_~tmp~0#1); 8281#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8282#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8252#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8253#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7497#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7498#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7746#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7190#L1214-3 assume !(0 == ~T5_E~0); 7191#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7938#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7939#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7970#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7363#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7364#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7795#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8372#L1254-3 assume !(0 == ~E_M~0); 8852#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8487#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7369#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7370#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8884#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7936#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7937#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7920#L1294-3 assume !(0 == ~E_8~0); 7921#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8303#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8304#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7833#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7834#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7842#L586-42 assume !(1 == ~m_pc~0); 7843#L586-44 is_master_triggered_~__retres1~0#1 := 0; 7438#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7439#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8863#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 7960#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7961#L605-42 assume 1 == ~t1_pc~0; 8558#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8266#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8267#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7962#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7963#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L624-42 assume !(1 == ~t2_pc~0); 7975#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8118#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7278#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7279#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7792#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7793#L643-42 assume 1 == ~t3_pc~0; 8134#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8099#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8100#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7932#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7933#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8648#L662-42 assume !(1 == ~t4_pc~0); 8841#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7461#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7462#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8028#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8880#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8846#L681-42 assume 1 == ~t5_pc~0; 8144#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7322#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7681#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7682#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8696#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7818#L700-42 assume 1 == ~t6_pc~0; 7819#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7629#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8618#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8704#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8705#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8894#L719-42 assume !(1 == ~t7_pc~0); 7513#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7514#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7564#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7565#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 7895#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7896#L738-42 assume 1 == ~t8_pc~0; 8088#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7851#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7404#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7367#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7368#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7888#L757-42 assume 1 == ~t9_pc~0; 8224#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7548#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7549#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7692#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7666#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7667#L776-42 assume 1 == ~t10_pc~0; 8637#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8624#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8671#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8933#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8934#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8461#L795-42 assume !(1 == ~t11_pc~0); 8462#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7508#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7509#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7604#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7605#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7905#L814-42 assume 1 == ~t12_pc~0; 8676#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7420#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7421#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7229#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7230#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7381#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7382#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7355#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7356#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8164#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8335#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8336#L1357-3 assume !(1 == ~T6_E~0); 8774#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8942#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8938#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7210#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7211#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7814#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 7815#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8645#L1397-3 assume !(1 == ~E_1~0); 8903#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8286#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7466#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7467#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8183#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8184#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8773#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8542#L1437-3 assume !(1 == ~E_9~0); 8305#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8306#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7264#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7265#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7870#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7716#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8528#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7457#L1822 assume !(0 == start_simulation_~tmp~3#1); 7458#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8407#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7712#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7713#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 8244#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8356#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8301#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8302#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 7326#L1803-2 [2022-07-14 16:03:18,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,445 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-07-14 16:03:18,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325057175] [2022-07-14 16:03:18,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325057175] [2022-07-14 16:03:18,522 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325057175] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,522 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,522 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803239748] [2022-07-14 16:03:18,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,523 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,524 INFO L85 PathProgramCache]: Analyzing trace with hash 561508340, now seen corresponding path program 1 times [2022-07-14 16:03:18,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82647099] [2022-07-14 16:03:18,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82647099] [2022-07-14 16:03:18,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82647099] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,594 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,594 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642075304] [2022-07-14 16:03:18,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,596 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:18,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:18,597 INFO L87 Difference]: Start difference. First operand 1785 states and 2645 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,628 INFO L93 Difference]: Finished difference Result 1785 states and 2644 transitions. [2022-07-14 16:03:18,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:18,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2644 transitions. [2022-07-14 16:03:18,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2644 transitions. [2022-07-14 16:03:18,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:18,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:18,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2644 transitions. [2022-07-14 16:03:18,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,657 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2022-07-14 16:03:18,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2644 transitions. [2022-07-14 16:03:18,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:18,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.481232492997199) internal successors, (2644), 1784 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2644 transitions. [2022-07-14 16:03:18,689 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2022-07-14 16:03:18,689 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2022-07-14 16:03:18,689 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:03:18,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2644 transitions. [2022-07-14 16:03:18,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,703 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,704 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,704 INFO L752 eck$LassoCheckResult]: Stem: 11545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 12327#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12328#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11065#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 11066#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10968#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10969#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12247#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11587#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11588#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11492#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11493#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11995#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11996#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11254#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11255#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11678#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11679#L1194 assume !(0 == ~M_E~0); 11827#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11828#L1199-1 assume !(0 == ~T2_E~0); 12125#L1204-1 assume !(0 == ~T3_E~0); 12049#L1209-1 assume !(0 == ~T4_E~0); 12050#L1214-1 assume !(0 == ~T5_E~0); 12435#L1219-1 assume !(0 == ~T6_E~0); 12523#L1224-1 assume !(0 == ~T7_E~0); 11328#L1229-1 assume !(0 == ~T8_E~0); 10885#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10886#L1239-1 assume !(0 == ~T10_E~0); 10928#L1244-1 assume !(0 == ~T11_E~0); 10929#L1249-1 assume !(0 == ~T12_E~0); 11622#L1254-1 assume !(0 == ~E_M~0); 10832#L1259-1 assume !(0 == ~E_1~0); 10796#L1264-1 assume !(0 == ~E_2~0); 10797#L1269-1 assume !(0 == ~E_3~0); 12526#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12465#L1279-1 assume !(0 == ~E_5~0); 11006#L1284-1 assume !(0 == ~E_6~0); 11007#L1289-1 assume !(0 == ~E_7~0); 11685#L1294-1 assume !(0 == ~E_8~0); 11686#L1299-1 assume !(0 == ~E_9~0); 11696#L1304-1 assume !(0 == ~E_10~0); 12517#L1309-1 assume !(0 == ~E_11~0); 12521#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 10960#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10882#L586 assume 1 == ~m_pc~0; 10883#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10954#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12019#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11162#L1485 assume !(0 != activate_threads_~tmp~1#1); 11163#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12250#L605 assume !(1 == ~t1_pc~0); 11766#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11517#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11518#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12400#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12096#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11435#L624 assume 1 == ~t2_pc~0; 10934#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10935#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11595#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12424#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 12287#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12165#L643 assume !(1 == ~t3_pc~0); 12012#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11708#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11621#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11264#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 11265#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11026#L662 assume 1 == ~t4_pc~0; 11027#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10985#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10986#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11740#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 10869#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10870#L681 assume !(1 == ~t5_pc~0); 10744#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10745#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11792#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12394#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 11276#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11277#L700 assume 1 == ~t6_pc~0; 11976#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11017#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11018#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11067#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 11068#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12331#L719 assume 1 == ~t7_pc~0; 12405#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11234#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12004#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12005#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 10758#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10759#L738 assume !(1 == ~t8_pc~0); 12131#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12041#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11127#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11128#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11824#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12188#L757 assume 1 == ~t9_pc~0; 12189#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10753#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10754#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11956#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 11784#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11785#L776 assume !(1 == ~t10_pc~0); 10778#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10777#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11166#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11008#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 11009#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10961#L795 assume 1 == ~t11_pc~0; 10962#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11295#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12239#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12240#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 12010#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11998#L814 assume !(1 == ~t12_pc~0); 11853#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11854#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12224#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12324#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 11219#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11220#L1332 assume !(1 == ~M_E~0); 12298#L1332-2 assume !(1 == ~T1_E~0); 12481#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11923#L1342-1 assume !(1 == ~T3_E~0); 11924#L1347-1 assume !(1 == ~T4_E~0); 12319#L1352-1 assume !(1 == ~T5_E~0); 12194#L1357-1 assume !(1 == ~T6_E~0); 11488#L1362-1 assume !(1 == ~T7_E~0); 11489#L1367-1 assume !(1 == ~T8_E~0); 11102#L1372-1 assume !(1 == ~T9_E~0); 11103#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11408#L1382-1 assume !(1 == ~T11_E~0); 11409#L1387-1 assume !(1 == ~T12_E~0); 12094#L1392-1 assume !(1 == ~E_M~0); 11436#L1397-1 assume !(1 == ~E_1~0); 11437#L1402-1 assume !(1 == ~E_2~0); 11113#L1407-1 assume !(1 == ~E_3~0); 11114#L1412-1 assume !(1 == ~E_4~0); 12265#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12266#L1422-1 assume !(1 == ~E_6~0); 12482#L1427-1 assume !(1 == ~E_7~0); 11296#L1432-1 assume !(1 == ~E_8~0); 11297#L1437-1 assume !(1 == ~E_9~0); 12215#L1442-1 assume !(1 == ~E_10~0); 12216#L1447-1 assume !(1 == ~E_11~0); 12084#L1452-1 assume !(1 == ~E_12~0); 10902#L1457-1 assume { :end_inline_reset_delta_events } true; 10903#L1803-2 [2022-07-14 16:03:18,704 INFO L754 eck$LassoCheckResult]: Loop: 10903#L1803-2 assume !false; 11239#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10775#L1169 assume !false; 11364#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11469#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10970#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10971#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11746#L996 assume !(0 != eval_~tmp~0#1); 11858#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11859#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11829#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11830#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11074#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11075#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11323#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10767#L1214-3 assume !(0 == ~T5_E~0); 10768#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11515#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11516#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11547#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10940#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10941#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11372#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11949#L1254-3 assume !(0 == ~E_M~0); 12429#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12064#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10946#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10947#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12461#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11513#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11514#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11497#L1294-3 assume !(0 == ~E_8~0); 11498#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11880#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11881#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11410#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11411#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11419#L586-42 assume !(1 == ~m_pc~0); 11420#L586-44 is_master_triggered_~__retres1~0#1 := 0; 11015#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11016#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12440#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 11537#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11538#L605-42 assume 1 == ~t1_pc~0; 12135#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11843#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11844#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11539#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11540#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11551#L624-42 assume !(1 == ~t2_pc~0); 11552#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11695#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10855#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10856#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11369#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11370#L643-42 assume !(1 == ~t3_pc~0); 11712#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11676#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11677#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11509#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11510#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12225#L662-42 assume !(1 == ~t4_pc~0); 12418#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 11038#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11039#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11605#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12457#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12423#L681-42 assume !(1 == ~t5_pc~0); 10898#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 10899#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11258#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11259#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12273#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11395#L700-42 assume 1 == ~t6_pc~0; 11396#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11206#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12195#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12281#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12282#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12471#L719-42 assume !(1 == ~t7_pc~0); 11090#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11091#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11141#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11142#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 11472#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11473#L738-42 assume 1 == ~t8_pc~0; 11665#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11428#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10981#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10944#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10945#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11465#L757-42 assume 1 == ~t9_pc~0; 11801#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11125#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11126#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11269#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11243#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11244#L776-42 assume 1 == ~t10_pc~0; 12214#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12201#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12248#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12510#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12511#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12038#L795-42 assume !(1 == ~t11_pc~0); 12039#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11085#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11086#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11181#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11182#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11482#L814-42 assume 1 == ~t12_pc~0; 12253#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10997#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10998#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10806#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10807#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10958#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10959#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10932#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10933#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11741#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11912#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11913#L1357-3 assume !(1 == ~T6_E~0); 12351#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12519#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12515#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10787#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10788#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11391#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11392#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12222#L1397-3 assume !(1 == ~E_1~0); 12480#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11863#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11043#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11044#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11760#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11761#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12350#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12119#L1437-3 assume !(1 == ~E_9~0); 11882#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11883#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10841#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 10842#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11447#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11293#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12105#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11034#L1822 assume !(0 == start_simulation_~tmp~3#1); 11035#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11984#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11289#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11290#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 11821#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11933#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11878#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11879#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 10903#L1803-2 [2022-07-14 16:03:18,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,706 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-07-14 16:03:18,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770154359] [2022-07-14 16:03:18,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770154359] [2022-07-14 16:03:18,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770154359] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,773 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,773 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491811958] [2022-07-14 16:03:18,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,776 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1260668790, now seen corresponding path program 1 times [2022-07-14 16:03:18,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231601711] [2022-07-14 16:03:18,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,855 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231601711] [2022-07-14 16:03:18,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231601711] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,855 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,856 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200427845] [2022-07-14 16:03:18,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,857 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:18,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:18,858 INFO L87 Difference]: Start difference. First operand 1785 states and 2644 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:18,891 INFO L93 Difference]: Finished difference Result 1785 states and 2643 transitions. [2022-07-14 16:03:18,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:18,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2643 transitions. [2022-07-14 16:03:18,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2643 transitions. [2022-07-14 16:03:18,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:18,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:18,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2643 transitions. [2022-07-14 16:03:18,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:18,917 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2022-07-14 16:03:18,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2643 transitions. [2022-07-14 16:03:18,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:18,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.480672268907563) internal successors, (2643), 1784 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2643 transitions. [2022-07-14 16:03:18,948 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2022-07-14 16:03:18,948 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2022-07-14 16:03:18,948 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:03:18,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2643 transitions. [2022-07-14 16:03:18,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:18,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,958 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,959 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,959 INFO L752 eck$LassoCheckResult]: Stem: 15122#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15904#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15905#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14642#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 14643#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14545#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14546#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15824#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15164#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15165#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15069#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15070#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15572#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15573#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14831#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14832#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15255#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15256#L1194 assume !(0 == ~M_E~0); 15404#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15405#L1199-1 assume !(0 == ~T2_E~0); 15702#L1204-1 assume !(0 == ~T3_E~0); 15626#L1209-1 assume !(0 == ~T4_E~0); 15627#L1214-1 assume !(0 == ~T5_E~0); 16012#L1219-1 assume !(0 == ~T6_E~0); 16100#L1224-1 assume !(0 == ~T7_E~0); 14905#L1229-1 assume !(0 == ~T8_E~0); 14462#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14463#L1239-1 assume !(0 == ~T10_E~0); 14505#L1244-1 assume !(0 == ~T11_E~0); 14506#L1249-1 assume !(0 == ~T12_E~0); 15199#L1254-1 assume !(0 == ~E_M~0); 14409#L1259-1 assume !(0 == ~E_1~0); 14373#L1264-1 assume !(0 == ~E_2~0); 14374#L1269-1 assume !(0 == ~E_3~0); 16103#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16042#L1279-1 assume !(0 == ~E_5~0); 14583#L1284-1 assume !(0 == ~E_6~0); 14584#L1289-1 assume !(0 == ~E_7~0); 15262#L1294-1 assume !(0 == ~E_8~0); 15263#L1299-1 assume !(0 == ~E_9~0); 15273#L1304-1 assume !(0 == ~E_10~0); 16094#L1309-1 assume !(0 == ~E_11~0); 16098#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14537#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14459#L586 assume 1 == ~m_pc~0; 14460#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14531#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15596#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14739#L1485 assume !(0 != activate_threads_~tmp~1#1); 14740#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15827#L605 assume !(1 == ~t1_pc~0); 15343#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15094#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15095#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15977#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15673#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15012#L624 assume 1 == ~t2_pc~0; 14511#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14512#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15172#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16001#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 15864#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15742#L643 assume !(1 == ~t3_pc~0); 15589#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15285#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15198#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14841#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 14842#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14603#L662 assume 1 == ~t4_pc~0; 14604#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14562#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14563#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15317#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 14446#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14447#L681 assume !(1 == ~t5_pc~0); 14321#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14322#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15369#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15971#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 14853#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14854#L700 assume 1 == ~t6_pc~0; 15553#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14594#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14595#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14644#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 14645#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15908#L719 assume 1 == ~t7_pc~0; 15982#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14811#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15581#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15582#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 14335#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14336#L738 assume !(1 == ~t8_pc~0); 15708#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15618#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14704#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14705#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15401#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15765#L757 assume 1 == ~t9_pc~0; 15766#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14330#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14331#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15533#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 15361#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15362#L776 assume !(1 == ~t10_pc~0); 14355#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14354#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14743#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14585#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 14586#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14538#L795 assume 1 == ~t11_pc~0; 14539#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14872#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15816#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15817#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 15587#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15575#L814 assume !(1 == ~t12_pc~0); 15430#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15431#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15801#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15901#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 14796#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14797#L1332 assume !(1 == ~M_E~0); 15875#L1332-2 assume !(1 == ~T1_E~0); 16058#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15500#L1342-1 assume !(1 == ~T3_E~0); 15501#L1347-1 assume !(1 == ~T4_E~0); 15896#L1352-1 assume !(1 == ~T5_E~0); 15771#L1357-1 assume !(1 == ~T6_E~0); 15065#L1362-1 assume !(1 == ~T7_E~0); 15066#L1367-1 assume !(1 == ~T8_E~0); 14679#L1372-1 assume !(1 == ~T9_E~0); 14680#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14985#L1382-1 assume !(1 == ~T11_E~0); 14986#L1387-1 assume !(1 == ~T12_E~0); 15671#L1392-1 assume !(1 == ~E_M~0); 15013#L1397-1 assume !(1 == ~E_1~0); 15014#L1402-1 assume !(1 == ~E_2~0); 14690#L1407-1 assume !(1 == ~E_3~0); 14691#L1412-1 assume !(1 == ~E_4~0); 15842#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15843#L1422-1 assume !(1 == ~E_6~0); 16059#L1427-1 assume !(1 == ~E_7~0); 14873#L1432-1 assume !(1 == ~E_8~0); 14874#L1437-1 assume !(1 == ~E_9~0); 15792#L1442-1 assume !(1 == ~E_10~0); 15793#L1447-1 assume !(1 == ~E_11~0); 15661#L1452-1 assume !(1 == ~E_12~0); 14479#L1457-1 assume { :end_inline_reset_delta_events } true; 14480#L1803-2 [2022-07-14 16:03:18,959 INFO L754 eck$LassoCheckResult]: Loop: 14480#L1803-2 assume !false; 14816#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14352#L1169 assume !false; 14941#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15046#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14547#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14548#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15323#L996 assume !(0 != eval_~tmp~0#1); 15435#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15436#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15406#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15407#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14651#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14652#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14900#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14344#L1214-3 assume !(0 == ~T5_E~0); 14345#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15092#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15093#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15124#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14517#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14518#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14949#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15526#L1254-3 assume !(0 == ~E_M~0); 16006#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15641#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14523#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14524#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16038#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15090#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15091#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15074#L1294-3 assume !(0 == ~E_8~0); 15075#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15457#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15458#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14987#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14988#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14996#L586-42 assume !(1 == ~m_pc~0); 14997#L586-44 is_master_triggered_~__retres1~0#1 := 0; 14592#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14593#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16017#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 15114#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15115#L605-42 assume 1 == ~t1_pc~0; 15712#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15420#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15421#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15116#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15117#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15128#L624-42 assume !(1 == ~t2_pc~0); 15129#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15272#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14432#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14433#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14946#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14947#L643-42 assume 1 == ~t3_pc~0; 15288#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15253#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15254#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15086#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15087#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15802#L662-42 assume !(1 == ~t4_pc~0); 15995#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14615#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14616#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15182#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16034#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16000#L681-42 assume 1 == ~t5_pc~0; 15298#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14476#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14835#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14836#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15850#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14972#L700-42 assume 1 == ~t6_pc~0; 14973#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14783#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15772#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15858#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15859#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16048#L719-42 assume 1 == ~t7_pc~0; 15569#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14668#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14718#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14719#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 15049#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15050#L738-42 assume 1 == ~t8_pc~0; 15242#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15005#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14558#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14521#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14522#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15042#L757-42 assume 1 == ~t9_pc~0; 15378#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14702#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14703#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14846#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14820#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14821#L776-42 assume !(1 == ~t10_pc~0); 15777#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15778#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15825#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16087#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16088#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15615#L795-42 assume !(1 == ~t11_pc~0); 15616#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 14662#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14663#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14758#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14759#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15059#L814-42 assume 1 == ~t12_pc~0; 15830#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14574#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14575#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14383#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14384#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14535#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14536#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14509#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14510#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15318#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15489#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15490#L1357-3 assume !(1 == ~T6_E~0); 15928#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16096#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16092#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14364#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14365#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14968#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14969#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15799#L1397-3 assume !(1 == ~E_1~0); 16057#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15440#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14620#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14621#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15337#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15338#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15927#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15696#L1437-3 assume !(1 == ~E_9~0); 15459#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15460#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14418#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14419#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15024#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14870#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15682#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14611#L1822 assume !(0 == start_simulation_~tmp~3#1); 14612#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15561#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14866#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14867#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 15398#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15510#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15455#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15456#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 14480#L1803-2 [2022-07-14 16:03:18,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-07-14 16:03:18,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791549728] [2022-07-14 16:03:18,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791549728] [2022-07-14 16:03:19,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [791549728] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,003 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,003 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727748183] [2022-07-14 16:03:19,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,003 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,004 INFO L85 PathProgramCache]: Analyzing trace with hash 660676148, now seen corresponding path program 1 times [2022-07-14 16:03:19,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124675803] [2022-07-14 16:03:19,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124675803] [2022-07-14 16:03:19,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124675803] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,047 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442443693] [2022-07-14 16:03:19,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,048 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,049 INFO L87 Difference]: Start difference. First operand 1785 states and 2643 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,077 INFO L93 Difference]: Finished difference Result 1785 states and 2642 transitions. [2022-07-14 16:03:19,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2642 transitions. [2022-07-14 16:03:19,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2642 transitions. [2022-07-14 16:03:19,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:19,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:19,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2642 transitions. [2022-07-14 16:03:19,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,125 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2022-07-14 16:03:19,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2642 transitions. [2022-07-14 16:03:19,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:19,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4801120448179272) internal successors, (2642), 1784 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2642 transitions. [2022-07-14 16:03:19,158 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2022-07-14 16:03:19,158 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2022-07-14 16:03:19,158 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:03:19,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2642 transitions. [2022-07-14 16:03:19,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,167 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,168 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,168 INFO L752 eck$LassoCheckResult]: Stem: 18706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19481#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19482#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18219#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 18220#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18122#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18123#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19401#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18741#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18742#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18646#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18647#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19149#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19150#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18408#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18409#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18834#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18835#L1194 assume !(0 == ~M_E~0); 18981#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18982#L1199-1 assume !(0 == ~T2_E~0); 19279#L1204-1 assume !(0 == ~T3_E~0); 19203#L1209-1 assume !(0 == ~T4_E~0); 19204#L1214-1 assume !(0 == ~T5_E~0); 19589#L1219-1 assume !(0 == ~T6_E~0); 19677#L1224-1 assume !(0 == ~T7_E~0); 18482#L1229-1 assume !(0 == ~T8_E~0); 18047#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18048#L1239-1 assume !(0 == ~T10_E~0); 18086#L1244-1 assume !(0 == ~T11_E~0); 18087#L1249-1 assume !(0 == ~T12_E~0); 18776#L1254-1 assume !(0 == ~E_M~0); 17986#L1259-1 assume !(0 == ~E_1~0); 17950#L1264-1 assume !(0 == ~E_2~0); 17951#L1269-1 assume !(0 == ~E_3~0); 19680#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19619#L1279-1 assume !(0 == ~E_5~0); 18160#L1284-1 assume !(0 == ~E_6~0); 18161#L1289-1 assume !(0 == ~E_7~0); 18840#L1294-1 assume !(0 == ~E_8~0); 18841#L1299-1 assume !(0 == ~E_9~0); 18852#L1304-1 assume !(0 == ~E_10~0); 19671#L1309-1 assume !(0 == ~E_11~0); 19675#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18115#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18036#L586 assume 1 == ~m_pc~0; 18037#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18108#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19175#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18316#L1485 assume !(0 != activate_threads_~tmp~1#1); 18317#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19404#L605 assume !(1 == ~t1_pc~0); 18920#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18671#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18672#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19554#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19251#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18589#L624 assume 1 == ~t2_pc~0; 18091#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18092#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18749#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19578#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 19441#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19319#L643 assume !(1 == ~t3_pc~0); 19166#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18868#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18775#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18418#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 18419#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18180#L662 assume 1 == ~t4_pc~0; 18181#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18141#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18142#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18894#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 18025#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18026#L681 assume !(1 == ~t5_pc~0); 17898#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17899#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18946#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19549#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 18430#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18431#L700 assume 1 == ~t6_pc~0; 19130#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18171#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18172#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18221#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 18222#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19485#L719 assume 1 == ~t7_pc~0; 19562#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18388#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19159#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19160#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 17912#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17913#L738 assume !(1 == ~t8_pc~0); 19285#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19195#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18281#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18282#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18978#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19342#L757 assume 1 == ~t9_pc~0; 19343#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17907#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17908#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19111#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 18938#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18939#L776 assume !(1 == ~t10_pc~0); 17932#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17931#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18323#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18162#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 18163#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18116#L795 assume 1 == ~t11_pc~0; 18117#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18451#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19393#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19394#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 19164#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19152#L814 assume !(1 == ~t12_pc~0); 19007#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19008#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19379#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19478#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 18373#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18374#L1332 assume !(1 == ~M_E~0); 19452#L1332-2 assume !(1 == ~T1_E~0); 19635#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19079#L1342-1 assume !(1 == ~T3_E~0); 19080#L1347-1 assume !(1 == ~T4_E~0); 19474#L1352-1 assume !(1 == ~T5_E~0); 19348#L1357-1 assume !(1 == ~T6_E~0); 18644#L1362-1 assume !(1 == ~T7_E~0); 18645#L1367-1 assume !(1 == ~T8_E~0); 18256#L1372-1 assume !(1 == ~T9_E~0); 18257#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18562#L1382-1 assume !(1 == ~T11_E~0); 18563#L1387-1 assume !(1 == ~T12_E~0); 19248#L1392-1 assume !(1 == ~E_M~0); 18590#L1397-1 assume !(1 == ~E_1~0); 18591#L1402-1 assume !(1 == ~E_2~0); 18269#L1407-1 assume !(1 == ~E_3~0); 18270#L1412-1 assume !(1 == ~E_4~0); 19419#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19420#L1422-1 assume !(1 == ~E_6~0); 19636#L1427-1 assume !(1 == ~E_7~0); 18452#L1432-1 assume !(1 == ~E_8~0); 18453#L1437-1 assume !(1 == ~E_9~0); 19369#L1442-1 assume !(1 == ~E_10~0); 19370#L1447-1 assume !(1 == ~E_11~0); 19239#L1452-1 assume !(1 == ~E_12~0); 18056#L1457-1 assume { :end_inline_reset_delta_events } true; 18057#L1803-2 [2022-07-14 16:03:19,169 INFO L754 eck$LassoCheckResult]: Loop: 18057#L1803-2 assume !false; 18393#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17929#L1169 assume !false; 18520#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18625#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18124#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18125#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18900#L996 assume !(0 != eval_~tmp~0#1); 19012#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19013#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18983#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18984#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18228#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18229#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18477#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17925#L1214-3 assume !(0 == ~T5_E~0); 17926#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18669#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18670#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18699#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18094#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18095#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18526#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 19103#L1254-3 assume !(0 == ~E_M~0); 19583#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19218#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18100#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18101#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19615#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18667#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18668#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18651#L1294-3 assume !(0 == ~E_8~0); 18652#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19034#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19035#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18564#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18565#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18573#L586-42 assume !(1 == ~m_pc~0); 18574#L586-44 is_master_triggered_~__retres1~0#1 := 0; 18169#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18170#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19594#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 18691#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18692#L605-42 assume 1 == ~t1_pc~0; 19289#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18997#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18998#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18693#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18694#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18703#L624-42 assume !(1 == ~t2_pc~0); 18704#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18849#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18009#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18010#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18523#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18524#L643-42 assume 1 == ~t3_pc~0; 18864#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18830#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18831#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18663#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18664#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19378#L662-42 assume !(1 == ~t4_pc~0); 19572#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18192#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18193#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18759#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19611#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19577#L681-42 assume !(1 == ~t5_pc~0); 18052#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 18053#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18412#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18413#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19427#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18549#L700-42 assume 1 == ~t6_pc~0; 18550#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18360#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19349#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19435#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19436#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19625#L719-42 assume !(1 == ~t7_pc~0); 18244#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18245#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18295#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18296#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 18626#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18627#L738-42 assume 1 == ~t8_pc~0; 18819#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18582#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18135#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18098#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18099#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18619#L757-42 assume 1 == ~t9_pc~0; 18955#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18279#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18280#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18423#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18396#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18397#L776-42 assume 1 == ~t10_pc~0; 19368#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19355#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19402#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19664#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19665#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19192#L795-42 assume !(1 == ~t11_pc~0); 19193#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18239#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18240#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18335#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18336#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18636#L814-42 assume !(1 == ~t12_pc~0); 18513#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 18151#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18152#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17960#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17961#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18112#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18113#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18084#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18085#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18895#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19066#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19067#L1357-3 assume !(1 == ~T6_E~0); 19505#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19673#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19669#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17941#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17942#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18545#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18546#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19376#L1397-3 assume !(1 == ~E_1~0); 19634#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19017#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18197#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18198#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18914#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18915#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19504#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19273#L1437-3 assume !(1 == ~E_9~0); 19036#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19037#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17995#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17996#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18601#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18447#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19259#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18188#L1822 assume !(0 == start_simulation_~tmp~3#1); 18189#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19138#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18443#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18444#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 18975#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19087#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19030#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19031#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 18057#L1803-2 [2022-07-14 16:03:19,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,169 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-07-14 16:03:19,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297259190] [2022-07-14 16:03:19,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297259190] [2022-07-14 16:03:19,198 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297259190] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,198 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,199 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743542858] [2022-07-14 16:03:19,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,200 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,200 INFO L85 PathProgramCache]: Analyzing trace with hash -1797209546, now seen corresponding path program 1 times [2022-07-14 16:03:19,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301128618] [2022-07-14 16:03:19,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301128618] [2022-07-14 16:03:19,242 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301128618] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,242 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,243 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065202170] [2022-07-14 16:03:19,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,243 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,244 INFO L87 Difference]: Start difference. First operand 1785 states and 2642 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,274 INFO L93 Difference]: Finished difference Result 1785 states and 2641 transitions. [2022-07-14 16:03:19,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2641 transitions. [2022-07-14 16:03:19,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2641 transitions. [2022-07-14 16:03:19,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:19,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:19,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2641 transitions. [2022-07-14 16:03:19,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,297 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2022-07-14 16:03:19,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2641 transitions. [2022-07-14 16:03:19,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:19,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4795518207282914) internal successors, (2641), 1784 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2641 transitions. [2022-07-14 16:03:19,330 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2022-07-14 16:03:19,330 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2022-07-14 16:03:19,330 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:03:19,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2641 transitions. [2022-07-14 16:03:19,336 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,339 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,339 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,339 INFO L752 eck$LassoCheckResult]: Stem: 22279#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 23058#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23059#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21796#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 21797#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21699#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21700#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22978#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22318#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22319#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22223#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22224#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22726#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22727#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21985#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21986#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22411#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22412#L1194 assume !(0 == ~M_E~0); 22558#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22559#L1199-1 assume !(0 == ~T2_E~0); 22856#L1204-1 assume !(0 == ~T3_E~0); 22780#L1209-1 assume !(0 == ~T4_E~0); 22781#L1214-1 assume !(0 == ~T5_E~0); 23166#L1219-1 assume !(0 == ~T6_E~0); 23254#L1224-1 assume !(0 == ~T7_E~0); 22059#L1229-1 assume !(0 == ~T8_E~0); 21624#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21625#L1239-1 assume !(0 == ~T10_E~0); 21661#L1244-1 assume !(0 == ~T11_E~0); 21662#L1249-1 assume !(0 == ~T12_E~0); 22353#L1254-1 assume !(0 == ~E_M~0); 21563#L1259-1 assume !(0 == ~E_1~0); 21527#L1264-1 assume !(0 == ~E_2~0); 21528#L1269-1 assume !(0 == ~E_3~0); 23257#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 23196#L1279-1 assume !(0 == ~E_5~0); 21737#L1284-1 assume !(0 == ~E_6~0); 21738#L1289-1 assume !(0 == ~E_7~0); 22416#L1294-1 assume !(0 == ~E_8~0); 22417#L1299-1 assume !(0 == ~E_9~0); 22429#L1304-1 assume !(0 == ~E_10~0); 23248#L1309-1 assume !(0 == ~E_11~0); 23252#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21692#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21613#L586 assume 1 == ~m_pc~0; 21614#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21685#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22752#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21893#L1485 assume !(0 != activate_threads_~tmp~1#1); 21894#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22981#L605 assume !(1 == ~t1_pc~0); 22497#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22248#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22249#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23131#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22828#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22166#L624 assume 1 == ~t2_pc~0; 21668#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21669#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22326#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23155#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 23018#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22896#L643 assume !(1 == ~t3_pc~0); 22743#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22445#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22352#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21995#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 21996#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21757#L662 assume 1 == ~t4_pc~0; 21758#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21718#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21719#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22471#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 21602#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21603#L681 assume !(1 == ~t5_pc~0); 21475#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21476#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22523#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23126#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 22007#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22008#L700 assume 1 == ~t6_pc~0; 22707#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21748#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21749#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21798#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 21799#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23062#L719 assume 1 == ~t7_pc~0; 23136#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21965#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22736#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22737#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 21489#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21490#L738 assume !(1 == ~t8_pc~0); 22862#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22772#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21858#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21859#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22555#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22919#L757 assume 1 == ~t9_pc~0; 22920#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21484#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21485#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22687#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 22515#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22516#L776 assume !(1 == ~t10_pc~0); 21509#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21508#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21897#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21739#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 21740#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21693#L795 assume 1 == ~t11_pc~0; 21694#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22026#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22970#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22971#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 22741#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22729#L814 assume !(1 == ~t12_pc~0); 22584#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22585#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22956#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23055#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 21950#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21951#L1332 assume !(1 == ~M_E~0); 23029#L1332-2 assume !(1 == ~T1_E~0); 23212#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22654#L1342-1 assume !(1 == ~T3_E~0); 22655#L1347-1 assume !(1 == ~T4_E~0); 23050#L1352-1 assume !(1 == ~T5_E~0); 22925#L1357-1 assume !(1 == ~T6_E~0); 22221#L1362-1 assume !(1 == ~T7_E~0); 22222#L1367-1 assume !(1 == ~T8_E~0); 21833#L1372-1 assume !(1 == ~T9_E~0); 21834#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22139#L1382-1 assume !(1 == ~T11_E~0); 22140#L1387-1 assume !(1 == ~T12_E~0); 22825#L1392-1 assume !(1 == ~E_M~0); 22167#L1397-1 assume !(1 == ~E_1~0); 22168#L1402-1 assume !(1 == ~E_2~0); 21846#L1407-1 assume !(1 == ~E_3~0); 21847#L1412-1 assume !(1 == ~E_4~0); 22996#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22997#L1422-1 assume !(1 == ~E_6~0); 23213#L1427-1 assume !(1 == ~E_7~0); 22027#L1432-1 assume !(1 == ~E_8~0); 22028#L1437-1 assume !(1 == ~E_9~0); 22946#L1442-1 assume !(1 == ~E_10~0); 22947#L1447-1 assume !(1 == ~E_11~0); 22815#L1452-1 assume !(1 == ~E_12~0); 21633#L1457-1 assume { :end_inline_reset_delta_events } true; 21634#L1803-2 [2022-07-14 16:03:19,340 INFO L754 eck$LassoCheckResult]: Loop: 21634#L1803-2 assume !false; 21970#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21506#L1169 assume !false; 22097#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22202#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21701#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21702#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22477#L996 assume !(0 != eval_~tmp~0#1); 22589#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22590#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22560#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22561#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21805#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21806#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22054#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21502#L1214-3 assume !(0 == ~T5_E~0); 21503#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22246#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22247#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22281#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21671#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21672#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22103#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22680#L1254-3 assume !(0 == ~E_M~0); 23160#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22795#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21677#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21678#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23192#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22244#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22245#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22228#L1294-3 assume !(0 == ~E_8~0); 22229#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22611#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22612#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22141#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22142#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22150#L586-42 assume !(1 == ~m_pc~0); 22151#L586-44 is_master_triggered_~__retres1~0#1 := 0; 21746#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21747#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23171#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 22268#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22269#L605-42 assume 1 == ~t1_pc~0; 22867#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22576#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22577#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22274#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22275#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22276#L624-42 assume !(1 == ~t2_pc~0); 22277#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22423#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21586#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21587#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22099#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22100#L643-42 assume 1 == ~t3_pc~0; 22441#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22407#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22408#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22240#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22241#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22955#L662-42 assume !(1 == ~t4_pc~0); 23146#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21769#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21770#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22336#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23188#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23154#L681-42 assume 1 == ~t5_pc~0; 22452#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21630#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21989#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21990#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23004#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22126#L700-42 assume !(1 == ~t6_pc~0); 21936#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21937#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22926#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23012#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23013#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23202#L719-42 assume 1 == ~t7_pc~0; 22723#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21822#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21872#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21873#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 22203#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22204#L738-42 assume 1 == ~t8_pc~0; 22396#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22159#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21712#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21675#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21676#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22196#L757-42 assume 1 == ~t9_pc~0; 22529#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21856#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21857#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22000#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21973#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21974#L776-42 assume 1 == ~t10_pc~0; 22945#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22932#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22979#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23241#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23242#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22769#L795-42 assume !(1 == ~t11_pc~0); 22770#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21816#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21817#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21910#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21911#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22213#L814-42 assume 1 == ~t12_pc~0; 22984#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21728#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21729#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21537#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21538#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21689#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21690#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21659#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21660#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22472#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22643#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22644#L1357-3 assume !(1 == ~T6_E~0); 23082#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23250#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23246#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21518#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21519#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22122#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22123#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22953#L1397-3 assume !(1 == ~E_1~0); 23211#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22594#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21774#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21775#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22491#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22492#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23081#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22849#L1437-3 assume !(1 == ~E_9~0); 22613#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22614#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21572#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21573#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22178#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22024#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22836#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21765#L1822 assume !(0 == start_simulation_~tmp~3#1); 21766#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22715#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22017#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22018#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 22552#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22664#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22607#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22608#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 21634#L1803-2 [2022-07-14 16:03:19,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,341 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-07-14 16:03:19,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971221030] [2022-07-14 16:03:19,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971221030] [2022-07-14 16:03:19,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971221030] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,369 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287078880] [2022-07-14 16:03:19,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,370 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,371 INFO L85 PathProgramCache]: Analyzing trace with hash 1880402740, now seen corresponding path program 1 times [2022-07-14 16:03:19,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025968193] [2022-07-14 16:03:19,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025968193] [2022-07-14 16:03:19,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025968193] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,408 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,409 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096501525] [2022-07-14 16:03:19,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,409 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,410 INFO L87 Difference]: Start difference. First operand 1785 states and 2641 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,437 INFO L93 Difference]: Finished difference Result 1785 states and 2640 transitions. [2022-07-14 16:03:19,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2640 transitions. [2022-07-14 16:03:19,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2640 transitions. [2022-07-14 16:03:19,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:19,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:19,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2640 transitions. [2022-07-14 16:03:19,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,459 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2022-07-14 16:03:19,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2640 transitions. [2022-07-14 16:03:19,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:19,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4789915966386555) internal successors, (2640), 1784 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2640 transitions. [2022-07-14 16:03:19,510 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2022-07-14 16:03:19,510 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2022-07-14 16:03:19,510 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:03:19,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2640 transitions. [2022-07-14 16:03:19,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,518 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,518 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,519 INFO L752 eck$LassoCheckResult]: Stem: 25853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26635#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26636#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25373#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 25374#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25276#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25277#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26555#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25895#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25896#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25800#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25801#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26303#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26304#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25562#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25563#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25988#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25989#L1194 assume !(0 == ~M_E~0); 26135#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26136#L1199-1 assume !(0 == ~T2_E~0); 26433#L1204-1 assume !(0 == ~T3_E~0); 26357#L1209-1 assume !(0 == ~T4_E~0); 26358#L1214-1 assume !(0 == ~T5_E~0); 26743#L1219-1 assume !(0 == ~T6_E~0); 26831#L1224-1 assume !(0 == ~T7_E~0); 25636#L1229-1 assume !(0 == ~T8_E~0); 25199#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25200#L1239-1 assume !(0 == ~T10_E~0); 25238#L1244-1 assume !(0 == ~T11_E~0); 25239#L1249-1 assume !(0 == ~T12_E~0); 25930#L1254-1 assume !(0 == ~E_M~0); 25140#L1259-1 assume !(0 == ~E_1~0); 25104#L1264-1 assume !(0 == ~E_2~0); 25105#L1269-1 assume !(0 == ~E_3~0); 26834#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26773#L1279-1 assume !(0 == ~E_5~0); 25314#L1284-1 assume !(0 == ~E_6~0); 25315#L1289-1 assume !(0 == ~E_7~0); 25993#L1294-1 assume !(0 == ~E_8~0); 25994#L1299-1 assume !(0 == ~E_9~0); 26004#L1304-1 assume !(0 == ~E_10~0); 26825#L1309-1 assume !(0 == ~E_11~0); 26829#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25269#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25190#L586 assume 1 == ~m_pc~0; 25191#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25262#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26327#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25470#L1485 assume !(0 != activate_threads_~tmp~1#1); 25471#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26558#L605 assume !(1 == ~t1_pc~0); 26074#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25825#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25826#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26708#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26405#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25743#L624 assume 1 == ~t2_pc~0; 25245#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25246#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25903#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26732#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 26595#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26473#L643 assume !(1 == ~t3_pc~0); 26320#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26018#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25929#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25572#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 25573#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25334#L662 assume 1 == ~t4_pc~0; 25335#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25295#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25296#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26048#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 25179#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25180#L681 assume !(1 == ~t5_pc~0); 25052#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25053#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26100#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26703#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 25584#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25585#L700 assume 1 == ~t6_pc~0; 26284#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25325#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25326#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25375#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 25376#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26639#L719 assume 1 == ~t7_pc~0; 26713#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25542#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26313#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26314#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 25066#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25067#L738 assume !(1 == ~t8_pc~0); 26439#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26349#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25435#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25436#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26132#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26496#L757 assume 1 == ~t9_pc~0; 26497#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25061#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25062#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26264#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 26092#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26093#L776 assume !(1 == ~t10_pc~0); 25086#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25085#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25474#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25316#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 25317#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25270#L795 assume 1 == ~t11_pc~0; 25271#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25603#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26547#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26548#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 26318#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26306#L814 assume !(1 == ~t12_pc~0); 26161#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26162#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26532#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26632#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 25527#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25528#L1332 assume !(1 == ~M_E~0); 26606#L1332-2 assume !(1 == ~T1_E~0); 26789#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26231#L1342-1 assume !(1 == ~T3_E~0); 26232#L1347-1 assume !(1 == ~T4_E~0); 26627#L1352-1 assume !(1 == ~T5_E~0); 26502#L1357-1 assume !(1 == ~T6_E~0); 25796#L1362-1 assume !(1 == ~T7_E~0); 25797#L1367-1 assume !(1 == ~T8_E~0); 25410#L1372-1 assume !(1 == ~T9_E~0); 25411#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25716#L1382-1 assume !(1 == ~T11_E~0); 25717#L1387-1 assume !(1 == ~T12_E~0); 26402#L1392-1 assume !(1 == ~E_M~0); 25744#L1397-1 assume !(1 == ~E_1~0); 25745#L1402-1 assume !(1 == ~E_2~0); 25421#L1407-1 assume !(1 == ~E_3~0); 25422#L1412-1 assume !(1 == ~E_4~0); 26573#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26574#L1422-1 assume !(1 == ~E_6~0); 26790#L1427-1 assume !(1 == ~E_7~0); 25604#L1432-1 assume !(1 == ~E_8~0); 25605#L1437-1 assume !(1 == ~E_9~0); 26523#L1442-1 assume !(1 == ~E_10~0); 26524#L1447-1 assume !(1 == ~E_11~0); 26392#L1452-1 assume !(1 == ~E_12~0); 25210#L1457-1 assume { :end_inline_reset_delta_events } true; 25211#L1803-2 [2022-07-14 16:03:19,519 INFO L754 eck$LassoCheckResult]: Loop: 25211#L1803-2 assume !false; 25547#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25083#L1169 assume !false; 25672#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25779#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25278#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25279#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26054#L996 assume !(0 != eval_~tmp~0#1); 26166#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26167#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26137#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26138#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25382#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25383#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25631#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25079#L1214-3 assume !(0 == ~T5_E~0); 25080#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25823#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25824#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25855#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25248#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25249#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25680#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26257#L1254-3 assume !(0 == ~E_M~0); 26737#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26372#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25254#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25255#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26769#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25821#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25822#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25805#L1294-3 assume !(0 == ~E_8~0); 25806#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26188#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26189#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25718#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25719#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25727#L586-42 assume !(1 == ~m_pc~0); 25728#L586-44 is_master_triggered_~__retres1~0#1 := 0; 25323#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25324#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26748#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 25845#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25846#L605-42 assume 1 == ~t1_pc~0; 26444#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26151#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26152#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25849#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25850#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25859#L624-42 assume !(1 == ~t2_pc~0); 25860#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26003#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25163#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25164#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25677#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25678#L643-42 assume 1 == ~t3_pc~0; 26021#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25984#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25985#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25817#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25818#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26533#L662-42 assume !(1 == ~t4_pc~0); 26726#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25346#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25347#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25913#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26765#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26731#L681-42 assume 1 == ~t5_pc~0; 26032#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25207#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25566#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25567#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26581#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25703#L700-42 assume 1 == ~t6_pc~0; 25704#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25514#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26503#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26589#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26590#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26779#L719-42 assume !(1 == ~t7_pc~0); 25395#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25396#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25449#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25450#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 25780#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25781#L738-42 assume 1 == ~t8_pc~0; 25973#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25734#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25289#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25252#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25253#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25773#L757-42 assume 1 == ~t9_pc~0; 26106#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25433#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25434#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25577#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25550#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25551#L776-42 assume 1 == ~t10_pc~0; 26522#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26509#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26556#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26818#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26819#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26346#L795-42 assume !(1 == ~t11_pc~0); 26347#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25393#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25394#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25487#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25488#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25790#L814-42 assume 1 == ~t12_pc~0; 26561#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25305#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25306#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25114#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25115#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25266#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25236#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25237#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26049#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26220#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26221#L1357-3 assume !(1 == ~T6_E~0); 26659#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26827#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26823#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25095#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25096#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25696#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25697#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26530#L1397-3 assume !(1 == ~E_1~0); 26788#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26171#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25351#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25352#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26068#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26069#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26658#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26426#L1437-3 assume !(1 == ~E_9~0); 26190#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26191#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25149#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25150#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25753#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25601#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26413#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25342#L1822 assume !(0 == start_simulation_~tmp~3#1); 25343#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26292#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25594#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25595#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 26129#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26241#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26184#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26185#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 25211#L1803-2 [2022-07-14 16:03:19,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,520 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-07-14 16:03:19,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503855365] [2022-07-14 16:03:19,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503855365] [2022-07-14 16:03:19,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503855365] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238673558] [2022-07-14 16:03:19,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,547 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,547 INFO L85 PathProgramCache]: Analyzing trace with hash 561508340, now seen corresponding path program 2 times [2022-07-14 16:03:19,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553512957] [2022-07-14 16:03:19,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553512957] [2022-07-14 16:03:19,585 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553512957] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,585 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,585 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201617994] [2022-07-14 16:03:19,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,586 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,586 INFO L87 Difference]: Start difference. First operand 1785 states and 2640 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,613 INFO L93 Difference]: Finished difference Result 1785 states and 2639 transitions. [2022-07-14 16:03:19,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2639 transitions. [2022-07-14 16:03:19,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2639 transitions. [2022-07-14 16:03:19,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:19,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:19,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2639 transitions. [2022-07-14 16:03:19,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,634 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2022-07-14 16:03:19,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2639 transitions. [2022-07-14 16:03:19,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:19,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4784313725490197) internal successors, (2639), 1784 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2639 transitions. [2022-07-14 16:03:19,664 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2022-07-14 16:03:19,664 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2022-07-14 16:03:19,664 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:03:19,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2639 transitions. [2022-07-14 16:03:19,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,672 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,672 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,672 INFO L752 eck$LassoCheckResult]: Stem: 29430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30212#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30213#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28950#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 28951#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28853#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28854#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30132#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29472#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29473#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29377#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29378#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29880#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29881#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29139#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29140#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29563#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29564#L1194 assume !(0 == ~M_E~0); 29712#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29713#L1199-1 assume !(0 == ~T2_E~0); 30010#L1204-1 assume !(0 == ~T3_E~0); 29934#L1209-1 assume !(0 == ~T4_E~0); 29935#L1214-1 assume !(0 == ~T5_E~0); 30320#L1219-1 assume !(0 == ~T6_E~0); 30408#L1224-1 assume !(0 == ~T7_E~0); 29213#L1229-1 assume !(0 == ~T8_E~0); 28770#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28771#L1239-1 assume !(0 == ~T10_E~0); 28813#L1244-1 assume !(0 == ~T11_E~0); 28814#L1249-1 assume !(0 == ~T12_E~0); 29507#L1254-1 assume !(0 == ~E_M~0); 28717#L1259-1 assume !(0 == ~E_1~0); 28681#L1264-1 assume !(0 == ~E_2~0); 28682#L1269-1 assume !(0 == ~E_3~0); 30411#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30350#L1279-1 assume !(0 == ~E_5~0); 28891#L1284-1 assume !(0 == ~E_6~0); 28892#L1289-1 assume !(0 == ~E_7~0); 29570#L1294-1 assume !(0 == ~E_8~0); 29571#L1299-1 assume !(0 == ~E_9~0); 29581#L1304-1 assume !(0 == ~E_10~0); 30402#L1309-1 assume !(0 == ~E_11~0); 30406#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28845#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28767#L586 assume 1 == ~m_pc~0; 28768#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28839#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29904#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29047#L1485 assume !(0 != activate_threads_~tmp~1#1); 29048#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30135#L605 assume !(1 == ~t1_pc~0); 29651#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29402#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29403#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30285#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29981#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29320#L624 assume 1 == ~t2_pc~0; 28819#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28820#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29480#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30309#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 30172#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30050#L643 assume !(1 == ~t3_pc~0); 29897#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29593#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29506#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29149#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 29150#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28911#L662 assume 1 == ~t4_pc~0; 28912#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28870#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28871#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29625#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 28754#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28755#L681 assume !(1 == ~t5_pc~0); 28629#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28630#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29677#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30279#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 29161#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29162#L700 assume 1 == ~t6_pc~0; 29861#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28902#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28903#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28952#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 28953#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30216#L719 assume 1 == ~t7_pc~0; 30290#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29119#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29889#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29890#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 28643#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28644#L738 assume !(1 == ~t8_pc~0); 30016#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29926#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29012#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29013#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29709#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30073#L757 assume 1 == ~t9_pc~0; 30074#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28638#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28639#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29841#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 29669#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29670#L776 assume !(1 == ~t10_pc~0); 28663#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28662#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29051#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28893#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 28894#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28846#L795 assume 1 == ~t11_pc~0; 28847#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29180#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30124#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30125#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 29895#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29883#L814 assume !(1 == ~t12_pc~0); 29738#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29739#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30109#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30209#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 29104#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29105#L1332 assume !(1 == ~M_E~0); 30183#L1332-2 assume !(1 == ~T1_E~0); 30366#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29808#L1342-1 assume !(1 == ~T3_E~0); 29809#L1347-1 assume !(1 == ~T4_E~0); 30204#L1352-1 assume !(1 == ~T5_E~0); 30079#L1357-1 assume !(1 == ~T6_E~0); 29373#L1362-1 assume !(1 == ~T7_E~0); 29374#L1367-1 assume !(1 == ~T8_E~0); 28987#L1372-1 assume !(1 == ~T9_E~0); 28988#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29293#L1382-1 assume !(1 == ~T11_E~0); 29294#L1387-1 assume !(1 == ~T12_E~0); 29979#L1392-1 assume !(1 == ~E_M~0); 29321#L1397-1 assume !(1 == ~E_1~0); 29322#L1402-1 assume !(1 == ~E_2~0); 28998#L1407-1 assume !(1 == ~E_3~0); 28999#L1412-1 assume !(1 == ~E_4~0); 30150#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30151#L1422-1 assume !(1 == ~E_6~0); 30367#L1427-1 assume !(1 == ~E_7~0); 29181#L1432-1 assume !(1 == ~E_8~0); 29182#L1437-1 assume !(1 == ~E_9~0); 30100#L1442-1 assume !(1 == ~E_10~0); 30101#L1447-1 assume !(1 == ~E_11~0); 29969#L1452-1 assume !(1 == ~E_12~0); 28787#L1457-1 assume { :end_inline_reset_delta_events } true; 28788#L1803-2 [2022-07-14 16:03:19,673 INFO L754 eck$LassoCheckResult]: Loop: 28788#L1803-2 assume !false; 29124#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28660#L1169 assume !false; 29249#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29354#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28855#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28856#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29631#L996 assume !(0 != eval_~tmp~0#1); 29743#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29744#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29714#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29715#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28959#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28960#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29208#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28652#L1214-3 assume !(0 == ~T5_E~0); 28653#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29400#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29401#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29432#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28825#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28826#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29257#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29834#L1254-3 assume !(0 == ~E_M~0); 30314#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29949#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28831#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28832#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30346#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29398#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29399#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29382#L1294-3 assume !(0 == ~E_8~0); 29383#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29765#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29766#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29295#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29296#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29304#L586-42 assume !(1 == ~m_pc~0); 29305#L586-44 is_master_triggered_~__retres1~0#1 := 0; 28900#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28901#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30325#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 29422#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29423#L605-42 assume 1 == ~t1_pc~0; 30020#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29728#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29729#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29424#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29425#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29436#L624-42 assume !(1 == ~t2_pc~0); 29437#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29580#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28740#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28741#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29254#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29255#L643-42 assume 1 == ~t3_pc~0; 29596#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29561#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29562#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29394#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29395#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30110#L662-42 assume 1 == ~t4_pc~0; 30304#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28923#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28924#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29490#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30342#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30308#L681-42 assume 1 == ~t5_pc~0; 29606#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28784#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29143#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29144#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30158#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29280#L700-42 assume 1 == ~t6_pc~0; 29281#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29091#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30080#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30166#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30167#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30356#L719-42 assume 1 == ~t7_pc~0; 29877#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28976#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29026#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29027#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 29357#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29358#L738-42 assume 1 == ~t8_pc~0; 29550#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29313#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28866#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28829#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28830#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29350#L757-42 assume 1 == ~t9_pc~0; 29686#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29010#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29011#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29154#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29128#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29129#L776-42 assume 1 == ~t10_pc~0; 30099#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30086#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30133#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30395#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30396#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29923#L795-42 assume !(1 == ~t11_pc~0); 29924#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 28970#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28971#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29066#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29067#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29367#L814-42 assume 1 == ~t12_pc~0; 30138#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28882#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28883#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28691#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28692#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28843#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28844#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28817#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28818#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29626#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29797#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29798#L1357-3 assume !(1 == ~T6_E~0); 30236#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30404#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30400#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28672#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28673#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29276#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29277#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30107#L1397-3 assume !(1 == ~E_1~0); 30365#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29748#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28928#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28929#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29645#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29646#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30235#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30004#L1437-3 assume !(1 == ~E_9~0); 29767#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29768#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28726#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28727#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29332#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29178#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29990#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28919#L1822 assume !(0 == start_simulation_~tmp~3#1); 28920#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29869#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29174#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29175#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 29706#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29818#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29763#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29764#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 28788#L1803-2 [2022-07-14 16:03:19,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,673 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-07-14 16:03:19,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227250746] [2022-07-14 16:03:19,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227250746] [2022-07-14 16:03:19,698 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227250746] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,698 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,698 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352789531] [2022-07-14 16:03:19,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,699 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,699 INFO L85 PathProgramCache]: Analyzing trace with hash -696776142, now seen corresponding path program 1 times [2022-07-14 16:03:19,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983151800] [2022-07-14 16:03:19,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983151800] [2022-07-14 16:03:19,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983151800] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670774796] [2022-07-14 16:03:19,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,734 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,735 INFO L87 Difference]: Start difference. First operand 1785 states and 2639 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,760 INFO L93 Difference]: Finished difference Result 1785 states and 2638 transitions. [2022-07-14 16:03:19,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2638 transitions. [2022-07-14 16:03:19,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2638 transitions. [2022-07-14 16:03:19,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:19,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:19,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2638 transitions. [2022-07-14 16:03:19,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,779 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2022-07-14 16:03:19,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2638 transitions. [2022-07-14 16:03:19,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:19,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4778711484593838) internal successors, (2638), 1784 states have internal predecessors, (2638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2638 transitions. [2022-07-14 16:03:19,806 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2022-07-14 16:03:19,806 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2022-07-14 16:03:19,806 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:03:19,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2638 transitions. [2022-07-14 16:03:19,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,814 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,814 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,814 INFO L752 eck$LassoCheckResult]: Stem: 33007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33008#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33789#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33790#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32527#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 32528#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32430#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32431#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33709#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33049#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33050#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32954#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32955#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33457#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33458#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32716#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32717#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33140#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33141#L1194 assume !(0 == ~M_E~0); 33289#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33290#L1199-1 assume !(0 == ~T2_E~0); 33587#L1204-1 assume !(0 == ~T3_E~0); 33511#L1209-1 assume !(0 == ~T4_E~0); 33512#L1214-1 assume !(0 == ~T5_E~0); 33897#L1219-1 assume !(0 == ~T6_E~0); 33985#L1224-1 assume !(0 == ~T7_E~0); 32790#L1229-1 assume !(0 == ~T8_E~0); 32347#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32348#L1239-1 assume !(0 == ~T10_E~0); 32390#L1244-1 assume !(0 == ~T11_E~0); 32391#L1249-1 assume !(0 == ~T12_E~0); 33084#L1254-1 assume !(0 == ~E_M~0); 32294#L1259-1 assume !(0 == ~E_1~0); 32258#L1264-1 assume !(0 == ~E_2~0); 32259#L1269-1 assume !(0 == ~E_3~0); 33988#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33927#L1279-1 assume !(0 == ~E_5~0); 32468#L1284-1 assume !(0 == ~E_6~0); 32469#L1289-1 assume !(0 == ~E_7~0); 33147#L1294-1 assume !(0 == ~E_8~0); 33148#L1299-1 assume !(0 == ~E_9~0); 33158#L1304-1 assume !(0 == ~E_10~0); 33979#L1309-1 assume !(0 == ~E_11~0); 33983#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32422#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32344#L586 assume 1 == ~m_pc~0; 32345#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32416#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33481#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32624#L1485 assume !(0 != activate_threads_~tmp~1#1); 32625#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33712#L605 assume !(1 == ~t1_pc~0); 33228#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32979#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32980#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33862#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33558#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32897#L624 assume 1 == ~t2_pc~0; 32396#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32397#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33057#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33886#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 33749#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33627#L643 assume !(1 == ~t3_pc~0); 33474#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33170#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33083#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32726#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 32727#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32488#L662 assume 1 == ~t4_pc~0; 32489#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32447#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32448#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33202#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 32331#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32332#L681 assume !(1 == ~t5_pc~0); 32206#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32207#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33254#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33856#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 32738#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32739#L700 assume 1 == ~t6_pc~0; 33438#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32479#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32480#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32529#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 32530#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33793#L719 assume 1 == ~t7_pc~0; 33867#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32696#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33466#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33467#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 32220#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32221#L738 assume !(1 == ~t8_pc~0); 33593#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33503#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32589#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32590#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33286#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33650#L757 assume 1 == ~t9_pc~0; 33651#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32215#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32216#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33418#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 33246#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33247#L776 assume !(1 == ~t10_pc~0); 32240#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32239#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32628#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32470#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 32471#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32423#L795 assume 1 == ~t11_pc~0; 32424#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32757#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33701#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33702#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 33472#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33460#L814 assume !(1 == ~t12_pc~0); 33315#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33316#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33686#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33786#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 32681#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32682#L1332 assume !(1 == ~M_E~0); 33760#L1332-2 assume !(1 == ~T1_E~0); 33943#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33385#L1342-1 assume !(1 == ~T3_E~0); 33386#L1347-1 assume !(1 == ~T4_E~0); 33781#L1352-1 assume !(1 == ~T5_E~0); 33656#L1357-1 assume !(1 == ~T6_E~0); 32950#L1362-1 assume !(1 == ~T7_E~0); 32951#L1367-1 assume !(1 == ~T8_E~0); 32564#L1372-1 assume !(1 == ~T9_E~0); 32565#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32870#L1382-1 assume !(1 == ~T11_E~0); 32871#L1387-1 assume !(1 == ~T12_E~0); 33556#L1392-1 assume !(1 == ~E_M~0); 32898#L1397-1 assume !(1 == ~E_1~0); 32899#L1402-1 assume !(1 == ~E_2~0); 32575#L1407-1 assume !(1 == ~E_3~0); 32576#L1412-1 assume !(1 == ~E_4~0); 33727#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33728#L1422-1 assume !(1 == ~E_6~0); 33944#L1427-1 assume !(1 == ~E_7~0); 32758#L1432-1 assume !(1 == ~E_8~0); 32759#L1437-1 assume !(1 == ~E_9~0); 33677#L1442-1 assume !(1 == ~E_10~0); 33678#L1447-1 assume !(1 == ~E_11~0); 33546#L1452-1 assume !(1 == ~E_12~0); 32364#L1457-1 assume { :end_inline_reset_delta_events } true; 32365#L1803-2 [2022-07-14 16:03:19,815 INFO L754 eck$LassoCheckResult]: Loop: 32365#L1803-2 assume !false; 32701#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32237#L1169 assume !false; 32826#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32931#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32432#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32433#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33208#L996 assume !(0 != eval_~tmp~0#1); 33320#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33321#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33291#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33292#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32536#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32537#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32785#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32229#L1214-3 assume !(0 == ~T5_E~0); 32230#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32977#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32978#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33009#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32402#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32403#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32834#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33411#L1254-3 assume !(0 == ~E_M~0); 33891#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33526#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32408#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32409#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33923#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32975#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32976#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32959#L1294-3 assume !(0 == ~E_8~0); 32960#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33342#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33343#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32872#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32873#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32881#L586-42 assume !(1 == ~m_pc~0); 32882#L586-44 is_master_triggered_~__retres1~0#1 := 0; 32477#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32478#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33902#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 32999#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33000#L605-42 assume 1 == ~t1_pc~0; 33597#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33305#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33306#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33001#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33002#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33013#L624-42 assume !(1 == ~t2_pc~0); 33014#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33157#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32317#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32318#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32831#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32832#L643-42 assume 1 == ~t3_pc~0; 33173#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33138#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33139#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32971#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32972#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33687#L662-42 assume !(1 == ~t4_pc~0); 33880#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32500#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32501#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33067#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33919#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33885#L681-42 assume !(1 == ~t5_pc~0); 32360#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 32361#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32720#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32721#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33735#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32857#L700-42 assume 1 == ~t6_pc~0; 32858#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32668#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33657#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33743#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33744#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33933#L719-42 assume !(1 == ~t7_pc~0); 32552#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 32553#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32603#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32604#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 32934#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32935#L738-42 assume 1 == ~t8_pc~0; 33127#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32890#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32443#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32406#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32407#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32927#L757-42 assume !(1 == ~t9_pc~0); 33264#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 32587#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32588#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32731#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32705#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32706#L776-42 assume 1 == ~t10_pc~0; 33676#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33663#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33710#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33972#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33973#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33500#L795-42 assume !(1 == ~t11_pc~0); 33501#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32547#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32548#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32643#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32644#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32944#L814-42 assume 1 == ~t12_pc~0; 33715#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32459#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32460#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32268#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32269#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32420#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32421#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32394#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32395#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33203#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33374#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33375#L1357-3 assume !(1 == ~T6_E~0); 33813#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33981#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33977#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32249#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32250#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32853#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32854#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33684#L1397-3 assume !(1 == ~E_1~0); 33942#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33325#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32505#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32506#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33222#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33223#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33812#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33581#L1437-3 assume !(1 == ~E_9~0); 33344#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33345#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32303#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32304#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32909#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32755#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33567#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32496#L1822 assume !(0 == start_simulation_~tmp~3#1); 32497#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33446#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32751#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32752#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 33283#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33395#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33340#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33341#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 32365#L1803-2 [2022-07-14 16:03:19,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,816 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-07-14 16:03:19,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518540853] [2022-07-14 16:03:19,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518540853] [2022-07-14 16:03:19,840 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518540853] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,840 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,840 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260646555] [2022-07-14 16:03:19,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,841 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:19,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,841 INFO L85 PathProgramCache]: Analyzing trace with hash -346803210, now seen corresponding path program 1 times [2022-07-14 16:03:19,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278723578] [2022-07-14 16:03:19,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:19,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:19,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:19,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278723578] [2022-07-14 16:03:19,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278723578] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:19,876 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:19,876 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:19,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293793042] [2022-07-14 16:03:19,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:19,877 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:19,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:19,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:19,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:19,877 INFO L87 Difference]: Start difference. First operand 1785 states and 2638 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,924 INFO L93 Difference]: Finished difference Result 1785 states and 2637 transitions. [2022-07-14 16:03:19,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:19,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2637 transitions. [2022-07-14 16:03:19,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2637 transitions. [2022-07-14 16:03:19,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:19,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:19,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2637 transitions. [2022-07-14 16:03:19,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:19,943 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2022-07-14 16:03:19,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2637 transitions. [2022-07-14 16:03:19,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:19,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.477310924369748) internal successors, (2637), 1784 states have internal predecessors, (2637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2637 transitions. [2022-07-14 16:03:19,968 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2022-07-14 16:03:19,969 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2022-07-14 16:03:19,969 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:03:19,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2637 transitions. [2022-07-14 16:03:19,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:19,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:19,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:19,976 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,976 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:19,976 INFO L752 eck$LassoCheckResult]: Stem: 36584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37366#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37367#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36104#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 36105#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36007#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36008#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37286#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36626#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36627#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36531#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36532#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37034#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37035#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36293#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36294#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36717#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36718#L1194 assume !(0 == ~M_E~0); 36866#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36867#L1199-1 assume !(0 == ~T2_E~0); 37164#L1204-1 assume !(0 == ~T3_E~0); 37088#L1209-1 assume !(0 == ~T4_E~0); 37089#L1214-1 assume !(0 == ~T5_E~0); 37474#L1219-1 assume !(0 == ~T6_E~0); 37562#L1224-1 assume !(0 == ~T7_E~0); 36367#L1229-1 assume !(0 == ~T8_E~0); 35924#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35925#L1239-1 assume !(0 == ~T10_E~0); 35967#L1244-1 assume !(0 == ~T11_E~0); 35968#L1249-1 assume !(0 == ~T12_E~0); 36661#L1254-1 assume !(0 == ~E_M~0); 35871#L1259-1 assume !(0 == ~E_1~0); 35835#L1264-1 assume !(0 == ~E_2~0); 35836#L1269-1 assume !(0 == ~E_3~0); 37565#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37504#L1279-1 assume !(0 == ~E_5~0); 36045#L1284-1 assume !(0 == ~E_6~0); 36046#L1289-1 assume !(0 == ~E_7~0); 36724#L1294-1 assume !(0 == ~E_8~0); 36725#L1299-1 assume !(0 == ~E_9~0); 36735#L1304-1 assume !(0 == ~E_10~0); 37556#L1309-1 assume !(0 == ~E_11~0); 37560#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 35999#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35921#L586 assume 1 == ~m_pc~0; 35922#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35993#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37058#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36201#L1485 assume !(0 != activate_threads_~tmp~1#1); 36202#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37289#L605 assume !(1 == ~t1_pc~0); 36805#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36556#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36557#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37439#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37135#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36474#L624 assume 1 == ~t2_pc~0; 35973#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35974#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36634#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37463#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 37326#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37204#L643 assume !(1 == ~t3_pc~0); 37051#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36747#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36660#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36303#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 36304#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36065#L662 assume 1 == ~t4_pc~0; 36066#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36024#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36025#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36779#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 35908#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35909#L681 assume !(1 == ~t5_pc~0); 35783#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 35784#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36831#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37433#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 36315#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36316#L700 assume 1 == ~t6_pc~0; 37015#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36056#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36057#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36106#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 36107#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37370#L719 assume 1 == ~t7_pc~0; 37444#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36273#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37043#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37044#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 35797#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35798#L738 assume !(1 == ~t8_pc~0); 37170#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37080#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36166#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36167#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36863#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37227#L757 assume 1 == ~t9_pc~0; 37228#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35792#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35793#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36995#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 36823#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36824#L776 assume !(1 == ~t10_pc~0); 35817#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35816#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36205#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36047#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 36048#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36000#L795 assume 1 == ~t11_pc~0; 36001#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36334#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37278#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37279#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 37049#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37037#L814 assume !(1 == ~t12_pc~0); 36892#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36893#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37263#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37363#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 36258#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36259#L1332 assume !(1 == ~M_E~0); 37337#L1332-2 assume !(1 == ~T1_E~0); 37520#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36962#L1342-1 assume !(1 == ~T3_E~0); 36963#L1347-1 assume !(1 == ~T4_E~0); 37358#L1352-1 assume !(1 == ~T5_E~0); 37233#L1357-1 assume !(1 == ~T6_E~0); 36527#L1362-1 assume !(1 == ~T7_E~0); 36528#L1367-1 assume !(1 == ~T8_E~0); 36141#L1372-1 assume !(1 == ~T9_E~0); 36142#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36447#L1382-1 assume !(1 == ~T11_E~0); 36448#L1387-1 assume !(1 == ~T12_E~0); 37133#L1392-1 assume !(1 == ~E_M~0); 36475#L1397-1 assume !(1 == ~E_1~0); 36476#L1402-1 assume !(1 == ~E_2~0); 36152#L1407-1 assume !(1 == ~E_3~0); 36153#L1412-1 assume !(1 == ~E_4~0); 37304#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37305#L1422-1 assume !(1 == ~E_6~0); 37521#L1427-1 assume !(1 == ~E_7~0); 36335#L1432-1 assume !(1 == ~E_8~0); 36336#L1437-1 assume !(1 == ~E_9~0); 37254#L1442-1 assume !(1 == ~E_10~0); 37255#L1447-1 assume !(1 == ~E_11~0); 37123#L1452-1 assume !(1 == ~E_12~0); 35941#L1457-1 assume { :end_inline_reset_delta_events } true; 35942#L1803-2 [2022-07-14 16:03:19,977 INFO L754 eck$LassoCheckResult]: Loop: 35942#L1803-2 assume !false; 36278#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35814#L1169 assume !false; 36403#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36508#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36009#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36010#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 36785#L996 assume !(0 != eval_~tmp~0#1); 36897#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36898#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36868#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36869#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36113#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36114#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36362#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35806#L1214-3 assume !(0 == ~T5_E~0); 35807#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36554#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36555#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36586#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35979#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35980#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36411#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36988#L1254-3 assume !(0 == ~E_M~0); 37468#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37103#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35985#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35986#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37500#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36552#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36553#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36536#L1294-3 assume !(0 == ~E_8~0); 36537#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36919#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36920#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36449#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36450#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36458#L586-42 assume !(1 == ~m_pc~0); 36459#L586-44 is_master_triggered_~__retres1~0#1 := 0; 36054#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36055#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37479#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 36576#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36577#L605-42 assume 1 == ~t1_pc~0; 37174#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36882#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36883#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36578#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36579#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36590#L624-42 assume 1 == ~t2_pc~0; 36592#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36734#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35894#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35895#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36408#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36409#L643-42 assume 1 == ~t3_pc~0; 36750#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36715#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36716#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36548#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36549#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37264#L662-42 assume !(1 == ~t4_pc~0); 37457#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36077#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36078#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36644#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37496#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37462#L681-42 assume !(1 == ~t5_pc~0); 35937#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 35938#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36297#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36298#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37312#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36434#L700-42 assume 1 == ~t6_pc~0; 36435#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36245#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37234#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37320#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37321#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37510#L719-42 assume !(1 == ~t7_pc~0); 36129#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36130#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36180#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36181#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 36511#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36512#L738-42 assume 1 == ~t8_pc~0; 36704#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36467#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36020#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35983#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35984#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36504#L757-42 assume 1 == ~t9_pc~0; 36840#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36164#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36165#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36308#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36282#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36283#L776-42 assume 1 == ~t10_pc~0; 37253#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37240#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37287#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37549#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37550#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37077#L795-42 assume !(1 == ~t11_pc~0); 37078#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36124#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36125#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36220#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36221#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36521#L814-42 assume 1 == ~t12_pc~0; 37292#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36036#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36037#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35845#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 35846#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35997#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35998#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35971#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35972#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36780#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36951#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36952#L1357-3 assume !(1 == ~T6_E~0); 37390#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37558#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37554#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35826#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35827#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36430#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36431#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37261#L1397-3 assume !(1 == ~E_1~0); 37519#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36902#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36082#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36083#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36799#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36800#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37389#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37158#L1437-3 assume !(1 == ~E_9~0); 36921#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36922#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35880#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35881#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36486#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36332#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37144#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36073#L1822 assume !(0 == start_simulation_~tmp~3#1); 36074#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37023#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36328#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36329#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 36860#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36972#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36917#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36918#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 35942#L1803-2 [2022-07-14 16:03:19,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:19,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-07-14 16:03:19,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:19,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101263337] [2022-07-14 16:03:19,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:19,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:19,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101263337] [2022-07-14 16:03:20,004 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101263337] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,004 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,005 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [314481948] [2022-07-14 16:03:20,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,005 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:20,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,006 INFO L85 PathProgramCache]: Analyzing trace with hash -1211191756, now seen corresponding path program 1 times [2022-07-14 16:03:20,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670982146] [2022-07-14 16:03:20,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670982146] [2022-07-14 16:03:20,043 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670982146] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,043 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,043 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966799777] [2022-07-14 16:03:20,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,044 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:20,044 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:20,045 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:20,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:20,045 INFO L87 Difference]: Start difference. First operand 1785 states and 2637 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:20,072 INFO L93 Difference]: Finished difference Result 1785 states and 2636 transitions. [2022-07-14 16:03:20,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:20,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2636 transitions. [2022-07-14 16:03:20,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:20,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2636 transitions. [2022-07-14 16:03:20,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:20,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:20,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2636 transitions. [2022-07-14 16:03:20,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:20,091 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2022-07-14 16:03:20,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2636 transitions. [2022-07-14 16:03:20,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:20,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4767507002801121) internal successors, (2636), 1784 states have internal predecessors, (2636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2636 transitions. [2022-07-14 16:03:20,119 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2022-07-14 16:03:20,119 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2022-07-14 16:03:20,119 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:03:20,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2636 transitions. [2022-07-14 16:03:20,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:20,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:20,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:20,127 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,127 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,128 INFO L752 eck$LassoCheckResult]: Stem: 40161#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40943#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40944#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39681#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 39682#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39584#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39585#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40863#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40203#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40204#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40108#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40109#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40611#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40612#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39870#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39871#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40294#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40295#L1194 assume !(0 == ~M_E~0); 40443#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40444#L1199-1 assume !(0 == ~T2_E~0); 40741#L1204-1 assume !(0 == ~T3_E~0); 40665#L1209-1 assume !(0 == ~T4_E~0); 40666#L1214-1 assume !(0 == ~T5_E~0); 41051#L1219-1 assume !(0 == ~T6_E~0); 41139#L1224-1 assume !(0 == ~T7_E~0); 39944#L1229-1 assume !(0 == ~T8_E~0); 39501#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39502#L1239-1 assume !(0 == ~T10_E~0); 39544#L1244-1 assume !(0 == ~T11_E~0); 39545#L1249-1 assume !(0 == ~T12_E~0); 40238#L1254-1 assume !(0 == ~E_M~0); 39448#L1259-1 assume !(0 == ~E_1~0); 39412#L1264-1 assume !(0 == ~E_2~0); 39413#L1269-1 assume !(0 == ~E_3~0); 41142#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41081#L1279-1 assume !(0 == ~E_5~0); 39622#L1284-1 assume !(0 == ~E_6~0); 39623#L1289-1 assume !(0 == ~E_7~0); 40301#L1294-1 assume !(0 == ~E_8~0); 40302#L1299-1 assume !(0 == ~E_9~0); 40312#L1304-1 assume !(0 == ~E_10~0); 41133#L1309-1 assume !(0 == ~E_11~0); 41137#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39576#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39498#L586 assume 1 == ~m_pc~0; 39499#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39570#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40635#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39778#L1485 assume !(0 != activate_threads_~tmp~1#1); 39779#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40866#L605 assume !(1 == ~t1_pc~0); 40382#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40133#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40134#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41016#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40712#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40051#L624 assume 1 == ~t2_pc~0; 39550#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39551#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40211#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41040#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 40903#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40781#L643 assume !(1 == ~t3_pc~0); 40628#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40324#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40237#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39880#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 39881#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39642#L662 assume 1 == ~t4_pc~0; 39643#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39601#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39602#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40356#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 39485#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39486#L681 assume !(1 == ~t5_pc~0); 39360#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39361#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40408#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41010#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 39892#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39893#L700 assume 1 == ~t6_pc~0; 40592#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39633#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39634#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39683#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 39684#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40947#L719 assume 1 == ~t7_pc~0; 41021#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39850#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40620#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40621#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 39374#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39375#L738 assume !(1 == ~t8_pc~0); 40747#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40657#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39743#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39744#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40440#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40804#L757 assume 1 == ~t9_pc~0; 40805#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39369#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39370#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40572#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 40400#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40401#L776 assume !(1 == ~t10_pc~0); 39394#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39393#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39782#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39624#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 39625#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39577#L795 assume 1 == ~t11_pc~0; 39578#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39911#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40855#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40856#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 40626#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40614#L814 assume !(1 == ~t12_pc~0); 40469#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40470#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40840#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40940#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 39835#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39836#L1332 assume !(1 == ~M_E~0); 40914#L1332-2 assume !(1 == ~T1_E~0); 41097#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40539#L1342-1 assume !(1 == ~T3_E~0); 40540#L1347-1 assume !(1 == ~T4_E~0); 40935#L1352-1 assume !(1 == ~T5_E~0); 40810#L1357-1 assume !(1 == ~T6_E~0); 40104#L1362-1 assume !(1 == ~T7_E~0); 40105#L1367-1 assume !(1 == ~T8_E~0); 39718#L1372-1 assume !(1 == ~T9_E~0); 39719#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40024#L1382-1 assume !(1 == ~T11_E~0); 40025#L1387-1 assume !(1 == ~T12_E~0); 40710#L1392-1 assume !(1 == ~E_M~0); 40052#L1397-1 assume !(1 == ~E_1~0); 40053#L1402-1 assume !(1 == ~E_2~0); 39729#L1407-1 assume !(1 == ~E_3~0); 39730#L1412-1 assume !(1 == ~E_4~0); 40881#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40882#L1422-1 assume !(1 == ~E_6~0); 41098#L1427-1 assume !(1 == ~E_7~0); 39912#L1432-1 assume !(1 == ~E_8~0); 39913#L1437-1 assume !(1 == ~E_9~0); 40831#L1442-1 assume !(1 == ~E_10~0); 40832#L1447-1 assume !(1 == ~E_11~0); 40700#L1452-1 assume !(1 == ~E_12~0); 39518#L1457-1 assume { :end_inline_reset_delta_events } true; 39519#L1803-2 [2022-07-14 16:03:20,128 INFO L754 eck$LassoCheckResult]: Loop: 39519#L1803-2 assume !false; 39855#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39391#L1169 assume !false; 39980#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40085#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39586#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39587#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40362#L996 assume !(0 != eval_~tmp~0#1); 40474#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40475#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40445#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40446#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39690#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39691#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39939#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39383#L1214-3 assume !(0 == ~T5_E~0); 39384#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40131#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40132#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40163#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39556#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39557#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39988#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40565#L1254-3 assume !(0 == ~E_M~0); 41045#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40680#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39562#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39563#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41077#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40129#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40130#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40113#L1294-3 assume !(0 == ~E_8~0); 40114#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40496#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40497#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40026#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40027#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40035#L586-42 assume !(1 == ~m_pc~0); 40036#L586-44 is_master_triggered_~__retres1~0#1 := 0; 39631#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39632#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41056#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 40153#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40154#L605-42 assume !(1 == ~t1_pc~0); 40752#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40459#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40460#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40155#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40156#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40167#L624-42 assume !(1 == ~t2_pc~0); 40168#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40311#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39471#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39472#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39985#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39986#L643-42 assume 1 == ~t3_pc~0; 40327#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40292#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40293#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40125#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40126#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40841#L662-42 assume !(1 == ~t4_pc~0); 41034#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39654#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39655#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40221#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41073#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41039#L681-42 assume 1 == ~t5_pc~0; 40337#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39515#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39874#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39875#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40889#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40011#L700-42 assume 1 == ~t6_pc~0; 40012#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39822#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40811#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40897#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40898#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41087#L719-42 assume 1 == ~t7_pc~0; 40608#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39707#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39757#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39758#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 40088#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40089#L738-42 assume 1 == ~t8_pc~0; 40281#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40044#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39597#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39560#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39561#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40081#L757-42 assume 1 == ~t9_pc~0; 40417#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39741#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39742#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39885#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39859#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39860#L776-42 assume !(1 == ~t10_pc~0); 40816#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 40817#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40864#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41126#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41127#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40654#L795-42 assume 1 == ~t11_pc~0; 40656#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39701#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39702#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39797#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39798#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40098#L814-42 assume 1 == ~t12_pc~0; 40869#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 39613#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39614#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39422#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39423#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39574#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39575#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39548#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39549#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40357#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40528#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40529#L1357-3 assume !(1 == ~T6_E~0); 40967#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41135#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41131#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39403#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39404#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40007#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40008#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40838#L1397-3 assume !(1 == ~E_1~0); 41096#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40479#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39659#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39660#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40376#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40377#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40966#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40735#L1437-3 assume !(1 == ~E_9~0); 40498#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40499#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39457#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39458#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40063#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39909#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40721#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39650#L1822 assume !(0 == start_simulation_~tmp~3#1); 39651#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40600#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39905#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39906#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 40437#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40549#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40494#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40495#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 39519#L1803-2 [2022-07-14 16:03:20,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,129 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-07-14 16:03:20,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905895346] [2022-07-14 16:03:20,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905895346] [2022-07-14 16:03:20,155 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905895346] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,155 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584533903] [2022-07-14 16:03:20,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,156 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:20,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,157 INFO L85 PathProgramCache]: Analyzing trace with hash -808370508, now seen corresponding path program 1 times [2022-07-14 16:03:20,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432384] [2022-07-14 16:03:20,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432384] [2022-07-14 16:03:20,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432384] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,192 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527526205] [2022-07-14 16:03:20,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,192 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:20,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:20,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:20,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:20,193 INFO L87 Difference]: Start difference. First operand 1785 states and 2636 transitions. cyclomatic complexity: 852 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:20,219 INFO L93 Difference]: Finished difference Result 1785 states and 2635 transitions. [2022-07-14 16:03:20,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:20,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2635 transitions. [2022-07-14 16:03:20,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:20,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2635 transitions. [2022-07-14 16:03:20,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:20,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:20,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2635 transitions. [2022-07-14 16:03:20,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:20,238 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2022-07-14 16:03:20,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2635 transitions. [2022-07-14 16:03:20,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:20,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4761904761904763) internal successors, (2635), 1784 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2635 transitions. [2022-07-14 16:03:20,266 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2022-07-14 16:03:20,266 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2022-07-14 16:03:20,266 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:03:20,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2635 transitions. [2022-07-14 16:03:20,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:20,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:20,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:20,274 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,274 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,274 INFO L752 eck$LassoCheckResult]: Stem: 43738#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44520#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44521#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43258#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 43259#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43161#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43162#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44440#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43780#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43781#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43685#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43686#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44188#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44189#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43447#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43448#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 43871#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43872#L1194 assume !(0 == ~M_E~0); 44020#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44021#L1199-1 assume !(0 == ~T2_E~0); 44318#L1204-1 assume !(0 == ~T3_E~0); 44242#L1209-1 assume !(0 == ~T4_E~0); 44243#L1214-1 assume !(0 == ~T5_E~0); 44628#L1219-1 assume !(0 == ~T6_E~0); 44716#L1224-1 assume !(0 == ~T7_E~0); 43521#L1229-1 assume !(0 == ~T8_E~0); 43078#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43079#L1239-1 assume !(0 == ~T10_E~0); 43121#L1244-1 assume !(0 == ~T11_E~0); 43122#L1249-1 assume !(0 == ~T12_E~0); 43815#L1254-1 assume !(0 == ~E_M~0); 43025#L1259-1 assume !(0 == ~E_1~0); 42989#L1264-1 assume !(0 == ~E_2~0); 42990#L1269-1 assume !(0 == ~E_3~0); 44719#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44658#L1279-1 assume !(0 == ~E_5~0); 43199#L1284-1 assume !(0 == ~E_6~0); 43200#L1289-1 assume !(0 == ~E_7~0); 43878#L1294-1 assume !(0 == ~E_8~0); 43879#L1299-1 assume !(0 == ~E_9~0); 43889#L1304-1 assume !(0 == ~E_10~0); 44710#L1309-1 assume !(0 == ~E_11~0); 44714#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43153#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43075#L586 assume 1 == ~m_pc~0; 43076#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43147#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44212#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43355#L1485 assume !(0 != activate_threads_~tmp~1#1); 43356#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44443#L605 assume !(1 == ~t1_pc~0); 43959#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43710#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43711#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44593#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44289#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43628#L624 assume 1 == ~t2_pc~0; 43127#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43128#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43788#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44617#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 44480#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44358#L643 assume !(1 == ~t3_pc~0); 44205#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43901#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43814#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43457#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 43458#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43219#L662 assume 1 == ~t4_pc~0; 43220#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43178#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43179#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43933#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 43062#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43063#L681 assume !(1 == ~t5_pc~0); 42937#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42938#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43985#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44587#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 43469#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43470#L700 assume 1 == ~t6_pc~0; 44169#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43210#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43211#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43260#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 43261#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44524#L719 assume 1 == ~t7_pc~0; 44598#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43427#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44197#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44198#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 42951#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42952#L738 assume !(1 == ~t8_pc~0); 44324#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44234#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43320#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43321#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44017#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44381#L757 assume 1 == ~t9_pc~0; 44382#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42946#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42947#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44149#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 43977#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43978#L776 assume !(1 == ~t10_pc~0); 42971#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42970#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43359#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43201#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 43202#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43154#L795 assume 1 == ~t11_pc~0; 43155#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43488#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44432#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44433#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 44203#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44191#L814 assume !(1 == ~t12_pc~0); 44046#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44047#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44417#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44517#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 43412#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43413#L1332 assume !(1 == ~M_E~0); 44491#L1332-2 assume !(1 == ~T1_E~0); 44674#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44116#L1342-1 assume !(1 == ~T3_E~0); 44117#L1347-1 assume !(1 == ~T4_E~0); 44512#L1352-1 assume !(1 == ~T5_E~0); 44387#L1357-1 assume !(1 == ~T6_E~0); 43681#L1362-1 assume !(1 == ~T7_E~0); 43682#L1367-1 assume !(1 == ~T8_E~0); 43295#L1372-1 assume !(1 == ~T9_E~0); 43296#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43601#L1382-1 assume !(1 == ~T11_E~0); 43602#L1387-1 assume !(1 == ~T12_E~0); 44287#L1392-1 assume !(1 == ~E_M~0); 43629#L1397-1 assume !(1 == ~E_1~0); 43630#L1402-1 assume !(1 == ~E_2~0); 43306#L1407-1 assume !(1 == ~E_3~0); 43307#L1412-1 assume !(1 == ~E_4~0); 44458#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44459#L1422-1 assume !(1 == ~E_6~0); 44675#L1427-1 assume !(1 == ~E_7~0); 43489#L1432-1 assume !(1 == ~E_8~0); 43490#L1437-1 assume !(1 == ~E_9~0); 44408#L1442-1 assume !(1 == ~E_10~0); 44409#L1447-1 assume !(1 == ~E_11~0); 44277#L1452-1 assume !(1 == ~E_12~0); 43095#L1457-1 assume { :end_inline_reset_delta_events } true; 43096#L1803-2 [2022-07-14 16:03:20,275 INFO L754 eck$LassoCheckResult]: Loop: 43096#L1803-2 assume !false; 43432#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42968#L1169 assume !false; 43557#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43662#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43163#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43164#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 43939#L996 assume !(0 != eval_~tmp~0#1); 44051#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44052#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44022#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44023#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43267#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43268#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43516#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42960#L1214-3 assume !(0 == ~T5_E~0); 42961#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43708#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43709#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43740#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43133#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43134#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43565#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44142#L1254-3 assume !(0 == ~E_M~0); 44622#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44257#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43139#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43140#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44654#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43706#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43707#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43690#L1294-3 assume !(0 == ~E_8~0); 43691#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44073#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44074#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43603#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43604#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43612#L586-42 assume !(1 == ~m_pc~0); 43613#L586-44 is_master_triggered_~__retres1~0#1 := 0; 43208#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43209#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44633#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 43730#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43731#L605-42 assume 1 == ~t1_pc~0; 44328#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44036#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44037#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43732#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43733#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43744#L624-42 assume !(1 == ~t2_pc~0); 43745#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43888#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43048#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43049#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43562#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43563#L643-42 assume 1 == ~t3_pc~0; 43904#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43869#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43870#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43702#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43703#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44418#L662-42 assume !(1 == ~t4_pc~0); 44611#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43231#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43232#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43798#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44650#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44616#L681-42 assume !(1 == ~t5_pc~0); 43091#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 43092#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43451#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43452#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44466#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43588#L700-42 assume 1 == ~t6_pc~0; 43589#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43399#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44388#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44474#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44475#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44664#L719-42 assume !(1 == ~t7_pc~0); 43283#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43284#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43334#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43335#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 43665#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43666#L738-42 assume 1 == ~t8_pc~0; 43858#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43621#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43174#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43137#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43138#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43658#L757-42 assume 1 == ~t9_pc~0; 43994#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43318#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43319#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43462#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43436#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43437#L776-42 assume 1 == ~t10_pc~0; 44407#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44394#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44441#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44703#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44704#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44231#L795-42 assume !(1 == ~t11_pc~0); 44232#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43278#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43279#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43374#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43375#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43675#L814-42 assume !(1 == ~t12_pc~0); 43552#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43190#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43191#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42999#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43000#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43151#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43152#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43125#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43126#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43934#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44105#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44106#L1357-3 assume !(1 == ~T6_E~0); 44544#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44712#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44708#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42980#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42981#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43584#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43585#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44415#L1397-3 assume !(1 == ~E_1~0); 44673#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44056#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43236#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43237#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43953#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43954#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44543#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44312#L1437-3 assume !(1 == ~E_9~0); 44075#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44076#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43034#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43035#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43640#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43486#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44298#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 43227#L1822 assume !(0 == start_simulation_~tmp~3#1); 43228#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44177#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43482#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43483#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 44014#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44126#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44071#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44072#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 43096#L1803-2 [2022-07-14 16:03:20,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,276 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-07-14 16:03:20,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067163075] [2022-07-14 16:03:20,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067163075] [2022-07-14 16:03:20,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2067163075] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,307 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,308 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:20,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374293237] [2022-07-14 16:03:20,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,308 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:20,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1797209546, now seen corresponding path program 2 times [2022-07-14 16:03:20,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917192163] [2022-07-14 16:03:20,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [917192163] [2022-07-14 16:03:20,372 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [917192163] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,373 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952102452] [2022-07-14 16:03:20,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,374 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:20,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:20,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:20,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:20,375 INFO L87 Difference]: Start difference. First operand 1785 states and 2635 transitions. cyclomatic complexity: 851 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:20,440 INFO L93 Difference]: Finished difference Result 1785 states and 2630 transitions. [2022-07-14 16:03:20,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:20,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2630 transitions. [2022-07-14 16:03:20,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:20,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2630 transitions. [2022-07-14 16:03:20,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-07-14 16:03:20,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-07-14 16:03:20,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2630 transitions. [2022-07-14 16:03:20,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:20,458 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2630 transitions. [2022-07-14 16:03:20,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2630 transitions. [2022-07-14 16:03:20,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-07-14 16:03:20,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.473389355742297) internal successors, (2630), 1784 states have internal predecessors, (2630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2630 transitions. [2022-07-14 16:03:20,486 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2630 transitions. [2022-07-14 16:03:20,486 INFO L374 stractBuchiCegarLoop]: Abstraction has 1785 states and 2630 transitions. [2022-07-14 16:03:20,486 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:03:20,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2630 transitions. [2022-07-14 16:03:20,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-07-14 16:03:20,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:20,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:20,493 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,494 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,494 INFO L752 eck$LassoCheckResult]: Stem: 47321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48097#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48098#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46835#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 46836#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46738#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46739#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48017#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47357#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47358#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47262#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47263#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47765#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47766#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47024#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47025#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47450#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47451#L1194 assume !(0 == ~M_E~0); 47597#L1194-2 assume !(0 == ~T1_E~0); 47598#L1199-1 assume !(0 == ~T2_E~0); 47895#L1204-1 assume !(0 == ~T3_E~0); 47819#L1209-1 assume !(0 == ~T4_E~0); 47820#L1214-1 assume !(0 == ~T5_E~0); 48205#L1219-1 assume !(0 == ~T6_E~0); 48293#L1224-1 assume !(0 == ~T7_E~0); 47098#L1229-1 assume !(0 == ~T8_E~0); 46663#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46664#L1239-1 assume !(0 == ~T10_E~0); 46702#L1244-1 assume !(0 == ~T11_E~0); 46703#L1249-1 assume !(0 == ~T12_E~0); 47392#L1254-1 assume !(0 == ~E_M~0); 46602#L1259-1 assume !(0 == ~E_1~0); 46566#L1264-1 assume !(0 == ~E_2~0); 46567#L1269-1 assume !(0 == ~E_3~0); 48296#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48235#L1279-1 assume !(0 == ~E_5~0); 46776#L1284-1 assume !(0 == ~E_6~0); 46777#L1289-1 assume !(0 == ~E_7~0); 47456#L1294-1 assume !(0 == ~E_8~0); 47457#L1299-1 assume !(0 == ~E_9~0); 47468#L1304-1 assume !(0 == ~E_10~0); 48287#L1309-1 assume !(0 == ~E_11~0); 48291#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 46731#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46652#L586 assume 1 == ~m_pc~0; 46653#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46724#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47791#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46932#L1485 assume !(0 != activate_threads_~tmp~1#1); 46933#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48020#L605 assume !(1 == ~t1_pc~0); 47536#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47287#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47288#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48170#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47867#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47205#L624 assume 1 == ~t2_pc~0; 46707#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46708#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47365#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48194#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 48057#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47935#L643 assume !(1 == ~t3_pc~0); 47782#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47484#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47391#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47034#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 47035#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46796#L662 assume 1 == ~t4_pc~0; 46797#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46757#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46758#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47510#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 46641#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46642#L681 assume !(1 == ~t5_pc~0); 46514#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46515#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47562#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48165#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 47046#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47047#L700 assume 1 == ~t6_pc~0; 47746#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46787#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46788#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46837#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 46838#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48101#L719 assume 1 == ~t7_pc~0; 48178#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47004#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47775#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47776#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 46528#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46529#L738 assume !(1 == ~t8_pc~0); 47901#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47811#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46897#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46898#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47594#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47958#L757 assume 1 == ~t9_pc~0; 47959#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46523#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46524#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47727#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 47554#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47555#L776 assume !(1 == ~t10_pc~0); 46548#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46547#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46939#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46778#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 46779#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46732#L795 assume 1 == ~t11_pc~0; 46733#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47067#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48009#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48010#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 47780#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47768#L814 assume !(1 == ~t12_pc~0); 47623#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47624#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47995#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48094#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 46989#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46990#L1332 assume !(1 == ~M_E~0); 48068#L1332-2 assume !(1 == ~T1_E~0); 48251#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47695#L1342-1 assume !(1 == ~T3_E~0); 47696#L1347-1 assume !(1 == ~T4_E~0); 48090#L1352-1 assume !(1 == ~T5_E~0); 47964#L1357-1 assume !(1 == ~T6_E~0); 47260#L1362-1 assume !(1 == ~T7_E~0); 47261#L1367-1 assume !(1 == ~T8_E~0); 46872#L1372-1 assume !(1 == ~T9_E~0); 46873#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47178#L1382-1 assume !(1 == ~T11_E~0); 47179#L1387-1 assume !(1 == ~T12_E~0); 47864#L1392-1 assume !(1 == ~E_M~0); 47206#L1397-1 assume !(1 == ~E_1~0); 47207#L1402-1 assume !(1 == ~E_2~0); 46885#L1407-1 assume !(1 == ~E_3~0); 46886#L1412-1 assume !(1 == ~E_4~0); 48035#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 48036#L1422-1 assume !(1 == ~E_6~0); 48252#L1427-1 assume !(1 == ~E_7~0); 47068#L1432-1 assume !(1 == ~E_8~0); 47069#L1437-1 assume !(1 == ~E_9~0); 47985#L1442-1 assume !(1 == ~E_10~0); 47986#L1447-1 assume !(1 == ~E_11~0); 47855#L1452-1 assume !(1 == ~E_12~0); 46672#L1457-1 assume { :end_inline_reset_delta_events } true; 46673#L1803-2 [2022-07-14 16:03:20,494 INFO L754 eck$LassoCheckResult]: Loop: 46673#L1803-2 assume !false; 47009#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46545#L1169 assume !false; 47136#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47241#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46740#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46741#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47516#L996 assume !(0 != eval_~tmp~0#1); 47628#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47629#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47599#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47600#L1194-5 assume !(0 == ~T1_E~0); 46844#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46845#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47093#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46541#L1214-3 assume !(0 == ~T5_E~0); 46542#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47285#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47286#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47323#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46710#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46711#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47142#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47719#L1254-3 assume !(0 == ~E_M~0); 48199#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47834#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46716#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46717#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48231#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47283#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47284#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47267#L1294-3 assume !(0 == ~E_8~0); 47268#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47650#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47651#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47180#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47181#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47189#L586-42 assume !(1 == ~m_pc~0); 47190#L586-44 is_master_triggered_~__retres1~0#1 := 0; 46782#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46783#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48210#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 47307#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47308#L605-42 assume 1 == ~t1_pc~0; 47905#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47613#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47614#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47309#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47310#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47318#L624-42 assume !(1 == ~t2_pc~0); 47319#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47465#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46625#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46626#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47139#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47140#L643-42 assume 1 == ~t3_pc~0; 47480#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47446#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47447#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47279#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47280#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47994#L662-42 assume !(1 == ~t4_pc~0); 48188#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 46808#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46809#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47375#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48227#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48193#L681-42 assume 1 == ~t5_pc~0; 47491#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46669#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47028#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47029#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48043#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47165#L700-42 assume 1 == ~t6_pc~0; 47166#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46976#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47965#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48051#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48052#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48241#L719-42 assume 1 == ~t7_pc~0; 47762#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46861#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46911#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46912#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 47242#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47243#L738-42 assume 1 == ~t8_pc~0; 47435#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47198#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46751#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46714#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46715#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47235#L757-42 assume 1 == ~t9_pc~0; 47568#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46895#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46896#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47039#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47012#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47013#L776-42 assume 1 == ~t10_pc~0; 47984#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47971#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48018#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48280#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48281#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47808#L795-42 assume !(1 == ~t11_pc~0); 47809#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 46855#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46856#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46951#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46952#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47252#L814-42 assume 1 == ~t12_pc~0; 48023#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46767#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46768#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46576#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46577#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46728#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46729#L1332-5 assume !(1 == ~T1_E~0); 46700#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46701#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47511#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47682#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47683#L1357-3 assume !(1 == ~T6_E~0); 48121#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48289#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48285#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46557#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46558#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47161#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47162#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47992#L1397-3 assume !(1 == ~E_1~0); 48250#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47633#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46813#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46814#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47530#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47531#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48120#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47889#L1437-3 assume !(1 == ~E_9~0); 47652#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47653#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46611#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46612#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47217#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47063#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47875#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 46804#L1822 assume !(0 == start_simulation_~tmp~3#1); 46805#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47754#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47059#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47060#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 47591#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47703#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47646#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47647#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 46673#L1803-2 [2022-07-14 16:03:20,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,495 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-07-14 16:03:20,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691786054] [2022-07-14 16:03:20,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,534 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691786054] [2022-07-14 16:03:20,534 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691786054] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743064913] [2022-07-14 16:03:20,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,535 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:20,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,536 INFO L85 PathProgramCache]: Analyzing trace with hash -182395981, now seen corresponding path program 1 times [2022-07-14 16:03:20,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572752179] [2022-07-14 16:03:20,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572752179] [2022-07-14 16:03:20,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572752179] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,572 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,572 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121530331] [2022-07-14 16:03:20,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,573 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:20,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:20,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:20,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:20,574 INFO L87 Difference]: Start difference. First operand 1785 states and 2630 transitions. cyclomatic complexity: 846 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:20,684 INFO L93 Difference]: Finished difference Result 3314 states and 4868 transitions. [2022-07-14 16:03:20,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:20,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3314 states and 4868 transitions. [2022-07-14 16:03:20,700 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3125 [2022-07-14 16:03:20,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3314 states to 3314 states and 4868 transitions. [2022-07-14 16:03:20,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3314 [2022-07-14 16:03:20,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3314 [2022-07-14 16:03:20,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3314 states and 4868 transitions. [2022-07-14 16:03:20,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:20,719 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3314 states and 4868 transitions. [2022-07-14 16:03:20,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3314 states and 4868 transitions. [2022-07-14 16:03:20,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3314 to 3314. [2022-07-14 16:03:20,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3314 states, 3314 states have (on average 1.4689197344598672) internal successors, (4868), 3313 states have internal predecessors, (4868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:20,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3314 states to 3314 states and 4868 transitions. [2022-07-14 16:03:20,783 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3314 states and 4868 transitions. [2022-07-14 16:03:20,783 INFO L374 stractBuchiCegarLoop]: Abstraction has 3314 states and 4868 transitions. [2022-07-14 16:03:20,783 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:03:20,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3314 states and 4868 transitions. [2022-07-14 16:03:20,794 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3125 [2022-07-14 16:03:20,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:20,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:20,797 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,797 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:20,797 INFO L752 eck$LassoCheckResult]: Stem: 52436#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53250#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53251#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51944#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 51945#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51847#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51848#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53157#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52472#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52473#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52377#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52378#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52892#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52893#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52134#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52135#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52568#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52569#L1194 assume !(0 == ~M_E~0); 52719#L1194-2 assume !(0 == ~T1_E~0); 52720#L1199-1 assume !(0 == ~T2_E~0); 53025#L1204-1 assume !(0 == ~T3_E~0); 52948#L1209-1 assume !(0 == ~T4_E~0); 52949#L1214-1 assume !(0 == ~T5_E~0); 53377#L1219-1 assume !(0 == ~T6_E~0); 53487#L1224-1 assume !(0 == ~T7_E~0); 52211#L1229-1 assume !(0 == ~T8_E~0); 51772#L1234-1 assume !(0 == ~T9_E~0); 51773#L1239-1 assume !(0 == ~T10_E~0); 51811#L1244-1 assume !(0 == ~T11_E~0); 51812#L1249-1 assume !(0 == ~T12_E~0); 52508#L1254-1 assume !(0 == ~E_M~0); 51711#L1259-1 assume !(0 == ~E_1~0); 51675#L1264-1 assume !(0 == ~E_2~0); 51676#L1269-1 assume !(0 == ~E_3~0); 53493#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53415#L1279-1 assume !(0 == ~E_5~0); 51885#L1284-1 assume !(0 == ~E_6~0); 51886#L1289-1 assume !(0 == ~E_7~0); 52573#L1294-1 assume !(0 == ~E_8~0); 52574#L1299-1 assume !(0 == ~E_9~0); 52586#L1304-1 assume !(0 == ~E_10~0); 53477#L1309-1 assume !(0 == ~E_11~0); 53485#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 51840#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51761#L586 assume 1 == ~m_pc~0; 51762#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51833#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52918#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52042#L1485 assume !(0 != activate_threads_~tmp~1#1); 52043#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53162#L605 assume !(1 == ~t1_pc~0); 52655#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52402#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52403#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53331#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52996#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52320#L624 assume 1 == ~t2_pc~0; 51816#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51817#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52480#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53361#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 53204#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53068#L643 assume !(1 == ~t3_pc~0); 52909#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52602#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52507#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52144#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 52145#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51905#L662 assume 1 == ~t4_pc~0; 51906#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51866#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51867#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52628#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 51750#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51751#L681 assume !(1 == ~t5_pc~0); 51623#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 51624#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52682#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53326#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 52158#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52159#L700 assume 1 == ~t6_pc~0; 52873#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51896#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51897#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51946#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 51947#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53254#L719 assume 1 == ~t7_pc~0; 53340#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52114#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52902#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52903#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 51637#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51638#L738 assume !(1 == ~t8_pc~0); 53031#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52938#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52007#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52008#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52716#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53091#L757 assume 1 == ~t9_pc~0; 53092#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51632#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51633#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52853#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 52674#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52675#L776 assume !(1 == ~t10_pc~0); 51657#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 51656#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52046#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51887#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 51888#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51841#L795 assume 1 == ~t11_pc~0; 51842#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52179#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53149#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53150#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 52907#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52895#L814 assume !(1 == ~t12_pc~0); 52745#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52746#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53131#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53247#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 52099#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52100#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 53216#L1332-2 assume !(1 == ~T1_E~0); 54653#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54652#L1342-1 assume !(1 == ~T3_E~0); 54651#L1347-1 assume !(1 == ~T4_E~0); 54650#L1352-1 assume !(1 == ~T5_E~0); 54649#L1357-1 assume !(1 == ~T6_E~0); 54648#L1362-1 assume !(1 == ~T7_E~0); 54647#L1367-1 assume !(1 == ~T8_E~0); 54646#L1372-1 assume !(1 == ~T9_E~0); 51982#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52291#L1382-1 assume !(1 == ~T11_E~0); 52292#L1387-1 assume !(1 == ~T12_E~0); 52993#L1392-1 assume !(1 == ~E_M~0); 52321#L1397-1 assume !(1 == ~E_1~0); 52322#L1402-1 assume !(1 == ~E_2~0); 51995#L1407-1 assume !(1 == ~E_3~0); 51996#L1412-1 assume !(1 == ~E_4~0); 53178#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53179#L1422-1 assume !(1 == ~E_6~0); 53437#L1427-1 assume !(1 == ~E_7~0); 52180#L1432-1 assume !(1 == ~E_8~0); 52181#L1437-1 assume !(1 == ~E_9~0); 53120#L1442-1 assume !(1 == ~E_10~0); 53121#L1447-1 assume !(1 == ~E_11~0); 52983#L1452-1 assume !(1 == ~E_12~0); 51781#L1457-1 assume { :end_inline_reset_delta_events } true; 51782#L1803-2 [2022-07-14 16:03:20,798 INFO L754 eck$LassoCheckResult]: Loop: 51782#L1803-2 assume !false; 53411#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53514#L1169 assume !false; 53513#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53510#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53499#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52634#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 52635#L996 assume !(0 != eval_~tmp~0#1); 52750#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52751#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53473#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53479#L1194-5 assume !(0 == ~T1_E~0); 51953#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51954#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52206#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51650#L1214-3 assume !(0 == ~T5_E~0); 51651#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52400#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52401#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52438#L1234-3 assume !(0 == ~T9_E~0); 51819#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51820#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52255#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52845#L1254-3 assume !(0 == ~E_M~0); 53371#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52963#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51825#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51826#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53410#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52398#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52399#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 52382#L1294-3 assume !(0 == ~E_8~0); 52383#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52772#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52773#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52293#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52294#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52299#L586-42 assume !(1 == ~m_pc~0); 52300#L586-44 is_master_triggered_~__retres1~0#1 := 0; 51891#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51892#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53383#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 52422#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52423#L605-42 assume 1 == ~t1_pc~0; 53035#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52735#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52736#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52424#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52425#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52433#L624-42 assume !(1 == ~t2_pc~0); 52434#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 52583#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51734#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51735#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52252#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52253#L643-42 assume 1 == ~t3_pc~0; 52598#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52564#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52565#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52394#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52395#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53130#L662-42 assume !(1 == ~t4_pc~0); 53351#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51917#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51918#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52491#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53405#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53360#L681-42 assume 1 == ~t5_pc~0; 52609#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51778#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52138#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52139#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53187#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52278#L700-42 assume !(1 == ~t6_pc~0); 52085#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 52086#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53098#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53198#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53199#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53424#L719-42 assume !(1 == ~t7_pc~0); 51969#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 51970#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52021#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52022#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 52357#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52358#L738-42 assume 1 == ~t8_pc~0; 52553#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52313#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51860#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51823#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51824#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52350#L757-42 assume 1 == ~t9_pc~0; 52688#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52005#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52006#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52149#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52122#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52123#L776-42 assume 1 == ~t10_pc~0; 53119#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53104#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53158#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53468#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53469#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52935#L795-42 assume !(1 == ~t11_pc~0); 52936#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 51964#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51965#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52061#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52062#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52367#L814-42 assume !(1 == ~t12_pc~0); 52242#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 51876#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51877#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51685#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51686#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51837#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51838#L1332-5 assume !(1 == ~T1_E~0); 51809#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51810#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52629#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52805#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52806#L1357-3 assume !(1 == ~T6_E~0); 53275#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53483#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53474#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51666#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51667#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52274#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52275#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53127#L1397-3 assume !(1 == ~E_1~0); 53435#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52755#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51922#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51923#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52649#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52650#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53274#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53018#L1437-3 assume !(1 == ~E_9~0); 52774#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52775#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51720#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51721#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52332#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52175#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53005#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 51913#L1822 assume !(0 == start_simulation_~tmp~3#1); 51914#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52881#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52482#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52712#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 52713#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52939#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52940#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 53303#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 51782#L1803-2 [2022-07-14 16:03:20,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,799 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2022-07-14 16:03:20,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177071279] [2022-07-14 16:03:20,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177071279] [2022-07-14 16:03:20,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1177071279] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162296627] [2022-07-14 16:03:20,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,831 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:20,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:20,831 INFO L85 PathProgramCache]: Analyzing trace with hash 1944173368, now seen corresponding path program 1 times [2022-07-14 16:03:20,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:20,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604291012] [2022-07-14 16:03:20,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:20,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:20,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:20,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:20,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:20,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604291012] [2022-07-14 16:03:20,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604291012] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:20,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:20,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:20,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13358303] [2022-07-14 16:03:20,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:20,902 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:20,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:20,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:20,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:20,903 INFO L87 Difference]: Start difference. First operand 3314 states and 4868 transitions. cyclomatic complexity: 1556 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:21,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:21,215 INFO L93 Difference]: Finished difference Result 6162 states and 9033 transitions. [2022-07-14 16:03:21,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:21,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6162 states and 9033 transitions. [2022-07-14 16:03:21,249 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5945 [2022-07-14 16:03:21,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6162 states to 6162 states and 9033 transitions. [2022-07-14 16:03:21,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6162 [2022-07-14 16:03:21,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6162 [2022-07-14 16:03:21,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6162 states and 9033 transitions. [2022-07-14 16:03:21,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:21,281 INFO L369 hiAutomatonCegarLoop]: Abstraction has 6162 states and 9033 transitions. [2022-07-14 16:03:21,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6162 states and 9033 transitions. [2022-07-14 16:03:21,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6162 to 6160. [2022-07-14 16:03:21,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6160 states, 6160 states have (on average 1.4660714285714285) internal successors, (9031), 6159 states have internal predecessors, (9031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:21,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6160 states to 6160 states and 9031 transitions. [2022-07-14 16:03:21,408 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6160 states and 9031 transitions. [2022-07-14 16:03:21,408 INFO L374 stractBuchiCegarLoop]: Abstraction has 6160 states and 9031 transitions. [2022-07-14 16:03:21,408 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:03:21,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6160 states and 9031 transitions. [2022-07-14 16:03:21,430 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5945 [2022-07-14 16:03:21,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:21,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:21,432 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:21,432 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:21,432 INFO L752 eck$LassoCheckResult]: Stem: 61923#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61924#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62764#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62765#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61434#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 61435#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61336#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61337#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62669#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61965#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 61966#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61870#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61871#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62387#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62388#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 61624#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 61625#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62061#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62062#L1194 assume !(0 == ~M_E~0); 62215#L1194-2 assume !(0 == ~T1_E~0); 62216#L1199-1 assume !(0 == ~T2_E~0); 62527#L1204-1 assume !(0 == ~T3_E~0); 62445#L1209-1 assume !(0 == ~T4_E~0); 62446#L1214-1 assume !(0 == ~T5_E~0); 62895#L1219-1 assume !(0 == ~T6_E~0); 63019#L1224-1 assume !(0 == ~T7_E~0); 61699#L1229-1 assume !(0 == ~T8_E~0); 61250#L1234-1 assume !(0 == ~T9_E~0); 61251#L1239-1 assume !(0 == ~T10_E~0); 61294#L1244-1 assume !(0 == ~T11_E~0); 61295#L1249-1 assume !(0 == ~T12_E~0); 62001#L1254-1 assume !(0 == ~E_M~0); 61197#L1259-1 assume !(0 == ~E_1~0); 61161#L1264-1 assume !(0 == ~E_2~0); 61162#L1269-1 assume !(0 == ~E_3~0); 63025#L1274-1 assume !(0 == ~E_4~0); 62934#L1279-1 assume !(0 == ~E_5~0); 61374#L1284-1 assume !(0 == ~E_6~0); 61375#L1289-1 assume !(0 == ~E_7~0); 62068#L1294-1 assume !(0 == ~E_8~0); 62069#L1299-1 assume !(0 == ~E_9~0); 62079#L1304-1 assume !(0 == ~E_10~0); 63009#L1309-1 assume !(0 == ~E_11~0); 63015#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61327#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61247#L586 assume 1 == ~m_pc~0; 61248#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61320#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62414#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61531#L1485 assume !(0 != activate_threads_~tmp~1#1); 61532#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62674#L605 assume !(1 == ~t1_pc~0); 62151#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61895#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61896#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62850#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62496#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61810#L624 assume 1 == ~t2_pc~0; 61300#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61301#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61974#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62883#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 62713#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62570#L643 assume !(1 == ~t3_pc~0); 62407#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62093#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62000#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61634#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 61635#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61394#L662 assume 1 == ~t4_pc~0; 61395#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61353#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61354#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62125#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 61234#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61235#L681 assume !(1 == ~t5_pc~0); 61109#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61110#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62179#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62842#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 61646#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61647#L700 assume 1 == ~t6_pc~0; 62367#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61385#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61386#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61436#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 61437#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62768#L719 assume 1 == ~t7_pc~0; 62859#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61603#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62397#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62398#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 61123#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61124#L738 assume !(1 == ~t8_pc~0); 62533#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62437#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61496#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61497#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62212#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62598#L757 assume 1 == ~t9_pc~0; 62599#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61118#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61119#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62347#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 62171#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62172#L776 assume !(1 == ~t10_pc~0); 61143#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61142#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61535#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61376#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 61377#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61328#L795 assume 1 == ~t11_pc~0; 61329#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61665#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62661#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62662#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 62405#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62390#L814 assume !(1 == ~t12_pc~0); 62242#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62243#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62640#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62759#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 61588#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61589#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 62725#L1332-2 assume !(1 == ~T1_E~0); 63877#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63876#L1342-1 assume !(1 == ~T3_E~0); 63875#L1347-1 assume !(1 == ~T4_E~0); 63874#L1352-1 assume !(1 == ~T5_E~0); 62605#L1357-1 assume !(1 == ~T6_E~0); 61866#L1362-1 assume !(1 == ~T7_E~0); 61867#L1367-1 assume !(1 == ~T8_E~0); 61471#L1372-1 assume !(1 == ~T9_E~0); 61472#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62027#L1382-1 assume !(1 == ~T11_E~0); 62493#L1387-1 assume !(1 == ~T12_E~0); 62494#L1392-1 assume !(1 == ~E_M~0); 61811#L1397-1 assume !(1 == ~E_1~0); 61812#L1402-1 assume !(1 == ~E_2~0); 61482#L1407-1 assume !(1 == ~E_3~0); 61483#L1412-1 assume !(1 == ~E_4~0); 63786#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63782#L1422-1 assume !(1 == ~E_6~0); 63778#L1427-1 assume !(1 == ~E_7~0); 63769#L1432-1 assume !(1 == ~E_8~0); 63153#L1437-1 assume !(1 == ~E_9~0); 63124#L1442-1 assume !(1 == ~E_10~0); 63104#L1447-1 assume !(1 == ~E_11~0); 63092#L1452-1 assume !(1 == ~E_12~0); 63081#L1457-1 assume { :end_inline_reset_delta_events } true; 63073#L1803-2 [2022-07-14 16:03:21,433 INFO L754 eck$LassoCheckResult]: Loop: 63073#L1803-2 assume !false; 63067#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63062#L1169 assume !false; 63061#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63058#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63047#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63046#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63044#L996 assume !(0 != eval_~tmp~0#1); 63043#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63042#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63040#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63041#L1194-5 assume !(0 == ~T1_E~0); 65989#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65987#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65985#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65983#L1214-3 assume !(0 == ~T5_E~0); 65981#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65979#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65976#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 65974#L1234-3 assume !(0 == ~T9_E~0); 65972#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65970#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65968#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65966#L1254-3 assume !(0 == ~E_M~0); 65963#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65961#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65959#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65957#L1274-3 assume !(0 == ~E_4~0); 65955#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65953#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65950#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65947#L1294-3 assume !(0 == ~E_8~0); 65943#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65940#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65937#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65934#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 65930#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65927#L586-42 assume !(1 == ~m_pc~0); 65923#L586-44 is_master_triggered_~__retres1~0#1 := 0; 65919#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65916#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65913#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 65908#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65903#L605-42 assume 1 == ~t1_pc~0; 65897#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65893#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65889#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65885#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65880#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65875#L624-42 assume !(1 == ~t2_pc~0); 65869#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 65865#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65861#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65857#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65852#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65847#L643-42 assume 1 == ~t3_pc~0; 65841#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65837#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65833#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65828#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65821#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65815#L662-42 assume 1 == ~t4_pc~0; 65805#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65798#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65777#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65772#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65766#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65761#L681-42 assume !(1 == ~t5_pc~0); 65755#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 65749#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65742#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65739#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65738#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65737#L700-42 assume !(1 == ~t6_pc~0); 65687#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64057#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64055#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64053#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64051#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64049#L719-42 assume 1 == ~t7_pc~0; 64045#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64043#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64041#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64039#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 64037#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64035#L738-42 assume !(1 == ~t8_pc~0); 64032#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 64029#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64027#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64025#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64023#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64021#L757-42 assume 1 == ~t9_pc~0; 64017#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64015#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64013#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64011#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64009#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64007#L776-42 assume 1 == ~t10_pc~0; 64003#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64001#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63999#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 63997#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63995#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63993#L795-42 assume !(1 == ~t11_pc~0); 63989#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 63987#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63985#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63983#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 63981#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63979#L814-42 assume 1 == ~t12_pc~0; 63975#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 63973#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63971#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 63969#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63967#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63965#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61325#L1332-5 assume !(1 == ~T1_E~0); 63962#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63960#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63958#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63957#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63942#L1357-3 assume !(1 == ~T6_E~0); 63922#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63920#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63918#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63001#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63901#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63872#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63871#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63869#L1397-3 assume !(1 == ~E_1~0); 63850#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63824#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63817#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63811#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63807#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63803#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63799#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63794#L1437-3 assume !(1 == ~E_9~0); 63788#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63784#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 63780#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63776#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63767#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63752#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63750#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 63748#L1822 assume !(0 == start_simulation_~tmp~3#1); 62602#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63146#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63137#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63136#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 63120#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63103#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63091#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63080#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 63073#L1803-2 [2022-07-14 16:03:21,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:21,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2022-07-14 16:03:21,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:21,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025039966] [2022-07-14 16:03:21,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:21,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:21,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:21,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:21,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:21,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025039966] [2022-07-14 16:03:21,466 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025039966] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:21,466 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:21,466 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:21,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700149486] [2022-07-14 16:03:21,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:21,467 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:21,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:21,467 INFO L85 PathProgramCache]: Analyzing trace with hash 777249657, now seen corresponding path program 1 times [2022-07-14 16:03:21,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:21,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051992251] [2022-07-14 16:03:21,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:21,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:21,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:21,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:21,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:21,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051992251] [2022-07-14 16:03:21,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051992251] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:21,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:21,501 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:21,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832448354] [2022-07-14 16:03:21,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:21,501 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:21,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:21,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:21,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:21,502 INFO L87 Difference]: Start difference. First operand 6160 states and 9031 transitions. cyclomatic complexity: 2875 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:21,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:21,694 INFO L93 Difference]: Finished difference Result 11630 states and 17014 transitions. [2022-07-14 16:03:21,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:21,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11630 states and 17014 transitions. [2022-07-14 16:03:21,754 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11399 [2022-07-14 16:03:21,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11630 states to 11630 states and 17014 transitions. [2022-07-14 16:03:21,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11630 [2022-07-14 16:03:21,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11630 [2022-07-14 16:03:21,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11630 states and 17014 transitions. [2022-07-14 16:03:21,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:21,868 INFO L369 hiAutomatonCegarLoop]: Abstraction has 11630 states and 17014 transitions. [2022-07-14 16:03:21,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11630 states and 17014 transitions. [2022-07-14 16:03:22,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11630 to 11626. [2022-07-14 16:03:22,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11626 states, 11626 states have (on average 1.4630999483915361) internal successors, (17010), 11625 states have internal predecessors, (17010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:22,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11626 states to 11626 states and 17010 transitions. [2022-07-14 16:03:22,057 INFO L392 hiAutomatonCegarLoop]: Abstraction has 11626 states and 17010 transitions. [2022-07-14 16:03:22,057 INFO L374 stractBuchiCegarLoop]: Abstraction has 11626 states and 17010 transitions. [2022-07-14 16:03:22,057 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:03:22,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11626 states and 17010 transitions. [2022-07-14 16:03:22,094 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11399 [2022-07-14 16:03:22,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:22,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:22,097 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:22,097 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:22,097 INFO L752 eck$LassoCheckResult]: Stem: 79720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 79721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80527#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80528#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79233#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 79234#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79134#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79135#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80442#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79762#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 79763#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 79667#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 79668#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 80180#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80181#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 79423#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 79424#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 79856#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79857#L1194 assume !(0 == ~M_E~0); 80006#L1194-2 assume !(0 == ~T1_E~0); 80007#L1199-1 assume !(0 == ~T2_E~0); 80318#L1204-1 assume !(0 == ~T3_E~0); 80236#L1209-1 assume !(0 == ~T4_E~0); 80237#L1214-1 assume !(0 == ~T5_E~0); 80640#L1219-1 assume !(0 == ~T6_E~0); 80741#L1224-1 assume !(0 == ~T7_E~0); 79500#L1229-1 assume !(0 == ~T8_E~0); 79050#L1234-1 assume !(0 == ~T9_E~0); 79051#L1239-1 assume !(0 == ~T10_E~0); 79093#L1244-1 assume !(0 == ~T11_E~0); 79094#L1249-1 assume !(0 == ~T12_E~0); 79797#L1254-1 assume !(0 == ~E_M~0); 78997#L1259-1 assume !(0 == ~E_1~0); 78961#L1264-1 assume !(0 == ~E_2~0); 78962#L1269-1 assume !(0 == ~E_3~0); 80745#L1274-1 assume !(0 == ~E_4~0); 80675#L1279-1 assume !(0 == ~E_5~0); 79172#L1284-1 assume !(0 == ~E_6~0); 79173#L1289-1 assume !(0 == ~E_7~0); 79863#L1294-1 assume !(0 == ~E_8~0); 79864#L1299-1 assume !(0 == ~E_9~0); 79874#L1304-1 assume !(0 == ~E_10~0); 80734#L1309-1 assume !(0 == ~E_11~0); 80739#L1314-1 assume !(0 == ~E_12~0); 79126#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79047#L586 assume 1 == ~m_pc~0; 79048#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79119#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80206#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79331#L1485 assume !(0 != activate_threads_~tmp~1#1); 79332#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80446#L605 assume !(1 == ~t1_pc~0); 79944#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79692#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79693#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80603#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80286#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79610#L624 assume 1 == ~t2_pc~0; 79099#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79100#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79770#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80629#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 80485#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80358#L643 assume !(1 == ~t3_pc~0); 80199#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79886#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79796#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79433#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 79434#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79192#L662 assume 1 == ~t4_pc~0; 79193#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79151#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79152#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79918#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 79034#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79035#L681 assume !(1 == ~t5_pc~0); 78909#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 78910#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79971#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80597#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 79445#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79446#L700 assume 1 == ~t6_pc~0; 80161#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79183#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79184#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79235#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 79236#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80531#L719 assume 1 == ~t7_pc~0; 80608#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79403#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80190#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80191#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 78923#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78924#L738 assume !(1 == ~t8_pc~0); 80324#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 80228#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79296#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79297#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80003#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80381#L757 assume 1 == ~t9_pc~0; 80382#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78918#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78919#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80140#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 79963#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79964#L776 assume !(1 == ~t10_pc~0); 78943#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 78942#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79335#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79174#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 79175#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79127#L795 assume 1 == ~t11_pc~0; 79128#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 79466#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80434#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80435#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 80196#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80183#L814 assume !(1 == ~t12_pc~0); 80033#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 80034#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80419#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80524#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 79388#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79389#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 80496#L1332-2 assume !(1 == ~T1_E~0); 80691#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80105#L1342-1 assume !(1 == ~T3_E~0); 80106#L1347-1 assume !(1 == ~T4_E~0); 80519#L1352-1 assume !(1 == ~T5_E~0); 80388#L1357-1 assume !(1 == ~T6_E~0); 79663#L1362-1 assume !(1 == ~T7_E~0); 79664#L1367-1 assume !(1 == ~T8_E~0); 79271#L1372-1 assume !(1 == ~T9_E~0); 79272#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 79581#L1382-1 assume !(1 == ~T11_E~0); 79582#L1387-1 assume !(1 == ~T12_E~0); 80284#L1392-1 assume !(1 == ~E_M~0); 81018#L1397-1 assume !(1 == ~E_1~0); 80976#L1402-1 assume !(1 == ~E_2~0); 80974#L1407-1 assume !(1 == ~E_3~0); 80972#L1412-1 assume !(1 == ~E_4~0); 80928#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 80926#L1422-1 assume !(1 == ~E_6~0); 80924#L1427-1 assume !(1 == ~E_7~0); 80884#L1432-1 assume !(1 == ~E_8~0); 80836#L1437-1 assume !(1 == ~E_9~0); 80822#L1442-1 assume !(1 == ~E_10~0); 80820#L1447-1 assume !(1 == ~E_11~0); 80805#L1452-1 assume !(1 == ~E_12~0); 80792#L1457-1 assume { :end_inline_reset_delta_events } true; 80784#L1803-2 [2022-07-14 16:03:22,098 INFO L754 eck$LassoCheckResult]: Loop: 80784#L1803-2 assume !false; 80778#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80773#L1169 assume !false; 80772#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 80769#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 80758#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 80757#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 80755#L996 assume !(0 != eval_~tmp~0#1); 80754#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80753#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80751#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 80752#L1194-5 assume !(0 == ~T1_E~0); 85624#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85622#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85620#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85618#L1214-3 assume !(0 == ~T5_E~0); 85615#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85613#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85611#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85609#L1234-3 assume !(0 == ~T9_E~0); 85607#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85605#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85602#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85600#L1254-3 assume !(0 == ~E_M~0); 85598#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85596#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 85594#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85592#L1274-3 assume !(0 == ~E_4~0); 85589#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 85587#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85585#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 85583#L1294-3 assume !(0 == ~E_8~0); 85581#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85579#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85576#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 85574#L1314-3 assume !(0 == ~E_12~0); 85572#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85570#L586-42 assume !(1 == ~m_pc~0); 85568#L586-44 is_master_triggered_~__retres1~0#1 := 0; 85565#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85562#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 85560#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 85558#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85556#L605-42 assume 1 == ~t1_pc~0; 85553#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85551#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85548#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85546#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85544#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85542#L624-42 assume !(1 == ~t2_pc~0); 85539#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 85537#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85534#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85532#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85530#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85528#L643-42 assume 1 == ~t3_pc~0; 85525#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 85521#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85519#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85517#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85516#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85515#L662-42 assume !(1 == ~t4_pc~0); 85513#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 85512#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85511#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85510#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 85509#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85508#L681-42 assume !(1 == ~t5_pc~0); 85507#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 84905#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84902#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84900#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 84898#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84896#L700-42 assume !(1 == ~t6_pc~0); 84893#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 84891#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84888#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84886#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 84884#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84882#L719-42 assume !(1 == ~t7_pc~0); 84880#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 84877#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84874#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84872#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 84870#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84868#L738-42 assume 1 == ~t8_pc~0; 84865#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84863#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84860#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84858#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84856#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84854#L757-42 assume 1 == ~t9_pc~0; 84843#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84841#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84839#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84837#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 84835#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84833#L776-42 assume 1 == ~t10_pc~0; 84829#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 84827#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84825#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84823#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84821#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84819#L795-42 assume !(1 == ~t11_pc~0); 84741#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 84739#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84737#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84723#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84714#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81336#L814-42 assume 1 == ~t12_pc~0; 81333#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 81331#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81329#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81327#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 81325#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81323#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 79124#L1332-5 assume !(1 == ~T1_E~0); 81228#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81225#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81223#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81222#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81219#L1357-3 assume !(1 == ~T6_E~0); 81140#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81138#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81136#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81133#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81129#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 81128#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81055#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81053#L1397-3 assume !(1 == ~E_1~0); 81050#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81048#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 80989#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80985#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80983#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80951#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 80949#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 80947#L1437-3 assume !(1 == ~E_9~0); 80945#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 80943#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 80941#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 80936#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 80881#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 80868#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 80866#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 80863#L1822 assume !(0 == start_simulation_~tmp~3#1); 80385#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 80830#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 80821#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 80819#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 80817#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80815#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80802#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 80791#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 80784#L1803-2 [2022-07-14 16:03:22,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:22,098 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2022-07-14 16:03:22,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:22,099 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117265406] [2022-07-14 16:03:22,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:22,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:22,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:22,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:22,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:22,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117265406] [2022-07-14 16:03:22,128 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117265406] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:22,128 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:22,128 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:22,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602691501] [2022-07-14 16:03:22,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:22,129 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:22,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:22,129 INFO L85 PathProgramCache]: Analyzing trace with hash -384267012, now seen corresponding path program 1 times [2022-07-14 16:03:22,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:22,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021224462] [2022-07-14 16:03:22,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:22,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:22,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:22,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:22,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:22,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021224462] [2022-07-14 16:03:22,164 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2021224462] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:22,164 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:22,164 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:22,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816496301] [2022-07-14 16:03:22,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:22,165 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:22,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:22,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:22,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:22,166 INFO L87 Difference]: Start difference. First operand 11626 states and 17010 transitions. cyclomatic complexity: 5392 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:22,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:22,329 INFO L93 Difference]: Finished difference Result 22895 states and 33292 transitions. [2022-07-14 16:03:22,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:22,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22895 states and 33292 transitions. [2022-07-14 16:03:22,536 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22661 [2022-07-14 16:03:22,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22895 states to 22895 states and 33292 transitions. [2022-07-14 16:03:22,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22895 [2022-07-14 16:03:22,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22895 [2022-07-14 16:03:22,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22895 states and 33292 transitions. [2022-07-14 16:03:22,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:22,675 INFO L369 hiAutomatonCegarLoop]: Abstraction has 22895 states and 33292 transitions. [2022-07-14 16:03:22,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22895 states and 33292 transitions. [2022-07-14 16:03:22,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22895 to 22175. [2022-07-14 16:03:23,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22175 states, 22175 states have (on average 1.4555129650507328) internal successors, (32276), 22174 states have internal predecessors, (32276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:23,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22175 states to 22175 states and 32276 transitions. [2022-07-14 16:03:23,070 INFO L392 hiAutomatonCegarLoop]: Abstraction has 22175 states and 32276 transitions. [2022-07-14 16:03:23,070 INFO L374 stractBuchiCegarLoop]: Abstraction has 22175 states and 32276 transitions. [2022-07-14 16:03:23,070 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:03:23,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22175 states and 32276 transitions. [2022-07-14 16:03:23,139 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21941 [2022-07-14 16:03:23,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:23,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:23,141 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:23,141 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:23,141 INFO L752 eck$LassoCheckResult]: Stem: 114253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 114254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 115122#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115123#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113758#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 113759#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113661#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113662#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115019#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114295#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 114296#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 114190#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 114191#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 114726#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 114727#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 113948#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 113949#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 114391#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114392#L1194 assume !(0 == ~M_E~0); 114541#L1194-2 assume !(0 == ~T1_E~0); 114542#L1199-1 assume !(0 == ~T2_E~0); 114873#L1204-1 assume !(0 == ~T3_E~0); 114783#L1209-1 assume !(0 == ~T4_E~0); 114784#L1214-1 assume !(0 == ~T5_E~0); 115282#L1219-1 assume !(0 == ~T6_E~0); 115412#L1224-1 assume !(0 == ~T7_E~0); 114023#L1229-1 assume !(0 == ~T8_E~0); 113586#L1234-1 assume !(0 == ~T9_E~0); 113587#L1239-1 assume !(0 == ~T10_E~0); 113624#L1244-1 assume !(0 == ~T11_E~0); 113625#L1249-1 assume !(0 == ~T12_E~0); 114330#L1254-1 assume !(0 == ~E_M~0); 113526#L1259-1 assume !(0 == ~E_1~0); 113489#L1264-1 assume !(0 == ~E_2~0); 113490#L1269-1 assume !(0 == ~E_3~0); 115427#L1274-1 assume !(0 == ~E_4~0); 115324#L1279-1 assume !(0 == ~E_5~0); 113699#L1284-1 assume !(0 == ~E_6~0); 113700#L1289-1 assume !(0 == ~E_7~0); 114397#L1294-1 assume !(0 == ~E_8~0); 114398#L1299-1 assume !(0 == ~E_9~0); 114410#L1304-1 assume !(0 == ~E_10~0); 115401#L1309-1 assume !(0 == ~E_11~0); 115407#L1314-1 assume !(0 == ~E_12~0); 113654#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113576#L586 assume !(1 == ~m_pc~0); 113577#L586-2 is_master_triggered_~__retres1~0#1 := 0; 113646#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114753#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 113856#L1485 assume !(0 != activate_threads_~tmp~1#1); 113857#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115023#L605 assume !(1 == ~t1_pc~0); 114480#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114215#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114216#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115235#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114838#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114131#L624 assume 1 == ~t2_pc~0; 113629#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 113630#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114303#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115268#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 115068#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114920#L643 assume !(1 == ~t3_pc~0); 114746#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 114427#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114329#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113958#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 113959#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113718#L662 assume 1 == ~t4_pc~0; 113719#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113680#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113681#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114454#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 113565#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113566#L681 assume !(1 == ~t5_pc~0); 113437#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 113438#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114506#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115225#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 113971#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113972#L700 assume 1 == ~t6_pc~0; 114701#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 113709#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113710#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113760#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 113761#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115126#L719 assume 1 == ~t7_pc~0; 115248#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 113929#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114737#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114738#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 113451#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 113452#L738 assume !(1 == ~t8_pc~0); 114881#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 114775#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 113821#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113822#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114538#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114944#L757 assume 1 == ~t9_pc~0; 114945#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 113446#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 113447#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 114681#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 114498#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 114499#L776 assume !(1 == ~t10_pc~0); 113471#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 113470#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 113863#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 113701#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 113702#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 113655#L795 assume 1 == ~t11_pc~0; 113656#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 113992#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115008#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 115009#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 114742#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 114729#L814 assume !(1 == ~t12_pc~0); 114568#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 114569#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 114988#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 115118#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 113913#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113914#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 115080#L1332-2 assume !(1 == ~T1_E~0); 115348#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114646#L1342-1 assume !(1 == ~T3_E~0); 114647#L1347-1 assume !(1 == ~T4_E~0); 115112#L1352-1 assume !(1 == ~T5_E~0); 114951#L1357-1 assume !(1 == ~T6_E~0); 114188#L1362-1 assume !(1 == ~T7_E~0); 114189#L1367-1 assume !(1 == ~T8_E~0); 113796#L1372-1 assume !(1 == ~T9_E~0); 113797#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 116418#L1382-1 assume !(1 == ~T11_E~0); 114834#L1387-1 assume !(1 == ~T12_E~0); 114835#L1392-1 assume !(1 == ~E_M~0); 115948#L1397-1 assume !(1 == ~E_1~0); 115946#L1402-1 assume !(1 == ~E_2~0); 115944#L1407-1 assume !(1 == ~E_3~0); 115942#L1412-1 assume !(1 == ~E_4~0); 115940#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 115937#L1422-1 assume !(1 == ~E_6~0); 115935#L1427-1 assume !(1 == ~E_7~0); 115933#L1432-1 assume !(1 == ~E_8~0); 115694#L1437-1 assume !(1 == ~E_9~0); 115657#L1442-1 assume !(1 == ~E_10~0); 115655#L1447-1 assume !(1 == ~E_11~0); 115639#L1452-1 assume !(1 == ~E_12~0); 115626#L1457-1 assume { :end_inline_reset_delta_events } true; 115618#L1803-2 [2022-07-14 16:03:23,142 INFO L754 eck$LassoCheckResult]: Loop: 115618#L1803-2 assume !false; 115612#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115607#L1169 assume !false; 115606#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 115603#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 115592#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 115591#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 115589#L996 assume !(0 != eval_~tmp~0#1); 115588#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 115587#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 115584#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 115585#L1194-5 assume !(0 == ~T1_E~0); 117947#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117945#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117942#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117940#L1214-3 assume !(0 == ~T5_E~0); 117938#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117936#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117934#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117932#L1234-3 assume !(0 == ~T9_E~0); 117929#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117927#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117925#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117923#L1254-3 assume !(0 == ~E_M~0); 117921#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117919#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117916#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117914#L1274-3 assume !(0 == ~E_4~0); 117912#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117624#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117623#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117622#L1294-3 assume !(0 == ~E_8~0); 117621#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117620#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 117619#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117618#L1314-3 assume !(0 == ~E_12~0); 117617#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117616#L586-42 assume !(1 == ~m_pc~0); 117615#L586-44 is_master_triggered_~__retres1~0#1 := 0; 117614#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117613#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 117612#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 117611#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117609#L605-42 assume !(1 == ~t1_pc~0); 117607#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 117604#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117602#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117600#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117598#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117596#L624-42 assume 1 == ~t2_pc~0; 117593#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 117590#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117588#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117586#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117584#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117582#L643-42 assume 1 == ~t3_pc~0; 117495#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 117493#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117491#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117489#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117487#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117485#L662-42 assume 1 == ~t4_pc~0; 117483#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 117405#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117397#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117387#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117379#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117370#L681-42 assume 1 == ~t5_pc~0; 117361#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 117352#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117345#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117336#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 117329#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117321#L700-42 assume !(1 == ~t6_pc~0); 117313#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 117305#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117298#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117289#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117282#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117275#L719-42 assume !(1 == ~t7_pc~0); 117269#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 117261#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117255#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117247#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 117241#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117234#L738-42 assume 1 == ~t8_pc~0; 117227#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117221#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117216#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117210#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 117205#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117199#L757-42 assume 1 == ~t9_pc~0; 117193#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 117187#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117182#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117175#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 116767#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116764#L776-42 assume 1 == ~t10_pc~0; 116761#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 116759#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116756#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 116754#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 116752#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116750#L795-42 assume !(1 == ~t11_pc~0); 116747#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 116745#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116742#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116740#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116738#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116736#L814-42 assume !(1 == ~t12_pc~0); 116731#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 116728#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 116726#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 116724#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 116722#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116719#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 116601#L1332-5 assume !(1 == ~T1_E~0); 116714#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116712#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116710#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116708#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116707#L1357-3 assume !(1 == ~T6_E~0); 116704#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116702#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116700#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116696#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 116694#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 116557#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 116527#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116519#L1397-3 assume !(1 == ~E_1~0); 116511#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116502#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116494#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116484#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116475#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116470#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 116465#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 116459#L1437-3 assume !(1 == ~E_9~0); 116454#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 116449#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 116442#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 116438#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 115927#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 115914#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 115911#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 115909#L1822 assume !(0 == start_simulation_~tmp~3#1); 115907#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 115687#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 115678#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 115676#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 115672#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 115653#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 115636#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 115625#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 115618#L1803-2 [2022-07-14 16:03:23,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:23,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2022-07-14 16:03:23,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:23,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51728409] [2022-07-14 16:03:23,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:23,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:23,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:23,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:23,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:23,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51728409] [2022-07-14 16:03:23,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51728409] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:23,267 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:23,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:23,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685101542] [2022-07-14 16:03:23,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:23,268 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:23,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:23,269 INFO L85 PathProgramCache]: Analyzing trace with hash -452069957, now seen corresponding path program 1 times [2022-07-14 16:03:23,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:23,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138780941] [2022-07-14 16:03:23,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:23,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:23,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:23,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:23,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:23,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138780941] [2022-07-14 16:03:23,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138780941] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:23,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:23,306 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:23,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710961536] [2022-07-14 16:03:23,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:23,307 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:23,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:23,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:23,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:23,308 INFO L87 Difference]: Start difference. First operand 22175 states and 32276 transitions. cyclomatic complexity: 10117 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:23,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:23,830 INFO L93 Difference]: Finished difference Result 63271 states and 91896 transitions. [2022-07-14 16:03:23,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:23,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63271 states and 91896 transitions. [2022-07-14 16:03:24,359 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62680 [2022-07-14 16:03:24,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63271 states to 63271 states and 91896 transitions. [2022-07-14 16:03:24,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63271 [2022-07-14 16:03:24,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63271 [2022-07-14 16:03:24,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63271 states and 91896 transitions. [2022-07-14 16:03:24,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:24,737 INFO L369 hiAutomatonCegarLoop]: Abstraction has 63271 states and 91896 transitions. [2022-07-14 16:03:24,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63271 states and 91896 transitions. [2022-07-14 16:03:25,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63271 to 22784. [2022-07-14 16:03:25,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22784 states, 22784 states have (on average 1.4433374297752808) internal successors, (32885), 22783 states have internal predecessors, (32885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:25,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22784 states to 22784 states and 32885 transitions. [2022-07-14 16:03:25,286 INFO L392 hiAutomatonCegarLoop]: Abstraction has 22784 states and 32885 transitions. [2022-07-14 16:03:25,286 INFO L374 stractBuchiCegarLoop]: Abstraction has 22784 states and 32885 transitions. [2022-07-14 16:03:25,286 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 16:03:25,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22784 states and 32885 transitions. [2022-07-14 16:03:25,355 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22547 [2022-07-14 16:03:25,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:25,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:25,357 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:25,357 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:25,358 INFO L752 eck$LassoCheckResult]: Stem: 199714#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 199715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 200615#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200616#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 199222#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 199223#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199121#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199122#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 200490#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 199759#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 199760#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 199659#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 199660#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 200188#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 200189#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 199411#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 199412#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 199852#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 199853#L1194 assume !(0 == ~M_E~0); 200008#L1194-2 assume !(0 == ~T1_E~0); 200009#L1199-1 assume !(0 == ~T2_E~0); 200338#L1204-1 assume !(0 == ~T3_E~0); 200249#L1209-1 assume !(0 == ~T4_E~0); 200250#L1214-1 assume !(0 == ~T5_E~0); 200769#L1219-1 assume !(0 == ~T6_E~0); 200909#L1224-1 assume !(0 == ~T7_E~0); 199488#L1229-1 assume !(0 == ~T8_E~0); 199037#L1234-1 assume !(0 == ~T9_E~0); 199038#L1239-1 assume !(0 == ~T10_E~0); 199080#L1244-1 assume !(0 == ~T11_E~0); 199081#L1249-1 assume !(0 == ~T12_E~0); 199795#L1254-1 assume !(0 == ~E_M~0); 198984#L1259-1 assume !(0 == ~E_1~0); 198948#L1264-1 assume !(0 == ~E_2~0); 198949#L1269-1 assume !(0 == ~E_3~0); 200922#L1274-1 assume !(0 == ~E_4~0); 200813#L1279-1 assume !(0 == ~E_5~0); 199159#L1284-1 assume !(0 == ~E_6~0); 199160#L1289-1 assume !(0 == ~E_7~0); 199859#L1294-1 assume !(0 == ~E_8~0); 199860#L1299-1 assume !(0 == ~E_9~0); 199870#L1304-1 assume !(0 == ~E_10~0); 200898#L1309-1 assume !(0 == ~E_11~0); 200907#L1314-1 assume !(0 == ~E_12~0); 199113#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199035#L586 assume !(1 == ~m_pc~0); 199036#L586-2 is_master_triggered_~__retres1~0#1 := 0; 199106#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200218#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 199319#L1485 assume !(0 != activate_threads_~tmp~1#1); 199320#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200495#L605 assume !(1 == ~t1_pc~0); 199945#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 199685#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199686#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 200762#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 200303#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199600#L624 assume 1 == ~t2_pc~0; 199086#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199087#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199768#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 200752#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 200555#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200385#L643 assume !(1 == ~t3_pc~0); 200211#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 199884#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199794#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 199421#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 199422#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 199179#L662 assume 1 == ~t4_pc~0; 199180#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 199138#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 199139#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 199917#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 199022#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199023#L681 assume !(1 == ~t5_pc~0); 198896#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 198897#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199972#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 200704#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 199434#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 199435#L700 assume 1 == ~t6_pc~0; 200167#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 199169#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199170#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 199224#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 199225#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 200619#L719 assume 1 == ~t7_pc~0; 200725#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 199391#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 200200#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200201#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 198910#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 198911#L738 assume !(1 == ~t8_pc~0); 200345#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 200241#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 199284#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 199285#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 200005#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200412#L757 assume 1 == ~t9_pc~0; 200413#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 198905#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 198906#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 200146#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 199964#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 199965#L776 assume !(1 == ~t10_pc~0); 198930#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 198929#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 199323#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 199161#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 199162#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 199114#L795 assume 1 == ~t11_pc~0; 199115#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 199455#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200481#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200482#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 200208#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 200191#L814 assume !(1 == ~t12_pc~0); 200037#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 200038#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 200461#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 200612#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 199376#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199377#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 200571#L1332-2 assume !(1 == ~T1_E~0); 200840#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200110#L1342-1 assume !(1 == ~T3_E~0); 200111#L1347-1 assume !(1 == ~T4_E~0); 200597#L1352-1 assume !(1 == ~T5_E~0); 200419#L1357-1 assume !(1 == ~T6_E~0); 199655#L1362-1 assume !(1 == ~T7_E~0); 199656#L1367-1 assume !(1 == ~T8_E~0); 199259#L1372-1 assume !(1 == ~T9_E~0); 199260#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 199574#L1382-1 assume !(1 == ~T11_E~0); 199575#L1387-1 assume !(1 == ~T12_E~0); 200301#L1392-1 assume !(1 == ~E_M~0); 199601#L1397-1 assume !(1 == ~E_1~0); 199602#L1402-1 assume !(1 == ~E_2~0); 199270#L1407-1 assume !(1 == ~E_3~0); 199271#L1412-1 assume !(1 == ~E_4~0); 200524#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 200525#L1422-1 assume !(1 == ~E_6~0); 200841#L1427-1 assume !(1 == ~E_7~0); 199456#L1432-1 assume !(1 == ~E_8~0); 199457#L1437-1 assume !(1 == ~E_9~0); 200451#L1442-1 assume !(1 == ~E_10~0); 200452#L1447-1 assume !(1 == ~E_11~0); 200290#L1452-1 assume !(1 == ~E_12~0); 199054#L1457-1 assume { :end_inline_reset_delta_events } true; 199055#L1803-2 [2022-07-14 16:03:25,359 INFO L754 eck$LassoCheckResult]: Loop: 199055#L1803-2 assume !false; 201617#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200984#L1169 assume !false; 201496#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 201214#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 201125#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 201117#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 201098#L996 assume !(0 != eval_~tmp~0#1); 200042#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 200043#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 200010#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 200011#L1194-5 assume !(0 == ~T1_E~0); 199231#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 199232#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 221414#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 221412#L1214-3 assume !(0 == ~T5_E~0); 221410#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 221408#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 221406#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 221404#L1234-3 assume !(0 == ~T9_E~0); 221401#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 221399#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 221397#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 221395#L1254-3 assume !(0 == ~E_M~0); 221393#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221391#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 221388#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 221386#L1274-3 assume !(0 == ~E_4~0); 221384#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 221382#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 221378#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 221375#L1294-3 assume !(0 == ~E_8~0); 221372#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 221370#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 221368#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 221367#L1314-3 assume !(0 == ~E_12~0); 221366#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221365#L586-42 assume !(1 == ~m_pc~0); 221364#L586-44 is_master_triggered_~__retres1~0#1 := 0; 221363#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200774#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 200775#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 199706#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199707#L605-42 assume !(1 == ~t1_pc~0); 200432#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 200926#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221309#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 199708#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 199709#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199720#L624-42 assume 1 == ~t2_pc~0; 199722#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199869#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199008#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 199009#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 199533#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199534#L643-42 assume !(1 == ~t3_pc~0); 199889#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 199888#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220260#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220257#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 220255#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220253#L662-42 assume 1 == ~t4_pc~0; 220251#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 220248#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220246#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220243#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220241#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220239#L681-42 assume !(1 == ~t5_pc~0); 220237#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 220234#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220232#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220229#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 220227#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220202#L700-42 assume !(1 == ~t6_pc~0); 220199#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 220197#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220196#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220193#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 220191#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220189#L719-42 assume !(1 == ~t7_pc~0); 220187#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 220184#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 220182#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 220179#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 220177#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220175#L738-42 assume !(1 == ~t8_pc~0); 220170#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 220167#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220161#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 220153#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 220146#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220140#L757-42 assume !(1 == ~t9_pc~0); 220133#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 220125#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 220050#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 220048#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 220029#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 220028#L776-42 assume !(1 == ~t10_pc~0); 220017#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 220006#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 219998#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 219994#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 219990#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 219927#L795-42 assume 1 == ~t11_pc~0; 219883#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 219875#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 219872#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 219870#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 219868#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 219866#L814-42 assume !(1 == ~t12_pc~0); 219862#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 219858#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 219856#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 219854#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 219852#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219850#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 199111#L1332-5 assume !(1 == ~T1_E~0); 219846#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 219844#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 219842#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 219840#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 219838#L1357-3 assume !(1 == ~T6_E~0); 219836#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 219833#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 219831#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 217856#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 219821#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 219819#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 219817#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 219815#L1397-3 assume !(1 == ~E_1~0); 219813#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 219811#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 219808#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 199200#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 219805#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 219803#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 219801#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 219799#L1437-3 assume !(1 == ~E_9~0); 219796#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 219795#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 219794#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 216071#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 219756#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 219743#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 219741#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 219739#L1822 assume !(0 == start_simulation_~tmp~3#1); 200416#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 201656#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 201644#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 201640#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 201635#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 201631#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 201627#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 201623#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 199055#L1803-2 [2022-07-14 16:03:25,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:25,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2022-07-14 16:03:25,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:25,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089200264] [2022-07-14 16:03:25,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:25,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:25,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:25,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:25,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:25,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089200264] [2022-07-14 16:03:25,398 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089200264] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:25,398 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:25,398 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:25,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [718632962] [2022-07-14 16:03:25,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:25,400 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:25,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:25,401 INFO L85 PathProgramCache]: Analyzing trace with hash -2134071231, now seen corresponding path program 1 times [2022-07-14 16:03:25,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:25,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63868713] [2022-07-14 16:03:25,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:25,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:25,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:25,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:25,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:25,438 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63868713] [2022-07-14 16:03:25,438 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63868713] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:25,438 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:25,438 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:25,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594963290] [2022-07-14 16:03:25,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:25,440 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:25,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:25,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:25,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:25,441 INFO L87 Difference]: Start difference. First operand 22784 states and 32885 transitions. cyclomatic complexity: 10117 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:25,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:25,968 INFO L93 Difference]: Finished difference Result 55544 states and 79620 transitions. [2022-07-14 16:03:25,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:25,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55544 states and 79620 transitions. [2022-07-14 16:03:26,252 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54500 [2022-07-14 16:03:26,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55544 states to 55544 states and 79620 transitions. [2022-07-14 16:03:26,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55544 [2022-07-14 16:03:26,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55544 [2022-07-14 16:03:26,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55544 states and 79620 transitions. [2022-07-14 16:03:26,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:26,748 INFO L369 hiAutomatonCegarLoop]: Abstraction has 55544 states and 79620 transitions. [2022-07-14 16:03:26,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55544 states and 79620 transitions. [2022-07-14 16:03:27,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55544 to 43576. [2022-07-14 16:03:27,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43576 states, 43576 states have (on average 1.437465577382045) internal successors, (62639), 43575 states have internal predecessors, (62639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:27,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43576 states to 43576 states and 62639 transitions. [2022-07-14 16:03:27,592 INFO L392 hiAutomatonCegarLoop]: Abstraction has 43576 states and 62639 transitions. [2022-07-14 16:03:27,592 INFO L374 stractBuchiCegarLoop]: Abstraction has 43576 states and 62639 transitions. [2022-07-14 16:03:27,592 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 16:03:27,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43576 states and 62639 transitions. [2022-07-14 16:03:27,681 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43332 [2022-07-14 16:03:27,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:27,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:27,684 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:27,685 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:27,685 INFO L752 eck$LassoCheckResult]: Stem: 278051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 278052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 278941#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 278942#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 277552#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 277553#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 277455#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 277456#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 278830#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 278094#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 278095#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 277992#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 277993#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 278535#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 278536#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 277743#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 277744#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 278196#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 278197#L1194 assume !(0 == ~M_E~0); 278347#L1194-2 assume !(0 == ~T1_E~0); 278348#L1199-1 assume !(0 == ~T2_E~0); 278686#L1204-1 assume !(0 == ~T3_E~0); 278596#L1209-1 assume !(0 == ~T4_E~0); 278597#L1214-1 assume !(0 == ~T5_E~0); 279091#L1219-1 assume !(0 == ~T6_E~0); 279255#L1224-1 assume !(0 == ~T7_E~0); 277820#L1229-1 assume !(0 == ~T8_E~0); 277383#L1234-1 assume !(0 == ~T9_E~0); 277384#L1239-1 assume !(0 == ~T10_E~0); 277419#L1244-1 assume !(0 == ~T11_E~0); 277420#L1249-1 assume !(0 == ~T12_E~0); 278132#L1254-1 assume !(0 == ~E_M~0); 277321#L1259-1 assume !(0 == ~E_1~0); 277286#L1264-1 assume !(0 == ~E_2~0); 277287#L1269-1 assume !(0 == ~E_3~0); 279269#L1274-1 assume !(0 == ~E_4~0); 279138#L1279-1 assume !(0 == ~E_5~0); 277492#L1284-1 assume !(0 == ~E_6~0); 277493#L1289-1 assume !(0 == ~E_7~0); 278201#L1294-1 assume !(0 == ~E_8~0); 278202#L1299-1 assume !(0 == ~E_9~0); 278215#L1304-1 assume !(0 == ~E_10~0); 279237#L1309-1 assume !(0 == ~E_11~0); 279253#L1314-1 assume !(0 == ~E_12~0); 277447#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 277373#L586 assume !(1 == ~m_pc~0); 277374#L586-2 is_master_triggered_~__retres1~0#1 := 0; 277440#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278566#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 277650#L1485 assume !(0 != activate_threads_~tmp~1#1); 277651#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278833#L605 assume !(1 == ~t1_pc~0); 278285#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 278018#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278019#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 279044#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 278653#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 277930#L624 assume !(1 == ~t2_pc~0); 277931#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 278102#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278103#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 279078#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 278882#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278734#L643 assume !(1 == ~t3_pc~0); 278557#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 278232#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278129#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 277753#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 277754#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 277513#L662 assume 1 == ~t4_pc~0; 277514#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 277473#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277474#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 278258#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 277362#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 277363#L681 assume !(1 == ~t5_pc~0); 277234#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 277235#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278312#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279032#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 277766#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 277767#L700 assume 1 == ~t6_pc~0; 278512#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 277503#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 277504#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 277554#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 277555#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278945#L719 assume 1 == ~t7_pc~0; 279051#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 277720#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278547#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 278548#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 277248#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 277249#L738 assume !(1 == ~t8_pc~0); 278694#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 278589#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 277615#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 277616#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 278344#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 278758#L757 assume 1 == ~t9_pc~0; 278759#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 277243#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 277244#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 278491#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 278304#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 278305#L776 assume !(1 == ~t10_pc~0); 277268#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 277267#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277654#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 277494#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 277495#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 277448#L795 assume 1 == ~t11_pc~0; 277449#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 277785#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 278822#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 278823#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 278554#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 278538#L814 assume !(1 == ~t12_pc~0); 278373#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 278374#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 278805#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 278937#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 277706#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277707#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 278896#L1332-2 assume !(1 == ~T1_E~0); 279163#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278455#L1342-1 assume !(1 == ~T3_E~0); 278456#L1347-1 assume !(1 == ~T4_E~0); 278924#L1352-1 assume !(1 == ~T5_E~0); 278925#L1357-1 assume !(1 == ~T6_E~0); 277990#L1362-1 assume !(1 == ~T7_E~0); 277991#L1367-1 assume !(1 == ~T8_E~0); 277590#L1372-1 assume !(1 == ~T9_E~0); 277591#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 277903#L1382-1 assume !(1 == ~T11_E~0); 277904#L1387-1 assume !(1 == ~T12_E~0); 278650#L1392-1 assume !(1 == ~E_M~0); 277932#L1397-1 assume !(1 == ~E_1~0); 277933#L1402-1 assume !(1 == ~E_2~0); 291197#L1407-1 assume !(1 == ~E_3~0); 279233#L1412-1 assume !(1 == ~E_4~0); 279234#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 295517#L1422-1 assume !(1 == ~E_6~0); 295518#L1427-1 assume !(1 == ~E_7~0); 295499#L1432-1 assume !(1 == ~E_8~0); 295500#L1437-1 assume !(1 == ~E_9~0); 295493#L1442-1 assume !(1 == ~E_10~0); 295494#L1447-1 assume !(1 == ~E_11~0); 295488#L1452-1 assume !(1 == ~E_12~0); 277392#L1457-1 assume { :end_inline_reset_delta_events } true; 277393#L1803-2 [2022-07-14 16:03:27,685 INFO L754 eck$LassoCheckResult]: Loop: 277393#L1803-2 assume !false; 277727#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 277265#L1169 assume !false; 277860#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 277970#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 277457#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 277458#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 278264#L996 assume !(0 != eval_~tmp~0#1); 278905#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 301552#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 301551#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 301550#L1194-5 assume !(0 == ~T1_E~0); 301549#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 301548#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 301547#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 301546#L1214-3 assume !(0 == ~T5_E~0); 301545#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 301544#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 301543#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 301542#L1234-3 assume !(0 == ~T9_E~0); 301541#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 301540#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 301539#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 301538#L1254-3 assume !(0 == ~E_M~0); 301537#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 301536#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 301535#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 301534#L1274-3 assume !(0 == ~E_4~0); 301533#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 301532#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 301531#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 301530#L1294-3 assume !(0 == ~E_8~0); 301529#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 301528#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 301526#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 301524#L1314-3 assume !(0 == ~E_12~0); 301522#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 301520#L586-42 assume !(1 == ~m_pc~0); 301518#L586-44 is_master_triggered_~__retres1~0#1 := 0; 301516#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 301515#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 301514#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 301513#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 301512#L605-42 assume 1 == ~t1_pc~0; 301511#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 301510#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 301509#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 301508#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 278044#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278049#L624-42 assume !(1 == ~t2_pc~0); 278050#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 301495#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 301493#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 301491#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 301489#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 301487#L643-42 assume 1 == ~t3_pc~0; 301484#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 301482#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 301480#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 301478#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 301476#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 301474#L662-42 assume 1 == ~t4_pc~0; 301472#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 301469#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 301467#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 301465#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 301463#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 301461#L681-42 assume 1 == ~t5_pc~0; 301262#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 278534#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 277747#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 277748#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 278865#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 277890#L700-42 assume 1 == ~t6_pc~0; 277891#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 277693#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278766#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 278874#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 278875#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 279146#L719-42 assume 1 == ~t7_pc~0; 278532#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 277579#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 277629#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 277630#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 277971#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 277972#L738-42 assume 1 == ~t8_pc~0; 301126#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 301124#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 301123#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 301122#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 301121#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 301120#L757-42 assume 1 == ~t9_pc~0; 301118#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 301117#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 301116#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 301115#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 301114#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 278835#L776-42 assume !(1 == ~t10_pc~0); 278774#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 278775#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278831#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 279225#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 279226#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 278586#L795-42 assume 1 == ~t11_pc~0; 278588#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 277573#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 277574#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 300402#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 300400#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 300398#L814-42 assume 1 == ~t12_pc~0; 300394#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 300392#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 279219#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 277296#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 277297#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277444#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 277445#L1332-5 assume !(1 == ~T1_E~0); 277417#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 277418#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 278259#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 278442#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 278443#L1357-3 assume !(1 == ~T6_E~0); 278969#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 279246#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 279231#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 277277#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 277278#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 277883#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 277884#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 278802#L1397-3 assume !(1 == ~E_1~0); 279160#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 278386#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 277530#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 277531#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 278278#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 278279#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 278966#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 278679#L1437-3 assume !(1 == ~E_9~0); 278410#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 278411#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 277331#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 277332#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 277941#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 277783#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 278664#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 277521#L1822 assume !(0 == start_simulation_~tmp~3#1); 277522#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 278523#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 301337#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 301176#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 301175#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 301174#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 301155#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 279005#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 277393#L1803-2 [2022-07-14 16:03:27,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:27,686 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2022-07-14 16:03:27,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:27,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282825753] [2022-07-14 16:03:27,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:27,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:27,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:27,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:27,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:27,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1282825753] [2022-07-14 16:03:27,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1282825753] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:27,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:27,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:27,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305813431] [2022-07-14 16:03:27,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:27,721 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:27,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:27,721 INFO L85 PathProgramCache]: Analyzing trace with hash 723803320, now seen corresponding path program 1 times [2022-07-14 16:03:27,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:27,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744034282] [2022-07-14 16:03:27,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:27,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:27,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:27,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:27,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:27,756 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744034282] [2022-07-14 16:03:27,756 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744034282] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:27,756 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:27,756 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:27,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330400963] [2022-07-14 16:03:27,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:27,757 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:27,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:27,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:27,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:27,758 INFO L87 Difference]: Start difference. First operand 43576 states and 62639 transitions. cyclomatic complexity: 19079 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:28,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:28,256 INFO L93 Difference]: Finished difference Result 83495 states and 119552 transitions. [2022-07-14 16:03:28,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:28,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83495 states and 119552 transitions. [2022-07-14 16:03:28,759 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83172 [2022-07-14 16:03:28,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83495 states to 83495 states and 119552 transitions. [2022-07-14 16:03:28,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83495 [2022-07-14 16:03:29,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83495 [2022-07-14 16:03:29,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83495 states and 119552 transitions. [2022-07-14 16:03:29,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:29,093 INFO L369 hiAutomatonCegarLoop]: Abstraction has 83495 states and 119552 transitions. [2022-07-14 16:03:29,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83495 states and 119552 transitions. [2022-07-14 16:03:29,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83495 to 83431. [2022-07-14 16:03:29,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83431 states, 83431 states have (on average 1.4321774879840827) internal successors, (119488), 83430 states have internal predecessors, (119488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:30,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83431 states to 83431 states and 119488 transitions. [2022-07-14 16:03:30,445 INFO L392 hiAutomatonCegarLoop]: Abstraction has 83431 states and 119488 transitions. [2022-07-14 16:03:30,445 INFO L374 stractBuchiCegarLoop]: Abstraction has 83431 states and 119488 transitions. [2022-07-14 16:03:30,445 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 16:03:30,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83431 states and 119488 transitions. [2022-07-14 16:03:30,649 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83108 [2022-07-14 16:03:30,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:30,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:30,652 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:30,652 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:30,652 INFO L752 eck$LassoCheckResult]: Stem: 405121#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 405122#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 406040#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 406041#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 404628#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 404629#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 404532#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 404533#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 405933#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 405164#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 405165#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 405064#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 405065#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 405621#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 405622#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 404820#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 404821#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 405265#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 405266#L1194 assume !(0 == ~M_E~0); 405425#L1194-2 assume !(0 == ~T1_E~0); 405426#L1199-1 assume !(0 == ~T2_E~0); 405773#L1204-1 assume !(0 == ~T3_E~0); 405686#L1209-1 assume !(0 == ~T4_E~0); 405687#L1214-1 assume !(0 == ~T5_E~0); 406178#L1219-1 assume !(0 == ~T6_E~0); 406361#L1224-1 assume !(0 == ~T7_E~0); 404897#L1229-1 assume !(0 == ~T8_E~0); 404457#L1234-1 assume !(0 == ~T9_E~0); 404458#L1239-1 assume !(0 == ~T10_E~0); 404496#L1244-1 assume !(0 == ~T11_E~0); 404497#L1249-1 assume !(0 == ~T12_E~0); 405203#L1254-1 assume !(0 == ~E_M~0); 404399#L1259-1 assume !(0 == ~E_1~0); 404364#L1264-1 assume !(0 == ~E_2~0); 404365#L1269-1 assume !(0 == ~E_3~0); 406377#L1274-1 assume !(0 == ~E_4~0); 406229#L1279-1 assume !(0 == ~E_5~0); 404569#L1284-1 assume !(0 == ~E_6~0); 404570#L1289-1 assume !(0 == ~E_7~0); 405272#L1294-1 assume !(0 == ~E_8~0); 405273#L1299-1 assume !(0 == ~E_9~0); 405284#L1304-1 assume !(0 == ~E_10~0); 406348#L1309-1 assume !(0 == ~E_11~0); 406358#L1314-1 assume !(0 == ~E_12~0); 404524#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 404449#L586 assume !(1 == ~m_pc~0); 404450#L586-2 is_master_triggered_~__retres1~0#1 := 0; 404517#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405654#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 404727#L1485 assume !(0 != activate_threads_~tmp~1#1); 404728#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 405937#L605 assume !(1 == ~t1_pc~0); 405363#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 405091#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 405092#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 406134#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 405742#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405006#L624 assume !(1 == ~t2_pc~0); 405007#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 405174#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 405175#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 406167#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 405986#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 405819#L643 assume !(1 == ~t3_pc~0); 405647#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405300#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 405201#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 404830#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 404831#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404590#L662 assume !(1 == ~t4_pc~0); 404591#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 404550#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 404551#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 405334#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 404439#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 404440#L681 assume !(1 == ~t5_pc~0); 404312#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404313#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405390#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 406126#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 404843#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 404844#L700 assume 1 == ~t6_pc~0; 405595#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 404580#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 404581#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 404630#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 404631#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406044#L719 assume 1 == ~t7_pc~0; 406143#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 404797#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 405633#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 405634#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 404326#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 404327#L738 assume !(1 == ~t8_pc~0); 405779#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 405679#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 404692#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 404693#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 405422#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 405847#L757 assume 1 == ~t9_pc~0; 405848#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 404321#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 404322#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 405573#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 405382#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 405383#L776 assume !(1 == ~t10_pc~0); 404346#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 404345#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 404731#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 404571#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 404572#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 404525#L795 assume 1 == ~t11_pc~0; 404526#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 404862#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 405924#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 405925#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 405643#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 405624#L814 assume !(1 == ~t12_pc~0); 405453#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405454#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 405899#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 406036#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 404783#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404784#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 406000#L1332-2 assume !(1 == ~T1_E~0); 406269#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 405535#L1342-1 assume !(1 == ~T3_E~0); 405536#L1347-1 assume !(1 == ~T4_E~0); 406028#L1352-1 assume !(1 == ~T5_E~0); 405854#L1357-1 assume !(1 == ~T6_E~0); 405060#L1362-1 assume !(1 == ~T7_E~0); 405061#L1367-1 assume !(1 == ~T8_E~0); 404666#L1372-1 assume !(1 == ~T9_E~0); 404667#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 404979#L1382-1 assume !(1 == ~T11_E~0); 404980#L1387-1 assume !(1 == ~T12_E~0); 405739#L1392-1 assume !(1 == ~E_M~0); 405008#L1397-1 assume !(1 == ~E_1~0); 405009#L1402-1 assume !(1 == ~E_2~0); 404678#L1407-1 assume !(1 == ~E_3~0); 404679#L1412-1 assume !(1 == ~E_4~0); 405960#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 405961#L1422-1 assume !(1 == ~E_6~0); 406270#L1427-1 assume !(1 == ~E_7~0); 404863#L1432-1 assume !(1 == ~E_8~0); 404864#L1437-1 assume !(1 == ~E_9~0); 405889#L1442-1 assume !(1 == ~E_10~0); 405890#L1447-1 assume !(1 == ~E_11~0); 405726#L1452-1 assume !(1 == ~E_12~0); 404468#L1457-1 assume { :end_inline_reset_delta_events } true; 404469#L1803-2 [2022-07-14 16:03:30,653 INFO L754 eck$LassoCheckResult]: Loop: 404469#L1803-2 assume !false; 443041#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 443027#L1169 assume !false; 440507#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 427262#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 427250#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 427249#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 427247#L996 assume !(0 != eval_~tmp~0#1); 427248#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 449481#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 449480#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 449479#L1194-5 assume !(0 == ~T1_E~0); 449478#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 449477#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 449476#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 449475#L1214-3 assume !(0 == ~T5_E~0); 449474#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 449473#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 449472#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 449471#L1234-3 assume !(0 == ~T9_E~0); 449470#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 449469#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 449468#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 449467#L1254-3 assume !(0 == ~E_M~0); 449466#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 449465#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 449464#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 449463#L1274-3 assume !(0 == ~E_4~0); 449462#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 449461#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 449460#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 449459#L1294-3 assume !(0 == ~E_8~0); 449458#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 449457#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 449456#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 449455#L1314-3 assume !(0 == ~E_12~0); 449454#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 449453#L586-42 assume !(1 == ~m_pc~0); 449452#L586-44 is_master_triggered_~__retres1~0#1 := 0; 449451#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 449450#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 449449#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 449448#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 449447#L605-42 assume !(1 == ~t1_pc~0); 449446#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 449444#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 449442#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 449440#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 449438#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 449437#L624-42 assume !(1 == ~t2_pc~0); 438489#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 449436#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 449435#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 449434#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 449433#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 449432#L643-42 assume 1 == ~t3_pc~0; 449430#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 449429#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 449428#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 449427#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 449426#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 449425#L662-42 assume !(1 == ~t4_pc~0); 449424#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 449423#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 449422#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 449421#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 449420#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 449419#L681-42 assume !(1 == ~t5_pc~0); 449418#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 449416#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 449415#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 449414#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 449413#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 449412#L700-42 assume !(1 == ~t6_pc~0); 449410#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 449409#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 449408#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 449407#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 449406#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 449405#L719-42 assume !(1 == ~t7_pc~0); 449404#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 449402#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 449401#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 449400#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 449399#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 449398#L738-42 assume 1 == ~t8_pc~0; 449396#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 449395#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 449394#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 449393#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 449392#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 449391#L757-42 assume !(1 == ~t9_pc~0); 449390#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 449388#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 449387#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 449386#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 449385#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 449384#L776-42 assume 1 == ~t10_pc~0; 449382#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 449381#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 449380#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 449379#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 449378#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 449377#L795-42 assume 1 == ~t11_pc~0; 449376#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 449374#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 449373#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 449372#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 449371#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 449370#L814-42 assume 1 == ~t12_pc~0; 449368#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 449367#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 449366#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 404374#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 404375#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404521#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 404522#L1332-5 assume !(1 == ~T1_E~0); 404494#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 404495#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 405335#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 405520#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 405521#L1357-3 assume !(1 == ~T6_E~0); 406069#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 406355#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 406342#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 404355#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 404356#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 404962#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 404963#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 405897#L1397-3 assume !(1 == ~E_1~0); 406263#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 405464#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 404606#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 404607#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 405355#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 405356#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 406068#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 405765#L1437-3 assume !(1 == ~E_9~0); 405489#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 405490#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 404409#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 404410#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 405018#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 404860#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 405750#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 404597#L1822 assume !(0 == start_simulation_~tmp~3#1); 404598#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 443111#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 443102#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 443100#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 443098#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 443094#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 443092#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 443061#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 404469#L1803-2 [2022-07-14 16:03:30,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:30,654 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2022-07-14 16:03:30,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:30,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093688450] [2022-07-14 16:03:30,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:30,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:30,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:30,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:30,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:30,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093688450] [2022-07-14 16:03:30,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093688450] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:30,700 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:30,700 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:30,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955507918] [2022-07-14 16:03:30,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:30,701 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:30,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:30,701 INFO L85 PathProgramCache]: Analyzing trace with hash 876721791, now seen corresponding path program 1 times [2022-07-14 16:03:30,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:30,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347610195] [2022-07-14 16:03:30,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:30,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:30,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:30,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:30,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:30,736 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347610195] [2022-07-14 16:03:30,736 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347610195] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:30,736 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:30,737 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:30,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570798063] [2022-07-14 16:03:30,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:30,737 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:30,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:30,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:30,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:30,739 INFO L87 Difference]: Start difference. First operand 83431 states and 119488 transitions. cyclomatic complexity: 36089 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:32,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:32,013 INFO L93 Difference]: Finished difference Result 202350 states and 288049 transitions. [2022-07-14 16:03:32,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:32,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202350 states and 288049 transitions. [2022-07-14 16:03:33,037 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 198732 [2022-07-14 16:03:33,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202350 states to 202350 states and 288049 transitions. [2022-07-14 16:03:33,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202350 [2022-07-14 16:03:33,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202350 [2022-07-14 16:03:33,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202350 states and 288049 transitions. [2022-07-14 16:03:33,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:33,802 INFO L369 hiAutomatonCegarLoop]: Abstraction has 202350 states and 288049 transitions. [2022-07-14 16:03:33,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202350 states and 288049 transitions. [2022-07-14 16:03:35,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202350 to 159714. [2022-07-14 16:03:35,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159714 states, 159714 states have (on average 1.4273075622675533) internal successors, (227961), 159713 states have internal predecessors, (227961), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:36,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159714 states to 159714 states and 227961 transitions. [2022-07-14 16:03:36,042 INFO L392 hiAutomatonCegarLoop]: Abstraction has 159714 states and 227961 transitions. [2022-07-14 16:03:36,042 INFO L374 stractBuchiCegarLoop]: Abstraction has 159714 states and 227961 transitions. [2022-07-14 16:03:36,042 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-14 16:03:36,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 159714 states and 227961 transitions. [2022-07-14 16:03:36,441 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 159296 [2022-07-14 16:03:36,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:36,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:36,444 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:36,444 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:36,445 INFO L752 eck$LassoCheckResult]: Stem: 690909#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 690910#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 691770#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 691771#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 690416#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 690417#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 690322#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 690323#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 691664#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 690943#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 690944#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 690850#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 690851#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 691378#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 691379#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 690604#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 690605#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 691041#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 691042#L1194 assume !(0 == ~M_E~0); 691197#L1194-2 assume !(0 == ~T1_E~0); 691198#L1199-1 assume !(0 == ~T2_E~0); 691522#L1204-1 assume !(0 == ~T3_E~0); 691434#L1209-1 assume !(0 == ~T4_E~0); 691435#L1214-1 assume !(0 == ~T5_E~0); 691905#L1219-1 assume !(0 == ~T6_E~0); 692027#L1224-1 assume !(0 == ~T7_E~0); 690683#L1229-1 assume !(0 == ~T8_E~0); 690251#L1234-1 assume !(0 == ~T9_E~0); 690252#L1239-1 assume !(0 == ~T10_E~0); 690289#L1244-1 assume !(0 == ~T11_E~0); 690290#L1249-1 assume !(0 == ~T12_E~0); 690982#L1254-1 assume !(0 == ~E_M~0); 690190#L1259-1 assume !(0 == ~E_1~0); 690155#L1264-1 assume !(0 == ~E_2~0); 690156#L1269-1 assume !(0 == ~E_3~0); 692047#L1274-1 assume !(0 == ~E_4~0); 691945#L1279-1 assume !(0 == ~E_5~0); 690359#L1284-1 assume !(0 == ~E_6~0); 690360#L1289-1 assume !(0 == ~E_7~0); 691049#L1294-1 assume !(0 == ~E_8~0); 691050#L1299-1 assume !(0 == ~E_9~0); 691062#L1304-1 assume !(0 == ~E_10~0); 692015#L1309-1 assume !(0 == ~E_11~0); 692025#L1314-1 assume !(0 == ~E_12~0); 690315#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 690241#L586 assume !(1 == ~m_pc~0); 690242#L586-2 is_master_triggered_~__retres1~0#1 := 0; 690308#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 691406#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690514#L1485 assume !(0 != activate_threads_~tmp~1#1); 690515#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 691670#L605 assume !(1 == ~t1_pc~0); 691134#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 690875#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 690876#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 691865#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 691491#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 690791#L624 assume !(1 == ~t2_pc~0); 690792#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 690952#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690953#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 691892#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 691721#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 691566#L643 assume !(1 == ~t3_pc~0); 691399#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691077#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 690979#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 690614#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 690615#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 690379#L662 assume !(1 == ~t4_pc~0); 690380#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 690340#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 690341#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 691107#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 690230#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 690231#L681 assume !(1 == ~t5_pc~0); 690103#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 690104#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 691162#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 691854#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 690627#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 690628#L700 assume !(1 == ~t6_pc~0); 690458#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 690369#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690370#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 690418#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 690419#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 691774#L719 assume 1 == ~t7_pc~0; 691872#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 690585#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691390#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 691391#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 690117#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 690118#L738 assume !(1 == ~t8_pc~0); 691528#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691427#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 690479#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 690480#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 691194#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 691590#L757 assume 1 == ~t9_pc~0; 691591#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 690112#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 690113#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 691337#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 691153#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 691154#L776 assume !(1 == ~t10_pc~0); 690137#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 690136#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 690520#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 690361#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 690362#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 690316#L795 assume 1 == ~t11_pc~0; 690317#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 690648#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 691656#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 691657#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 691395#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 691381#L814 assume !(1 == ~t12_pc~0); 691223#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 691224#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 691635#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 691767#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 690570#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 690571#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 691733#L1332-2 assume !(1 == ~T1_E~0); 691966#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 691304#L1342-1 assume !(1 == ~T3_E~0); 691305#L1347-1 assume !(1 == ~T4_E~0); 691759#L1352-1 assume !(1 == ~T5_E~0); 691596#L1357-1 assume !(1 == ~T6_E~0); 690848#L1362-1 assume !(1 == ~T7_E~0); 690849#L1367-1 assume !(1 == ~T8_E~0); 690454#L1372-1 assume !(1 == ~T9_E~0); 690455#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 690765#L1382-1 assume !(1 == ~T11_E~0); 690766#L1387-1 assume !(1 == ~T12_E~0); 691920#L1392-1 assume !(1 == ~E_M~0); 691921#L1397-1 assume !(1 == ~E_1~0); 691968#L1402-1 assume !(1 == ~E_2~0); 691969#L1407-1 assume !(1 == ~E_3~0); 692012#L1412-1 assume !(1 == ~E_4~0); 692013#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 824868#L1422-1 assume !(1 == ~E_6~0); 824866#L1427-1 assume !(1 == ~E_7~0); 824863#L1432-1 assume !(1 == ~E_8~0); 824861#L1437-1 assume !(1 == ~E_9~0); 824859#L1442-1 assume !(1 == ~E_10~0); 824857#L1447-1 assume !(1 == ~E_11~0); 824855#L1452-1 assume !(1 == ~E_12~0); 691476#L1457-1 assume { :end_inline_reset_delta_events } true; 824850#L1803-2 [2022-07-14 16:03:36,445 INFO L754 eck$LassoCheckResult]: Loop: 824850#L1803-2 assume !false; 824848#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 824842#L1169 assume !false; 824840#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 824831#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 824819#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 824817#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 824812#L996 assume !(0 != eval_~tmp~0#1); 824813#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 846112#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 846109#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 846107#L1194-5 assume !(0 == ~T1_E~0); 846105#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 846103#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 846101#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 846099#L1214-3 assume !(0 == ~T5_E~0); 846096#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 846094#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 846092#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 846090#L1234-3 assume !(0 == ~T9_E~0); 846088#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 846086#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 846085#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 846083#L1254-3 assume !(0 == ~E_M~0); 846081#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 846079#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 846077#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 846075#L1274-3 assume !(0 == ~E_4~0); 846073#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 846071#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 846069#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 846068#L1294-3 assume !(0 == ~E_8~0); 846066#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 846064#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 846062#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 846060#L1314-3 assume !(0 == ~E_12~0); 846058#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 846056#L586-42 assume !(1 == ~m_pc~0); 846054#L586-44 is_master_triggered_~__retres1~0#1 := 0; 846053#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 846051#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 846049#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 846047#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 846045#L605-42 assume !(1 == ~t1_pc~0); 846041#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 846039#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 846037#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 846036#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 846034#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 846033#L624-42 assume !(1 == ~t2_pc~0); 820460#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 846018#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 846017#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 846016#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 846015#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 846014#L643-42 assume 1 == ~t3_pc~0; 846012#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 846011#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 845039#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 845033#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 845031#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 845029#L662-42 assume !(1 == ~t4_pc~0); 845027#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 845025#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 845023#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 845021#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 845019#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 845017#L681-42 assume 1 == ~t5_pc~0; 845014#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 845012#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 845010#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 845008#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 845006#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 825095#L700-42 assume !(1 == ~t6_pc~0); 825092#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 825090#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 825088#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 825086#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 825084#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 825082#L719-42 assume 1 == ~t7_pc~0; 825078#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 825076#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 825074#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 825072#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 825070#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 825068#L738-42 assume 1 == ~t8_pc~0; 825064#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 825062#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 825060#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 825058#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 825056#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 825054#L757-42 assume 1 == ~t9_pc~0; 825050#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 825048#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 825046#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 825044#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 825042#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 825040#L776-42 assume 1 == ~t10_pc~0; 825036#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 825034#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 825032#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 825030#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 825028#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 825026#L795-42 assume !(1 == ~t11_pc~0); 825022#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 825020#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 825018#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 825016#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 825014#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 825013#L814-42 assume 1 == ~t12_pc~0; 825008#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 825006#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 825004#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 825003#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 825002#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 825000#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 778491#L1332-5 assume !(1 == ~T1_E~0); 824995#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 824993#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 824991#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 824989#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 824985#L1357-3 assume !(1 == ~T6_E~0); 824983#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 824981#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 824979#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 824044#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 824975#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 824973#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 824972#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 824970#L1397-3 assume !(1 == ~E_1~0); 824968#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 824966#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 824964#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 824960#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 824957#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 824955#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 824953#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 824951#L1437-3 assume !(1 == ~E_9~0); 824949#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 824947#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 824945#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 824941#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 824936#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 824923#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 824920#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 824918#L1822 assume !(0 == start_simulation_~tmp~3#1); 824915#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 824903#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 824894#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 824892#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 824889#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 824887#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 824885#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 824853#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 824850#L1803-2 [2022-07-14 16:03:36,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:36,446 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2022-07-14 16:03:36,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:36,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953895061] [2022-07-14 16:03:36,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:36,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:36,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:36,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:36,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:36,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953895061] [2022-07-14 16:03:36,480 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953895061] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:36,480 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:36,480 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:36,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778457370] [2022-07-14 16:03:36,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:36,481 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:36,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:36,482 INFO L85 PathProgramCache]: Analyzing trace with hash -456907395, now seen corresponding path program 1 times [2022-07-14 16:03:36,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:36,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837265600] [2022-07-14 16:03:36,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:36,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:36,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:36,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:36,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:36,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837265600] [2022-07-14 16:03:36,515 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837265600] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:36,515 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:36,515 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:36,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672361943] [2022-07-14 16:03:36,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:36,516 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:36,516 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:36,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:36,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:36,517 INFO L87 Difference]: Start difference. First operand 159714 states and 227961 transitions. cyclomatic complexity: 68279 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,325 INFO L93 Difference]: Finished difference Result 386469 states and 548410 transitions. [2022-07-14 16:03:38,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:38,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 386469 states and 548410 transitions. [2022-07-14 16:03:40,509 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 379492 [2022-07-14 16:03:41,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 386469 states to 386469 states and 548410 transitions. [2022-07-14 16:03:41,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 386469 [2022-07-14 16:03:41,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 386469 [2022-07-14 16:03:41,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 386469 states and 548410 transitions. [2022-07-14 16:03:41,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:41,713 INFO L369 hiAutomatonCegarLoop]: Abstraction has 386469 states and 548410 transitions. [2022-07-14 16:03:41,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386469 states and 548410 transitions. [2022-07-14 16:03:45,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386469 to 305489. [2022-07-14 16:03:45,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 305489 states, 305489 states have (on average 1.4227877272176739) internal successors, (434646), 305488 states have internal predecessors, (434646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305489 states to 305489 states and 434646 transitions. [2022-07-14 16:03:46,010 INFO L392 hiAutomatonCegarLoop]: Abstraction has 305489 states and 434646 transitions. [2022-07-14 16:03:46,010 INFO L374 stractBuchiCegarLoop]: Abstraction has 305489 states and 434646 transitions. [2022-07-14 16:03:46,010 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-14 16:03:46,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 305489 states and 434646 transitions. [2022-07-14 16:03:47,361 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 304880 [2022-07-14 16:03:47,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:47,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:47,364 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:47,365 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:47,365 INFO L752 eck$LassoCheckResult]: Stem: 1237116#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1237117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1238030#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1238031#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1236614#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 1236615#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1236518#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1236519#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1237921#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1237153#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1237154#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1237056#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1237057#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1237609#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1237610#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1236804#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1236805#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1237255#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1237256#L1194 assume !(0 == ~M_E~0); 1237412#L1194-2 assume !(0 == ~T1_E~0); 1237413#L1199-1 assume !(0 == ~T2_E~0); 1237758#L1204-1 assume !(0 == ~T3_E~0); 1237664#L1209-1 assume !(0 == ~T4_E~0); 1237665#L1214-1 assume !(0 == ~T5_E~0); 1238186#L1219-1 assume !(0 == ~T6_E~0); 1238347#L1224-1 assume !(0 == ~T7_E~0); 1236883#L1229-1 assume !(0 == ~T8_E~0); 1236444#L1234-1 assume !(0 == ~T9_E~0); 1236445#L1239-1 assume !(0 == ~T10_E~0); 1236484#L1244-1 assume !(0 == ~T11_E~0); 1236485#L1249-1 assume !(0 == ~T12_E~0); 1237194#L1254-1 assume !(0 == ~E_M~0); 1236383#L1259-1 assume !(0 == ~E_1~0); 1236348#L1264-1 assume !(0 == ~E_2~0); 1236349#L1269-1 assume !(0 == ~E_3~0); 1238375#L1274-1 assume !(0 == ~E_4~0); 1238236#L1279-1 assume !(0 == ~E_5~0); 1236555#L1284-1 assume !(0 == ~E_6~0); 1236556#L1289-1 assume !(0 == ~E_7~0); 1237263#L1294-1 assume !(0 == ~E_8~0); 1237264#L1299-1 assume !(0 == ~E_9~0); 1237275#L1304-1 assume !(0 == ~E_10~0); 1238333#L1309-1 assume !(0 == ~E_11~0); 1238341#L1314-1 assume !(0 == ~E_12~0); 1236511#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1236434#L586 assume !(1 == ~m_pc~0); 1236435#L586-2 is_master_triggered_~__retres1~0#1 := 0; 1236503#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1237636#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1236713#L1485 assume !(0 != activate_threads_~tmp~1#1); 1236714#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1237927#L605 assume !(1 == ~t1_pc~0); 1237348#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1237081#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1237082#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1238134#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 1237720#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1236996#L624 assume !(1 == ~t2_pc~0); 1236997#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1237163#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1237164#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1238169#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 1237978#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1237803#L643 assume !(1 == ~t3_pc~0); 1237629#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1237292#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1237191#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1236814#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 1236815#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1236576#L662 assume !(1 == ~t4_pc~0); 1236577#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1236536#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1236537#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1237320#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 1236423#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1236424#L681 assume !(1 == ~t5_pc~0); 1236296#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1236297#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1237375#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1238126#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 1236827#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1236828#L700 assume !(1 == ~t6_pc~0); 1236656#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1236566#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1236567#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1236616#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 1236617#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238034#L719 assume !(1 == ~t7_pc~0); 1236783#L719-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1236784#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1237619#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1237620#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 1236310#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1236311#L738 assume !(1 == ~t8_pc~0); 1237764#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1237657#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1236678#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1236679#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1237409#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1237832#L757 assume 1 == ~t9_pc~0; 1237833#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1236305#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1236306#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1237562#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 1237367#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1237368#L776 assume !(1 == ~t10_pc~0); 1236330#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1236329#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1236719#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1236557#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 1236558#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1236512#L795 assume 1 == ~t11_pc~0; 1236513#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1236849#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1237910#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1237911#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 1237625#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1237612#L814 assume !(1 == ~t12_pc~0); 1237439#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1237440#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1237888#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1238027#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 1236769#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1236770#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 1237992#L1332-2 assume !(1 == ~T1_E~0); 1238266#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1237529#L1342-1 assume !(1 == ~T3_E~0); 1237530#L1347-1 assume !(1 == ~T4_E~0); 1238021#L1352-1 assume !(1 == ~T5_E~0); 1238022#L1357-1 assume !(1 == ~T6_E~0); 1237054#L1362-1 assume !(1 == ~T7_E~0); 1237055#L1367-1 assume !(1 == ~T8_E~0); 1236652#L1372-1 assume !(1 == ~T9_E~0); 1236653#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1236968#L1382-1 assume !(1 == ~T11_E~0); 1236969#L1387-1 assume !(1 == ~T12_E~0); 1238204#L1392-1 assume !(1 == ~E_M~0); 1238205#L1397-1 assume !(1 == ~E_1~0); 1238268#L1402-1 assume !(1 == ~E_2~0); 1238269#L1407-1 assume !(1 == ~E_3~0); 1238330#L1412-1 assume !(1 == ~E_4~0); 1238331#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1353422#L1422-1 assume !(1 == ~E_6~0); 1238267#L1427-1 assume !(1 == ~E_7~0); 1236850#L1432-1 assume !(1 == ~E_8~0); 1236851#L1437-1 assume !(1 == ~E_9~0); 1237877#L1442-1 assume !(1 == ~E_10~0); 1237878#L1447-1 assume !(1 == ~E_11~0); 1237706#L1452-1 assume !(1 == ~E_12~0); 1236453#L1457-1 assume { :end_inline_reset_delta_events } true; 1236454#L1803-2 [2022-07-14 16:03:47,366 INFO L754 eck$LassoCheckResult]: Loop: 1236454#L1803-2 assume !false; 1367900#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1367894#L1169 assume !false; 1367873#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1367792#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1367779#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1367778#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1367776#L996 assume !(0 != eval_~tmp~0#1); 1367777#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1382451#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1382448#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1382445#L1194-5 assume !(0 == ~T1_E~0); 1382442#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1382430#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1382425#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1382418#L1214-3 assume !(0 == ~T5_E~0); 1382413#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1382408#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1382403#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1382397#L1234-3 assume !(0 == ~T9_E~0); 1382394#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1382334#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1382329#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1382322#L1254-3 assume !(0 == ~E_M~0); 1382316#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1382299#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1382291#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1382286#L1274-3 assume !(0 == ~E_4~0); 1382281#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1382274#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1382268#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1381909#L1294-3 assume !(0 == ~E_8~0); 1381908#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1381907#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1381900#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1381862#L1314-3 assume !(0 == ~E_12~0); 1381855#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1380279#L586-42 assume !(1 == ~m_pc~0); 1380274#L586-44 is_master_triggered_~__retres1~0#1 := 0; 1380268#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1380261#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1380254#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 1379321#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1376801#L605-42 assume 1 == ~t1_pc~0; 1376799#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1376800#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1376802#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1376791#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1376789#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1372177#L624-42 assume !(1 == ~t2_pc~0); 1372169#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1372162#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1372156#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1372150#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1372144#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1372139#L643-42 assume !(1 == ~t3_pc~0); 1372004#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1372001#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1371999#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1371997#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1371995#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1371993#L662-42 assume !(1 == ~t4_pc~0); 1371990#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1371988#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1371986#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1371984#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1371982#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1371980#L681-42 assume 1 == ~t5_pc~0; 1371978#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1371976#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1371974#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1371972#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1371970#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1371968#L700-42 assume !(1 == ~t6_pc~0); 1330888#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1371966#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1371964#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1371962#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1371960#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1371958#L719-42 assume !(1 == ~t7_pc~0); 1286447#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1371955#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1371953#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1371951#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 1371949#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1371947#L738-42 assume 1 == ~t8_pc~0; 1371944#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1371931#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1371925#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1371769#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1371766#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1371764#L757-42 assume 1 == ~t9_pc~0; 1371761#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1371759#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1371757#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1371755#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1371752#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1371750#L776-42 assume !(1 == ~t10_pc~0); 1371744#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1371740#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1371738#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1371736#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1371734#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1371732#L795-42 assume !(1 == ~t11_pc~0); 1371730#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1371727#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1371725#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1371723#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1371721#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1371719#L814-42 assume 1 == ~t12_pc~0; 1371716#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1371715#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1371713#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1371711#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1371709#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1371707#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1315820#L1332-5 assume !(1 == ~T1_E~0); 1371705#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1371703#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1371701#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1371699#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1371697#L1357-3 assume !(1 == ~T6_E~0); 1371695#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1371692#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1371690#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1315800#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1371687#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1371685#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1371683#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1371682#L1397-3 assume !(1 == ~E_1~0); 1371679#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1371677#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1371675#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1350531#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1371672#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1371670#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1371667#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1371665#L1437-3 assume !(1 == ~E_9~0); 1371632#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1371622#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1371610#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1353998#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1370491#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1370475#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1370473#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1370471#L1822 assume !(0 == start_simulation_~tmp~3#1); 1370469#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1370106#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1370090#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1370084#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 1370075#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1370068#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1370063#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1369484#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 1236454#L1803-2 [2022-07-14 16:03:47,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:47,366 INFO L85 PathProgramCache]: Analyzing trace with hash -1728090755, now seen corresponding path program 1 times [2022-07-14 16:03:47,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:47,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935725820] [2022-07-14 16:03:47,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:47,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:47,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:47,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:47,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:47,404 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935725820] [2022-07-14 16:03:47,404 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935725820] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:47,404 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:47,404 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:47,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742809439] [2022-07-14 16:03:47,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:47,405 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:47,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:47,406 INFO L85 PathProgramCache]: Analyzing trace with hash -769326147, now seen corresponding path program 1 times [2022-07-14 16:03:47,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:47,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567768794] [2022-07-14 16:03:47,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:47,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:47,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:47,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:47,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:47,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567768794] [2022-07-14 16:03:47,438 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1567768794] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:47,438 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:47,438 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:47,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105002033] [2022-07-14 16:03:47,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:47,439 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:47,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:47,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:47,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:47,440 INFO L87 Difference]: Start difference. First operand 305489 states and 434646 transitions. cyclomatic complexity: 129189 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:50,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:50,095 INFO L93 Difference]: Finished difference Result 737652 states and 1056403 transitions. [2022-07-14 16:03:50,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:50,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 737652 states and 1056403 transitions. [2022-07-14 16:03:54,134 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 736032 [2022-07-14 16:03:56,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 737652 states to 737652 states and 1056403 transitions. [2022-07-14 16:03:56,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 737652 [2022-07-14 16:03:56,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 737652 [2022-07-14 16:03:56,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 737652 states and 1056403 transitions. [2022-07-14 16:03:57,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:57,569 INFO L369 hiAutomatonCegarLoop]: Abstraction has 737652 states and 1056403 transitions. [2022-07-14 16:03:57,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 737652 states and 1056403 transitions.