./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:03:34,467 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:03:34,468 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:03:34,506 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:03:34,507 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:03:34,508 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:03:34,512 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:03:34,516 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:03:34,518 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:03:34,522 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:03:34,522 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:03:34,524 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:03:34,525 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:03:34,526 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:03:34,528 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:03:34,529 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:03:34,529 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:03:34,530 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:03:34,533 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:03:34,538 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:03:34,540 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:03:34,540 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:03:34,541 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:03:34,542 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:03:34,543 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:03:34,548 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:03:34,548 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:03:34,548 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:03:34,549 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:03:34,550 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:03:34,551 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:03:34,551 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:03:34,552 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:03:34,553 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:03:34,553 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:03:34,554 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:03:34,554 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:03:34,555 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:03:34,555 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:03:34,555 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:03:34,556 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:03:34,557 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:03:34,559 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:03:34,588 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:03:34,588 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:03:34,588 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:03:34,589 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:03:34,590 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:03:34,591 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:03:34,591 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:03:34,591 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:03:34,591 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:03:34,592 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:03:34,592 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:03:34,592 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:03:34,592 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:03:34,593 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:03:34,593 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:03:34,593 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:03:34,593 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:03:34,593 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:03:34,593 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:03:34,594 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:03:34,594 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:03:34,594 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:03:34,594 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:03:34,594 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:03:34,594 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:03:34,595 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:03:34,595 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:03:34,595 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:03:34,595 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:03:34,596 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:03:34,596 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:03:34,597 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:03:34,598 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2022-07-14 16:03:34,807 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:03:34,824 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:03:34,827 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:03:34,828 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:03:34,828 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:03:34,829 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.02.cil.c [2022-07-14 16:03:34,887 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4e15bf99d/af8fd0adbcf34bb58ecc24907836773c/FLAG89c5c4b97 [2022-07-14 16:03:35,323 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:03:35,324 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c [2022-07-14 16:03:35,330 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4e15bf99d/af8fd0adbcf34bb58ecc24907836773c/FLAG89c5c4b97 [2022-07-14 16:03:35,722 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4e15bf99d/af8fd0adbcf34bb58ecc24907836773c [2022-07-14 16:03:35,725 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:03:35,726 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:03:35,727 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:35,727 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:03:35,734 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:03:35,735 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:35,736 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7619101 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35, skipping insertion in model container [2022-07-14 16:03:35,736 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:35,743 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:03:35,766 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:03:35,896 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2022-07-14 16:03:35,933 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:35,943 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:03:35,953 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2022-07-14 16:03:35,973 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:35,986 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:03:35,986 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35 WrapperNode [2022-07-14 16:03:35,987 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:35,988 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:35,988 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:03:35,988 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:03:35,994 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,002 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,035 INFO L137 Inliner]: procedures = 32, calls = 36, calls flagged for inlining = 31, calls inlined = 44, statements flattened = 530 [2022-07-14 16:03:36,036 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:36,036 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:03:36,037 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:03:36,037 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:03:36,042 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,042 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,045 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,045 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,052 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,059 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,062 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,065 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:03:36,066 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:03:36,066 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:03:36,066 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:03:36,067 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (1/1) ... [2022-07-14 16:03:36,091 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:03:36,102 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:03:36,121 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:03:36,123 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:03:36,152 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:03:36,153 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:03:36,153 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:03:36,153 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:03:36,209 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:03:36,212 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:03:36,588 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:03:36,597 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:03:36,598 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2022-07-14 16:03:36,600 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:36 BoogieIcfgContainer [2022-07-14 16:03:36,600 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:03:36,601 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:03:36,601 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:03:36,610 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:03:36,611 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:36,611 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:03:35" (1/3) ... [2022-07-14 16:03:36,612 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4b16d9ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:36, skipping insertion in model container [2022-07-14 16:03:36,613 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:36,613 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:35" (2/3) ... [2022-07-14 16:03:36,613 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4b16d9ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:36, skipping insertion in model container [2022-07-14 16:03:36,613 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:36,614 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:36" (3/3) ... [2022-07-14 16:03:36,615 INFO L354 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2022-07-14 16:03:36,671 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:03:36,671 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:03:36,672 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:03:36,672 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:03:36,672 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:03:36,672 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:03:36,672 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:03:36,673 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:03:36,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:36,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2022-07-14 16:03:36,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:36,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:36,714 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:36,714 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:36,715 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:03:36,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:36,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2022-07-14 16:03:36,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:36,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:36,726 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:36,727 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:36,734 INFO L752 eck$LassoCheckResult]: Stem: 196#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 143#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3#L491true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 199#L214true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 54#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 37#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 148#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30#L334true assume !(0 == ~M_E~0); 155#L334-2true assume !(0 == ~T1_E~0); 98#L339-1true assume !(0 == ~T2_E~0); 93#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 130#L349-1true assume !(0 == ~E_2~0); 36#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104#L156true assume !(1 == ~m_pc~0); 141#L156-2true is_master_triggered_~__retres1~0#1 := 0; 124#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#L168true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 70#L405true assume !(0 != activate_threads_~tmp~1#1); 57#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112#L175true assume 1 == ~t1_pc~0; 147#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100#L187true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 101#L413true assume !(0 != activate_threads_~tmp___0~0#1); 178#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 181#L194true assume !(1 == ~t2_pc~0); 200#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 64#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31#L206true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24#L421true assume !(0 != activate_threads_~tmp___1~0#1); 75#L421-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11#L367true assume !(1 == ~M_E~0); 180#L367-2true assume !(1 == ~T1_E~0); 118#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 121#L377-1true assume !(1 == ~E_1~0); 21#L382-1true assume !(1 == ~E_2~0); 72#L387-1true assume { :end_inline_reset_delta_events } true; 92#L528-2true [2022-07-14 16:03:36,736 INFO L754 eck$LassoCheckResult]: Loop: 92#L528-2true assume !false; 76#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174#L309true assume false; 12#L324true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71#L214-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 203#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 144#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 102#L339-3true assume !(0 == ~T2_E~0); 176#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 68#L349-3true assume 0 == ~E_2~0;~E_2~0 := 1; 29#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L156-9true assume !(1 == ~m_pc~0); 5#L156-11true is_master_triggered_~__retres1~0#1 := 0; 52#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 166#L168-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 105#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 188#L175-9true assume 1 == ~t1_pc~0; 42#L176-3true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99#L187-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 140#L413-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185#L194-9true assume !(1 == ~t2_pc~0); 25#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 192#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74#L206-3true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 96#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131#L421-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume !(1 == ~T1_E~0); 32#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 16#L377-3true assume 1 == ~E_1~0;~E_1~0 := 2; 27#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 97#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 132#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 168#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22#L262-1true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 139#L547true assume !(0 == start_simulation_~tmp~3#1); 151#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 136#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 48#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 165#L262-2true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 35#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 173#L510true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 17#L560true assume !(0 != start_simulation_~tmp___0~1#1); 92#L528-2true [2022-07-14 16:03:36,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:36,742 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2022-07-14 16:03:36,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:36,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941877355] [2022-07-14 16:03:36,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:36,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:36,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:36,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:36,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:36,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941877355] [2022-07-14 16:03:36,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941877355] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:36,969 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:36,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:36,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807824273] [2022-07-14 16:03:36,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:36,975 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:36,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:36,976 INFO L85 PathProgramCache]: Analyzing trace with hash 764586486, now seen corresponding path program 1 times [2022-07-14 16:03:36,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:36,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841479926] [2022-07-14 16:03:36,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:36,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:36,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841479926] [2022-07-14 16:03:37,007 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841479926] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,007 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,007 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:37,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221073307] [2022-07-14 16:03:37,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,009 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:37,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:37,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:37,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:37,039 INFO L87 Difference]: Start difference. First operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:37,069 INFO L93 Difference]: Finished difference Result 204 states and 299 transitions. [2022-07-14 16:03:37,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:37,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 299 transitions. [2022-07-14 16:03:37,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-07-14 16:03:37,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 198 states and 293 transitions. [2022-07-14 16:03:37,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2022-07-14 16:03:37,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2022-07-14 16:03:37,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 293 transitions. [2022-07-14 16:03:37,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:37,101 INFO L369 hiAutomatonCegarLoop]: Abstraction has 198 states and 293 transitions. [2022-07-14 16:03:37,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 293 transitions. [2022-07-14 16:03:37,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2022-07-14 16:03:37,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 293 transitions. [2022-07-14 16:03:37,132 INFO L392 hiAutomatonCegarLoop]: Abstraction has 198 states and 293 transitions. [2022-07-14 16:03:37,132 INFO L374 stractBuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2022-07-14 16:03:37,135 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:03:37,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 293 transitions. [2022-07-14 16:03:37,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-07-14 16:03:37,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:37,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:37,146 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,146 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,147 INFO L752 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 421#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 514#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 489#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 476#L334 assume !(0 == ~M_E~0); 477#L334-2 assume !(0 == ~T1_E~0); 565#L339-1 assume !(0 == ~T2_E~0); 559#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 560#L349-1 assume !(0 == ~E_2~0); 486#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487#L156 assume !(1 == ~m_pc~0); 429#L156-2 is_master_triggered_~__retres1~0#1 := 0; 428#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 534#L405 assume !(0 != activate_threads_~tmp~1#1); 518#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519#L175 assume 1 == ~t1_pc~0; 578#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 520#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 567#L413 assume !(0 != activate_threads_~tmp___0~0#1); 568#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611#L194 assume !(1 == ~t2_pc~0); 558#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 530#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 465#L421 assume !(0 != activate_threads_~tmp___1~0#1); 466#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 440#L367 assume !(1 == ~M_E~0); 441#L367-2 assume !(1 == ~T1_E~0); 585#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 586#L377-1 assume !(1 == ~E_1~0); 460#L382-1 assume !(1 == ~E_2~0); 461#L387-1 assume { :end_inline_reset_delta_events } true; 452#L528-2 [2022-07-14 16:03:37,147 INFO L754 eck$LassoCheckResult]: Loop: 452#L528-2 assume !false; 539#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 513#L309 assume !false; 492#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 432#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 433#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 577#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 418#L276 assume !(0 != eval_~tmp~0#1); 420#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 535#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 602#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 569#L339-3 assume !(0 == ~T2_E~0); 570#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 533#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475#L156-9 assume !(1 == ~m_pc~0); 425#L156-11 is_master_triggered_~__retres1~0#1 := 0; 426#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 572#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 453#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 454#L175-9 assume 1 == ~t1_pc~0; 496#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 443#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 566#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 596#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 597#L194-9 assume !(1 == ~t2_pc~0); 467#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 468#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 538#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 563#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 430#L367-5 assume !(1 == ~T1_E~0); 431#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 449#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 450#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 471#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 564#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 480#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 462#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 463#L547 assume !(0 == start_simulation_~tmp~3#1); 587#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 598#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 505#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 506#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 484#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 485#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 451#L560 assume !(0 != start_simulation_~tmp___0~1#1); 452#L528-2 [2022-07-14 16:03:37,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2022-07-14 16:03:37,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095738501] [2022-07-14 16:03:37,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,201 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095738501] [2022-07-14 16:03:37,201 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095738501] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,201 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,201 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539188550] [2022-07-14 16:03:37,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,202 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:37,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,203 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 1 times [2022-07-14 16:03:37,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96802921] [2022-07-14 16:03:37,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96802921] [2022-07-14 16:03:37,297 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96802921] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,297 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,297 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764197222] [2022-07-14 16:03:37,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,297 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:37,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:37,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:37,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:37,299 INFO L87 Difference]: Start difference. First operand 198 states and 293 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:37,335 INFO L93 Difference]: Finished difference Result 198 states and 292 transitions. [2022-07-14 16:03:37,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:37,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 292 transitions. [2022-07-14 16:03:37,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-07-14 16:03:37,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 292 transitions. [2022-07-14 16:03:37,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2022-07-14 16:03:37,344 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2022-07-14 16:03:37,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 292 transitions. [2022-07-14 16:03:37,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:37,348 INFO L369 hiAutomatonCegarLoop]: Abstraction has 198 states and 292 transitions. [2022-07-14 16:03:37,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 292 transitions. [2022-07-14 16:03:37,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2022-07-14 16:03:37,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 292 transitions. [2022-07-14 16:03:37,360 INFO L392 hiAutomatonCegarLoop]: Abstraction has 198 states and 292 transitions. [2022-07-14 16:03:37,360 INFO L374 stractBuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2022-07-14 16:03:37,361 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:03:37,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 292 transitions. [2022-07-14 16:03:37,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2022-07-14 16:03:37,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:37,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:37,364 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,365 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,366 INFO L752 eck$LassoCheckResult]: Stem: 1018#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1004#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 824#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 825#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1012#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 917#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 891#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 892#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 879#L334 assume !(0 == ~M_E~0); 880#L334-2 assume !(0 == ~T1_E~0); 968#L339-1 assume !(0 == ~T2_E~0); 962#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 963#L349-1 assume !(0 == ~E_2~0); 889#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 890#L156 assume !(1 == ~m_pc~0); 832#L156-2 is_master_triggered_~__retres1~0#1 := 0; 831#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 937#L405 assume !(0 != activate_threads_~tmp~1#1); 921#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922#L175 assume 1 == ~t1_pc~0; 981#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 923#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 924#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 970#L413 assume !(0 != activate_threads_~tmp___0~0#1); 971#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1014#L194 assume !(1 == ~t2_pc~0); 961#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 933#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 881#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 868#L421 assume !(0 != activate_threads_~tmp___1~0#1); 869#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843#L367 assume !(1 == ~M_E~0); 844#L367-2 assume !(1 == ~T1_E~0); 988#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 989#L377-1 assume !(1 == ~E_1~0); 863#L382-1 assume !(1 == ~E_2~0); 864#L387-1 assume { :end_inline_reset_delta_events } true; 855#L528-2 [2022-07-14 16:03:37,367 INFO L754 eck$LassoCheckResult]: Loop: 855#L528-2 assume !false; 942#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 916#L309 assume !false; 895#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 835#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 836#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 980#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 821#L276 assume !(0 != eval_~tmp~0#1); 823#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 845#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 938#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1005#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 972#L339-3 assume !(0 == ~T2_E~0); 973#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 936#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 877#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 878#L156-9 assume !(1 == ~m_pc~0); 828#L156-11 is_master_triggered_~__retres1~0#1 := 0; 829#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 914#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 975#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 856#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 857#L175-9 assume 1 == ~t1_pc~0; 899#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 846#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 847#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 969#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 999#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1000#L194-9 assume !(1 == ~t2_pc~0); 870#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 871#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 940#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 941#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 966#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 911#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 833#L367-5 assume !(1 == ~T1_E~0); 834#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 852#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 853#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 874#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 967#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 883#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 865#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 866#L547 assume !(0 == start_simulation_~tmp~3#1); 990#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1001#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 908#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 909#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 887#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 888#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 904#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 854#L560 assume !(0 != start_simulation_~tmp___0~1#1); 855#L528-2 [2022-07-14 16:03:37,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,371 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2022-07-14 16:03:37,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428214040] [2022-07-14 16:03:37,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,441 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428214040] [2022-07-14 16:03:37,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428214040] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,442 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856829095] [2022-07-14 16:03:37,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,444 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:37,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,444 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 2 times [2022-07-14 16:03:37,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705922564] [2022-07-14 16:03:37,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705922564] [2022-07-14 16:03:37,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705922564] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,501 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,502 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940024413] [2022-07-14 16:03:37,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,502 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:37,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:37,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:37,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:37,504 INFO L87 Difference]: Start difference. First operand 198 states and 292 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:37,612 INFO L93 Difference]: Finished difference Result 336 states and 492 transitions. [2022-07-14 16:03:37,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:37,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 336 states and 492 transitions. [2022-07-14 16:03:37,615 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2022-07-14 16:03:37,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 336 states to 336 states and 492 transitions. [2022-07-14 16:03:37,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 336 [2022-07-14 16:03:37,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 336 [2022-07-14 16:03:37,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 336 states and 492 transitions. [2022-07-14 16:03:37,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:37,619 INFO L369 hiAutomatonCegarLoop]: Abstraction has 336 states and 492 transitions. [2022-07-14 16:03:37,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states and 492 transitions. [2022-07-14 16:03:37,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 334. [2022-07-14 16:03:37,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 334 states, 334 states have (on average 1.467065868263473) internal successors, (490), 333 states have internal predecessors, (490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 490 transitions. [2022-07-14 16:03:37,647 INFO L392 hiAutomatonCegarLoop]: Abstraction has 334 states and 490 transitions. [2022-07-14 16:03:37,647 INFO L374 stractBuchiCegarLoop]: Abstraction has 334 states and 490 transitions. [2022-07-14 16:03:37,647 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:03:37,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 334 states and 490 transitions. [2022-07-14 16:03:37,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2022-07-14 16:03:37,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:37,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:37,651 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,651 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,652 INFO L752 eck$LassoCheckResult]: Stem: 1590#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1567#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1368#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1369#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1580#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1467#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1440#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1441#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1426#L334 assume !(0 == ~M_E~0); 1427#L334-2 assume !(0 == ~T1_E~0); 1522#L339-1 assume !(0 == ~T2_E~0); 1516#L344-1 assume !(0 == ~E_1~0); 1517#L349-1 assume !(0 == ~E_2~0); 1438#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1439#L156 assume !(1 == ~m_pc~0); 1376#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1375#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1539#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1488#L405 assume !(0 != activate_threads_~tmp~1#1); 1471#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1472#L175 assume 1 == ~t1_pc~0; 1536#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1473#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1474#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1524#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1525#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1583#L194 assume !(1 == ~t2_pc~0); 1515#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1484#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1428#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1414#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1415#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1387#L367 assume !(1 == ~M_E~0); 1388#L367-2 assume !(1 == ~T1_E~0); 1543#L372-1 assume !(1 == ~T2_E~0); 1544#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1549#L382-1 assume !(1 == ~E_2~0); 1491#L387-1 assume { :end_inline_reset_delta_events } true; 1401#L528-2 [2022-07-14 16:03:37,656 INFO L754 eck$LassoCheckResult]: Loop: 1401#L528-2 assume !false; 1495#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1466#L309 assume !false; 1444#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1445#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1534#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1535#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1365#L276 assume !(0 != eval_~tmp~0#1); 1367#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1489#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1490#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1568#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1569#L339-3 assume !(0 == ~T2_E~0); 1581#L344-3 assume !(0 == ~E_1~0); 1487#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1424#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1425#L156-9 assume 1 == ~m_pc~0; 1510#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1373#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1464#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1529#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1402#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1403#L175-9 assume 1 == ~t1_pc~0; 1449#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1391#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1392#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1523#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1559#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1560#L194-9 assume 1 == ~t2_pc~0; 1492#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1417#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1493#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1494#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1520#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1461#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1377#L367-5 assume !(1 == ~T1_E~0); 1378#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1430#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1398#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1652#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1648#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1646#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1645#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1644#L547 assume !(0 == start_simulation_~tmp~3#1); 1642#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1562#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1458#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1459#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1436#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1437#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1454#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1400#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1401#L528-2 [2022-07-14 16:03:37,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,657 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2022-07-14 16:03:37,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,657 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651652351] [2022-07-14 16:03:37,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651652351] [2022-07-14 16:03:37,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651652351] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,722 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,722 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214330037] [2022-07-14 16:03:37,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,723 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:37,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,723 INFO L85 PathProgramCache]: Analyzing trace with hash 23037699, now seen corresponding path program 1 times [2022-07-14 16:03:37,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195095356] [2022-07-14 16:03:37,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195095356] [2022-07-14 16:03:37,784 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195095356] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,784 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,784 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888045476] [2022-07-14 16:03:37,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,785 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:37,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:37,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:37,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:37,786 INFO L87 Difference]: Start difference. First operand 334 states and 490 transitions. cyclomatic complexity: 158 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:37,867 INFO L93 Difference]: Finished difference Result 823 states and 1183 transitions. [2022-07-14 16:03:37,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:37,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 823 states and 1183 transitions. [2022-07-14 16:03:37,877 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 745 [2022-07-14 16:03:37,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 823 states to 823 states and 1183 transitions. [2022-07-14 16:03:37,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 823 [2022-07-14 16:03:37,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 823 [2022-07-14 16:03:37,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 823 states and 1183 transitions. [2022-07-14 16:03:37,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:37,889 INFO L369 hiAutomatonCegarLoop]: Abstraction has 823 states and 1183 transitions. [2022-07-14 16:03:37,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states and 1183 transitions. [2022-07-14 16:03:37,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 762. [2022-07-14 16:03:37,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 762 states, 762 states have (on average 1.4514435695538057) internal successors, (1106), 761 states have internal predecessors, (1106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:37,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 762 states to 762 states and 1106 transitions. [2022-07-14 16:03:37,917 INFO L392 hiAutomatonCegarLoop]: Abstraction has 762 states and 1106 transitions. [2022-07-14 16:03:37,917 INFO L374 stractBuchiCegarLoop]: Abstraction has 762 states and 1106 transitions. [2022-07-14 16:03:37,917 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:03:37,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 762 states and 1106 transitions. [2022-07-14 16:03:37,921 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 715 [2022-07-14 16:03:37,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:37,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:37,923 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,923 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:37,924 INFO L752 eck$LassoCheckResult]: Stem: 2767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2535#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2536#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2752#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2630#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2602#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2603#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2589#L334 assume !(0 == ~M_E~0); 2590#L334-2 assume !(0 == ~T1_E~0); 2686#L339-1 assume !(0 == ~T2_E~0); 2680#L344-1 assume !(0 == ~E_1~0); 2681#L349-1 assume !(0 == ~E_2~0); 2600#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2601#L156 assume !(1 == ~m_pc~0); 2693#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2719#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2702#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2650#L405 assume !(0 != activate_threads_~tmp~1#1); 2635#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2636#L175 assume !(1 == ~t1_pc~0); 2642#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2637#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2638#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2688#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2691#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2754#L194 assume !(1 == ~t2_pc~0); 2678#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2647#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2594#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2578#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2579#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2550#L367 assume !(1 == ~M_E~0); 2551#L367-2 assume !(1 == ~T1_E~0); 2708#L372-1 assume !(1 == ~T2_E~0); 2709#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2715#L382-1 assume !(1 == ~E_2~0); 2651#L387-1 assume { :end_inline_reset_delta_events } true; 2652#L528-2 [2022-07-14 16:03:37,924 INFO L754 eck$LassoCheckResult]: Loop: 2652#L528-2 assume !false; 2657#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2629#L309 assume !false; 2609#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2543#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2544#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2699#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2532#L276 assume !(0 != eval_~tmp~0#1); 2534#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3276#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3274#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3272#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3270#L339-3 assume !(0 == ~T2_E~0); 3268#L344-3 assume !(0 == ~E_1~0); 3266#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3263#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3261#L156-9 assume !(1 == ~m_pc~0); 3259#L156-11 is_master_triggered_~__retres1~0#1 := 0; 3257#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3255#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3253#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3252#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3251#L175-9 assume !(1 == ~t1_pc~0); 3250#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3228#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3225#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3223#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3220#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3218#L194-9 assume !(1 == ~t2_pc~0); 3216#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 3213#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3210#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3208#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3206#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3203#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3200#L367-5 assume !(1 == ~T1_E~0); 3196#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3180#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3178#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3190#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3150#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3147#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3120#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3115#L547 assume !(0 == start_simulation_~tmp~3#1); 3108#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3099#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3095#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3090#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3087#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3084#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3081#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3077#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2652#L528-2 [2022-07-14 16:03:37,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,925 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2022-07-14 16:03:37,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090145671] [2022-07-14 16:03:37,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090145671] [2022-07-14 16:03:37,954 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090145671] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,954 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054491348] [2022-07-14 16:03:37,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,955 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:37,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:37,955 INFO L85 PathProgramCache]: Analyzing trace with hash 905649184, now seen corresponding path program 1 times [2022-07-14 16:03:37,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:37,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561868241] [2022-07-14 16:03:37,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:37,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:37,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:37,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:37,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:37,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561868241] [2022-07-14 16:03:37,980 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561868241] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:37,981 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:37,981 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:37,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047147714] [2022-07-14 16:03:37,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:37,982 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:37,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:37,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:37,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:37,983 INFO L87 Difference]: Start difference. First operand 762 states and 1106 transitions. cyclomatic complexity: 348 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,032 INFO L93 Difference]: Finished difference Result 679 states and 958 transitions. [2022-07-14 16:03:38,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:38,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 679 states and 958 transitions. [2022-07-14 16:03:38,039 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 631 [2022-07-14 16:03:38,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 679 states to 679 states and 958 transitions. [2022-07-14 16:03:38,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 679 [2022-07-14 16:03:38,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 679 [2022-07-14 16:03:38,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 679 states and 958 transitions. [2022-07-14 16:03:38,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:38,045 INFO L369 hiAutomatonCegarLoop]: Abstraction has 679 states and 958 transitions. [2022-07-14 16:03:38,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 679 states and 958 transitions. [2022-07-14 16:03:38,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 679 to 663. [2022-07-14 16:03:38,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 663 states, 663 states have (on average 1.4147812971342384) internal successors, (938), 662 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 663 states to 663 states and 938 transitions. [2022-07-14 16:03:38,060 INFO L392 hiAutomatonCegarLoop]: Abstraction has 663 states and 938 transitions. [2022-07-14 16:03:38,060 INFO L374 stractBuchiCegarLoop]: Abstraction has 663 states and 938 transitions. [2022-07-14 16:03:38,060 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:03:38,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 663 states and 938 transitions. [2022-07-14 16:03:38,063 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 619 [2022-07-14 16:03:38,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:38,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:38,066 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,066 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,067 INFO L752 eck$LassoCheckResult]: Stem: 4200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3986#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3987#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4191#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4077#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4051#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4052#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4038#L334 assume !(0 == ~M_E~0); 4039#L334-2 assume !(0 == ~T1_E~0); 4131#L339-1 assume !(0 == ~T2_E~0); 4124#L344-1 assume !(0 == ~E_1~0); 4125#L349-1 assume !(0 == ~E_2~0); 4049#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4050#L156 assume !(1 == ~m_pc~0); 4138#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4158#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4147#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4097#L405 assume !(0 != activate_threads_~tmp~1#1); 4081#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4082#L175 assume !(1 == ~t1_pc~0); 4089#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4083#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4084#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4133#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4134#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4193#L194 assume !(1 == ~t2_pc~0); 4123#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4093#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4040#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4027#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4028#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4001#L367 assume !(1 == ~M_E~0); 4002#L367-2 assume !(1 == ~T1_E~0); 4151#L372-1 assume !(1 == ~T2_E~0); 4152#L377-1 assume !(1 == ~E_1~0); 4022#L382-1 assume !(1 == ~E_2~0); 4023#L387-1 assume { :end_inline_reset_delta_events } true; 4099#L528-2 [2022-07-14 16:03:38,067 INFO L754 eck$LassoCheckResult]: Loop: 4099#L528-2 assume !false; 4253#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4248#L309 assume !false; 4247#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4245#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4243#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4242#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4237#L276 assume !(0 != eval_~tmp~0#1); 4238#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4332#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4331#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4330#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4329#L339-3 assume !(0 == ~T2_E~0); 4328#L344-3 assume !(0 == ~E_1~0); 4327#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4326#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4325#L156-9 assume !(1 == ~m_pc~0); 4324#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4323#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4322#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4321#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4319#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4317#L175-9 assume !(1 == ~t1_pc~0); 4315#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4313#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4311#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4309#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4307#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4305#L194-9 assume 1 == ~t2_pc~0; 4302#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4300#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4298#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4296#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4294#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4291#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4289#L367-5 assume !(1 == ~T1_E~0); 4287#L372-3 assume !(1 == ~T2_E~0); 4285#L377-3 assume !(1 == ~E_1~0); 4283#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4281#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4278#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4275#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4273#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4270#L547 assume !(0 == start_simulation_~tmp~3#1); 4268#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4266#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4264#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4263#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4262#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4261#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4260#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4258#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4099#L528-2 [2022-07-14 16:03:38,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,068 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2022-07-14 16:03:38,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514732273] [2022-07-14 16:03:38,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,081 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:38,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,135 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:38,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,136 INFO L85 PathProgramCache]: Analyzing trace with hash 195112129, now seen corresponding path program 1 times [2022-07-14 16:03:38,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020524800] [2022-07-14 16:03:38,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:38,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:38,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:38,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020524800] [2022-07-14 16:03:38,200 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020524800] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:38,200 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:38,200 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:38,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304573002] [2022-07-14 16:03:38,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:38,201 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:38,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:38,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:38,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:38,203 INFO L87 Difference]: Start difference. First operand 663 states and 938 transitions. cyclomatic complexity: 278 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,222 INFO L93 Difference]: Finished difference Result 819 states and 1148 transitions. [2022-07-14 16:03:38,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:38,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 819 states and 1148 transitions. [2022-07-14 16:03:38,241 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 750 [2022-07-14 16:03:38,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 819 states to 819 states and 1148 transitions. [2022-07-14 16:03:38,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 819 [2022-07-14 16:03:38,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 819 [2022-07-14 16:03:38,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 819 states and 1148 transitions. [2022-07-14 16:03:38,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:38,248 INFO L369 hiAutomatonCegarLoop]: Abstraction has 819 states and 1148 transitions. [2022-07-14 16:03:38,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 819 states and 1148 transitions. [2022-07-14 16:03:38,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 819 to 819. [2022-07-14 16:03:38,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 819 states, 819 states have (on average 1.4017094017094016) internal successors, (1148), 818 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 819 states and 1148 transitions. [2022-07-14 16:03:38,263 INFO L392 hiAutomatonCegarLoop]: Abstraction has 819 states and 1148 transitions. [2022-07-14 16:03:38,263 INFO L374 stractBuchiCegarLoop]: Abstraction has 819 states and 1148 transitions. [2022-07-14 16:03:38,263 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:03:38,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 819 states and 1148 transitions. [2022-07-14 16:03:38,267 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 750 [2022-07-14 16:03:38,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:38,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:38,269 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,269 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,269 INFO L752 eck$LassoCheckResult]: Stem: 5721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5474#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5475#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5701#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 5568#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5538#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5539#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5526#L334 assume !(0 == ~M_E~0); 5527#L334-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5625#L339-1 assume !(0 == ~T2_E~0); 5626#L344-1 assume !(0 == ~E_1~0); 5878#L349-1 assume !(0 == ~E_2~0); 5536#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5537#L156 assume !(1 == ~m_pc~0); 5634#L156-2 is_master_triggered_~__retres1~0#1 := 0; 5876#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5875#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5589#L405 assume !(0 != activate_threads_~tmp~1#1); 5573#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5574#L175 assume !(1 == ~t1_pc~0); 5581#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5575#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5576#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5629#L413 assume !(0 != activate_threads_~tmp___0~0#1); 5630#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5704#L194 assume !(1 == ~t2_pc~0); 5618#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5585#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5528#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5515#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5516#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5489#L367 assume !(1 == ~M_E~0); 5490#L367-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5649#L372-1 assume !(1 == ~T2_E~0); 5650#L377-1 assume !(1 == ~E_1~0); 5510#L382-1 assume !(1 == ~E_2~0); 5511#L387-1 assume { :end_inline_reset_delta_events } true; 5592#L528-2 [2022-07-14 16:03:38,270 INFO L754 eck$LassoCheckResult]: Loop: 5592#L528-2 assume !false; 5758#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5753#L309 assume !false; 5752#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5750#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5748#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5747#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5745#L276 assume !(0 != eval_~tmp~0#1); 5746#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5847#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5845#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5842#L334-5 assume !(0 == ~T1_E~0); 5843#L339-3 assume !(0 == ~T2_E~0); 5861#L344-3 assume !(0 == ~E_1~0); 5860#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5859#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5858#L156-9 assume !(1 == ~m_pc~0); 5857#L156-11 is_master_triggered_~__retres1~0#1 := 0; 5856#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5855#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5854#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5853#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5852#L175-9 assume !(1 == ~t1_pc~0); 5851#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5850#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5849#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5848#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5846#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5844#L194-9 assume 1 == ~t2_pc~0; 5840#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5838#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5836#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5834#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5832#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5830#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5794#L367-5 assume !(1 == ~T1_E~0); 5792#L372-3 assume !(1 == ~T2_E~0); 5790#L377-3 assume !(1 == ~E_1~0); 5788#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5786#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5782#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5779#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5777#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 5774#L547 assume !(0 == start_simulation_~tmp~3#1); 5772#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5770#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5768#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5767#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 5765#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5764#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5763#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5761#L560 assume !(0 != start_simulation_~tmp___0~1#1); 5592#L528-2 [2022-07-14 16:03:38,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1536562243, now seen corresponding path program 1 times [2022-07-14 16:03:38,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428918530] [2022-07-14 16:03:38,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:38,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:38,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:38,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428918530] [2022-07-14 16:03:38,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428918530] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:38,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:38,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:38,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598951597] [2022-07-14 16:03:38,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:38,313 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:38,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,313 INFO L85 PathProgramCache]: Analyzing trace with hash 618758851, now seen corresponding path program 1 times [2022-07-14 16:03:38,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726150781] [2022-07-14 16:03:38,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:38,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:38,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:38,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726150781] [2022-07-14 16:03:38,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726150781] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:38,348 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:38,348 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:38,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044697218] [2022-07-14 16:03:38,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:38,349 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:38,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:38,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:38,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:38,359 INFO L87 Difference]: Start difference. First operand 819 states and 1148 transitions. cyclomatic complexity: 332 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,373 INFO L93 Difference]: Finished difference Result 663 states and 921 transitions. [2022-07-14 16:03:38,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:38,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 663 states and 921 transitions. [2022-07-14 16:03:38,380 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 619 [2022-07-14 16:03:38,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 663 states to 663 states and 921 transitions. [2022-07-14 16:03:38,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 663 [2022-07-14 16:03:38,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 663 [2022-07-14 16:03:38,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 663 states and 921 transitions. [2022-07-14 16:03:38,386 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:38,387 INFO L369 hiAutomatonCegarLoop]: Abstraction has 663 states and 921 transitions. [2022-07-14 16:03:38,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 663 states and 921 transitions. [2022-07-14 16:03:38,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 663 to 663. [2022-07-14 16:03:38,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 663 states, 663 states have (on average 1.3891402714932126) internal successors, (921), 662 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 663 states to 663 states and 921 transitions. [2022-07-14 16:03:38,399 INFO L392 hiAutomatonCegarLoop]: Abstraction has 663 states and 921 transitions. [2022-07-14 16:03:38,399 INFO L374 stractBuchiCegarLoop]: Abstraction has 663 states and 921 transitions. [2022-07-14 16:03:38,399 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:03:38,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 663 states and 921 transitions. [2022-07-14 16:03:38,402 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 619 [2022-07-14 16:03:38,403 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:38,403 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:38,403 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,403 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,404 INFO L752 eck$LassoCheckResult]: Stem: 7193#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6965#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6966#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7181#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 7059#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7029#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7030#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7017#L334 assume !(0 == ~M_E~0); 7018#L334-2 assume !(0 == ~T1_E~0); 7115#L339-1 assume !(0 == ~T2_E~0); 7109#L344-1 assume !(0 == ~E_1~0); 7110#L349-1 assume !(0 == ~E_2~0); 7027#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7028#L156 assume !(1 == ~m_pc~0); 7122#L156-2 is_master_triggered_~__retres1~0#1 := 0; 7143#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7131#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7080#L405 assume !(0 != activate_threads_~tmp~1#1); 7064#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7065#L175 assume !(1 == ~t1_pc~0); 7072#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7066#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7067#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7117#L413 assume !(0 != activate_threads_~tmp___0~0#1); 7118#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7183#L194 assume !(1 == ~t2_pc~0); 7108#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7076#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7019#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7006#L421 assume !(0 != activate_threads_~tmp___1~0#1); 7007#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6980#L367 assume !(1 == ~M_E~0); 6981#L367-2 assume !(1 == ~T1_E~0); 7135#L372-1 assume !(1 == ~T2_E~0); 7136#L377-1 assume !(1 == ~E_1~0); 7001#L382-1 assume !(1 == ~E_2~0); 7002#L387-1 assume { :end_inline_reset_delta_events } true; 7082#L528-2 [2022-07-14 16:03:38,404 INFO L754 eck$LassoCheckResult]: Loop: 7082#L528-2 assume !false; 7254#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7249#L309 assume !false; 7248#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6973#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6974#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7128#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6962#L276 assume !(0 != eval_~tmp~0#1); 6964#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7333#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7332#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7331#L334-5 assume !(0 == ~T1_E~0); 7330#L339-3 assume !(0 == ~T2_E~0); 7329#L344-3 assume !(0 == ~E_1~0); 7328#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7327#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7326#L156-9 assume !(1 == ~m_pc~0); 7325#L156-11 is_master_triggered_~__retres1~0#1 := 0; 7324#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7323#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7322#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7320#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7318#L175-9 assume !(1 == ~t1_pc~0); 7316#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 7314#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7312#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7310#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7308#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7306#L194-9 assume 1 == ~t2_pc~0; 7303#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7301#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7299#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7297#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7295#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7292#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7290#L367-5 assume !(1 == ~T1_E~0); 7288#L372-3 assume !(1 == ~T2_E~0); 7286#L377-3 assume !(1 == ~E_1~0); 7284#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7282#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7279#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7276#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7274#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 7271#L547 assume !(0 == start_simulation_~tmp~3#1); 7269#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7267#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7265#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7264#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 7263#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7262#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7261#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7259#L560 assume !(0 != start_simulation_~tmp___0~1#1); 7082#L528-2 [2022-07-14 16:03:38,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,405 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2022-07-14 16:03:38,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772454829] [2022-07-14 16:03:38,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,422 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:38,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,443 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:38,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,444 INFO L85 PathProgramCache]: Analyzing trace with hash 618758851, now seen corresponding path program 2 times [2022-07-14 16:03:38,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650125798] [2022-07-14 16:03:38,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:38,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:38,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:38,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650125798] [2022-07-14 16:03:38,478 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650125798] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:38,478 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:38,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:38,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412564696] [2022-07-14 16:03:38,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:38,482 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:38,482 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:38,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:38,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:38,483 INFO L87 Difference]: Start difference. First operand 663 states and 921 transitions. cyclomatic complexity: 261 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,550 INFO L93 Difference]: Finished difference Result 1116 states and 1528 transitions. [2022-07-14 16:03:38,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:03:38,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1116 states and 1528 transitions. [2022-07-14 16:03:38,559 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1067 [2022-07-14 16:03:38,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1116 states to 1116 states and 1528 transitions. [2022-07-14 16:03:38,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1116 [2022-07-14 16:03:38,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1116 [2022-07-14 16:03:38,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1116 states and 1528 transitions. [2022-07-14 16:03:38,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:38,574 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1116 states and 1528 transitions. [2022-07-14 16:03:38,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1116 states and 1528 transitions. [2022-07-14 16:03:38,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1116 to 678. [2022-07-14 16:03:38,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 678 states, 678 states have (on average 1.3805309734513274) internal successors, (936), 677 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 936 transitions. [2022-07-14 16:03:38,587 INFO L392 hiAutomatonCegarLoop]: Abstraction has 678 states and 936 transitions. [2022-07-14 16:03:38,588 INFO L374 stractBuchiCegarLoop]: Abstraction has 678 states and 936 transitions. [2022-07-14 16:03:38,588 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:03:38,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 678 states and 936 transitions. [2022-07-14 16:03:38,590 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 634 [2022-07-14 16:03:38,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:38,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:38,592 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,592 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,592 INFO L752 eck$LassoCheckResult]: Stem: 9000#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8759#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8760#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8985#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 8852#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8825#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8826#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8813#L334 assume !(0 == ~M_E~0); 8814#L334-2 assume !(0 == ~T1_E~0); 8907#L339-1 assume !(0 == ~T2_E~0); 8900#L344-1 assume !(0 == ~E_1~0); 8901#L349-1 assume !(0 == ~E_2~0); 8823#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8824#L156 assume !(1 == ~m_pc~0); 8915#L156-2 is_master_triggered_~__retres1~0#1 := 0; 8938#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8925#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8875#L405 assume !(0 != activate_threads_~tmp~1#1); 8860#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8861#L175 assume !(1 == ~t1_pc~0); 8865#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8862#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8863#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 8913#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8989#L194 assume !(1 == ~t2_pc~0); 8899#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8871#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8817#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8801#L421 assume !(0 != activate_threads_~tmp___1~0#1); 8802#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8774#L367 assume !(1 == ~M_E~0); 8775#L367-2 assume !(1 == ~T1_E~0); 8929#L372-1 assume !(1 == ~T2_E~0); 8930#L377-1 assume !(1 == ~E_1~0); 8796#L382-1 assume !(1 == ~E_2~0); 8797#L387-1 assume { :end_inline_reset_delta_events } true; 8876#L528-2 [2022-07-14 16:03:38,597 INFO L754 eck$LassoCheckResult]: Loop: 8876#L528-2 assume !false; 9409#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8984#L309 assume !false; 8829#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8767#L244 assume !(0 == ~m_st~0); 8769#L248 assume !(0 == ~t1_st~0); 8921#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 8963#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9299#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9293#L276 assume !(0 != eval_~tmp~0#1); 9294#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8873#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8874#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9005#L334-5 assume !(0 == ~T1_E~0); 9289#L339-3 assume !(0 == ~T2_E~0); 9287#L344-3 assume !(0 == ~E_1~0); 8872#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8811#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8812#L156-9 assume !(1 == ~m_pc~0); 8895#L156-11 is_master_triggered_~__retres1~0#1 := 0; 9393#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9392#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9391#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9390#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9389#L175-9 assume !(1 == ~t1_pc~0); 9388#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 8776#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8777#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8957#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8958#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8991#L194-9 assume 1 == ~t2_pc~0; 8992#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9387#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9386#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9385#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9384#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9383#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8765#L367-5 assume !(1 == ~T1_E~0); 8766#L372-3 assume !(1 == ~T2_E~0); 8785#L377-3 assume !(1 == ~E_1~0); 8786#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8905#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8906#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9421#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8798#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 8799#L547 assume !(0 == start_simulation_~tmp~3#1); 8955#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8952#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8840#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8841#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 8821#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8822#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8838#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9410#L560 assume !(0 != start_simulation_~tmp___0~1#1); 8876#L528-2 [2022-07-14 16:03:38,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,598 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2022-07-14 16:03:38,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918704891] [2022-07-14 16:03:38,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,607 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:38,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,624 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:38,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,625 INFO L85 PathProgramCache]: Analyzing trace with hash 2132958556, now seen corresponding path program 1 times [2022-07-14 16:03:38,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42183679] [2022-07-14 16:03:38,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:38,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:38,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:38,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42183679] [2022-07-14 16:03:38,716 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42183679] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:38,716 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:38,716 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:38,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007695416] [2022-07-14 16:03:38,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:38,717 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:38,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:38,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:38,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:38,718 INFO L87 Difference]: Start difference. First operand 678 states and 936 transitions. cyclomatic complexity: 261 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,829 INFO L93 Difference]: Finished difference Result 1640 states and 2247 transitions. [2022-07-14 16:03:38,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:38,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1640 states and 2247 transitions. [2022-07-14 16:03:38,838 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1596 [2022-07-14 16:03:38,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1640 states to 1640 states and 2247 transitions. [2022-07-14 16:03:38,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1640 [2022-07-14 16:03:38,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1640 [2022-07-14 16:03:38,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1640 states and 2247 transitions. [2022-07-14 16:03:38,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:38,850 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1640 states and 2247 transitions. [2022-07-14 16:03:38,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1640 states and 2247 transitions. [2022-07-14 16:03:38,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1640 to 714. [2022-07-14 16:03:38,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 714 states, 714 states have (on average 1.3571428571428572) internal successors, (969), 713 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 714 states to 714 states and 969 transitions. [2022-07-14 16:03:38,867 INFO L392 hiAutomatonCegarLoop]: Abstraction has 714 states and 969 transitions. [2022-07-14 16:03:38,867 INFO L374 stractBuchiCegarLoop]: Abstraction has 714 states and 969 transitions. [2022-07-14 16:03:38,867 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:03:38,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 714 states and 969 transitions. [2022-07-14 16:03:38,870 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 670 [2022-07-14 16:03:38,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:38,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:38,877 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,877 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,877 INFO L752 eck$LassoCheckResult]: Stem: 11333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 11292#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11090#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11091#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11317#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 11184#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11155#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11156#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11143#L334 assume !(0 == ~M_E~0); 11144#L334-2 assume !(0 == ~T1_E~0); 11244#L339-1 assume !(0 == ~T2_E~0); 11238#L344-1 assume !(0 == ~E_1~0); 11239#L349-1 assume !(0 == ~E_2~0); 11153#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11154#L156 assume !(1 == ~m_pc~0); 11252#L156-2 is_master_triggered_~__retres1~0#1 := 0; 11276#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11263#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11207#L405 assume !(0 != activate_threads_~tmp~1#1); 11189#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11190#L175 assume !(1 == ~t1_pc~0); 11197#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11191#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11192#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11246#L413 assume !(0 != activate_threads_~tmp___0~0#1); 11247#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11319#L194 assume !(1 == ~t2_pc~0); 11237#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11201#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11145#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11132#L421 assume !(0 != activate_threads_~tmp___1~0#1); 11133#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11105#L367 assume !(1 == ~M_E~0); 11106#L367-2 assume !(1 == ~T1_E~0); 11268#L372-1 assume !(1 == ~T2_E~0); 11269#L377-1 assume !(1 == ~E_1~0); 11126#L382-1 assume !(1 == ~E_2~0); 11127#L387-1 assume { :end_inline_reset_delta_events } true; 11209#L528-2 [2022-07-14 16:03:38,877 INFO L754 eck$LassoCheckResult]: Loop: 11209#L528-2 assume !false; 11363#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11358#L309 assume !false; 11357#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11355#L244 assume !(0 == ~m_st~0); 11356#L248 assume !(0 == ~t1_st~0); 11353#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11354#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11349#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11350#L276 assume !(0 != eval_~tmp~0#1); 11442#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11441#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11440#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11439#L334-5 assume !(0 == ~T1_E~0); 11438#L339-3 assume !(0 == ~T2_E~0); 11437#L344-3 assume !(0 == ~E_1~0); 11436#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11435#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11434#L156-9 assume !(1 == ~m_pc~0); 11433#L156-11 is_master_triggered_~__retres1~0#1 := 0; 11432#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11431#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11430#L405-9 assume !(0 != activate_threads_~tmp~1#1); 11428#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11426#L175-9 assume !(1 == ~t1_pc~0); 11424#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 11422#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11420#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11418#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11416#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11414#L194-9 assume 1 == ~t2_pc~0; 11411#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11409#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11407#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11405#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11403#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11400#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11398#L367-5 assume !(1 == ~T1_E~0); 11396#L372-3 assume !(1 == ~T2_E~0); 11394#L377-3 assume !(1 == ~E_1~0); 11392#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11390#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11387#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11384#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11382#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 11379#L547 assume !(0 == start_simulation_~tmp~3#1); 11377#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11375#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11373#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11372#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 11371#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11370#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11369#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11367#L560 assume !(0 != start_simulation_~tmp___0~1#1); 11209#L528-2 [2022-07-14 16:03:38,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,878 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2022-07-14 16:03:38,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53187055] [2022-07-14 16:03:38,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,891 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:38,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:38,906 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:38,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1887249126, now seen corresponding path program 1 times [2022-07-14 16:03:38,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623438676] [2022-07-14 16:03:38,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:38,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:38,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:38,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:38,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623438676] [2022-07-14 16:03:38,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623438676] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:38,928 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:38,928 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:38,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550582917] [2022-07-14 16:03:38,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:38,929 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:38,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:38,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:38,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:38,930 INFO L87 Difference]: Start difference. First operand 714 states and 969 transitions. cyclomatic complexity: 258 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:38,958 INFO L93 Difference]: Finished difference Result 1157 states and 1543 transitions. [2022-07-14 16:03:38,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:38,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1157 states and 1543 transitions. [2022-07-14 16:03:38,965 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1111 [2022-07-14 16:03:38,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1157 states to 1157 states and 1543 transitions. [2022-07-14 16:03:38,970 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1157 [2022-07-14 16:03:38,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1157 [2022-07-14 16:03:38,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1157 states and 1543 transitions. [2022-07-14 16:03:38,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:38,973 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1157 states and 1543 transitions. [2022-07-14 16:03:38,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1157 states and 1543 transitions. [2022-07-14 16:03:38,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1157 to 1122. [2022-07-14 16:03:38,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1122 states, 1122 states have (on average 1.3351158645276293) internal successors, (1498), 1121 states have internal predecessors, (1498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:38,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 1122 states and 1498 transitions. [2022-07-14 16:03:38,990 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1122 states and 1498 transitions. [2022-07-14 16:03:38,990 INFO L374 stractBuchiCegarLoop]: Abstraction has 1122 states and 1498 transitions. [2022-07-14 16:03:38,991 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:03:38,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1122 states and 1498 transitions. [2022-07-14 16:03:38,995 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1076 [2022-07-14 16:03:38,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:38,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:38,995 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,996 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:38,996 INFO L752 eck$LassoCheckResult]: Stem: 13207#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 13166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12967#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12968#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13189#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 13058#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13030#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13031#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13018#L334 assume !(0 == ~M_E~0); 13019#L334-2 assume !(0 == ~T1_E~0); 13113#L339-1 assume !(0 == ~T2_E~0); 13106#L344-1 assume !(0 == ~E_1~0); 13107#L349-1 assume !(0 == ~E_2~0); 13028#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13029#L156 assume !(1 == ~m_pc~0); 13122#L156-2 is_master_triggered_~__retres1~0#1 := 0; 13148#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13136#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13081#L405 assume !(0 != activate_threads_~tmp~1#1); 13065#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13066#L175 assume !(1 == ~t1_pc~0); 13070#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13067#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13068#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13116#L413 assume !(0 != activate_threads_~tmp___0~0#1); 13119#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13191#L194 assume !(1 == ~t2_pc~0); 13105#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13076#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13022#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13007#L421 assume !(0 != activate_threads_~tmp___1~0#1); 13008#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12981#L367 assume !(1 == ~M_E~0); 12982#L367-2 assume !(1 == ~T1_E~0); 13140#L372-1 assume !(1 == ~T2_E~0); 13141#L377-1 assume !(1 == ~E_1~0); 13002#L382-1 assume !(1 == ~E_2~0); 13003#L387-1 assume { :end_inline_reset_delta_events } true; 13082#L528-2 assume !false; 13232#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13227#L309 [2022-07-14 16:03:38,996 INFO L754 eck$LassoCheckResult]: Loop: 13227#L309 assume !false; 13226#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13224#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13223#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13222#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13221#L276 assume 0 != eval_~tmp~0#1; 13220#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13218#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 13219#L281 assume !(0 == ~t1_st~0); 13231#L295 assume !(0 == ~t2_st~0); 13227#L309 [2022-07-14 16:03:38,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:38,997 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2022-07-14 16:03:38,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:38,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750430454] [2022-07-14 16:03:38,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:38,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,006 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1417539670, now seen corresponding path program 1 times [2022-07-14 16:03:39,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44739616] [2022-07-14 16:03:39,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,025 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,028 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1345054088, now seen corresponding path program 1 times [2022-07-14 16:03:39,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332212971] [2022-07-14 16:03:39,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:39,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:39,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:39,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332212971] [2022-07-14 16:03:39,049 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332212971] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:39,049 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:39,049 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:39,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592115551] [2022-07-14 16:03:39,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:39,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:39,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:39,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:39,115 INFO L87 Difference]: Start difference. First operand 1122 states and 1498 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 16.666666666666668) internal successors, (50), 3 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:39,171 INFO L93 Difference]: Finished difference Result 1971 states and 2598 transitions. [2022-07-14 16:03:39,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:39,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1971 states and 2598 transitions. [2022-07-14 16:03:39,182 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1829 [2022-07-14 16:03:39,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1971 states to 1971 states and 2598 transitions. [2022-07-14 16:03:39,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1971 [2022-07-14 16:03:39,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1971 [2022-07-14 16:03:39,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1971 states and 2598 transitions. [2022-07-14 16:03:39,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:39,195 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1971 states and 2598 transitions. [2022-07-14 16:03:39,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1971 states and 2598 transitions. [2022-07-14 16:03:39,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1971 to 1875. [2022-07-14 16:03:39,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1875 states, 1875 states have (on average 1.3221333333333334) internal successors, (2479), 1874 states have internal predecessors, (2479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1875 states to 1875 states and 2479 transitions. [2022-07-14 16:03:39,222 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1875 states and 2479 transitions. [2022-07-14 16:03:39,222 INFO L374 stractBuchiCegarLoop]: Abstraction has 1875 states and 2479 transitions. [2022-07-14 16:03:39,223 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:03:39,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1875 states and 2479 transitions. [2022-07-14 16:03:39,229 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1768 [2022-07-14 16:03:39,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:39,240 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:39,240 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:39,240 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:39,241 INFO L752 eck$LassoCheckResult]: Stem: 16324#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 16282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16068#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16069#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16305#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 16160#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 16132#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16133#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16119#L334 assume !(0 == ~M_E~0); 16120#L334-2 assume !(0 == ~T1_E~0); 16222#L339-1 assume !(0 == ~T2_E~0); 16223#L344-1 assume !(0 == ~E_1~0); 16269#L349-1 assume !(0 == ~E_2~0); 16270#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16234#L156 assume !(1 == ~m_pc~0); 16235#L156-2 is_master_triggered_~__retres1~0#1 := 0; 16262#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16263#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16183#L405 assume !(0 != activate_threads_~tmp~1#1); 16184#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16245#L175 assume !(1 == ~t1_pc~0); 16246#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16167#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16168#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16227#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16228#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16309#L194 assume !(1 == ~t2_pc~0); 16214#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16215#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16121#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16122#L421 assume !(0 != activate_threads_~tmp___1~0#1); 16191#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16192#L367 assume !(1 == ~M_E~0); 16311#L367-2 assume !(1 == ~T1_E~0); 16255#L372-1 assume !(1 == ~T2_E~0); 16256#L377-1 assume !(1 == ~E_1~0); 16259#L382-1 assume !(1 == ~E_2~0); 16186#L387-1 assume { :end_inline_reset_delta_events } true; 16187#L528-2 assume !false; 17937#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17933#L309 [2022-07-14 16:03:39,241 INFO L754 eck$LassoCheckResult]: Loop: 17933#L309 assume !false; 17932#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17931#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17930#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17929#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17928#L276 assume 0 != eval_~tmp~0#1; 17927#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16162#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 16163#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16258#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 16275#L295 assume !(0 == ~t2_st~0); 17933#L309 [2022-07-14 16:03:39,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,241 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2022-07-14 16:03:39,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393762242] [2022-07-14 16:03:39,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:39,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:39,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:39,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393762242] [2022-07-14 16:03:39,271 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393762242] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:39,271 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:39,271 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:39,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691190412] [2022-07-14 16:03:39,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:39,272 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:39,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,272 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 1 times [2022-07-14 16:03:39,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129202660] [2022-07-14 16:03:39,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,277 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,279 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:39,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:39,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:39,368 INFO L87 Difference]: Start difference. First operand 1875 states and 2479 transitions. cyclomatic complexity: 609 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:39,379 INFO L93 Difference]: Finished difference Result 1701 states and 2255 transitions. [2022-07-14 16:03:39,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:39,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2255 transitions. [2022-07-14 16:03:39,390 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1655 [2022-07-14 16:03:39,398 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2255 transitions. [2022-07-14 16:03:39,398 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2022-07-14 16:03:39,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2022-07-14 16:03:39,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2255 transitions. [2022-07-14 16:03:39,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:39,402 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2255 transitions. [2022-07-14 16:03:39,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2255 transitions. [2022-07-14 16:03:39,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2022-07-14 16:03:39,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.3256907701352145) internal successors, (2255), 1700 states have internal predecessors, (2255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2255 transitions. [2022-07-14 16:03:39,457 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2255 transitions. [2022-07-14 16:03:39,457 INFO L374 stractBuchiCegarLoop]: Abstraction has 1701 states and 2255 transitions. [2022-07-14 16:03:39,457 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:03:39,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2255 transitions. [2022-07-14 16:03:39,462 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1655 [2022-07-14 16:03:39,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:39,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:39,462 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:39,463 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:39,463 INFO L752 eck$LassoCheckResult]: Stem: 19875#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 19840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19650#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19651#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19859#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 19742#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19715#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19716#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19701#L334 assume !(0 == ~M_E~0); 19702#L334-2 assume !(0 == ~T1_E~0); 19797#L339-1 assume !(0 == ~T2_E~0); 19790#L344-1 assume !(0 == ~E_1~0); 19791#L349-1 assume !(0 == ~E_2~0); 19713#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19714#L156 assume !(1 == ~m_pc~0); 19804#L156-2 is_master_triggered_~__retres1~0#1 := 0; 19824#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19814#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19764#L405 assume !(0 != activate_threads_~tmp~1#1); 19746#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19747#L175 assume !(1 == ~t1_pc~0); 19754#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19748#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19749#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19799#L413 assume !(0 != activate_threads_~tmp___0~0#1); 19800#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19862#L194 assume !(1 == ~t2_pc~0); 19789#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19758#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19703#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19690#L421 assume !(0 != activate_threads_~tmp___1~0#1); 19691#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19664#L367 assume !(1 == ~M_E~0); 19665#L367-2 assume !(1 == ~T1_E~0); 19818#L372-1 assume !(1 == ~T2_E~0); 19819#L377-1 assume !(1 == ~E_1~0); 19685#L382-1 assume !(1 == ~E_2~0); 19686#L387-1 assume { :end_inline_reset_delta_events } true; 19766#L528-2 assume !false; 21313#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21308#L309 [2022-07-14 16:03:39,463 INFO L754 eck$LassoCheckResult]: Loop: 21308#L309 assume !false; 21307#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21165#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21162#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21163#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21155#L276 assume 0 != eval_~tmp~0#1; 21156#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 19743#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 19744#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 19821#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 19834#L295 assume !(0 == ~t2_st~0); 21308#L309 [2022-07-14 16:03:39,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,463 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2022-07-14 16:03:39,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906377973] [2022-07-14 16:03:39,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,470 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,477 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,478 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 2 times [2022-07-14 16:03:39,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451477672] [2022-07-14 16:03:39,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,481 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,483 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,484 INFO L85 PathProgramCache]: Analyzing trace with hash 1252891474, now seen corresponding path program 1 times [2022-07-14 16:03:39,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141935802] [2022-07-14 16:03:39,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:39,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:39,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:39,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141935802] [2022-07-14 16:03:39,503 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141935802] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:39,503 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:39,503 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:39,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904697701] [2022-07-14 16:03:39,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:39,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:39,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:39,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:39,563 INFO L87 Difference]: Start difference. First operand 1701 states and 2255 transitions. cyclomatic complexity: 557 Second operand has 3 states, 2 states have (on average 25.5) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:39,598 INFO L93 Difference]: Finished difference Result 3003 states and 3954 transitions. [2022-07-14 16:03:39,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:39,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3003 states and 3954 transitions. [2022-07-14 16:03:39,612 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2952 [2022-07-14 16:03:39,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3003 states to 3003 states and 3954 transitions. [2022-07-14 16:03:39,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3003 [2022-07-14 16:03:39,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3003 [2022-07-14 16:03:39,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3003 states and 3954 transitions. [2022-07-14 16:03:39,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:39,630 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3003 states and 3954 transitions. [2022-07-14 16:03:39,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3003 states and 3954 transitions. [2022-07-14 16:03:39,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3003 to 3003. [2022-07-14 16:03:39,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3003 states, 3003 states have (on average 1.3166833166833167) internal successors, (3954), 3002 states have internal predecessors, (3954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:39,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3003 states to 3003 states and 3954 transitions. [2022-07-14 16:03:39,675 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3003 states and 3954 transitions. [2022-07-14 16:03:39,675 INFO L374 stractBuchiCegarLoop]: Abstraction has 3003 states and 3954 transitions. [2022-07-14 16:03:39,675 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:03:39,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3003 states and 3954 transitions. [2022-07-14 16:03:39,682 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2952 [2022-07-14 16:03:39,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:39,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:39,683 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:39,683 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:39,683 INFO L752 eck$LassoCheckResult]: Stem: 24597#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 24563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24362#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24363#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24584#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 24454#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24425#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24426#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24413#L334 assume !(0 == ~M_E~0); 24414#L334-2 assume !(0 == ~T1_E~0); 24515#L339-1 assume !(0 == ~T2_E~0); 24508#L344-1 assume !(0 == ~E_1~0); 24509#L349-1 assume !(0 == ~E_2~0); 24423#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24424#L156 assume !(1 == ~m_pc~0); 24522#L156-2 is_master_triggered_~__retres1~0#1 := 0; 24545#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24533#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24478#L405 assume !(0 != activate_threads_~tmp~1#1); 24459#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24460#L175 assume !(1 == ~t1_pc~0); 24468#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24461#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24462#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24517#L413 assume !(0 != activate_threads_~tmp___0~0#1); 24518#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24588#L194 assume !(1 == ~t2_pc~0); 24507#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24472#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24415#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24402#L421 assume !(0 != activate_threads_~tmp___1~0#1); 24403#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24376#L367 assume !(1 == ~M_E~0); 24377#L367-2 assume !(1 == ~T1_E~0); 24538#L372-1 assume !(1 == ~T2_E~0); 24539#L377-1 assume !(1 == ~E_1~0); 24397#L382-1 assume !(1 == ~E_2~0); 24398#L387-1 assume { :end_inline_reset_delta_events } true; 24481#L528-2 assume !false; 27319#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27184#L309 [2022-07-14 16:03:39,683 INFO L754 eck$LassoCheckResult]: Loop: 27184#L309 assume !false; 27314#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27313#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 27312#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27311#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27309#L276 assume 0 != eval_~tmp~0#1; 27291#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 24455#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 24457#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 27187#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 27185#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 26950#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 27184#L309 [2022-07-14 16:03:39,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,684 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2022-07-14 16:03:39,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697746112] [2022-07-14 16:03:39,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,690 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,696 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,696 INFO L85 PathProgramCache]: Analyzing trace with hash 747741784, now seen corresponding path program 1 times [2022-07-14 16:03:39,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858975855] [2022-07-14 16:03:39,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,699 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:39,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:39,702 INFO L85 PathProgramCache]: Analyzing trace with hash 184929274, now seen corresponding path program 1 times [2022-07-14 16:03:39,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:39,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70927671] [2022-07-14 16:03:39,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:39,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:39,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,708 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:39,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:39,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:40,419 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 14.07 04:03:40 BoogieIcfgContainer [2022-07-14 16:03:40,419 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-14 16:03:40,420 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-14 16:03:40,420 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-14 16:03:40,420 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-14 16:03:40,420 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:36" (3/4) ... [2022-07-14 16:03:40,422 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-14 16:03:40,465 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-14 16:03:40,466 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-14 16:03:40,466 INFO L158 Benchmark]: Toolchain (without parser) took 4740.29ms. Allocated memory was 144.7MB in the beginning and 174.1MB in the end (delta: 29.4MB). Free memory was 116.0MB in the beginning and 109.0MB in the end (delta: 7.0MB). Peak memory consumption was 36.7MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,466 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 88.1MB. Free memory was 45.6MB in the beginning and 45.5MB in the end (delta: 43.5kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-14 16:03:40,467 INFO L158 Benchmark]: CACSL2BoogieTranslator took 259.96ms. Allocated memory is still 144.7MB. Free memory was 115.6MB in the beginning and 118.6MB in the end (delta: -3.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,467 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.16ms. Allocated memory is still 144.7MB. Free memory was 118.6MB in the beginning and 115.9MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,467 INFO L158 Benchmark]: Boogie Preprocessor took 28.93ms. Allocated memory is still 144.7MB. Free memory was 115.9MB in the beginning and 113.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,467 INFO L158 Benchmark]: RCFGBuilder took 534.15ms. Allocated memory is still 144.7MB. Free memory was 113.8MB in the beginning and 91.7MB in the end (delta: 22.1MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,468 INFO L158 Benchmark]: BuchiAutomizer took 3818.35ms. Allocated memory was 144.7MB in the beginning and 174.1MB in the end (delta: 29.4MB). Free memory was 91.7MB in the beginning and 112.1MB in the end (delta: -20.4MB). Peak memory consumption was 79.6MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,468 INFO L158 Benchmark]: Witness Printer took 45.78ms. Allocated memory is still 174.1MB. Free memory was 112.1MB in the beginning and 109.0MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-07-14 16:03:40,469 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 88.1MB. Free memory was 45.6MB in the beginning and 45.5MB in the end (delta: 43.5kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 259.96ms. Allocated memory is still 144.7MB. Free memory was 115.6MB in the beginning and 118.6MB in the end (delta: -3.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.16ms. Allocated memory is still 144.7MB. Free memory was 118.6MB in the beginning and 115.9MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 28.93ms. Allocated memory is still 144.7MB. Free memory was 115.9MB in the beginning and 113.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 534.15ms. Allocated memory is still 144.7MB. Free memory was 113.8MB in the beginning and 91.7MB in the end (delta: 22.1MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 3818.35ms. Allocated memory was 144.7MB in the beginning and 174.1MB in the end (delta: 29.4MB). Free memory was 91.7MB in the beginning and 112.1MB in the end (delta: -20.4MB). Peak memory consumption was 79.6MB. Max. memory is 16.1GB. * Witness Printer took 45.78ms. Allocated memory is still 174.1MB. Free memory was 112.1MB in the beginning and 109.0MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3003 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.7s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 2.2s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 13 MinimizatonAttempts, 1574 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4699 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4699 mSDsluCounter, 7557 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3730 mSDsCounter, 123 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 321 IncrementalHoareTripleChecker+Invalid, 444 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 123 mSolverCounterUnsat, 3827 mSDtfsCounter, 321 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1014d808=0, NULL=1, \result=0, tmp=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4613f101=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@311cdf77=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@69fe91ae=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@686f8b26=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@528f735b=0, t1_pc=0, tmp_ndt_2=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@796ab3e9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@743582ca=0, E_1=2, __retres1=0, M_E=2, __retres1=1, tmp_ndt_1=0, t2_i=1, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f1edbb=0, \result=0, m_i=1, t1_st=0, __retres1=0, t2_pc=0, m_st=0, NULL=0, kernel_st=1, __retres1=0, tmp___0=0, t1_i=1, m_pc=0, \result=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_1 == 0) [L354] COND FALSE !(E_2 == 0) [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) [L372] COND FALSE !(T1_E == 1) [L377] COND FALSE !(T2_E == 1) [L382] COND FALSE !(E_1 == 1) [L387] COND FALSE !(E_2 == 1) [L525] RET reset_delta_events() [L528] COND TRUE 1 [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-14 16:03:40,515 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)