./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:03:40,412 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:03:40,416 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:03:40,450 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:03:40,451 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:03:40,452 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:03:40,453 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:03:40,455 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:03:40,456 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:03:40,460 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:03:40,460 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:03:40,462 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:03:40,462 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:03:40,464 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:03:40,465 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:03:40,467 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:03:40,468 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:03:40,469 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:03:40,470 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:03:40,474 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:03:40,475 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:03:40,476 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:03:40,477 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:03:40,477 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:03:40,478 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:03:40,483 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:03:40,484 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:03:40,484 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:03:40,485 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:03:40,485 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:03:40,486 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:03:40,486 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:03:40,487 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:03:40,488 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:03:40,488 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:03:40,489 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:03:40,490 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:03:40,490 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:03:40,490 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:03:40,490 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:03:40,491 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:03:40,492 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:03:40,493 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:03:40,516 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:03:40,517 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:03:40,517 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:03:40,517 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:03:40,518 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:03:40,519 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:03:40,519 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:03:40,519 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:03:40,519 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:03:40,520 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:03:40,520 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:03:40,520 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:03:40,520 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:03:40,520 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:03:40,520 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:03:40,521 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:03:40,522 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:03:40,522 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:03:40,522 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:03:40,522 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:03:40,522 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:03:40,522 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:03:40,523 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:03:40,523 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:03:40,523 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:03:40,524 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:03:40,524 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2022-07-14 16:03:40,713 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:03:40,726 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:03:40,730 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:03:40,731 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:03:40,732 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:03:40,733 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.06.cil.c [2022-07-14 16:03:40,793 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4f260d3b3/1e2f51a397724f5c81d7f035fc468cf1/FLAGcacdee02c [2022-07-14 16:03:41,160 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:03:41,161 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c [2022-07-14 16:03:41,175 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4f260d3b3/1e2f51a397724f5c81d7f035fc468cf1/FLAGcacdee02c [2022-07-14 16:03:41,186 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4f260d3b3/1e2f51a397724f5c81d7f035fc468cf1 [2022-07-14 16:03:41,189 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:03:41,190 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:03:41,191 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:41,191 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:03:41,196 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:03:41,196 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,197 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e18be01 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41, skipping insertion in model container [2022-07-14 16:03:41,197 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,202 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:03:41,226 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:03:41,342 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2022-07-14 16:03:41,392 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:41,406 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:03:41,421 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2022-07-14 16:03:41,469 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:03:41,490 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:03:41,491 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41 WrapperNode [2022-07-14 16:03:41,491 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:03:41,492 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:41,493 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:03:41,493 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:03:41,498 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,511 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,552 INFO L137 Inliner]: procedures = 40, calls = 48, calls flagged for inlining = 43, calls inlined = 104, statements flattened = 1522 [2022-07-14 16:03:41,553 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:03:41,553 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:03:41,554 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:03:41,554 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:03:41,560 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,560 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,564 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,564 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,576 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,600 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,604 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,615 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:03:41,628 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:03:41,628 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:03:41,628 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:03:41,629 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (1/1) ... [2022-07-14 16:03:41,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:03:41,644 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:03:41,655 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:03:41,661 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:03:41,689 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:03:41,689 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:03:41,690 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:03:41,690 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:03:41,783 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:03:41,784 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:03:42,403 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:03:42,412 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:03:42,413 INFO L299 CfgBuilder]: Removed 10 assume(true) statements. [2022-07-14 16:03:42,414 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:42 BoogieIcfgContainer [2022-07-14 16:03:42,415 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:03:42,415 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:03:42,416 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:03:42,418 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:03:42,418 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:42,418 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:03:41" (1/3) ... [2022-07-14 16:03:42,419 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@22cc6c97 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:42, skipping insertion in model container [2022-07-14 16:03:42,419 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:42,419 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:03:41" (2/3) ... [2022-07-14 16:03:42,420 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@22cc6c97 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:03:42, skipping insertion in model container [2022-07-14 16:03:42,420 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:03:42,420 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:42" (3/3) ... [2022-07-14 16:03:42,421 INFO L354 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2022-07-14 16:03:42,468 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:03:42,468 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:03:42,468 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:03:42,469 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:03:42,469 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:03:42,469 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:03:42,469 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:03:42,470 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:03:42,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:42,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2022-07-14 16:03:42,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:42,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:42,530 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:42,530 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:42,531 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:03:42,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:42,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2022-07-14 16:03:42,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:42,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:42,550 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:42,550 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:42,556 INFO L752 eck$LassoCheckResult]: Stem: 624#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 512#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 413#L987true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4#L454true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 339#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 554#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 609#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 44#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 271#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 129#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 53#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 524#L670true assume !(0 == ~M_E~0); 300#L670-2true assume !(0 == ~T1_E~0); 250#L675-1true assume !(0 == ~T2_E~0); 337#L680-1true assume !(0 == ~T3_E~0); 431#L685-1true assume !(0 == ~T4_E~0); 305#L690-1true assume !(0 == ~T5_E~0); 608#L695-1true assume !(0 == ~T6_E~0); 383#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 372#L705-1true assume !(0 == ~E_2~0); 546#L710-1true assume !(0 == ~E_3~0); 248#L715-1true assume !(0 == ~E_4~0); 191#L720-1true assume !(0 == ~E_5~0); 233#L725-1true assume !(0 == ~E_6~0); 274#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 404#L320true assume 1 == ~m_pc~0; 221#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 152#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 497#L332true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 130#L825true assume !(0 != activate_threads_~tmp~1#1); 446#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133#L339true assume !(1 == ~t1_pc~0); 419#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 120#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387#L351true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56#L833true assume !(0 != activate_threads_~tmp___0~0#1); 536#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13#L358true assume 1 == ~t2_pc~0; 587#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 510#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 302#L370true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 237#L841true assume !(0 != activate_threads_~tmp___1~0#1); 127#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 451#L377true assume !(1 == ~t3_pc~0); 319#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 329#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 316#L389true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132#L849true assume !(0 != activate_threads_~tmp___2~0#1); 334#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100#L396true assume 1 == ~t4_pc~0; 442#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 606#L408true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 262#L857true assume !(0 != activate_threads_~tmp___3~0#1); 84#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121#L415true assume 1 == ~t5_pc~0; 323#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 275#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 582#L427true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 422#L865true assume !(0 != activate_threads_~tmp___4~0#1); 34#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 320#L434true assume !(1 == ~t6_pc~0); 213#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 350#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 603#L446true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 351#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138#L873-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 534#L743true assume !(1 == ~M_E~0); 79#L743-2true assume !(1 == ~T1_E~0); 483#L748-1true assume !(1 == ~T2_E~0); 267#L753-1true assume !(1 == ~T3_E~0); 388#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 457#L763-1true assume !(1 == ~T5_E~0); 551#L768-1true assume !(1 == ~T6_E~0); 135#L773-1true assume !(1 == ~E_1~0); 622#L778-1true assume !(1 == ~E_2~0); 125#L783-1true assume !(1 == ~E_3~0); 596#L788-1true assume !(1 == ~E_4~0); 335#L793-1true assume !(1 == ~E_5~0); 292#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 64#L803-1true assume { :end_inline_reset_delta_events } true; 242#L1024-2true [2022-07-14 16:03:42,557 INFO L754 eck$LassoCheckResult]: Loop: 242#L1024-2true assume !false; 470#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L645true assume false; 588#L660true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 366#L454-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 227#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 149#L675-3true assume !(0 == ~T2_E~0); 425#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 332#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 602#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 557#L695-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 345#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 631#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 92#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 378#L715-3true assume !(0 == ~E_4~0); 239#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 306#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 494#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136#L320-21true assume 1 == ~m_pc~0; 455#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 529#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184#L332-7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 472#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 440#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98#L339-21true assume 1 == ~t1_pc~0; 157#L340-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 619#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85#L351-7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 579#L358-21true assume 1 == ~t2_pc~0; 134#L359-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241#L370-7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 394#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 463#L377-21true assume 1 == ~t3_pc~0; 560#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 261#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 356#L389-7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 280#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 166#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293#L396-21true assume !(1 == ~t4_pc~0); 183#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 222#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164#L408-7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17#L857-21true assume !(0 != activate_threads_~tmp___3~0#1); 296#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150#L415-21true assume 1 == ~t5_pc~0; 506#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 424#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76#L427-7true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 218#L865-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 194#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 373#L434-21true assume 1 == ~t6_pc~0; 200#L435-7true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 418#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 430#L446-7true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 146#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 255#L873-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 490#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 553#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 256#L753-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 208#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 160#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 521#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 464#L773-3true assume !(1 == ~E_1~0); 111#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 259#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 570#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 515#L793-3true assume 1 == ~E_5~0;~E_5~0 := 2; 528#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 298#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 106#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 390#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 202#L542-1true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 433#L1043true assume !(0 == start_simulation_~tmp~3#1); 428#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 257#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 322#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 235#L542-2true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 225#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 139#L1006true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 217#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 242#L1024-2true [2022-07-14 16:03:42,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:42,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2022-07-14 16:03:42,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:42,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944320622] [2022-07-14 16:03:42,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:42,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:42,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:42,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:42,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:42,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944320622] [2022-07-14 16:03:42,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944320622] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:42,717 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:42,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:42,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47047089] [2022-07-14 16:03:42,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:42,729 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:42,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:42,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1304949083, now seen corresponding path program 1 times [2022-07-14 16:03:42,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:42,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314796202] [2022-07-14 16:03:42,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:42,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:42,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:42,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:42,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:42,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314796202] [2022-07-14 16:03:42,780 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314796202] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:42,780 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:42,780 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:42,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372305655] [2022-07-14 16:03:42,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:42,781 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:42,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:42,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:42,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:42,809 INFO L87 Difference]: Start difference. First operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:42,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:42,853 INFO L93 Difference]: Finished difference Result 632 states and 943 transitions. [2022-07-14 16:03:42,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:42,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 632 states and 943 transitions. [2022-07-14 16:03:42,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:42,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 632 states to 626 states and 937 transitions. [2022-07-14 16:03:42,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-07-14 16:03:42,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-07-14 16:03:42,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 937 transitions. [2022-07-14 16:03:42,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:42,877 INFO L369 hiAutomatonCegarLoop]: Abstraction has 626 states and 937 transitions. [2022-07-14 16:03:42,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 937 transitions. [2022-07-14 16:03:42,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-07-14 16:03:42,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:42,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 937 transitions. [2022-07-14 16:03:42,914 INFO L392 hiAutomatonCegarLoop]: Abstraction has 626 states and 937 transitions. [2022-07-14 16:03:42,914 INFO L374 stractBuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2022-07-14 16:03:42,914 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:03:42,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 937 transitions. [2022-07-14 16:03:42,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:42,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:42,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:42,922 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:42,922 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:42,923 INFO L752 eck$LassoCheckResult]: Stem: 1899#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1834#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1278#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1274#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1275#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1790#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1893#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1370#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1371#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1523#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1387#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1388#L670 assume !(0 == ~M_E~0); 1758#L670-2 assume !(0 == ~T1_E~0); 1706#L675-1 assume !(0 == ~T2_E~0); 1707#L680-1 assume !(0 == ~T3_E~0); 1788#L685-1 assume !(0 == ~T4_E~0); 1761#L690-1 assume !(0 == ~T5_E~0); 1762#L695-1 assume !(0 == ~T6_E~0); 1820#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1812#L705-1 assume !(0 == ~E_2~0); 1813#L710-1 assume !(0 == ~E_3~0); 1705#L715-1 assume !(0 == ~E_4~0); 1629#L720-1 assume !(0 == ~E_5~0); 1630#L725-1 assume !(0 == ~E_6~0); 1683#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1730#L320 assume 1 == ~m_pc~0; 1671#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1565#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1566#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1524#L825 assume !(0 != activate_threads_~tmp~1#1); 1525#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1530#L339 assume !(1 == ~t1_pc~0); 1531#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1508#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1509#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1390#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1391#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1299#L358 assume 1 == ~t2_pc~0; 1300#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1808#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1759#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1687#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1521#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1522#L377 assume !(1 == ~t3_pc~0); 1774#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1775#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1528#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1529#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1474#L396 assume 1 == ~t4_pc~0; 1475#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1302#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1303#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1721#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1443#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1444#L415 assume 1 == ~t5_pc~0; 1510#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1555#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1731#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1838#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1345#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1346#L434 assume !(1 == ~t6_pc~0); 1660#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1661#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1800#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1801#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1541#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1542#L743 assume !(1 == ~M_E~0); 1435#L743-2 assume !(1 == ~T1_E~0); 1436#L748-1 assume !(1 == ~T2_E~0); 1724#L753-1 assume !(1 == ~T3_E~0); 1725#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1824#L763-1 assume !(1 == ~T5_E~0); 1856#L768-1 assume !(1 == ~T6_E~0); 1536#L773-1 assume !(1 == ~E_1~0); 1537#L778-1 assume !(1 == ~E_2~0); 1516#L783-1 assume !(1 == ~E_3~0); 1517#L788-1 assume !(1 == ~E_4~0); 1786#L793-1 assume !(1 == ~E_5~0); 1751#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1407#L803-1 assume { :end_inline_reset_delta_events } true; 1408#L1024-2 [2022-07-14 16:03:42,923 INFO L754 eck$LassoCheckResult]: Loop: 1408#L1024-2 assume !false; 1693#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1748#L645 assume !false; 1625#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1626#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1353#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1830#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1863#L556 assume !(0 != eval_~tmp~0#1); 1897#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1807#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1402#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1562#L675-3 assume !(0 == ~T2_E~0); 1563#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1783#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1784#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1894#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1794#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1795#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1456#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1457#L715-3 assume !(0 == ~E_4~0); 1688#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1689#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1763#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1538#L320-21 assume 1 == ~m_pc~0; 1539#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1686#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1612#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1613#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1848#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1469#L339-21 assume !(1 == ~t1_pc~0); 1470#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1573#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1445#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1327#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1328#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1427#L358-21 assume !(1 == ~t2_pc~0); 1481#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1409#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1410#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1692#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1446#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1447#L377-21 assume 1 == ~t3_pc~0; 1859#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1718#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1719#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1739#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1584#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1585#L396-21 assume 1 == ~t4_pc~0; 1752#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1611#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1582#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1309#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 1310#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L415-21 assume 1 == ~t5_pc~0; 1561#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1535#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1632#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633#L434-21 assume !(1 == ~t6_pc~0); 1332#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1333#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1835#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1556#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1557#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1551#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1552#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1872#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1714#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1652#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1575#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1576#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1860#L773-3 assume !(1 == ~E_1~0); 1494#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1717#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1884#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1885#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1756#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1485#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1381#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1645#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1646#L1043 assume !(0 == start_simulation_~tmp~3#1); 1839#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1715#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1684#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1673#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1395#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1396#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1543#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1408#L1024-2 [2022-07-14 16:03:42,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:42,924 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2022-07-14 16:03:42,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:42,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105317469] [2022-07-14 16:03:42,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:42,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:42,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:42,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:42,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:42,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [105317469] [2022-07-14 16:03:42,988 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [105317469] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:42,988 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:42,989 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:42,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721405245] [2022-07-14 16:03:42,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:42,989 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:42,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:42,990 INFO L85 PathProgramCache]: Analyzing trace with hash 2030983010, now seen corresponding path program 1 times [2022-07-14 16:03:42,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:42,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707142351] [2022-07-14 16:03:42,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:42,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707142351] [2022-07-14 16:03:43,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707142351] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,059 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,059 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927969722] [2022-07-14 16:03:43,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,060 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:43,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:43,061 INFO L87 Difference]: Start difference. First operand 626 states and 937 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,079 INFO L93 Difference]: Finished difference Result 626 states and 936 transitions. [2022-07-14 16:03:43,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:43,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 936 transitions. [2022-07-14 16:03:43,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 936 transitions. [2022-07-14 16:03:43,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-07-14 16:03:43,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-07-14 16:03:43,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 936 transitions. [2022-07-14 16:03:43,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,100 INFO L369 hiAutomatonCegarLoop]: Abstraction has 626 states and 936 transitions. [2022-07-14 16:03:43,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 936 transitions. [2022-07-14 16:03:43,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-07-14 16:03:43,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 936 transitions. [2022-07-14 16:03:43,119 INFO L392 hiAutomatonCegarLoop]: Abstraction has 626 states and 936 transitions. [2022-07-14 16:03:43,120 INFO L374 stractBuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2022-07-14 16:03:43,120 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:03:43,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 936 transitions. [2022-07-14 16:03:43,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,125 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,126 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,127 INFO L752 eck$LassoCheckResult]: Stem: 3158#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 3141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3093#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2537#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2533#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2534#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3049#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3152#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2629#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2630#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2782#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2647#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2648#L670 assume !(0 == ~M_E~0); 3017#L670-2 assume !(0 == ~T1_E~0); 2965#L675-1 assume !(0 == ~T2_E~0); 2966#L680-1 assume !(0 == ~T3_E~0); 3047#L685-1 assume !(0 == ~T4_E~0); 3021#L690-1 assume !(0 == ~T5_E~0); 3022#L695-1 assume !(0 == ~T6_E~0); 3079#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3071#L705-1 assume !(0 == ~E_2~0); 3072#L710-1 assume !(0 == ~E_3~0); 2964#L715-1 assume !(0 == ~E_4~0); 2888#L720-1 assume !(0 == ~E_5~0); 2889#L725-1 assume !(0 == ~E_6~0); 2942#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2989#L320 assume 1 == ~m_pc~0; 2930#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2824#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2825#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2783#L825 assume !(0 != activate_threads_~tmp~1#1); 2784#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2790#L339 assume !(1 == ~t1_pc~0); 2791#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2767#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2768#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2649#L833 assume !(0 != activate_threads_~tmp___0~0#1); 2650#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2558#L358 assume 1 == ~t2_pc~0; 2559#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3067#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3018#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2946#L841 assume !(0 != activate_threads_~tmp___1~0#1); 2780#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2781#L377 assume !(1 == ~t3_pc~0); 3033#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3034#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3029#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2787#L849 assume !(0 != activate_threads_~tmp___2~0#1); 2788#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2735#L396 assume 1 == ~t4_pc~0; 2736#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2561#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2562#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2980#L857 assume !(0 != activate_threads_~tmp___3~0#1); 2702#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2703#L415 assume 1 == ~t5_pc~0; 2770#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2814#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2990#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3097#L865 assume !(0 != activate_threads_~tmp___4~0#1); 2604#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2605#L434 assume !(1 == ~t6_pc~0); 2920#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2921#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3059#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3060#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2800#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L743 assume !(1 == ~M_E~0); 2694#L743-2 assume !(1 == ~T1_E~0); 2695#L748-1 assume !(1 == ~T2_E~0); 2984#L753-1 assume !(1 == ~T3_E~0); 2985#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3083#L763-1 assume !(1 == ~T5_E~0); 3115#L768-1 assume !(1 == ~T6_E~0); 2798#L773-1 assume !(1 == ~E_1~0); 2799#L778-1 assume !(1 == ~E_2~0); 2775#L783-1 assume !(1 == ~E_3~0); 2776#L788-1 assume !(1 == ~E_4~0); 3045#L793-1 assume !(1 == ~E_5~0); 3010#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2668#L803-1 assume { :end_inline_reset_delta_events } true; 2669#L1024-2 [2022-07-14 16:03:43,131 INFO L754 eck$LassoCheckResult]: Loop: 2669#L1024-2 assume !false; 2952#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3007#L645 assume !false; 2884#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2885#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2612#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3089#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3124#L556 assume !(0 != eval_~tmp~0#1); 3156#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3066#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2662#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2663#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2821#L675-3 assume !(0 == ~T2_E~0); 2822#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3042#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3043#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3153#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3051#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3052#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2715#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2716#L715-3 assume !(0 == ~E_4~0); 2947#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2948#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3020#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2793#L320-21 assume 1 == ~m_pc~0; 2794#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2945#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2871#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2872#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3106#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2728#L339-21 assume !(1 == ~t1_pc~0); 2729#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 2832#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2586#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2587#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2686#L358-21 assume !(1 == ~t2_pc~0); 2740#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 2666#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2667#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2951#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2705#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2706#L377-21 assume !(1 == ~t3_pc~0); 3062#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2977#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2978#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2998#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2843#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2844#L396-21 assume 1 == ~t4_pc~0; 3011#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2870#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2841#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2568#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 2569#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2819#L415-21 assume 1 == ~t5_pc~0; 2820#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2797#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2690#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2691#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2891#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2892#L434-21 assume !(1 == ~t6_pc~0); 2593#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 2594#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3095#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2815#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2816#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2810#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2811#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3131#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2973#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2911#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2834#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2835#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3119#L773-3 assume !(1 == ~E_1~0); 2753#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2754#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2976#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3143#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3144#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3016#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2744#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2640#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2904#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2905#L1043 assume !(0 == start_simulation_~tmp~3#1); 3098#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2974#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2761#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2944#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2932#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2654#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2655#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2802#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 2669#L1024-2 [2022-07-14 16:03:43,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,132 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2022-07-14 16:03:43,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724675922] [2022-07-14 16:03:43,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724675922] [2022-07-14 16:03:43,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724675922] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891949966] [2022-07-14 16:03:43,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,178 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:43,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,179 INFO L85 PathProgramCache]: Analyzing trace with hash 300645953, now seen corresponding path program 1 times [2022-07-14 16:03:43,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261046427] [2022-07-14 16:03:43,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261046427] [2022-07-14 16:03:43,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261046427] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,258 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,258 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816459140] [2022-07-14 16:03:43,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,259 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:43,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:43,260 INFO L87 Difference]: Start difference. First operand 626 states and 936 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,270 INFO L93 Difference]: Finished difference Result 626 states and 935 transitions. [2022-07-14 16:03:43,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:43,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 935 transitions. [2022-07-14 16:03:43,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 935 transitions. [2022-07-14 16:03:43,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-07-14 16:03:43,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-07-14 16:03:43,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 935 transitions. [2022-07-14 16:03:43,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,278 INFO L369 hiAutomatonCegarLoop]: Abstraction has 626 states and 935 transitions. [2022-07-14 16:03:43,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 935 transitions. [2022-07-14 16:03:43,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-07-14 16:03:43,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 935 transitions. [2022-07-14 16:03:43,287 INFO L392 hiAutomatonCegarLoop]: Abstraction has 626 states and 935 transitions. [2022-07-14 16:03:43,287 INFO L374 stractBuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2022-07-14 16:03:43,287 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:03:43,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 935 transitions. [2022-07-14 16:03:43,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,294 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,295 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,295 INFO L752 eck$LassoCheckResult]: Stem: 4417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4352#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3796#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3792#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3793#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4307#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4411#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3886#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3887#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4041#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3905#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3906#L670 assume !(0 == ~M_E~0); 4276#L670-2 assume !(0 == ~T1_E~0); 4224#L675-1 assume !(0 == ~T2_E~0); 4225#L680-1 assume !(0 == ~T3_E~0); 4306#L685-1 assume !(0 == ~T4_E~0); 4279#L690-1 assume !(0 == ~T5_E~0); 4280#L695-1 assume !(0 == ~T6_E~0); 4338#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4330#L705-1 assume !(0 == ~E_2~0); 4331#L710-1 assume !(0 == ~E_3~0); 4222#L715-1 assume !(0 == ~E_4~0); 4145#L720-1 assume !(0 == ~E_5~0); 4146#L725-1 assume !(0 == ~E_6~0); 4201#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4248#L320 assume 1 == ~m_pc~0; 4189#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4083#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4084#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4042#L825 assume !(0 != activate_threads_~tmp~1#1); 4043#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4048#L339 assume !(1 == ~t1_pc~0); 4049#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4026#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4027#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3908#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3909#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3817#L358 assume 1 == ~t2_pc~0; 3818#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4326#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4277#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4205#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4037#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4038#L377 assume !(1 == ~t3_pc~0); 4292#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4293#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4288#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4046#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4047#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3992#L396 assume 1 == ~t4_pc~0; 3993#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3820#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3821#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4239#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3961#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3962#L415 assume 1 == ~t5_pc~0; 4028#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4071#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4249#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4356#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3863#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3864#L434 assume !(1 == ~t6_pc~0); 4178#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4179#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4318#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4319#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4059#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4060#L743 assume !(1 == ~M_E~0); 3953#L743-2 assume !(1 == ~T1_E~0); 3954#L748-1 assume !(1 == ~T2_E~0); 4242#L753-1 assume !(1 == ~T3_E~0); 4243#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4342#L763-1 assume !(1 == ~T5_E~0); 4374#L768-1 assume !(1 == ~T6_E~0); 4052#L773-1 assume !(1 == ~E_1~0); 4053#L778-1 assume !(1 == ~E_2~0); 4034#L783-1 assume !(1 == ~E_3~0); 4035#L788-1 assume !(1 == ~E_4~0); 4304#L793-1 assume !(1 == ~E_5~0); 4269#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3925#L803-1 assume { :end_inline_reset_delta_events } true; 3926#L1024-2 [2022-07-14 16:03:43,295 INFO L754 eck$LassoCheckResult]: Loop: 3926#L1024-2 assume !false; 4211#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4266#L645 assume !false; 4143#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4144#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3871#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4348#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4381#L556 assume !(0 != eval_~tmp~0#1); 4415#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4325#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3917#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3918#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4078#L675-3 assume !(0 == ~T2_E~0); 4079#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4301#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4302#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4412#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4310#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4311#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3974#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3975#L715-3 assume !(0 == ~E_4~0); 4206#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4207#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4281#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4054#L320-21 assume 1 == ~m_pc~0; 4055#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4204#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4130#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4131#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4365#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3987#L339-21 assume !(1 == ~t1_pc~0); 3988#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 4091#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3963#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3845#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3846#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3945#L358-21 assume 1 == ~t2_pc~0; 4051#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3927#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3928#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4210#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3964#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3965#L377-21 assume !(1 == ~t3_pc~0); 4321#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 4237#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4238#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4257#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4102#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4103#L396-21 assume !(1 == ~t4_pc~0); 4128#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4129#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4100#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3827#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 3828#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4080#L415-21 assume 1 == ~t5_pc~0; 4081#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4058#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3949#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3950#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4150#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4151#L434-21 assume 1 == ~t6_pc~0; 4162#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3853#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4354#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4074#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4075#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4070#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4390#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4232#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4170#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4093#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4094#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4378#L773-3 assume !(1 == ~E_1~0); 4012#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4013#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4235#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4402#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4403#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4275#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4003#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3899#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4163#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4164#L1043 assume !(0 == start_simulation_~tmp~3#1); 4357#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4233#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4021#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4203#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4191#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3913#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3914#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4061#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3926#L1024-2 [2022-07-14 16:03:43,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,296 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2022-07-14 16:03:43,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,296 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524214667] [2022-07-14 16:03:43,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524214667] [2022-07-14 16:03:43,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524214667] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,348 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,348 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766772525] [2022-07-14 16:03:43,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,349 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:43,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,350 INFO L85 PathProgramCache]: Analyzing trace with hash -1901181918, now seen corresponding path program 1 times [2022-07-14 16:03:43,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063561860] [2022-07-14 16:03:43,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063561860] [2022-07-14 16:03:43,402 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063561860] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,403 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,403 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997233119] [2022-07-14 16:03:43,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,404 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:43,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:43,405 INFO L87 Difference]: Start difference. First operand 626 states and 935 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,416 INFO L93 Difference]: Finished difference Result 626 states and 934 transitions. [2022-07-14 16:03:43,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:43,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 934 transitions. [2022-07-14 16:03:43,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 934 transitions. [2022-07-14 16:03:43,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-07-14 16:03:43,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-07-14 16:03:43,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 934 transitions. [2022-07-14 16:03:43,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,424 INFO L369 hiAutomatonCegarLoop]: Abstraction has 626 states and 934 transitions. [2022-07-14 16:03:43,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 934 transitions. [2022-07-14 16:03:43,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-07-14 16:03:43,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 934 transitions. [2022-07-14 16:03:43,442 INFO L392 hiAutomatonCegarLoop]: Abstraction has 626 states and 934 transitions. [2022-07-14 16:03:43,442 INFO L374 stractBuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2022-07-14 16:03:43,442 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:03:43,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 934 transitions. [2022-07-14 16:03:43,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,445 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,445 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,445 INFO L752 eck$LassoCheckResult]: Stem: 5676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5611#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5055#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5051#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5052#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5566#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5670#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5145#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5146#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5300#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5164#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5165#L670 assume !(0 == ~M_E~0); 5535#L670-2 assume !(0 == ~T1_E~0); 5483#L675-1 assume !(0 == ~T2_E~0); 5484#L680-1 assume !(0 == ~T3_E~0); 5565#L685-1 assume !(0 == ~T4_E~0); 5538#L690-1 assume !(0 == ~T5_E~0); 5539#L695-1 assume !(0 == ~T6_E~0); 5597#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5589#L705-1 assume !(0 == ~E_2~0); 5590#L710-1 assume !(0 == ~E_3~0); 5481#L715-1 assume !(0 == ~E_4~0); 5404#L720-1 assume !(0 == ~E_5~0); 5405#L725-1 assume !(0 == ~E_6~0); 5460#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5507#L320 assume 1 == ~m_pc~0; 5448#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5342#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5343#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5301#L825 assume !(0 != activate_threads_~tmp~1#1); 5302#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5307#L339 assume !(1 == ~t1_pc~0); 5308#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5285#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5286#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5167#L833 assume !(0 != activate_threads_~tmp___0~0#1); 5168#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5076#L358 assume 1 == ~t2_pc~0; 5077#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5585#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5536#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5464#L841 assume !(0 != activate_threads_~tmp___1~0#1); 5296#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5297#L377 assume !(1 == ~t3_pc~0); 5551#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5552#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5547#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5305#L849 assume !(0 != activate_threads_~tmp___2~0#1); 5306#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5251#L396 assume 1 == ~t4_pc~0; 5252#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5079#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5080#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5498#L857 assume !(0 != activate_threads_~tmp___3~0#1); 5220#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5221#L415 assume 1 == ~t5_pc~0; 5287#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5330#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5508#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5615#L865 assume !(0 != activate_threads_~tmp___4~0#1); 5122#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5123#L434 assume !(1 == ~t6_pc~0); 5437#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5438#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5577#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5578#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5318#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5319#L743 assume !(1 == ~M_E~0); 5212#L743-2 assume !(1 == ~T1_E~0); 5213#L748-1 assume !(1 == ~T2_E~0); 5501#L753-1 assume !(1 == ~T3_E~0); 5502#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5601#L763-1 assume !(1 == ~T5_E~0); 5633#L768-1 assume !(1 == ~T6_E~0); 5311#L773-1 assume !(1 == ~E_1~0); 5312#L778-1 assume !(1 == ~E_2~0); 5293#L783-1 assume !(1 == ~E_3~0); 5294#L788-1 assume !(1 == ~E_4~0); 5563#L793-1 assume !(1 == ~E_5~0); 5528#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5184#L803-1 assume { :end_inline_reset_delta_events } true; 5185#L1024-2 [2022-07-14 16:03:43,446 INFO L754 eck$LassoCheckResult]: Loop: 5185#L1024-2 assume !false; 5470#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5525#L645 assume !false; 5402#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5403#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5130#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5607#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5640#L556 assume !(0 != eval_~tmp~0#1); 5674#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5584#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5176#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5177#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5337#L675-3 assume !(0 == ~T2_E~0); 5338#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5560#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5561#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5671#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5569#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5570#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5233#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5234#L715-3 assume !(0 == ~E_4~0); 5465#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5466#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5540#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5313#L320-21 assume 1 == ~m_pc~0; 5314#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5463#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5389#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5390#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5624#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5246#L339-21 assume 1 == ~t1_pc~0; 5248#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5350#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5222#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5104#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5105#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5204#L358-21 assume !(1 == ~t2_pc~0); 5258#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 5186#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5187#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5469#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5223#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5224#L377-21 assume 1 == ~t3_pc~0; 5636#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5496#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5497#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5516#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5361#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5362#L396-21 assume 1 == ~t4_pc~0; 5529#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5359#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5086#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 5087#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5339#L415-21 assume !(1 == ~t5_pc~0); 5316#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5317#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5208#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5209#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5409#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5410#L434-21 assume !(1 == ~t6_pc~0); 5111#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 5112#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5613#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5333#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5334#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5328#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5329#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5649#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5491#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5429#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5352#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5353#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5637#L773-3 assume !(1 == ~E_1~0); 5271#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5272#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5494#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5661#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5662#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5534#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5262#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5158#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5422#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5423#L1043 assume !(0 == start_simulation_~tmp~3#1); 5616#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5492#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5280#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5462#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5450#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5172#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5173#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5320#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5185#L1024-2 [2022-07-14 16:03:43,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,446 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2022-07-14 16:03:43,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324139825] [2022-07-14 16:03:43,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324139825] [2022-07-14 16:03:43,475 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324139825] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,475 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,475 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736173083] [2022-07-14 16:03:43,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,476 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:43,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,476 INFO L85 PathProgramCache]: Analyzing trace with hash 734577762, now seen corresponding path program 1 times [2022-07-14 16:03:43,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,476 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848683963] [2022-07-14 16:03:43,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848683963] [2022-07-14 16:03:43,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848683963] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252094197] [2022-07-14 16:03:43,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,500 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:43,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:43,501 INFO L87 Difference]: Start difference. First operand 626 states and 934 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,510 INFO L93 Difference]: Finished difference Result 626 states and 933 transitions. [2022-07-14 16:03:43,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:43,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 933 transitions. [2022-07-14 16:03:43,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 933 transitions. [2022-07-14 16:03:43,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-07-14 16:03:43,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-07-14 16:03:43,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 933 transitions. [2022-07-14 16:03:43,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,518 INFO L369 hiAutomatonCegarLoop]: Abstraction has 626 states and 933 transitions. [2022-07-14 16:03:43,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 933 transitions. [2022-07-14 16:03:43,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-07-14 16:03:43,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 933 transitions. [2022-07-14 16:03:43,525 INFO L392 hiAutomatonCegarLoop]: Abstraction has 626 states and 933 transitions. [2022-07-14 16:03:43,525 INFO L374 stractBuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2022-07-14 16:03:43,526 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:03:43,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 933 transitions. [2022-07-14 16:03:43,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,528 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,528 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,529 INFO L752 eck$LassoCheckResult]: Stem: 6935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6870#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6314#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6310#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6311#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6826#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6929#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6404#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6405#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6559#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6423#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6424#L670 assume !(0 == ~M_E~0); 6794#L670-2 assume !(0 == ~T1_E~0); 6742#L675-1 assume !(0 == ~T2_E~0); 6743#L680-1 assume !(0 == ~T3_E~0); 6824#L685-1 assume !(0 == ~T4_E~0); 6797#L690-1 assume !(0 == ~T5_E~0); 6798#L695-1 assume !(0 == ~T6_E~0); 6856#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6848#L705-1 assume !(0 == ~E_2~0); 6849#L710-1 assume !(0 == ~E_3~0); 6740#L715-1 assume !(0 == ~E_4~0); 6663#L720-1 assume !(0 == ~E_5~0); 6664#L725-1 assume !(0 == ~E_6~0); 6719#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6766#L320 assume 1 == ~m_pc~0; 6707#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6601#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6602#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6560#L825 assume !(0 != activate_threads_~tmp~1#1); 6561#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6566#L339 assume !(1 == ~t1_pc~0); 6567#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6544#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6545#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6426#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6427#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6335#L358 assume 1 == ~t2_pc~0; 6336#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6844#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6795#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6723#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6557#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6558#L377 assume !(1 == ~t3_pc~0); 6810#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6811#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6806#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6564#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6565#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6510#L396 assume 1 == ~t4_pc~0; 6511#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6338#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6339#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6757#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6479#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6480#L415 assume 1 == ~t5_pc~0; 6546#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6591#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6767#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6874#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6381#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6382#L434 assume !(1 == ~t6_pc~0); 6696#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6697#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6836#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6837#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6577#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6578#L743 assume !(1 == ~M_E~0); 6471#L743-2 assume !(1 == ~T1_E~0); 6472#L748-1 assume !(1 == ~T2_E~0); 6760#L753-1 assume !(1 == ~T3_E~0); 6761#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6860#L763-1 assume !(1 == ~T5_E~0); 6892#L768-1 assume !(1 == ~T6_E~0); 6572#L773-1 assume !(1 == ~E_1~0); 6573#L778-1 assume !(1 == ~E_2~0); 6552#L783-1 assume !(1 == ~E_3~0); 6553#L788-1 assume !(1 == ~E_4~0); 6822#L793-1 assume !(1 == ~E_5~0); 6787#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6443#L803-1 assume { :end_inline_reset_delta_events } true; 6444#L1024-2 [2022-07-14 16:03:43,529 INFO L754 eck$LassoCheckResult]: Loop: 6444#L1024-2 assume !false; 6729#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6784#L645 assume !false; 6661#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6662#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6389#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6866#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6899#L556 assume !(0 != eval_~tmp~0#1); 6933#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6843#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6437#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6438#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6598#L675-3 assume !(0 == ~T2_E~0); 6599#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6819#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6820#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6930#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6828#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6829#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6492#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6493#L715-3 assume !(0 == ~E_4~0); 6724#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6725#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6799#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6574#L320-21 assume !(1 == ~m_pc~0); 6576#L320-23 is_master_triggered_~__retres1~0#1 := 0; 6722#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6648#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6649#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6884#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6505#L339-21 assume !(1 == ~t1_pc~0); 6506#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 6609#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6481#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6363#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6364#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6463#L358-21 assume !(1 == ~t2_pc~0); 6517#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 6445#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6446#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6728#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6482#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6483#L377-21 assume 1 == ~t3_pc~0; 6896#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6755#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6756#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6775#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6620#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6621#L396-21 assume 1 == ~t4_pc~0; 6788#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6647#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6618#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6345#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 6346#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6596#L415-21 assume 1 == ~t5_pc~0; 6597#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6571#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6467#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6468#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6668#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6669#L434-21 assume !(1 == ~t6_pc~0); 6368#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6369#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6871#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6592#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6593#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6587#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6588#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6908#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6750#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6687#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6611#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6612#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6895#L773-3 assume !(1 == ~E_1~0); 6530#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6531#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6753#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6920#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6921#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6792#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6521#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6417#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6681#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6682#L1043 assume !(0 == start_simulation_~tmp~3#1); 6875#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6751#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6538#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6720#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6709#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6431#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6432#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6579#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6444#L1024-2 [2022-07-14 16:03:43,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,529 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2022-07-14 16:03:43,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444225181] [2022-07-14 16:03:43,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444225181] [2022-07-14 16:03:43,544 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444225181] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,544 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,544 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137702218] [2022-07-14 16:03:43,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,544 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:43,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,545 INFO L85 PathProgramCache]: Analyzing trace with hash -426171263, now seen corresponding path program 1 times [2022-07-14 16:03:43,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936933972] [2022-07-14 16:03:43,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936933972] [2022-07-14 16:03:43,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936933972] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,577 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,577 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238553364] [2022-07-14 16:03:43,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,577 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:43,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:43,578 INFO L87 Difference]: Start difference. First operand 626 states and 933 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,588 INFO L93 Difference]: Finished difference Result 626 states and 932 transitions. [2022-07-14 16:03:43,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:43,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 932 transitions. [2022-07-14 16:03:43,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 932 transitions. [2022-07-14 16:03:43,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-07-14 16:03:43,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-07-14 16:03:43,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 932 transitions. [2022-07-14 16:03:43,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,596 INFO L369 hiAutomatonCegarLoop]: Abstraction has 626 states and 932 transitions. [2022-07-14 16:03:43,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 932 transitions. [2022-07-14 16:03:43,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-07-14 16:03:43,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 932 transitions. [2022-07-14 16:03:43,603 INFO L392 hiAutomatonCegarLoop]: Abstraction has 626 states and 932 transitions. [2022-07-14 16:03:43,603 INFO L374 stractBuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2022-07-14 16:03:43,603 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:03:43,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 932 transitions. [2022-07-14 16:03:43,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-07-14 16:03:43,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,606 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,606 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,606 INFO L752 eck$LassoCheckResult]: Stem: 8194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 8177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8129#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7573#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7569#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7570#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8085#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8188#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7665#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7666#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7818#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7683#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7684#L670 assume !(0 == ~M_E~0); 8053#L670-2 assume !(0 == ~T1_E~0); 8001#L675-1 assume !(0 == ~T2_E~0); 8002#L680-1 assume !(0 == ~T3_E~0); 8083#L685-1 assume !(0 == ~T4_E~0); 8057#L690-1 assume !(0 == ~T5_E~0); 8058#L695-1 assume !(0 == ~T6_E~0); 8115#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8107#L705-1 assume !(0 == ~E_2~0); 8108#L710-1 assume !(0 == ~E_3~0); 8000#L715-1 assume !(0 == ~E_4~0); 7924#L720-1 assume !(0 == ~E_5~0); 7925#L725-1 assume !(0 == ~E_6~0); 7978#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8025#L320 assume 1 == ~m_pc~0; 7966#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7860#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7861#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7819#L825 assume !(0 != activate_threads_~tmp~1#1); 7820#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7826#L339 assume !(1 == ~t1_pc~0); 7827#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7803#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7804#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7685#L833 assume !(0 != activate_threads_~tmp___0~0#1); 7686#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7594#L358 assume 1 == ~t2_pc~0; 7595#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8103#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8054#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7982#L841 assume !(0 != activate_threads_~tmp___1~0#1); 7816#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7817#L377 assume !(1 == ~t3_pc~0); 8069#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8070#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8065#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7823#L849 assume !(0 != activate_threads_~tmp___2~0#1); 7824#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7769#L396 assume 1 == ~t4_pc~0; 7770#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7597#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7598#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8016#L857 assume !(0 != activate_threads_~tmp___3~0#1); 7738#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7739#L415 assume 1 == ~t5_pc~0; 7806#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7850#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8026#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8133#L865 assume !(0 != activate_threads_~tmp___4~0#1); 7640#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7641#L434 assume !(1 == ~t6_pc~0); 7955#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7956#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8095#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8096#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7836#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7837#L743 assume !(1 == ~M_E~0); 7730#L743-2 assume !(1 == ~T1_E~0); 7731#L748-1 assume !(1 == ~T2_E~0); 8019#L753-1 assume !(1 == ~T3_E~0); 8020#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8119#L763-1 assume !(1 == ~T5_E~0); 8151#L768-1 assume !(1 == ~T6_E~0); 7834#L773-1 assume !(1 == ~E_1~0); 7835#L778-1 assume !(1 == ~E_2~0); 7811#L783-1 assume !(1 == ~E_3~0); 7812#L788-1 assume !(1 == ~E_4~0); 8081#L793-1 assume !(1 == ~E_5~0); 8046#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7704#L803-1 assume { :end_inline_reset_delta_events } true; 7705#L1024-2 [2022-07-14 16:03:43,607 INFO L754 eck$LassoCheckResult]: Loop: 7705#L1024-2 assume !false; 7988#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8043#L645 assume !false; 7920#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7921#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7648#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8125#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8160#L556 assume !(0 != eval_~tmp~0#1); 8192#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8102#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7696#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7697#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7857#L675-3 assume !(0 == ~T2_E~0); 7858#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8078#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8079#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8189#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8089#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8090#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7751#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7752#L715-3 assume !(0 == ~E_4~0); 7983#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7984#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8056#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7829#L320-21 assume 1 == ~m_pc~0; 7830#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7981#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7907#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7908#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8142#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7764#L339-21 assume !(1 == ~t1_pc~0); 7765#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7868#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7740#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7622#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7623#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7722#L358-21 assume !(1 == ~t2_pc~0); 7776#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 7702#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7703#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7987#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7741#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7742#L377-21 assume !(1 == ~t3_pc~0); 8098#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 8013#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8014#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8034#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7879#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7880#L396-21 assume !(1 == ~t4_pc~0); 7905#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7906#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7877#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7604#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 7605#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7855#L415-21 assume 1 == ~t5_pc~0; 7856#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7833#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7726#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7727#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7927#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7928#L434-21 assume 1 == ~t6_pc~0; 7939#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7630#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8131#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7851#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7852#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7846#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7847#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8167#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8009#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7947#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7870#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7871#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8155#L773-3 assume !(1 == ~E_1~0); 7789#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7790#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8012#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8179#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8180#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8052#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7780#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7676#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7940#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7941#L1043 assume !(0 == start_simulation_~tmp~3#1); 8134#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8010#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7797#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7980#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7968#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7690#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7691#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7838#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 7705#L1024-2 [2022-07-14 16:03:43,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,607 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2022-07-14 16:03:43,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776988488] [2022-07-14 16:03:43,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776988488] [2022-07-14 16:03:43,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776988488] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,636 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115156091] [2022-07-14 16:03:43,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,636 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:43,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1893431359, now seen corresponding path program 1 times [2022-07-14 16:03:43,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361634067] [2022-07-14 16:03:43,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361634067] [2022-07-14 16:03:43,670 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361634067] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,670 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,670 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:43,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638823692] [2022-07-14 16:03:43,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,670 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:43,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:43,671 INFO L87 Difference]: Start difference. First operand 626 states and 932 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,780 INFO L93 Difference]: Finished difference Result 1124 states and 1672 transitions. [2022-07-14 16:03:43,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:43,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1124 states and 1672 transitions. [2022-07-14 16:03:43,797 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2022-07-14 16:03:43,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1124 states to 1124 states and 1672 transitions. [2022-07-14 16:03:43,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1124 [2022-07-14 16:03:43,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1124 [2022-07-14 16:03:43,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1124 states and 1672 transitions. [2022-07-14 16:03:43,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,803 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1124 states and 1672 transitions. [2022-07-14 16:03:43,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1124 states and 1672 transitions. [2022-07-14 16:03:43,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1124 to 1122. [2022-07-14 16:03:43,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 1122 states and 1670 transitions. [2022-07-14 16:03:43,821 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1122 states and 1670 transitions. [2022-07-14 16:03:43,821 INFO L374 stractBuchiCegarLoop]: Abstraction has 1122 states and 1670 transitions. [2022-07-14 16:03:43,821 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:03:43,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1122 states and 1670 transitions. [2022-07-14 16:03:43,825 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2022-07-14 16:03:43,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,826 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,826 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,826 INFO L752 eck$LassoCheckResult]: Stem: 9987#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9903#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9333#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9329#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 9330#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9854#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9980#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9424#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9425#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9580#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9443#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9444#L670 assume !(0 == ~M_E~0); 9821#L670-2 assume !(0 == ~T1_E~0); 9767#L675-1 assume !(0 == ~T2_E~0); 9768#L680-1 assume !(0 == ~T3_E~0); 9853#L685-1 assume !(0 == ~T4_E~0); 9824#L690-1 assume !(0 == ~T5_E~0); 9825#L695-1 assume !(0 == ~T6_E~0); 9887#L700-1 assume !(0 == ~E_1~0); 9879#L705-1 assume !(0 == ~E_2~0); 9880#L710-1 assume !(0 == ~E_3~0); 9765#L715-1 assume !(0 == ~E_4~0); 9687#L720-1 assume !(0 == ~E_5~0); 9688#L725-1 assume !(0 == ~E_6~0); 9744#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9793#L320 assume 1 == ~m_pc~0; 9731#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9623#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9624#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9581#L825 assume !(0 != activate_threads_~tmp~1#1); 9582#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9587#L339 assume !(1 == ~t1_pc~0); 9588#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9565#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9566#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9446#L833 assume !(0 != activate_threads_~tmp___0~0#1); 9447#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9354#L358 assume 1 == ~t2_pc~0; 9355#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9875#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9822#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9748#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9576#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9577#L377 assume !(1 == ~t3_pc~0); 9837#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9838#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9833#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9585#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9586#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9531#L396 assume 1 == ~t4_pc~0; 9532#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9357#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9358#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9784#L857 assume !(0 != activate_threads_~tmp___3~0#1); 9500#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9501#L415 assume 1 == ~t5_pc~0; 9567#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9611#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9794#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9908#L865 assume !(0 != activate_threads_~tmp___4~0#1); 9400#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9401#L434 assume !(1 == ~t6_pc~0); 9720#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9721#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9865#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9866#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9599#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9600#L743 assume !(1 == ~M_E~0); 9491#L743-2 assume !(1 == ~T1_E~0); 9492#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9949#L753-1 assume !(1 == ~T3_E~0); 9891#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9892#L763-1 assume !(1 == ~T5_E~0); 9930#L768-1 assume !(1 == ~T6_E~0); 9979#L773-1 assume !(1 == ~E_1~0); 9592#L778-1 assume !(1 == ~E_2~0); 10055#L783-1 assume !(1 == ~E_3~0); 10053#L788-1 assume !(1 == ~E_4~0); 10051#L793-1 assume !(1 == ~E_5~0); 10050#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 10020#L803-1 assume { :end_inline_reset_delta_events } true; 10013#L1024-2 [2022-07-14 16:03:43,827 INFO L754 eck$LassoCheckResult]: Loop: 10013#L1024-2 assume !false; 9943#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9811#L645 assume !false; 10003#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10002#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9995#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9938#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9939#L556 assume !(0 != eval_~tmp~0#1); 9984#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9874#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9455#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9456#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9989#L675-3 assume !(0 == ~T2_E~0); 9909#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9848#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9849#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9981#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9857#L700-3 assume !(0 == ~E_1~0); 9858#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9513#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9514#L715-3 assume !(0 == ~E_4~0); 9749#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9750#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9826#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9594#L320-21 assume 1 == ~m_pc~0; 9595#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9747#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9672#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9673#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9919#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9526#L339-21 assume !(1 == ~t1_pc~0); 9527#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 9631#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9502#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9382#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9383#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9483#L358-21 assume !(1 == ~t2_pc~0); 9538#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9465#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9466#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9753#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9503#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9504#L377-21 assume !(1 == ~t3_pc~0); 9868#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 9782#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9783#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9802#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9642#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9643#L396-21 assume !(1 == ~t4_pc~0); 9670#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9671#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9640#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9364#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 9365#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9620#L415-21 assume 1 == ~t5_pc~0; 9621#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9598#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9487#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9488#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9692#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9693#L434-21 assume 1 == ~t6_pc~0; 9704#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9390#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9906#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9614#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9615#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9609#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9610#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9954#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9777#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9712#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9633#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9634#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9935#L773-3 assume !(1 == ~E_1~0); 9551#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9552#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9780#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9968#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9969#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9820#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9542#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9437#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9705#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9706#L1043 assume !(0 == start_simulation_~tmp~3#1); 9910#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9778#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9560#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9841#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 10056#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10054#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10052#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10021#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 10013#L1024-2 [2022-07-14 16:03:43,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1234940959, now seen corresponding path program 1 times [2022-07-14 16:03:43,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017928421] [2022-07-14 16:03:43,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017928421] [2022-07-14 16:03:43,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017928421] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,855 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,855 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:43,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020483573] [2022-07-14 16:03:43,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,857 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:43,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,857 INFO L85 PathProgramCache]: Analyzing trace with hash -159326909, now seen corresponding path program 1 times [2022-07-14 16:03:43,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867853209] [2022-07-14 16:03:43,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:43,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:43,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:43,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867853209] [2022-07-14 16:03:43,888 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1867853209] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:43,888 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:43,888 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:43,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025250173] [2022-07-14 16:03:43,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:43,889 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:43,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:43,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:43,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:43,889 INFO L87 Difference]: Start difference. First operand 1122 states and 1670 transitions. cyclomatic complexity: 550 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:43,934 INFO L93 Difference]: Finished difference Result 1637 states and 2406 transitions. [2022-07-14 16:03:43,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:43,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1637 states and 2406 transitions. [2022-07-14 16:03:43,943 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1536 [2022-07-14 16:03:43,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1637 states to 1637 states and 2406 transitions. [2022-07-14 16:03:43,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1637 [2022-07-14 16:03:43,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1637 [2022-07-14 16:03:43,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1637 states and 2406 transitions. [2022-07-14 16:03:43,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:43,952 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1637 states and 2406 transitions. [2022-07-14 16:03:43,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1637 states and 2406 transitions. [2022-07-14 16:03:43,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1637 to 1586. [2022-07-14 16:03:43,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:43,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1586 states to 1586 states and 2336 transitions. [2022-07-14 16:03:43,972 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1586 states and 2336 transitions. [2022-07-14 16:03:43,972 INFO L374 stractBuchiCegarLoop]: Abstraction has 1586 states and 2336 transitions. [2022-07-14 16:03:43,972 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:03:43,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1586 states and 2336 transitions. [2022-07-14 16:03:43,977 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1486 [2022-07-14 16:03:43,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:43,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:43,978 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,978 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:43,978 INFO L752 eck$LassoCheckResult]: Stem: 12767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 12734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12664#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12101#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12097#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 12098#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12613#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12750#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12190#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12191#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12342#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12209#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12210#L670 assume !(0 == ~M_E~0); 12578#L670-2 assume !(0 == ~T1_E~0); 12524#L675-1 assume !(0 == ~T2_E~0); 12525#L680-1 assume !(0 == ~T3_E~0); 12612#L685-1 assume !(0 == ~T4_E~0); 12581#L690-1 assume !(0 == ~T5_E~0); 12582#L695-1 assume !(0 == ~T6_E~0); 12643#L700-1 assume !(0 == ~E_1~0); 12635#L705-1 assume !(0 == ~E_2~0); 12636#L710-1 assume !(0 == ~E_3~0); 12522#L715-1 assume !(0 == ~E_4~0); 12446#L720-1 assume !(0 == ~E_5~0); 12447#L725-1 assume !(0 == ~E_6~0); 12501#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12550#L320 assume !(1 == ~m_pc~0); 12661#L320-2 is_master_triggered_~__retres1~0#1 := 0; 12383#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12384#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12343#L825 assume !(0 != activate_threads_~tmp~1#1); 12344#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12349#L339 assume !(1 == ~t1_pc~0); 12350#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12327#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12328#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12212#L833 assume !(0 != activate_threads_~tmp___0~0#1); 12213#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12122#L358 assume 1 == ~t2_pc~0; 12123#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12631#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12579#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12505#L841 assume !(0 != activate_threads_~tmp___1~0#1); 12338#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12339#L377 assume !(1 == ~t3_pc~0); 12597#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12598#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12593#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12347#L849 assume !(0 != activate_threads_~tmp___2~0#1); 12348#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12295#L396 assume 1 == ~t4_pc~0; 12296#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12125#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12126#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12541#L857 assume !(0 != activate_threads_~tmp___3~0#1); 12265#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12266#L415 assume 1 == ~t5_pc~0; 12329#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12371#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12551#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12671#L865 assume !(0 != activate_threads_~tmp___4~0#1); 12168#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12169#L434 assume !(1 == ~t6_pc~0); 12479#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12480#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12624#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12625#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12359#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12360#L743 assume !(1 == ~M_E~0); 12257#L743-2 assume !(1 == ~T1_E~0); 12258#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12544#L753-1 assume !(1 == ~T3_E~0); 12545#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12647#L763-1 assume !(1 == ~T5_E~0); 12697#L768-1 assume !(1 == ~T6_E~0); 12353#L773-1 assume !(1 == ~E_1~0); 12354#L778-1 assume !(1 == ~E_2~0); 12335#L783-1 assume !(1 == ~E_3~0); 12336#L788-1 assume !(1 == ~E_4~0); 12610#L793-1 assume !(1 == ~E_5~0); 12571#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 12229#L803-1 assume { :end_inline_reset_delta_events } true; 12230#L1024-2 [2022-07-14 16:03:43,978 INFO L754 eck$LassoCheckResult]: Loop: 12230#L1024-2 assume !false; 12511#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12568#L645 assume !false; 13244#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13243#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13236#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12707#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12708#L556 assume !(0 != eval_~tmp~0#1); 12760#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12630#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12221#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12222#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13230#L675-3 assume !(0 == ~T2_E~0); 12672#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12607#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12608#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12753#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12616#L700-3 assume !(0 == ~E_1~0); 12617#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12278#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12279#L715-3 assume !(0 == ~E_4~0); 12506#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12507#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12583#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12355#L320-21 assume !(1 == ~m_pc~0); 12356#L320-23 is_master_triggered_~__retres1~0#1 := 0; 12504#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12431#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12432#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12685#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12290#L339-21 assume !(1 == ~t1_pc~0); 12291#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12391#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12267#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12150#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12151#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12249#L358-21 assume 1 == ~t2_pc~0; 12352#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12231#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12232#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12510#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12268#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12269#L377-21 assume !(1 == ~t3_pc~0); 12627#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 12539#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12540#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12559#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12402#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12403#L396-21 assume 1 == ~t4_pc~0; 12572#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12430#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12400#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12132#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 12133#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12380#L415-21 assume !(1 == ~t5_pc~0); 12357#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 12358#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12253#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12254#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12451#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12452#L434-21 assume !(1 == ~t6_pc~0); 12157#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 12158#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12669#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12374#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12375#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12533#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12723#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12724#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12534#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12471#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12393#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12394#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12703#L773-3 assume !(1 == ~E_1~0); 12315#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12316#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12537#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12757#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12740#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12577#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12306#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12203#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12464#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12465#L1043 assume !(0 == start_simulation_~tmp~3#1); 12675#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12535#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12322#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12503#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12490#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12217#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12218#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12361#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 12230#L1024-2 [2022-07-14 16:03:43,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:43,979 INFO L85 PathProgramCache]: Analyzing trace with hash -1227190400, now seen corresponding path program 1 times [2022-07-14 16:03:43,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:43,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949553075] [2022-07-14 16:03:43,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:43,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:43,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:44,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:44,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:44,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949553075] [2022-07-14 16:03:44,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949553075] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:44,002 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:44,002 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:44,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588109072] [2022-07-14 16:03:44,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:44,002 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:44,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:44,003 INFO L85 PathProgramCache]: Analyzing trace with hash 93166242, now seen corresponding path program 1 times [2022-07-14 16:03:44,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:44,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029686759] [2022-07-14 16:03:44,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:44,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:44,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:44,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:44,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:44,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029686759] [2022-07-14 16:03:44,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029686759] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:44,036 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:44,036 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:44,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361373225] [2022-07-14 16:03:44,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:44,036 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:44,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:44,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:44,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:44,037 INFO L87 Difference]: Start difference. First operand 1586 states and 2336 transitions. cyclomatic complexity: 753 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:44,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:44,167 INFO L93 Difference]: Finished difference Result 3886 states and 5661 transitions. [2022-07-14 16:03:44,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:44,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3886 states and 5661 transitions. [2022-07-14 16:03:44,187 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 3725 [2022-07-14 16:03:44,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3886 states to 3886 states and 5661 transitions. [2022-07-14 16:03:44,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3886 [2022-07-14 16:03:44,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3886 [2022-07-14 16:03:44,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3886 states and 5661 transitions. [2022-07-14 16:03:44,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:44,210 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3886 states and 5661 transitions. [2022-07-14 16:03:44,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3886 states and 5661 transitions. [2022-07-14 16:03:44,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3886 to 2893. [2022-07-14 16:03:44,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:44,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2893 states to 2893 states and 4237 transitions. [2022-07-14 16:03:44,254 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2893 states and 4237 transitions. [2022-07-14 16:03:44,254 INFO L374 stractBuchiCegarLoop]: Abstraction has 2893 states and 4237 transitions. [2022-07-14 16:03:44,254 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:03:44,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2893 states and 4237 transitions. [2022-07-14 16:03:44,266 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2793 [2022-07-14 16:03:44,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:44,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:44,267 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:44,267 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:44,267 INFO L752 eck$LassoCheckResult]: Stem: 18296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 18248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 18174#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17585#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17581#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 17582#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18114#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18271#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17674#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17675#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17831#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17692#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17693#L670 assume !(0 == ~M_E~0); 18074#L670-2 assume !(0 == ~T1_E~0); 18020#L675-1 assume !(0 == ~T2_E~0); 18021#L680-1 assume !(0 == ~T3_E~0); 18112#L685-1 assume !(0 == ~T4_E~0); 18078#L690-1 assume !(0 == ~T5_E~0); 18079#L695-1 assume !(0 == ~T6_E~0); 18149#L700-1 assume !(0 == ~E_1~0); 18140#L705-1 assume !(0 == ~E_2~0); 18141#L710-1 assume !(0 == ~E_3~0); 18019#L715-1 assume !(0 == ~E_4~0); 17943#L720-1 assume !(0 == ~E_5~0); 17944#L725-1 assume !(0 == ~E_6~0); 17997#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18045#L320 assume !(1 == ~m_pc~0); 18171#L320-2 is_master_triggered_~__retres1~0#1 := 0; 17876#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17877#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17832#L825 assume !(0 != activate_threads_~tmp~1#1); 17833#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17841#L339 assume !(1 == ~t1_pc~0); 17842#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17815#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17816#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17694#L833 assume !(0 != activate_threads_~tmp___0~0#1); 17695#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17606#L358 assume !(1 == ~t2_pc~0); 17607#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18135#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18075#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18001#L841 assume !(0 != activate_threads_~tmp___1~0#1); 17829#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17830#L377 assume !(1 == ~t3_pc~0); 18094#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18095#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18090#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17836#L849 assume !(0 != activate_threads_~tmp___2~0#1); 17837#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17779#L396 assume 1 == ~t4_pc~0; 17780#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17608#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17609#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18035#L857 assume !(0 != activate_threads_~tmp___3~0#1); 17749#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17750#L415 assume 1 == ~t5_pc~0; 17817#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17864#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18046#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18179#L865 assume !(0 != activate_threads_~tmp___4~0#1); 17650#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17651#L434 assume !(1 == ~t6_pc~0); 17974#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17975#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18125#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18126#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17850#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17851#L743 assume !(1 == ~M_E~0); 17742#L743-2 assume !(1 == ~T1_E~0); 17743#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18038#L753-1 assume !(1 == ~T3_E~0); 18039#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18211#L763-1 assume !(1 == ~T5_E~0); 18212#L768-1 assume !(1 == ~T6_E~0); 17848#L773-1 assume !(1 == ~E_1~0); 17849#L778-1 assume !(1 == ~E_2~0); 17824#L783-1 assume !(1 == ~E_3~0); 17825#L788-1 assume !(1 == ~E_4~0); 18109#L793-1 assume !(1 == ~E_5~0); 18110#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 17713#L803-1 assume { :end_inline_reset_delta_events } true; 17714#L1024-2 [2022-07-14 16:03:44,267 INFO L754 eck$LassoCheckResult]: Loop: 17714#L1024-2 assume !false; 18007#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18213#L645 assume !false; 17939#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17940#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17657#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 18166#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20101#L556 assume !(0 != eval_~tmp~0#1); 18284#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18134#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17705#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17706#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17994#L675-3 assume !(0 == ~T2_E~0); 20099#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20394#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20393#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20392#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20391#L700-3 assume !(0 == ~E_1~0); 20390#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20389#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20388#L715-3 assume !(0 == ~E_4~0); 20387#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20386#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20385#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20384#L320-21 assume !(1 == ~m_pc~0); 20383#L320-23 is_master_triggered_~__retres1~0#1 := 0; 20382#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20381#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20380#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20379#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20378#L339-21 assume !(1 == ~t1_pc~0); 20376#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 20375#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20374#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20373#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20372#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20371#L358-21 assume !(1 == ~t2_pc~0); 19347#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 20370#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20369#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20368#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20367#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20366#L377-21 assume !(1 == ~t3_pc~0); 20364#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 20363#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20362#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20361#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20360#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20359#L396-21 assume 1 == ~t4_pc~0; 20357#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20356#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20355#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20354#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 20353#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20352#L415-21 assume 1 == ~t5_pc~0; 20350#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20349#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20348#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20347#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20346#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20344#L434-21 assume !(1 == ~t6_pc~0); 20341#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 20339#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18186#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17865#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17866#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20325#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20323#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20321#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18270#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20318#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20315#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20313#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20311#L773-3 assume !(1 == ~E_1~0); 18217#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20308#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20306#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20303#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20301#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20299#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20271#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20266#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20264#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 20260#L1043 assume !(0 == start_simulation_~tmp~3#1); 20259#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20256#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20251#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20250#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 20249#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17699#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17700#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17852#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 17714#L1024-2 [2022-07-14 16:03:44,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:44,271 INFO L85 PathProgramCache]: Analyzing trace with hash 1792674207, now seen corresponding path program 1 times [2022-07-14 16:03:44,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:44,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733308208] [2022-07-14 16:03:44,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:44,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:44,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:44,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:44,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:44,299 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733308208] [2022-07-14 16:03:44,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733308208] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:44,302 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:44,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:44,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078113928] [2022-07-14 16:03:44,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:44,303 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:44,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:44,304 INFO L85 PathProgramCache]: Analyzing trace with hash -422403870, now seen corresponding path program 1 times [2022-07-14 16:03:44,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:44,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312896979] [2022-07-14 16:03:44,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:44,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:44,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:44,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:44,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:44,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312896979] [2022-07-14 16:03:44,329 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312896979] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:44,329 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:44,329 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:44,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838460860] [2022-07-14 16:03:44,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:44,330 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:44,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:44,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:44,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:44,331 INFO L87 Difference]: Start difference. First operand 2893 states and 4237 transitions. cyclomatic complexity: 1347 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:44,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:44,384 INFO L93 Difference]: Finished difference Result 5347 states and 7793 transitions. [2022-07-14 16:03:44,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:44,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5347 states and 7793 transitions. [2022-07-14 16:03:44,406 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5234 [2022-07-14 16:03:44,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5347 states to 5347 states and 7793 transitions. [2022-07-14 16:03:44,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5347 [2022-07-14 16:03:44,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5347 [2022-07-14 16:03:44,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5347 states and 7793 transitions. [2022-07-14 16:03:44,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:44,466 INFO L369 hiAutomatonCegarLoop]: Abstraction has 5347 states and 7793 transitions. [2022-07-14 16:03:44,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5347 states and 7793 transitions. [2022-07-14 16:03:44,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5347 to 5335. [2022-07-14 16:03:44,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:44,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5335 states to 5335 states and 7781 transitions. [2022-07-14 16:03:44,534 INFO L392 hiAutomatonCegarLoop]: Abstraction has 5335 states and 7781 transitions. [2022-07-14 16:03:44,534 INFO L374 stractBuchiCegarLoop]: Abstraction has 5335 states and 7781 transitions. [2022-07-14 16:03:44,534 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:03:44,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5335 states and 7781 transitions. [2022-07-14 16:03:44,551 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5222 [2022-07-14 16:03:44,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:44,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:44,552 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:44,552 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:44,552 INFO L752 eck$LassoCheckResult]: Stem: 26531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 26481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26413#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25834#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25830#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 25831#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26356#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26506#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25923#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25924#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26075#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25941#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25942#L670 assume !(0 == ~M_E~0); 26315#L670-2 assume !(0 == ~T1_E~0); 26261#L675-1 assume !(0 == ~T2_E~0); 26262#L680-1 assume !(0 == ~T3_E~0); 26354#L685-1 assume !(0 == ~T4_E~0); 26319#L690-1 assume !(0 == ~T5_E~0); 26320#L695-1 assume !(0 == ~T6_E~0); 26389#L700-1 assume !(0 == ~E_1~0); 26380#L705-1 assume !(0 == ~E_2~0); 26381#L710-1 assume !(0 == ~E_3~0); 26260#L715-1 assume !(0 == ~E_4~0); 26184#L720-1 assume !(0 == ~E_5~0); 26185#L725-1 assume !(0 == ~E_6~0); 26237#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26284#L320 assume !(1 == ~m_pc~0); 26407#L320-2 is_master_triggered_~__retres1~0#1 := 0; 26117#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26118#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26076#L825 assume !(0 != activate_threads_~tmp~1#1); 26077#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26083#L339 assume !(1 == ~t1_pc~0); 26084#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26059#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26060#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25943#L833 assume !(0 != activate_threads_~tmp___0~0#1); 25944#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25855#L358 assume !(1 == ~t2_pc~0); 25856#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26376#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26317#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26241#L841 assume !(0 != activate_threads_~tmp___1~0#1); 26073#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26074#L377 assume !(1 == ~t3_pc~0); 26336#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26337#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26331#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26080#L849 assume !(0 != activate_threads_~tmp___2~0#1); 26081#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26028#L396 assume !(1 == ~t4_pc~0); 26029#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25857#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25858#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26275#L857 assume !(0 != activate_threads_~tmp___3~0#1); 25997#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25998#L415 assume 1 == ~t5_pc~0; 26061#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26107#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26285#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26418#L865 assume !(0 != activate_threads_~tmp___4~0#1); 25899#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25900#L434 assume !(1 == ~t6_pc~0); 26215#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26216#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26367#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26368#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26093#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26094#L743 assume !(1 == ~M_E~0); 25989#L743-2 assume !(1 == ~T1_E~0); 25990#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26466#L753-1 assume !(1 == ~T3_E~0); 30676#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30675#L763-1 assume !(1 == ~T5_E~0); 30674#L768-1 assume !(1 == ~T6_E~0); 30673#L773-1 assume !(1 == ~E_1~0); 26089#L778-1 assume !(1 == ~E_2~0); 30672#L783-1 assume !(1 == ~E_3~0); 30671#L788-1 assume !(1 == ~E_4~0); 30670#L793-1 assume !(1 == ~E_5~0); 30669#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30437#L803-1 assume { :end_inline_reset_delta_events } true; 30436#L1024-2 [2022-07-14 16:03:44,552 INFO L754 eck$LassoCheckResult]: Loop: 30436#L1024-2 assume !false; 30435#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30430#L645 assume !false; 30429#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30428#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30421#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30420#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30418#L556 assume !(0 != eval_~tmp~0#1); 30419#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30643#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30641#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30639#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30637#L675-3 assume !(0 == ~T2_E~0); 30635#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30633#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30631#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30629#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30626#L700-3 assume !(0 == ~E_1~0); 30624#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30622#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30620#L715-3 assume !(0 == ~E_4~0); 30618#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30616#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30613#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30611#L320-21 assume !(1 == ~m_pc~0); 30609#L320-23 is_master_triggered_~__retres1~0#1 := 0; 30607#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30605#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30604#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30603#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30602#L339-21 assume !(1 == ~t1_pc~0); 30600#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 30599#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30598#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30597#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30596#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30571#L358-21 assume !(1 == ~t2_pc~0); 30570#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 30569#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30568#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30567#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30566#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30565#L377-21 assume !(1 == ~t3_pc~0); 30563#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 30562#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30561#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30560#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30559#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30558#L396-21 assume !(1 == ~t4_pc~0); 30557#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 30556#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30555#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30554#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 30553#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30552#L415-21 assume 1 == ~t5_pc~0; 30550#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30549#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30548#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30547#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30546#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28890#L434-21 assume !(1 == ~t6_pc~0); 28888#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 28887#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28886#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28885#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28884#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28883#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28882#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28880#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28878#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28876#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28874#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28869#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28870#L773-3 assume !(1 == ~E_1~0); 28866#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30524#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30522#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30520#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30518#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30515#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30501#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30497#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30496#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30452#L1043 assume !(0 == start_simulation_~tmp~3#1); 30451#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30448#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30443#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30442#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 30441#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30440#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30439#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 30438#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 30436#L1024-2 [2022-07-14 16:03:44,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:44,552 INFO L85 PathProgramCache]: Analyzing trace with hash -1583318466, now seen corresponding path program 1 times [2022-07-14 16:03:44,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:44,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216166373] [2022-07-14 16:03:44,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:44,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:44,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:44,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:44,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:44,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216166373] [2022-07-14 16:03:44,571 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216166373] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:44,571 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:44,571 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:44,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139238482] [2022-07-14 16:03:44,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:44,572 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:44,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:44,572 INFO L85 PathProgramCache]: Analyzing trace with hash -1697506559, now seen corresponding path program 1 times [2022-07-14 16:03:44,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:44,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173202020] [2022-07-14 16:03:44,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:44,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:44,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:44,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:44,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:44,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173202020] [2022-07-14 16:03:44,596 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173202020] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:44,596 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:44,597 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:44,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235908944] [2022-07-14 16:03:44,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:44,597 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:44,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:44,598 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:44,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:44,598 INFO L87 Difference]: Start difference. First operand 5335 states and 7781 transitions. cyclomatic complexity: 2452 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:44,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:44,705 INFO L93 Difference]: Finished difference Result 9904 states and 14392 transitions. [2022-07-14 16:03:44,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:44,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9904 states and 14392 transitions. [2022-07-14 16:03:44,750 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9752 [2022-07-14 16:03:44,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9904 states to 9904 states and 14392 transitions. [2022-07-14 16:03:44,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9904 [2022-07-14 16:03:44,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9904 [2022-07-14 16:03:44,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9904 states and 14392 transitions. [2022-07-14 16:03:44,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:44,816 INFO L369 hiAutomatonCegarLoop]: Abstraction has 9904 states and 14392 transitions. [2022-07-14 16:03:44,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9904 states and 14392 transitions. [2022-07-14 16:03:44,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9904 to 9880. [2022-07-14 16:03:44,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:44,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9880 states to 9880 states and 14368 transitions. [2022-07-14 16:03:44,999 INFO L392 hiAutomatonCegarLoop]: Abstraction has 9880 states and 14368 transitions. [2022-07-14 16:03:44,999 INFO L374 stractBuchiCegarLoop]: Abstraction has 9880 states and 14368 transitions. [2022-07-14 16:03:44,999 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:03:44,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9880 states and 14368 transitions. [2022-07-14 16:03:45,029 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9728 [2022-07-14 16:03:45,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:45,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:45,031 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:45,031 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:45,031 INFO L752 eck$LassoCheckResult]: Stem: 41805#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 41751#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 41681#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41082#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41078#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 41079#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41616#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41777#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41172#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41173#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41323#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41190#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41191#L670 assume !(0 == ~M_E~0); 41573#L670-2 assume !(0 == ~T1_E~0); 41513#L675-1 assume !(0 == ~T2_E~0); 41514#L680-1 assume !(0 == ~T3_E~0); 41614#L685-1 assume !(0 == ~T4_E~0); 41579#L690-1 assume !(0 == ~T5_E~0); 41580#L695-1 assume !(0 == ~T6_E~0); 41656#L700-1 assume !(0 == ~E_1~0); 41641#L705-1 assume !(0 == ~E_2~0); 41642#L710-1 assume !(0 == ~E_3~0); 41512#L715-1 assume !(0 == ~E_4~0); 41435#L720-1 assume !(0 == ~E_5~0); 41436#L725-1 assume !(0 == ~E_6~0); 41490#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41538#L320 assume !(1 == ~m_pc~0); 41674#L320-2 is_master_triggered_~__retres1~0#1 := 0; 41367#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41368#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41324#L825 assume !(0 != activate_threads_~tmp~1#1); 41325#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41333#L339 assume !(1 == ~t1_pc~0); 41334#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41309#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41310#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41192#L833 assume !(0 != activate_threads_~tmp___0~0#1); 41193#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41103#L358 assume !(1 == ~t2_pc~0); 41104#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41636#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41576#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41494#L841 assume !(0 != activate_threads_~tmp___1~0#1); 41321#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41322#L377 assume !(1 == ~t3_pc~0); 41597#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41598#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41596#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41328#L849 assume !(0 != activate_threads_~tmp___2~0#1); 41329#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41279#L396 assume !(1 == ~t4_pc~0); 41280#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41105#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41106#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41528#L857 assume !(0 != activate_threads_~tmp___3~0#1); 41245#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41246#L415 assume !(1 == ~t5_pc~0); 41312#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41356#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41539#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41686#L865 assume !(0 != activate_threads_~tmp___4~0#1); 41148#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41149#L434 assume !(1 == ~t6_pc~0); 41469#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41470#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41628#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41629#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41342#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41343#L743 assume !(1 == ~M_E~0); 41238#L743-2 assume !(1 == ~T1_E~0); 41239#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41532#L753-1 assume !(1 == ~T3_E~0); 41533#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41659#L763-1 assume !(1 == ~T5_E~0); 41714#L768-1 assume !(1 == ~T6_E~0); 41340#L773-1 assume !(1 == ~E_1~0); 41341#L778-1 assume !(1 == ~E_2~0); 41316#L783-1 assume !(1 == ~E_3~0); 41317#L788-1 assume !(1 == ~E_4~0); 41612#L793-1 assume !(1 == ~E_5~0); 41564#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 41565#L803-1 assume { :end_inline_reset_delta_events } true; 49268#L1024-2 [2022-07-14 16:03:45,031 INFO L754 eck$LassoCheckResult]: Loop: 49268#L1024-2 assume !false; 44937#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44933#L645 assume !false; 44924#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 44925#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 44767#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 44766#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44763#L556 assume !(0 != eval_~tmp~0#1); 44765#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49556#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49555#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49554#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49553#L675-3 assume !(0 == ~T2_E~0); 49551#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49549#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49547#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49545#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49543#L700-3 assume !(0 == ~E_1~0); 49541#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49539#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49536#L715-3 assume !(0 == ~E_4~0); 49534#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49527#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48168#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48160#L320-21 assume !(1 == ~m_pc~0); 48158#L320-23 is_master_triggered_~__retres1~0#1 := 0; 48156#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48153#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48151#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48149#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48147#L339-21 assume !(1 == ~t1_pc~0); 48144#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 48142#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48140#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48138#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48136#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48133#L358-21 assume !(1 == ~t2_pc~0); 47495#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 48130#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48128#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48126#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48123#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48122#L377-21 assume !(1 == ~t3_pc~0); 48120#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 48119#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48118#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48117#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48115#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48113#L396-21 assume !(1 == ~t4_pc~0); 48111#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 48109#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48107#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48105#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 48103#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48098#L415-21 assume !(1 == ~t5_pc~0); 48095#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 48091#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48088#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48076#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48075#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48074#L434-21 assume !(1 == ~t6_pc~0); 48072#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 48071#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48070#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48069#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48068#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48066#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48064#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48062#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48060#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48057#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48055#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48053#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48051#L773-3 assume !(1 == ~E_1~0); 48049#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48047#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48045#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48043#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48041#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48039#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48030#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 48025#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48023#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 45003#L1043 assume !(0 == start_simulation_~tmp~3#1); 45000#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 45001#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 49280#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49278#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 49276#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49274#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49272#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 49270#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 49268#L1024-2 [2022-07-14 16:03:45,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:45,031 INFO L85 PathProgramCache]: Analyzing trace with hash -944533987, now seen corresponding path program 1 times [2022-07-14 16:03:45,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:45,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77655615] [2022-07-14 16:03:45,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:45,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:45,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:45,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:45,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:45,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77655615] [2022-07-14 16:03:45,054 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77655615] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:45,054 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:45,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:45,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273569059] [2022-07-14 16:03:45,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:45,055 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:45,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:45,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1174185888, now seen corresponding path program 1 times [2022-07-14 16:03:45,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:45,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370987639] [2022-07-14 16:03:45,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:45,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:45,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:45,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:45,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:45,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370987639] [2022-07-14 16:03:45,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370987639] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:45,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:45,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:45,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723925574] [2022-07-14 16:03:45,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:45,078 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:45,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:45,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:45,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:45,078 INFO L87 Difference]: Start difference. First operand 9880 states and 14368 transitions. cyclomatic complexity: 4500 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:45,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:45,296 INFO L93 Difference]: Finished difference Result 22635 states and 33249 transitions. [2022-07-14 16:03:45,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:45,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22635 states and 33249 transitions. [2022-07-14 16:03:45,424 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22316 [2022-07-14 16:03:45,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22635 states to 22635 states and 33249 transitions. [2022-07-14 16:03:45,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22635 [2022-07-14 16:03:45,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22635 [2022-07-14 16:03:45,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22635 states and 33249 transitions. [2022-07-14 16:03:45,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:45,569 INFO L369 hiAutomatonCegarLoop]: Abstraction has 22635 states and 33249 transitions. [2022-07-14 16:03:45,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22635 states and 33249 transitions. [2022-07-14 16:03:45,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22635 to 10303. [2022-07-14 16:03:45,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10303 states, 10303 states have (on average 1.4356012811802388) internal successors, (14791), 10302 states have internal predecessors, (14791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:45,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10303 states to 10303 states and 14791 transitions. [2022-07-14 16:03:45,880 INFO L392 hiAutomatonCegarLoop]: Abstraction has 10303 states and 14791 transitions. [2022-07-14 16:03:45,880 INFO L374 stractBuchiCegarLoop]: Abstraction has 10303 states and 14791 transitions. [2022-07-14 16:03:45,880 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:03:45,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10303 states and 14791 transitions. [2022-07-14 16:03:45,908 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10148 [2022-07-14 16:03:45,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:45,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:45,909 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:45,909 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:45,909 INFO L752 eck$LassoCheckResult]: Stem: 74577#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 74449#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 74322#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73612#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73608#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 73609#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74224#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74496#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73701#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73702#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73869#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73721#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73722#L670 assume !(0 == ~M_E~0); 74160#L670-2 assume !(0 == ~T1_E~0); 74088#L675-1 assume !(0 == ~T2_E~0); 74089#L680-1 assume !(0 == ~T3_E~0); 74221#L685-1 assume !(0 == ~T4_E~0); 74170#L690-1 assume !(0 == ~T5_E~0); 74171#L695-1 assume !(0 == ~T6_E~0); 74289#L700-1 assume !(0 == ~E_1~0); 74271#L705-1 assume !(0 == ~E_2~0); 74272#L710-1 assume !(0 == ~E_3~0); 74087#L715-1 assume !(0 == ~E_4~0); 73994#L720-1 assume !(0 == ~E_5~0); 73995#L725-1 assume !(0 == ~E_6~0); 74062#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74121#L320 assume !(1 == ~m_pc~0); 74316#L320-2 is_master_triggered_~__retres1~0#1 := 0; 73915#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73916#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 73870#L825 assume !(0 != activate_threads_~tmp~1#1); 73871#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73878#L339 assume !(1 == ~t1_pc~0); 73879#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73854#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73855#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 73723#L833 assume !(0 != activate_threads_~tmp___0~0#1); 73724#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73633#L358 assume !(1 == ~t2_pc~0); 73634#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74261#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74166#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74068#L841 assume !(0 != activate_threads_~tmp___1~0#1); 73867#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73868#L377 assume !(1 == ~t3_pc~0); 74196#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74197#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74192#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73875#L849 assume !(0 != activate_threads_~tmp___2~0#1); 73876#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73815#L396 assume !(1 == ~t4_pc~0); 73816#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 73635#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73636#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74109#L857 assume !(0 != activate_threads_~tmp___3~0#1); 73782#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73783#L415 assume !(1 == ~t5_pc~0); 73857#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 73902#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74122#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74333#L865 assume !(0 != activate_threads_~tmp___4~0#1); 73676#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73677#L434 assume !(1 == ~t6_pc~0); 74036#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 74037#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74236#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74237#L873 assume !(0 != activate_threads_~tmp___5~0#1); 73888#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73889#L743 assume !(1 == ~M_E~0); 73773#L743-2 assume !(1 == ~T1_E~0); 73774#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74410#L753-1 assume !(1 == ~T3_E~0); 81020#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81019#L763-1 assume !(1 == ~T5_E~0); 81018#L768-1 assume !(1 == ~T6_E~0); 81017#L773-1 assume !(1 == ~E_1~0); 73886#L778-1 assume !(1 == ~E_2~0); 81016#L783-1 assume !(1 == ~E_3~0); 81015#L788-1 assume !(1 == ~E_4~0); 81014#L793-1 assume !(1 == ~E_5~0); 81013#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 80923#L803-1 assume { :end_inline_reset_delta_events } true; 80922#L1024-2 [2022-07-14 16:03:45,909 INFO L754 eck$LassoCheckResult]: Loop: 80922#L1024-2 assume !false; 80921#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80916#L645 assume !false; 80915#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80914#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80907#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80906#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 80904#L556 assume !(0 != eval_~tmp~0#1); 80905#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82190#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82049#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82024#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82023#L675-3 assume !(0 == ~T2_E~0); 82015#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81845#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81790#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81784#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81773#L700-3 assume !(0 == ~E_1~0); 81768#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 81767#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81713#L715-3 assume !(0 == ~E_4~0); 81691#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81683#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81677#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81675#L320-21 assume !(1 == ~m_pc~0); 81673#L320-23 is_master_triggered_~__retres1~0#1 := 0; 81671#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81669#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81667#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81665#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81663#L339-21 assume 1 == ~t1_pc~0; 81661#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 81657#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81655#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81653#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81651#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81547#L358-21 assume !(1 == ~t2_pc~0); 81546#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 81545#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81544#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81543#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81542#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81541#L377-21 assume !(1 == ~t3_pc~0); 81539#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 81538#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81537#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81536#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81535#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81534#L396-21 assume !(1 == ~t4_pc~0); 81533#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 81532#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81531#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81530#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 81529#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81528#L415-21 assume !(1 == ~t5_pc~0); 81527#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 81526#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81525#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81524#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81523#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81522#L434-21 assume !(1 == ~t6_pc~0); 81521#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 81519#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81517#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81515#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 81513#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81511#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 81509#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81507#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81248#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81505#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81504#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81328#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81272#L773-3 assume !(1 == ~E_1~0); 81044#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81254#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81249#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81246#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81245#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81244#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 81126#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 81100#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80448#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 80434#L1043 assume !(0 == start_simulation_~tmp~3#1); 80429#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80430#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80929#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80928#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 80927#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80926#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80925#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 80924#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 80922#L1024-2 [2022-07-14 16:03:45,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:45,910 INFO L85 PathProgramCache]: Analyzing trace with hash -1965602341, now seen corresponding path program 1 times [2022-07-14 16:03:45,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:45,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387877061] [2022-07-14 16:03:45,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:45,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:45,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:45,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:45,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:45,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387877061] [2022-07-14 16:03:45,943 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387877061] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:45,943 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:45,943 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:45,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539131103] [2022-07-14 16:03:45,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:45,944 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:45,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:45,945 INFO L85 PathProgramCache]: Analyzing trace with hash 791582399, now seen corresponding path program 1 times [2022-07-14 16:03:45,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:45,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956187695] [2022-07-14 16:03:45,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:45,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:45,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:45,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:45,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:45,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956187695] [2022-07-14 16:03:45,998 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956187695] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:45,998 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:45,998 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:45,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252633447] [2022-07-14 16:03:45,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:45,998 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:45,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:45,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:45,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:45,999 INFO L87 Difference]: Start difference. First operand 10303 states and 14791 transitions. cyclomatic complexity: 4500 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:46,060 INFO L93 Difference]: Finished difference Result 10298 states and 14716 transitions. [2022-07-14 16:03:46,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:46,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10298 states and 14716 transitions. [2022-07-14 16:03:46,092 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10148 [2022-07-14 16:03:46,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10298 states to 10298 states and 14716 transitions. [2022-07-14 16:03:46,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10298 [2022-07-14 16:03:46,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10298 [2022-07-14 16:03:46,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10298 states and 14716 transitions. [2022-07-14 16:03:46,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:46,131 INFO L369 hiAutomatonCegarLoop]: Abstraction has 10298 states and 14716 transitions. [2022-07-14 16:03:46,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10298 states and 14716 transitions. [2022-07-14 16:03:46,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10298 to 7072. [2022-07-14 16:03:46,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7072 states, 7072 states have (on average 1.4294400452488687) internal successors, (10109), 7071 states have internal predecessors, (10109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7072 states to 7072 states and 10109 transitions. [2022-07-14 16:03:46,223 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7072 states and 10109 transitions. [2022-07-14 16:03:46,223 INFO L374 stractBuchiCegarLoop]: Abstraction has 7072 states and 10109 transitions. [2022-07-14 16:03:46,223 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:03:46,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7072 states and 10109 transitions. [2022-07-14 16:03:46,236 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6944 [2022-07-14 16:03:46,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:46,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:46,237 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:46,238 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:46,238 INFO L752 eck$LassoCheckResult]: Stem: 94910#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 94860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 94797#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94220#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94216#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 94217#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94738#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94881#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94306#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94307#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94461#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 94325#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94326#L670 assume !(0 == ~M_E~0); 94701#L670-2 assume !(0 == ~T1_E~0); 94645#L675-1 assume !(0 == ~T2_E~0); 94646#L680-1 assume !(0 == ~T3_E~0); 94737#L685-1 assume !(0 == ~T4_E~0); 94704#L690-1 assume !(0 == ~T5_E~0); 94705#L695-1 assume !(0 == ~T6_E~0); 94773#L700-1 assume !(0 == ~E_1~0); 94762#L705-1 assume !(0 == ~E_2~0); 94763#L710-1 assume !(0 == ~E_3~0); 94643#L715-1 assume !(0 == ~E_4~0); 94565#L720-1 assume !(0 == ~E_5~0); 94566#L725-1 assume !(0 == ~E_6~0); 94622#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94671#L320 assume !(1 == ~m_pc~0); 94794#L320-2 is_master_triggered_~__retres1~0#1 := 0; 94500#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94501#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94462#L825 assume !(0 != activate_threads_~tmp~1#1); 94463#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94467#L339 assume !(1 == ~t1_pc~0); 94468#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94447#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94448#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94328#L833 assume !(0 != activate_threads_~tmp___0~0#1); 94329#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94241#L358 assume !(1 == ~t2_pc~0); 94242#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94756#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94702#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94626#L841 assume !(0 != activate_threads_~tmp___1~0#1); 94457#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94458#L377 assume !(1 == ~t3_pc~0); 94720#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94721#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94716#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 94465#L849 assume !(0 != activate_threads_~tmp___2~0#1); 94466#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94414#L396 assume !(1 == ~t4_pc~0); 94415#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94243#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94244#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94660#L857 assume !(0 != activate_threads_~tmp___3~0#1); 94382#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94383#L415 assume !(1 == ~t5_pc~0); 94449#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94489#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94672#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94802#L865 assume !(0 != activate_threads_~tmp___4~0#1); 94284#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94285#L434 assume !(1 == ~t6_pc~0); 94599#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 94600#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94900#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94750#L873 assume !(0 != activate_threads_~tmp___5~0#1); 94477#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94478#L743 assume !(1 == ~M_E~0); 94374#L743-2 assume !(1 == ~T1_E~0); 94375#L748-1 assume !(1 == ~T2_E~0); 94663#L753-1 assume !(1 == ~T3_E~0); 94664#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94776#L763-1 assume !(1 == ~T5_E~0); 94825#L768-1 assume !(1 == ~T6_E~0); 94471#L773-1 assume !(1 == ~E_1~0); 94472#L778-1 assume !(1 == ~E_2~0); 94454#L783-1 assume !(1 == ~E_3~0); 94455#L788-1 assume !(1 == ~E_4~0); 94735#L793-1 assume !(1 == ~E_5~0); 94694#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 94345#L803-1 assume { :end_inline_reset_delta_events } true; 94346#L1024-2 [2022-07-14 16:03:46,238 INFO L754 eck$LassoCheckResult]: Loop: 94346#L1024-2 assume !false; 98278#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98270#L645 assume !false; 98267#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98264#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98255#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98252#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 98250#L556 assume !(0 != eval_~tmp~0#1); 94897#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94755#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94337#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94338#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94496#L675-3 assume !(0 == ~T2_E~0); 94497#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94730#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94731#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94885#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94741#L700-3 assume !(0 == ~E_1~0); 94742#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 94397#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94398#L715-3 assume !(0 == ~E_4~0); 94627#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94628#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94706#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94473#L320-21 assume !(1 == ~m_pc~0); 94474#L320-23 is_master_triggered_~__retres1~0#1 := 0; 94625#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94550#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94551#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94812#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94409#L339-21 assume 1 == ~t1_pc~0; 94411#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 94508#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101210#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94266#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94267#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98676#L358-21 assume !(1 == ~t2_pc~0); 98671#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 98666#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98660#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98654#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98648#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98574#L377-21 assume 1 == ~t3_pc~0; 98571#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 98568#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98566#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98564#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98562#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98560#L396-21 assume !(1 == ~t4_pc~0); 98558#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 98556#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98553#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98551#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 98549#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98547#L415-21 assume !(1 == ~t5_pc~0); 98545#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 98543#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98540#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98538#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98536#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98454#L434-21 assume !(1 == ~t6_pc~0); 98450#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 98448#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98446#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98444#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 98441#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98439#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98437#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98435#L748-3 assume !(1 == ~T2_E~0); 98433#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98430#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98428#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98426#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98422#L773-3 assume !(1 == ~E_1~0); 98420#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98418#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98416#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98406#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98368#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98365#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98353#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98335#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98326#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 98316#L1043 assume !(0 == start_simulation_~tmp~3#1); 98313#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98301#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98296#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98295#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 98294#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98292#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98290#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 98288#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 94346#L1024-2 [2022-07-14 16:03:46,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:46,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1707436903, now seen corresponding path program 1 times [2022-07-14 16:03:46,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:46,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298213708] [2022-07-14 16:03:46,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:46,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:46,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:46,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:46,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:46,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298213708] [2022-07-14 16:03:46,264 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298213708] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:46,264 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:46,264 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:46,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74201046] [2022-07-14 16:03:46,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:46,265 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:46,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:46,266 INFO L85 PathProgramCache]: Analyzing trace with hash -1907061346, now seen corresponding path program 1 times [2022-07-14 16:03:46,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:46,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799303040] [2022-07-14 16:03:46,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:46,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:46,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:46,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:46,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:46,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799303040] [2022-07-14 16:03:46,284 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799303040] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:46,284 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:46,284 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:46,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16829158] [2022-07-14 16:03:46,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:46,285 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:46,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:46,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:46,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:46,286 INFO L87 Difference]: Start difference. First operand 7072 states and 10109 transitions. cyclomatic complexity: 3045 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:46,379 INFO L93 Difference]: Finished difference Result 15151 states and 21603 transitions. [2022-07-14 16:03:46,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:46,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15151 states and 21603 transitions. [2022-07-14 16:03:46,436 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14912 [2022-07-14 16:03:46,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15151 states to 15151 states and 21603 transitions. [2022-07-14 16:03:46,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15151 [2022-07-14 16:03:46,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15151 [2022-07-14 16:03:46,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15151 states and 21603 transitions. [2022-07-14 16:03:46,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:46,509 INFO L369 hiAutomatonCegarLoop]: Abstraction has 15151 states and 21603 transitions. [2022-07-14 16:03:46,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15151 states and 21603 transitions. [2022-07-14 16:03:46,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15151 to 8158. [2022-07-14 16:03:46,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8158 states, 8158 states have (on average 1.426084824711939) internal successors, (11634), 8157 states have internal predecessors, (11634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8158 states to 8158 states and 11634 transitions. [2022-07-14 16:03:46,634 INFO L392 hiAutomatonCegarLoop]: Abstraction has 8158 states and 11634 transitions. [2022-07-14 16:03:46,634 INFO L374 stractBuchiCegarLoop]: Abstraction has 8158 states and 11634 transitions. [2022-07-14 16:03:46,634 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:03:46,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8158 states and 11634 transitions. [2022-07-14 16:03:46,659 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7968 [2022-07-14 16:03:46,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:46,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:46,660 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:46,661 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:46,661 INFO L752 eck$LassoCheckResult]: Stem: 117230#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 117160#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 117076#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116453#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116449#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 116450#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117001#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117191#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116539#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 116540#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116692#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116558#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116559#L670 assume !(0 == ~M_E~0); 116953#L670-2 assume !(0 == ~T1_E~0); 116890#L675-1 assume !(0 == ~T2_E~0); 116891#L680-1 assume !(0 == ~T3_E~0); 116998#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116956#L690-1 assume !(0 == ~T5_E~0); 116957#L695-1 assume !(0 == ~T6_E~0); 117044#L700-1 assume !(0 == ~E_1~0); 117045#L705-1 assume !(0 == ~E_2~0); 117182#L710-1 assume !(0 == ~E_3~0); 116887#L715-1 assume !(0 == ~E_4~0); 116888#L720-1 assume !(0 == ~E_5~0); 116864#L725-1 assume !(0 == ~E_6~0); 116865#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117070#L320 assume !(1 == ~m_pc~0); 117071#L320-2 is_master_triggered_~__retres1~0#1 := 0; 116737#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116738#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116693#L825 assume !(0 != activate_threads_~tmp~1#1); 116694#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116698#L339 assume !(1 == ~t1_pc~0); 116699#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 116678#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116679#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 116561#L833 assume !(0 != activate_threads_~tmp___0~0#1); 116562#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116474#L358 assume !(1 == ~t2_pc~0); 116475#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117247#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116954#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116869#L841 assume !(0 != activate_threads_~tmp___1~0#1); 116688#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116689#L377 assume !(1 == ~t3_pc~0); 116970#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116971#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116965#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116966#L849 assume !(0 != activate_threads_~tmp___2~0#1); 116994#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116995#L396 assume !(1 == ~t4_pc~0); 117244#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 116476#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116477#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117243#L857 assume !(0 != activate_threads_~tmp___3~0#1); 116616#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116617#L415 assume !(1 == ~t5_pc~0); 116680#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 116921#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116922#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117083#L865 assume !(0 != activate_threads_~tmp___4~0#1); 117084#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116972#L434 assume !(1 == ~t6_pc~0); 116973#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 117239#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117240#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117016#L873 assume !(0 != activate_threads_~tmp___5~0#1); 117017#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117171#L743 assume !(1 == ~M_E~0); 117172#L743-2 assume !(1 == ~T1_E~0); 117241#L748-1 assume !(1 == ~T2_E~0); 116913#L753-1 assume !(1 == ~T3_E~0); 116914#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117052#L763-1 assume !(1 == ~T5_E~0); 117115#L768-1 assume !(1 == ~T6_E~0); 116704#L773-1 assume !(1 == ~E_1~0); 116705#L778-1 assume !(1 == ~E_2~0); 116685#L783-1 assume !(1 == ~E_3~0); 116686#L788-1 assume !(1 == ~E_4~0); 116996#L793-1 assume !(1 == ~E_5~0); 116945#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 116578#L803-1 assume { :end_inline_reset_delta_events } true; 116579#L1024-2 [2022-07-14 16:03:46,661 INFO L754 eck$LassoCheckResult]: Loop: 116579#L1024-2 assume !false; 117129#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116941#L645 assume !false; 117116#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 119771#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 119763#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 119761#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 119758#L556 assume !(0 != eval_~tmp~0#1); 119759#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123307#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123306#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 123305#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123304#L675-3 assume !(0 == ~T2_E~0); 123303#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123301#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123300#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123299#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123298#L700-3 assume !(0 == ~E_1~0); 123297#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123296#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123295#L715-3 assume !(0 == ~E_4~0); 123294#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123293#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123292#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123291#L320-21 assume !(1 == ~m_pc~0); 123290#L320-23 is_master_triggered_~__retres1~0#1 := 0; 123289#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123288#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123287#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123286#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123285#L339-21 assume !(1 == ~t1_pc~0); 123283#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 123282#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123281#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123280#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123279#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123278#L358-21 assume !(1 == ~t2_pc~0); 122909#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 123277#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123276#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 123275#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123274#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123273#L377-21 assume !(1 == ~t3_pc~0); 123271#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 123270#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123269#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 123268#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123267#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123266#L396-21 assume !(1 == ~t4_pc~0); 123265#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 123264#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123263#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123262#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 123261#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123260#L415-21 assume !(1 == ~t5_pc~0); 123259#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 123258#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123257#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123256#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 123255#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123254#L434-21 assume !(1 == ~t6_pc~0); 123253#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 123251#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123249#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123247#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 123245#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123244#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 123243#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 123242#L748-3 assume !(1 == ~T2_E~0); 123241#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123239#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123238#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 123236#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123234#L773-3 assume !(1 == ~E_1~0); 123232#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123230#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123228#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123225#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123223#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123221#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 123212#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 123207#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 123205#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 123146#L1043 assume !(0 == start_simulation_~tmp~3#1); 123144#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 123135#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 123129#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 123128#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 123127#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123125#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123123#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 123121#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 116579#L1024-2 [2022-07-14 16:03:46,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:46,662 INFO L85 PathProgramCache]: Analyzing trace with hash -975469477, now seen corresponding path program 1 times [2022-07-14 16:03:46,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:46,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653797368] [2022-07-14 16:03:46,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:46,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:46,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:46,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:46,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:46,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653797368] [2022-07-14 16:03:46,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653797368] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:46,719 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:46,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:46,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316729431] [2022-07-14 16:03:46,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:46,720 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:46,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:46,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1817672484, now seen corresponding path program 1 times [2022-07-14 16:03:46,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:46,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699196974] [2022-07-14 16:03:46,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:46,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:46,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:46,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:46,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699196974] [2022-07-14 16:03:46,743 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1699196974] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:46,743 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:46,743 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:46,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543235330] [2022-07-14 16:03:46,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:46,743 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:46,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:46,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:46,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:46,744 INFO L87 Difference]: Start difference. First operand 8158 states and 11634 transitions. cyclomatic complexity: 3484 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:46,787 INFO L93 Difference]: Finished difference Result 7072 states and 10059 transitions. [2022-07-14 16:03:46,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:46,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7072 states and 10059 transitions. [2022-07-14 16:03:46,814 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6944 [2022-07-14 16:03:46,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7072 states to 7072 states and 10059 transitions. [2022-07-14 16:03:46,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7072 [2022-07-14 16:03:46,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7072 [2022-07-14 16:03:46,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7072 states and 10059 transitions. [2022-07-14 16:03:46,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:46,844 INFO L369 hiAutomatonCegarLoop]: Abstraction has 7072 states and 10059 transitions. [2022-07-14 16:03:46,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7072 states and 10059 transitions. [2022-07-14 16:03:46,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7072 to 7072. [2022-07-14 16:03:46,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7072 states, 7072 states have (on average 1.4223699095022624) internal successors, (10059), 7071 states have internal predecessors, (10059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:46,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7072 states to 7072 states and 10059 transitions. [2022-07-14 16:03:46,927 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7072 states and 10059 transitions. [2022-07-14 16:03:46,927 INFO L374 stractBuchiCegarLoop]: Abstraction has 7072 states and 10059 transitions. [2022-07-14 16:03:46,928 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:03:46,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7072 states and 10059 transitions. [2022-07-14 16:03:46,942 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6944 [2022-07-14 16:03:46,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:46,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:46,943 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:46,943 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:46,944 INFO L752 eck$LassoCheckResult]: Stem: 132399#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 132347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 132282#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131695#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131691#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 131692#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132215#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132370#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131783#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131784#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131936#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131802#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131803#L670 assume !(0 == ~M_E~0); 132180#L670-2 assume !(0 == ~T1_E~0); 132126#L675-1 assume !(0 == ~T2_E~0); 132127#L680-1 assume !(0 == ~T3_E~0); 132214#L685-1 assume !(0 == ~T4_E~0); 132183#L690-1 assume !(0 == ~T5_E~0); 132184#L695-1 assume !(0 == ~T6_E~0); 132252#L700-1 assume !(0 == ~E_1~0); 132240#L705-1 assume !(0 == ~E_2~0); 132241#L710-1 assume !(0 == ~E_3~0); 132124#L715-1 assume !(0 == ~E_4~0); 132043#L720-1 assume !(0 == ~E_5~0); 132044#L725-1 assume !(0 == ~E_6~0); 132101#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132151#L320 assume !(1 == ~m_pc~0); 132272#L320-2 is_master_triggered_~__retres1~0#1 := 0; 131976#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131977#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131937#L825 assume !(0 != activate_threads_~tmp~1#1); 131938#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131942#L339 assume !(1 == ~t1_pc~0); 131943#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131922#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131923#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131805#L833 assume !(0 != activate_threads_~tmp___0~0#1); 131806#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131716#L358 assume !(1 == ~t2_pc~0); 131717#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132235#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132181#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 132107#L841 assume !(0 != activate_threads_~tmp___1~0#1); 131934#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131935#L377 assume !(1 == ~t3_pc~0); 132198#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132199#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132194#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 131940#L849 assume !(0 != activate_threads_~tmp___2~0#1); 131941#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131889#L396 assume !(1 == ~t4_pc~0); 131890#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131718#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131719#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132142#L857 assume !(0 != activate_threads_~tmp___3~0#1); 131860#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131861#L415 assume !(1 == ~t5_pc~0); 131924#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131966#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132152#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132287#L865 assume !(0 != activate_threads_~tmp___4~0#1); 131761#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131762#L434 assume !(1 == ~t6_pc~0); 132078#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 132079#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132390#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 132229#L873 assume !(0 != activate_threads_~tmp___5~0#1); 131952#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131953#L743 assume !(1 == ~M_E~0); 131850#L743-2 assume !(1 == ~T1_E~0); 131851#L748-1 assume !(1 == ~T2_E~0); 132145#L753-1 assume !(1 == ~T3_E~0); 132146#L758-1 assume !(1 == ~T4_E~0); 132255#L763-1 assume !(1 == ~T5_E~0); 132312#L768-1 assume !(1 == ~T6_E~0); 131946#L773-1 assume !(1 == ~E_1~0); 131947#L778-1 assume !(1 == ~E_2~0); 131929#L783-1 assume !(1 == ~E_3~0); 131930#L788-1 assume !(1 == ~E_4~0); 132212#L793-1 assume !(1 == ~E_5~0); 132174#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 131822#L803-1 assume { :end_inline_reset_delta_events } true; 131823#L1024-2 [2022-07-14 16:03:46,944 INFO L754 eck$LassoCheckResult]: Loop: 131823#L1024-2 assume !false; 134209#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134203#L645 assume !false; 134200#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 134198#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 134190#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 134188#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134185#L556 assume !(0 != eval_~tmp~0#1); 134186#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138137#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138136#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 138135#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 138134#L675-3 assume !(0 == ~T2_E~0); 138133#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138132#L685-3 assume !(0 == ~T4_E~0); 138131#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138129#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138127#L700-3 assume !(0 == ~E_1~0); 138124#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138121#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138117#L715-3 assume !(0 == ~E_4~0); 138114#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138112#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138109#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138106#L320-21 assume !(1 == ~m_pc~0); 138104#L320-23 is_master_triggered_~__retres1~0#1 := 0; 138102#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138101#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137987#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 137986#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137985#L339-21 assume 1 == ~t1_pc~0; 137984#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 137982#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137981#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 137980#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 137979#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134482#L358-21 assume !(1 == ~t2_pc~0); 134480#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 134478#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134474#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 134472#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134470#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134468#L377-21 assume !(1 == ~t3_pc~0); 134464#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 134462#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134458#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134456#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134454#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134449#L396-21 assume !(1 == ~t4_pc~0); 134445#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 134441#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134440#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134439#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 134438#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134437#L415-21 assume !(1 == ~t5_pc~0); 134436#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 134435#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134434#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134433#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 134432#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134431#L434-21 assume 1 == ~t6_pc~0; 134430#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 134429#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134427#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134423#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134421#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134418#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134416#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134414#L748-3 assume !(1 == ~T2_E~0); 134412#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 134410#L758-3 assume !(1 == ~T4_E~0); 134408#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134405#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134403#L773-3 assume !(1 == ~E_1~0); 134401#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134399#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 134397#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 134396#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 134395#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134394#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 134390#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 134386#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 134385#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 134240#L1043 assume !(0 == start_simulation_~tmp~3#1); 134238#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 134229#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 134223#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 134221#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 134218#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134216#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134214#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 134212#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 131823#L1024-2 [2022-07-14 16:03:46,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:46,944 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463913, now seen corresponding path program 1 times [2022-07-14 16:03:46,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:46,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431727430] [2022-07-14 16:03:46,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:46,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:46,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:46,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:46,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:46,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431727430] [2022-07-14 16:03:46,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431727430] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:46,969 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:46,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:46,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908087358] [2022-07-14 16:03:46,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:46,970 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:46,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:46,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1305955740, now seen corresponding path program 1 times [2022-07-14 16:03:46,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:46,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972820981] [2022-07-14 16:03:46,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:46,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:46,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:46,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:46,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:46,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972820981] [2022-07-14 16:03:46,990 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972820981] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:46,990 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:46,990 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:46,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650079967] [2022-07-14 16:03:46,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:46,991 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:46,991 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:46,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:46,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:46,991 INFO L87 Difference]: Start difference. First operand 7072 states and 10059 transitions. cyclomatic complexity: 2995 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:47,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:47,103 INFO L93 Difference]: Finished difference Result 14266 states and 20124 transitions. [2022-07-14 16:03:47,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:47,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14266 states and 20124 transitions. [2022-07-14 16:03:47,162 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14012 [2022-07-14 16:03:47,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14266 states to 14266 states and 20124 transitions. [2022-07-14 16:03:47,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14266 [2022-07-14 16:03:47,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14266 [2022-07-14 16:03:47,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14266 states and 20124 transitions. [2022-07-14 16:03:47,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:47,227 INFO L369 hiAutomatonCegarLoop]: Abstraction has 14266 states and 20124 transitions. [2022-07-14 16:03:47,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14266 states and 20124 transitions. [2022-07-14 16:03:47,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14266 to 7891. [2022-07-14 16:03:47,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7891 states, 7891 states have (on average 1.4116081611962996) internal successors, (11139), 7890 states have internal predecessors, (11139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:47,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7891 states to 7891 states and 11139 transitions. [2022-07-14 16:03:47,351 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7891 states and 11139 transitions. [2022-07-14 16:03:47,351 INFO L374 stractBuchiCegarLoop]: Abstraction has 7891 states and 11139 transitions. [2022-07-14 16:03:47,351 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:03:47,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7891 states and 11139 transitions. [2022-07-14 16:03:47,371 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7704 [2022-07-14 16:03:47,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:47,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:47,372 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:47,372 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:47,372 INFO L752 eck$LassoCheckResult]: Stem: 153825#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 153755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 153673#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153043#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153039#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 153040#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 153599#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 153783#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 153129#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153130#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153285#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 153148#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153149#L670 assume !(0 == ~M_E~0); 153544#L670-2 assume !(0 == ~T1_E~0); 153482#L675-1 assume !(0 == ~T2_E~0); 153483#L680-1 assume !(0 == ~T3_E~0); 153598#L685-1 assume !(0 == ~T4_E~0); 153550#L690-1 assume !(0 == ~T5_E~0); 153551#L695-1 assume !(0 == ~T6_E~0); 153642#L700-1 assume !(0 == ~E_1~0); 153631#L705-1 assume !(0 == ~E_2~0); 153632#L710-1 assume !(0 == ~E_3~0); 153479#L715-1 assume !(0 == ~E_4~0); 153397#L720-1 assume !(0 == ~E_5~0); 153398#L725-1 assume 0 == ~E_6~0;~E_6~0 := 1; 153457#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153667#L320 assume !(1 == ~m_pc~0); 153668#L320-2 is_master_triggered_~__retres1~0#1 := 0; 153330#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153331#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 153859#L825 assume !(0 != activate_threads_~tmp~1#1); 153696#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153697#L339 assume !(1 == ~t1_pc~0); 153501#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153502#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153645#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 153646#L833 assume !(0 != activate_threads_~tmp___0~0#1); 153766#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153767#L358 assume !(1 == ~t2_pc~0); 153624#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153625#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153753#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 153462#L841 assume !(0 != activate_threads_~tmp___1~0#1); 153281#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153282#L377 assume !(1 == ~t3_pc~0); 153577#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 153578#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153572#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153573#L849 assume !(0 != activate_threads_~tmp___2~0#1); 153594#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153595#L396 assume !(1 == ~t4_pc~0); 153854#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153066#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153067#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153853#L857 assume !(0 != activate_threads_~tmp___3~0#1); 153204#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153205#L415 assume !(1 == ~t5_pc~0); 153315#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153316#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153802#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153803#L865 assume !(0 != activate_threads_~tmp___4~0#1); 153107#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153108#L434 assume !(1 == ~t6_pc~0); 153852#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 153857#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153856#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153847#L873 assume !(0 != activate_threads_~tmp___5~0#1); 153846#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153845#L743 assume !(1 == ~M_E~0); 153844#L743-2 assume !(1 == ~T1_E~0); 153843#L748-1 assume !(1 == ~T2_E~0); 153842#L753-1 assume !(1 == ~T3_E~0); 153841#L758-1 assume !(1 == ~T4_E~0); 153840#L763-1 assume !(1 == ~T5_E~0); 153839#L768-1 assume !(1 == ~T6_E~0); 153838#L773-1 assume !(1 == ~E_1~0); 153837#L778-1 assume !(1 == ~E_2~0); 153836#L783-1 assume !(1 == ~E_3~0); 153835#L788-1 assume !(1 == ~E_4~0); 153834#L793-1 assume !(1 == ~E_5~0); 153833#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 153168#L803-1 assume { :end_inline_reset_delta_events } true; 153169#L1024-2 [2022-07-14 16:03:47,373 INFO L754 eck$LassoCheckResult]: Loop: 153169#L1024-2 assume !false; 158105#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 158098#L645 assume !false; 158096#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158094#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158086#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 157336#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 157329#L556 assume !(0 != eval_~tmp~0#1); 157330#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 158329#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 158327#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 158325#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 158323#L675-3 assume !(0 == ~T2_E~0); 158321#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 158319#L685-3 assume !(0 == ~T4_E~0); 158317#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 158315#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 158313#L700-3 assume !(0 == ~E_1~0); 158311#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 158309#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 158307#L715-3 assume !(0 == ~E_4~0); 158305#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 158302#L725-3 assume !(0 == ~E_6~0); 158303#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160507#L320-21 assume !(1 == ~m_pc~0); 160505#L320-23 is_master_triggered_~__retres1~0#1 := 0; 160502#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160500#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 160498#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 160496#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160494#L339-21 assume !(1 == ~t1_pc~0); 160491#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 160488#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160486#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160484#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 160482#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158402#L358-21 assume !(1 == ~t2_pc~0); 158400#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 158398#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158396#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 158394#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 158392#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158388#L377-21 assume 1 == ~t3_pc~0; 158386#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 158384#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158383#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158382#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158374#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158372#L396-21 assume !(1 == ~t4_pc~0); 158370#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 158368#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158366#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158364#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 158362#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158360#L415-21 assume !(1 == ~t5_pc~0); 158355#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 158353#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158351#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158343#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 158341#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158339#L434-21 assume !(1 == ~t6_pc~0); 158261#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 158332#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158331#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158330#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 158328#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158326#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 158324#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 158322#L748-3 assume !(1 == ~T2_E~0); 158320#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 158318#L758-3 assume !(1 == ~T4_E~0); 158316#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158314#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158312#L773-3 assume !(1 == ~E_1~0); 158310#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 158308#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 158306#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 158304#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 158240#L798-3 assume !(1 == ~E_6~0); 158236#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158227#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158223#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158221#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 158139#L1043 assume !(0 == start_simulation_~tmp~3#1); 158136#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158129#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158123#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158119#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 158117#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 158115#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 158111#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 158108#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 153169#L1024-2 [2022-07-14 16:03:47,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:47,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1760774297, now seen corresponding path program 1 times [2022-07-14 16:03:47,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:47,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682951586] [2022-07-14 16:03:47,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:47,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:47,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:47,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:47,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:47,395 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682951586] [2022-07-14 16:03:47,395 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682951586] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:47,395 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:47,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:47,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003123022] [2022-07-14 16:03:47,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:47,396 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:47,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:47,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1867893493, now seen corresponding path program 1 times [2022-07-14 16:03:47,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:47,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393593649] [2022-07-14 16:03:47,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:47,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:47,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:47,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:47,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:47,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393593649] [2022-07-14 16:03:47,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393593649] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:47,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:47,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:47,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204775277] [2022-07-14 16:03:47,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:47,420 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:47,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:47,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:47,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:47,420 INFO L87 Difference]: Start difference. First operand 7891 states and 11139 transitions. cyclomatic complexity: 3256 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:47,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:47,524 INFO L93 Difference]: Finished difference Result 9997 states and 14096 transitions. [2022-07-14 16:03:47,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:47,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9997 states and 14096 transitions. [2022-07-14 16:03:47,555 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9852 [2022-07-14 16:03:47,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9997 states to 9997 states and 14096 transitions. [2022-07-14 16:03:47,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9997 [2022-07-14 16:03:47,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9997 [2022-07-14 16:03:47,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9997 states and 14096 transitions. [2022-07-14 16:03:47,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:47,588 INFO L369 hiAutomatonCegarLoop]: Abstraction has 9997 states and 14096 transitions. [2022-07-14 16:03:47,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9997 states and 14096 transitions. [2022-07-14 16:03:47,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9997 to 6805. [2022-07-14 16:03:47,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6805 states, 6805 states have (on average 1.4054371785451873) internal successors, (9564), 6804 states have internal predecessors, (9564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:47,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6805 states to 6805 states and 9564 transitions. [2022-07-14 16:03:47,665 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6805 states and 9564 transitions. [2022-07-14 16:03:47,665 INFO L374 stractBuchiCegarLoop]: Abstraction has 6805 states and 9564 transitions. [2022-07-14 16:03:47,665 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:03:47,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6805 states and 9564 transitions. [2022-07-14 16:03:47,680 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6680 [2022-07-14 16:03:47,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:47,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:47,681 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:47,681 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:47,681 INFO L752 eck$LassoCheckResult]: Stem: 171615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 171575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 171521#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 170943#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170939#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 170940#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 171466#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171594#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 171032#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 171033#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171181#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 171050#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 171051#L670 assume !(0 == ~M_E~0); 171426#L670-2 assume !(0 == ~T1_E~0); 171371#L675-1 assume !(0 == ~T2_E~0); 171372#L680-1 assume !(0 == ~T3_E~0); 171464#L685-1 assume !(0 == ~T4_E~0); 171430#L690-1 assume !(0 == ~T5_E~0); 171431#L695-1 assume !(0 == ~T6_E~0); 171502#L700-1 assume !(0 == ~E_1~0); 171491#L705-1 assume !(0 == ~E_2~0); 171492#L710-1 assume !(0 == ~E_3~0); 171370#L715-1 assume !(0 == ~E_4~0); 171293#L720-1 assume !(0 == ~E_5~0); 171294#L725-1 assume !(0 == ~E_6~0); 171348#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171396#L320 assume !(1 == ~m_pc~0); 171518#L320-2 is_master_triggered_~__retres1~0#1 := 0; 171225#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 171226#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 171182#L825 assume !(0 != activate_threads_~tmp~1#1); 171183#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171191#L339 assume !(1 == ~t1_pc~0); 171192#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 171167#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171168#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171052#L833 assume !(0 != activate_threads_~tmp___0~0#1); 171053#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170964#L358 assume !(1 == ~t2_pc~0); 170965#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 171485#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171427#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 171352#L841 assume !(0 != activate_threads_~tmp___1~0#1); 171179#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171180#L377 assume !(1 == ~t3_pc~0); 171447#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 171448#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171446#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 171186#L849 assume !(0 != activate_threads_~tmp___2~0#1); 171187#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171138#L396 assume !(1 == ~t4_pc~0); 171139#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 170966#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 170967#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 171385#L857 assume !(0 != activate_threads_~tmp___3~0#1); 171105#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171106#L415 assume !(1 == ~t5_pc~0); 171170#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 171214#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 171397#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 171526#L865 assume !(0 != activate_threads_~tmp___4~0#1); 171008#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 171009#L434 assume !(1 == ~t6_pc~0); 171327#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 171328#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171476#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 171477#L873 assume !(0 != activate_threads_~tmp___5~0#1); 171200#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171201#L743 assume !(1 == ~M_E~0); 171097#L743-2 assume !(1 == ~T1_E~0); 171098#L748-1 assume !(1 == ~T2_E~0); 171390#L753-1 assume !(1 == ~T3_E~0); 171391#L758-1 assume !(1 == ~T4_E~0); 171505#L763-1 assume !(1 == ~T5_E~0); 171547#L768-1 assume !(1 == ~T6_E~0); 171198#L773-1 assume !(1 == ~E_1~0); 171199#L778-1 assume !(1 == ~E_2~0); 171174#L783-1 assume !(1 == ~E_3~0); 171175#L788-1 assume !(1 == ~E_4~0); 171461#L793-1 assume !(1 == ~E_5~0); 171419#L798-1 assume !(1 == ~E_6~0); 171071#L803-1 assume { :end_inline_reset_delta_events } true; 171072#L1024-2 [2022-07-14 16:03:47,682 INFO L754 eck$LassoCheckResult]: Loop: 171072#L1024-2 assume !false; 175640#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175624#L645 assume !false; 175618#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175439#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175432#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175398#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 175390#L556 assume !(0 != eval_~tmp~0#1); 175391#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176973#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176972#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176971#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176970#L675-3 assume !(0 == ~T2_E~0); 176969#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176968#L685-3 assume !(0 == ~T4_E~0); 176967#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 176966#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 176965#L700-3 assume !(0 == ~E_1~0); 176964#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176963#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176962#L715-3 assume !(0 == ~E_4~0); 176961#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176960#L725-3 assume !(0 == ~E_6~0); 176959#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176958#L320-21 assume !(1 == ~m_pc~0); 176957#L320-23 is_master_triggered_~__retres1~0#1 := 0; 176956#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176955#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176954#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176952#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176950#L339-21 assume !(1 == ~t1_pc~0); 176947#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 176890#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176888#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176886#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176884#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176095#L358-21 assume !(1 == ~t2_pc~0); 176094#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 176008#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176001#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 175995#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 175984#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175981#L377-21 assume !(1 == ~t3_pc~0); 175978#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 175976#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175974#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175972#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 175970#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175967#L396-21 assume !(1 == ~t4_pc~0); 175965#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 175963#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175961#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175959#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 175957#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 175954#L415-21 assume !(1 == ~t5_pc~0); 175952#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 175950#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 175938#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 175933#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 175928#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 175924#L434-21 assume !(1 == ~t6_pc~0); 175918#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 175914#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175911#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 175906#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 175905#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175904#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 175903#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 175902#L748-3 assume !(1 == ~T2_E~0); 175900#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175898#L758-3 assume !(1 == ~T4_E~0); 175896#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 175895#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175894#L773-3 assume !(1 == ~E_1~0); 175893#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 175891#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175889#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175887#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 175885#L798-3 assume !(1 == ~E_6~0); 175883#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175872#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175867#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175865#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 175803#L1043 assume !(0 == start_simulation_~tmp~3#1); 175801#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175794#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175788#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175757#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 175751#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 175745#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175738#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 175734#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 171072#L1024-2 [2022-07-14 16:03:47,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:47,682 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2022-07-14 16:03:47,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:47,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862247214] [2022-07-14 16:03:47,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:47,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:47,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:47,689 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:47,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:47,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:47,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:47,726 INFO L85 PathProgramCache]: Analyzing trace with hash 137556436, now seen corresponding path program 1 times [2022-07-14 16:03:47,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:47,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796257568] [2022-07-14 16:03:47,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:47,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:47,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:47,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:47,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:47,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796257568] [2022-07-14 16:03:47,752 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796257568] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:47,752 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:47,752 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:47,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070641623] [2022-07-14 16:03:47,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:47,752 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:47,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:47,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:47,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:47,753 INFO L87 Difference]: Start difference. First operand 6805 states and 9564 transitions. cyclomatic complexity: 2767 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:47,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:47,844 INFO L93 Difference]: Finished difference Result 12165 states and 16868 transitions. [2022-07-14 16:03:47,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:03:47,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12165 states and 16868 transitions. [2022-07-14 16:03:47,888 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12000 [2022-07-14 16:03:47,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12165 states to 12165 states and 16868 transitions. [2022-07-14 16:03:47,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12165 [2022-07-14 16:03:47,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12165 [2022-07-14 16:03:47,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12165 states and 16868 transitions. [2022-07-14 16:03:47,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:47,932 INFO L369 hiAutomatonCegarLoop]: Abstraction has 12165 states and 16868 transitions. [2022-07-14 16:03:47,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12165 states and 16868 transitions. [2022-07-14 16:03:47,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12165 to 6853. [2022-07-14 16:03:48,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6853 states, 6853 states have (on average 1.4025974025974026) internal successors, (9612), 6852 states have internal predecessors, (9612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:48,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6853 states to 6853 states and 9612 transitions. [2022-07-14 16:03:48,017 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6853 states and 9612 transitions. [2022-07-14 16:03:48,017 INFO L374 stractBuchiCegarLoop]: Abstraction has 6853 states and 9612 transitions. [2022-07-14 16:03:48,017 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 16:03:48,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6853 states and 9612 transitions. [2022-07-14 16:03:48,029 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6728 [2022-07-14 16:03:48,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:48,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:48,030 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:48,030 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:48,030 INFO L752 eck$LassoCheckResult]: Stem: 190637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 190587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 190516#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 189929#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189925#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 189926#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 190450#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 190618#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 190018#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 190019#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 190167#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 190036#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190037#L670 assume !(0 == ~M_E~0); 190410#L670-2 assume !(0 == ~T1_E~0); 190356#L675-1 assume !(0 == ~T2_E~0); 190357#L680-1 assume !(0 == ~T3_E~0); 190448#L685-1 assume !(0 == ~T4_E~0); 190415#L690-1 assume !(0 == ~T5_E~0); 190416#L695-1 assume !(0 == ~T6_E~0); 190488#L700-1 assume !(0 == ~E_1~0); 190476#L705-1 assume !(0 == ~E_2~0); 190477#L710-1 assume !(0 == ~E_3~0); 190355#L715-1 assume !(0 == ~E_4~0); 190275#L720-1 assume !(0 == ~E_5~0); 190276#L725-1 assume !(0 == ~E_6~0); 190332#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190381#L320 assume !(1 == ~m_pc~0); 190512#L320-2 is_master_triggered_~__retres1~0#1 := 0; 190209#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190210#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 190168#L825 assume !(0 != activate_threads_~tmp~1#1); 190169#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190176#L339 assume !(1 == ~t1_pc~0); 190177#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 190153#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190154#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 190038#L833 assume !(0 != activate_threads_~tmp___0~0#1); 190039#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189950#L358 assume !(1 == ~t2_pc~0); 189951#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 190471#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190412#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190336#L841 assume !(0 != activate_threads_~tmp___1~0#1); 190165#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190166#L377 assume !(1 == ~t3_pc~0); 190432#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 190433#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 190431#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190171#L849 assume !(0 != activate_threads_~tmp___2~0#1); 190172#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190124#L396 assume !(1 == ~t4_pc~0); 190125#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 189952#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189953#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190371#L857 assume !(0 != activate_threads_~tmp___3~0#1); 190090#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190091#L415 assume !(1 == ~t5_pc~0); 190156#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190199#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190382#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 190521#L865 assume !(0 != activate_threads_~tmp___4~0#1); 189992#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189993#L434 assume !(1 == ~t6_pc~0); 190309#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 190310#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190460#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190461#L873 assume !(0 != activate_threads_~tmp___5~0#1); 190185#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190186#L743 assume !(1 == ~M_E~0); 190083#L743-2 assume !(1 == ~T1_E~0); 190084#L748-1 assume !(1 == ~T2_E~0); 190374#L753-1 assume !(1 == ~T3_E~0); 190375#L758-1 assume !(1 == ~T4_E~0); 190492#L763-1 assume !(1 == ~T5_E~0); 190549#L768-1 assume !(1 == ~T6_E~0); 190183#L773-1 assume !(1 == ~E_1~0); 190184#L778-1 assume !(1 == ~E_2~0); 190160#L783-1 assume !(1 == ~E_3~0); 190161#L788-1 assume !(1 == ~E_4~0); 190446#L793-1 assume !(1 == ~E_5~0); 190401#L798-1 assume !(1 == ~E_6~0); 190057#L803-1 assume { :end_inline_reset_delta_events } true; 190058#L1024-2 [2022-07-14 16:03:48,031 INFO L754 eck$LassoCheckResult]: Loop: 190058#L1024-2 assume !false; 193437#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193066#L645 assume !false; 192970#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 192613#L504 assume !(0 == ~m_st~0); 192608#L508 assume !(0 == ~t1_st~0); 192609#L512 assume !(0 == ~t2_st~0); 192611#L516 assume !(0 == ~t3_st~0); 192606#L520 assume !(0 == ~t4_st~0); 192607#L524 assume !(0 == ~t5_st~0); 192610#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 192612#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 192600#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 192601#L556 assume !(0 != eval_~tmp~0#1); 193675#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 193673#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 193671#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 193669#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 193667#L675-3 assume !(0 == ~T2_E~0); 193665#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 193663#L685-3 assume !(0 == ~T4_E~0); 193661#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 193659#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 193657#L700-3 assume !(0 == ~E_1~0); 193655#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 193653#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 193651#L715-3 assume !(0 == ~E_4~0); 193649#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 193647#L725-3 assume !(0 == ~E_6~0); 193645#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 193643#L320-21 assume !(1 == ~m_pc~0); 193641#L320-23 is_master_triggered_~__retres1~0#1 := 0; 193639#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 193637#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 193635#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 193633#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 193631#L339-21 assume !(1 == ~t1_pc~0); 193627#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 193625#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193623#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 193621#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 193619#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193616#L358-21 assume !(1 == ~t2_pc~0); 193615#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 193614#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193613#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 193612#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 193611#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193610#L377-21 assume !(1 == ~t3_pc~0); 193608#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 193607#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193606#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193605#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 193604#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193603#L396-21 assume !(1 == ~t4_pc~0); 193602#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 193601#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193600#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193599#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 193598#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193597#L415-21 assume !(1 == ~t5_pc~0); 193596#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 193595#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193594#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 193593#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 193592#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 193591#L434-21 assume !(1 == ~t6_pc~0); 193589#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 193588#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193587#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 193586#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 193585#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 193584#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 193583#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 193582#L748-3 assume !(1 == ~T2_E~0); 193581#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 193580#L758-3 assume !(1 == ~T4_E~0); 193579#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 193578#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 193577#L773-3 assume !(1 == ~E_1~0); 193576#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 193575#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 193574#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 193573#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 193572#L798-3 assume !(1 == ~E_6~0); 193571#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 193567#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 193562#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 193560#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 193556#L1043 assume !(0 == start_simulation_~tmp~3#1); 193521#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 193518#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 193512#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 193504#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 193456#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 193451#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 193449#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 193447#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 190058#L1024-2 [2022-07-14 16:03:48,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:48,031 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2022-07-14 16:03:48,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:48,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691635486] [2022-07-14 16:03:48,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:48,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:48,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:48,038 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:48,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:48,053 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:48,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:48,053 INFO L85 PathProgramCache]: Analyzing trace with hash 2141557411, now seen corresponding path program 1 times [2022-07-14 16:03:48,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:48,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667805813] [2022-07-14 16:03:48,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:48,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:48,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:48,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:48,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:48,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667805813] [2022-07-14 16:03:48,091 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667805813] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:48,091 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:48,091 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:48,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765614341] [2022-07-14 16:03:48,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:48,092 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:48,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:48,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:48,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:48,092 INFO L87 Difference]: Start difference. First operand 6853 states and 9612 transitions. cyclomatic complexity: 2767 Second operand has 5 states, 5 states have (on average 19.6) internal successors, (98), 5 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:48,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:48,243 INFO L93 Difference]: Finished difference Result 13641 states and 19003 transitions. [2022-07-14 16:03:48,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:48,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13641 states and 19003 transitions. [2022-07-14 16:03:48,297 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13484 [2022-07-14 16:03:48,335 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13641 states to 13641 states and 19003 transitions. [2022-07-14 16:03:48,335 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13641 [2022-07-14 16:03:48,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13641 [2022-07-14 16:03:48,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13641 states and 19003 transitions. [2022-07-14 16:03:48,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:48,355 INFO L369 hiAutomatonCegarLoop]: Abstraction has 13641 states and 19003 transitions. [2022-07-14 16:03:48,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13641 states and 19003 transitions. [2022-07-14 16:03:48,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13641 to 7009. [2022-07-14 16:03:48,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7009 states, 7009 states have (on average 1.3872164360108432) internal successors, (9723), 7008 states have internal predecessors, (9723), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:48,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7009 states to 7009 states and 9723 transitions. [2022-07-14 16:03:48,458 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7009 states and 9723 transitions. [2022-07-14 16:03:48,458 INFO L374 stractBuchiCegarLoop]: Abstraction has 7009 states and 9723 transitions. [2022-07-14 16:03:48,458 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 16:03:48,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7009 states and 9723 transitions. [2022-07-14 16:03:48,476 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6884 [2022-07-14 16:03:48,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:48,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:48,478 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:48,478 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:48,478 INFO L752 eck$LassoCheckResult]: Stem: 211165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 211114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 211042#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 210436#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 210432#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 210433#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210965#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 211141#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 210522#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 210523#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 210678#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 210541#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 210542#L670 assume !(0 == ~M_E~0); 210924#L670-2 assume !(0 == ~T1_E~0); 210866#L675-1 assume !(0 == ~T2_E~0); 210867#L680-1 assume !(0 == ~T3_E~0); 210964#L685-1 assume !(0 == ~T4_E~0); 210928#L690-1 assume !(0 == ~T5_E~0); 210929#L695-1 assume !(0 == ~T6_E~0); 211010#L700-1 assume !(0 == ~E_1~0); 210998#L705-1 assume !(0 == ~E_2~0); 210999#L710-1 assume !(0 == ~E_3~0); 210864#L715-1 assume !(0 == ~E_4~0); 210783#L720-1 assume !(0 == ~E_5~0); 210784#L725-1 assume !(0 == ~E_6~0); 210841#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210892#L320 assume !(1 == ~m_pc~0); 211034#L320-2 is_master_triggered_~__retres1~0#1 := 0; 210720#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210721#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 210679#L825 assume !(0 != activate_threads_~tmp~1#1); 210680#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210684#L339 assume !(1 == ~t1_pc~0); 210685#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 210663#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210664#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 210544#L833 assume !(0 != activate_threads_~tmp___0~0#1); 210545#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210457#L358 assume !(1 == ~t2_pc~0); 210458#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 210993#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210925#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 210846#L841 assume !(0 != activate_threads_~tmp___1~0#1); 210674#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210675#L377 assume !(1 == ~t3_pc~0); 210945#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 210946#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 210941#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 210682#L849 assume !(0 != activate_threads_~tmp___2~0#1); 210683#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 210628#L396 assume !(1 == ~t4_pc~0); 210629#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 210459#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 210460#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 210880#L857 assume !(0 != activate_threads_~tmp___3~0#1); 210598#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210599#L415 assume !(1 == ~t5_pc~0); 210665#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 210707#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 210893#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 211047#L865 assume !(0 != activate_threads_~tmp___4~0#1); 210500#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 210501#L434 assume !(1 == ~t6_pc~0); 210817#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 210818#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 210980#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 210981#L873 assume !(0 != activate_threads_~tmp___5~0#1); 210695#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210696#L743 assume !(1 == ~M_E~0); 210590#L743-2 assume !(1 == ~T1_E~0); 210591#L748-1 assume !(1 == ~T2_E~0); 210883#L753-1 assume !(1 == ~T3_E~0); 210884#L758-1 assume !(1 == ~T4_E~0); 211014#L763-1 assume !(1 == ~T5_E~0); 211075#L768-1 assume !(1 == ~T6_E~0); 210688#L773-1 assume !(1 == ~E_1~0); 210689#L778-1 assume !(1 == ~E_2~0); 210670#L783-1 assume !(1 == ~E_3~0); 210671#L788-1 assume !(1 == ~E_4~0); 210962#L793-1 assume !(1 == ~E_5~0); 210916#L798-1 assume !(1 == ~E_6~0); 210561#L803-1 assume { :end_inline_reset_delta_events } true; 210562#L1024-2 [2022-07-14 16:03:48,478 INFO L754 eck$LassoCheckResult]: Loop: 210562#L1024-2 assume !false; 213314#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 213305#L645 assume !false; 213302#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 213230#L504 assume !(0 == ~m_st~0); 213225#L508 assume !(0 == ~t1_st~0); 213226#L512 assume !(0 == ~t2_st~0); 213228#L516 assume !(0 == ~t3_st~0); 213223#L520 assume !(0 == ~t4_st~0); 213224#L524 assume !(0 == ~t5_st~0); 213227#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 213229#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 212814#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 212815#L556 assume !(0 != eval_~tmp~0#1); 213960#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 213953#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 213948#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 213943#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 213935#L675-3 assume !(0 == ~T2_E~0); 213934#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 213933#L685-3 assume !(0 == ~T4_E~0); 213929#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 213927#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 213923#L700-3 assume !(0 == ~E_1~0); 213919#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 213916#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 213913#L715-3 assume !(0 == ~E_4~0); 213910#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 213907#L725-3 assume !(0 == ~E_6~0); 213901#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213897#L320-21 assume !(1 == ~m_pc~0); 213893#L320-23 is_master_triggered_~__retres1~0#1 := 0; 213889#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213885#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 213881#L825-21 assume !(0 != activate_threads_~tmp~1#1); 213876#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 213871#L339-21 assume 1 == ~t1_pc~0; 213867#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 213862#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213858#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 213854#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 213849#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213844#L358-21 assume !(1 == ~t2_pc~0); 213498#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 213837#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213833#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 213827#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 213823#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213819#L377-21 assume 1 == ~t3_pc~0; 213815#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 213810#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213806#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213802#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 213797#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213793#L396-21 assume !(1 == ~t4_pc~0); 213789#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 213785#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213781#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 213777#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 213773#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213769#L415-21 assume !(1 == ~t5_pc~0); 213765#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 213761#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213757#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 213753#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 213741#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 213727#L434-21 assume !(1 == ~t6_pc~0); 213721#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 213714#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213628#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 213609#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 213607#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 213604#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 213602#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 213600#L748-3 assume !(1 == ~T2_E~0); 213598#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 213595#L758-3 assume !(1 == ~T4_E~0); 213592#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 213588#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 213585#L773-3 assume !(1 == ~E_1~0); 213582#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 213577#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 213572#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 213564#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 213561#L798-3 assume !(1 == ~E_6~0); 213481#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 213422#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 213414#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 213409#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 213402#L1043 assume !(0 == start_simulation_~tmp~3#1); 213398#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 213333#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 213327#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 213325#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 213323#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 213321#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 213319#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 213317#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 210562#L1024-2 [2022-07-14 16:03:48,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:48,479 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2022-07-14 16:03:48,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:48,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897683917] [2022-07-14 16:03:48,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:48,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:48,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:48,486 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:48,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:48,502 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:48,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:48,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1997775651, now seen corresponding path program 1 times [2022-07-14 16:03:48,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:48,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481106361] [2022-07-14 16:03:48,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:48,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:48,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:48,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:48,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:48,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481106361] [2022-07-14 16:03:48,527 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481106361] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:48,527 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:48,527 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:48,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977082703] [2022-07-14 16:03:48,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:48,528 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:48,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:48,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:48,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:48,528 INFO L87 Difference]: Start difference. First operand 7009 states and 9723 transitions. cyclomatic complexity: 2722 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:48,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:48,604 INFO L93 Difference]: Finished difference Result 12757 states and 17488 transitions. [2022-07-14 16:03:48,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:48,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12757 states and 17488 transitions. [2022-07-14 16:03:48,661 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12548 [2022-07-14 16:03:48,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12757 states to 12757 states and 17488 transitions. [2022-07-14 16:03:48,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12757 [2022-07-14 16:03:48,712 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12757 [2022-07-14 16:03:48,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12757 states and 17488 transitions. [2022-07-14 16:03:48,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:48,722 INFO L369 hiAutomatonCegarLoop]: Abstraction has 12757 states and 17488 transitions. [2022-07-14 16:03:48,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12757 states and 17488 transitions. [2022-07-14 16:03:48,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12757 to 12717. [2022-07-14 16:03:48,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12717 states, 12717 states have (on average 1.3720217032318942) internal successors, (17448), 12716 states have internal predecessors, (17448), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:48,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12717 states to 12717 states and 17448 transitions. [2022-07-14 16:03:48,961 INFO L392 hiAutomatonCegarLoop]: Abstraction has 12717 states and 17448 transitions. [2022-07-14 16:03:48,961 INFO L374 stractBuchiCegarLoop]: Abstraction has 12717 states and 17448 transitions. [2022-07-14 16:03:48,961 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 16:03:48,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12717 states and 17448 transitions. [2022-07-14 16:03:48,984 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12516 [2022-07-14 16:03:48,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:48,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:48,986 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:48,986 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:48,986 INFO L752 eck$LassoCheckResult]: Stem: 230962#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 230880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 230807#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 230208#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 230204#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 230205#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 230740#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 230916#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 230294#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 230295#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 230450#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 230313#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 230314#L670 assume !(0 == ~M_E~0); 230696#L670-2 assume !(0 == ~T1_E~0); 230641#L675-1 assume !(0 == ~T2_E~0); 230642#L680-1 assume !(0 == ~T3_E~0); 230739#L685-1 assume !(0 == ~T4_E~0); 230699#L690-1 assume !(0 == ~T5_E~0); 230700#L695-1 assume !(0 == ~T6_E~0); 230780#L700-1 assume !(0 == ~E_1~0); 230769#L705-1 assume !(0 == ~E_2~0); 230770#L710-1 assume !(0 == ~E_3~0); 230639#L715-1 assume !(0 == ~E_4~0); 230559#L720-1 assume !(0 == ~E_5~0); 230560#L725-1 assume !(0 == ~E_6~0); 230618#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 230666#L320 assume !(1 == ~m_pc~0); 230803#L320-2 is_master_triggered_~__retres1~0#1 := 0; 230493#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 230494#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 230451#L825 assume !(0 != activate_threads_~tmp~1#1); 230452#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 230456#L339 assume !(1 == ~t1_pc~0); 230457#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 230811#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 230783#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 230317#L833 assume !(0 != activate_threads_~tmp___0~0#1); 230318#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 230991#L358 assume !(1 == ~t2_pc~0); 230763#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 230764#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 230878#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 230989#L841 assume !(0 != activate_threads_~tmp___1~0#1); 230988#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 230987#L377 assume !(1 == ~t3_pc~0); 230720#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 230721#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 230729#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 230454#L849 assume !(0 != activate_threads_~tmp___2~0#1); 230455#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 230403#L396 assume !(1 == ~t4_pc~0); 230404#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 230231#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 230232#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 230981#L857 assume !(0 != activate_threads_~tmp___3~0#1); 230980#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 230979#L415 assume !(1 == ~t5_pc~0); 230480#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 230481#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 230935#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 230813#L865 assume !(0 != activate_threads_~tmp___4~0#1); 230271#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 230272#L434 assume !(1 == ~t6_pc~0); 230595#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 230596#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230752#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 230972#L873 assume !(0 != activate_threads_~tmp___5~0#1); 230466#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 230467#L743 assume !(1 == ~M_E~0); 230363#L743-2 assume !(1 == ~T1_E~0); 230364#L748-1 assume !(1 == ~T2_E~0); 230861#L753-1 assume !(1 == ~T3_E~0); 230970#L758-1 assume !(1 == ~T4_E~0); 230969#L763-1 assume !(1 == ~T5_E~0); 230968#L768-1 assume !(1 == ~T6_E~0); 230967#L773-1 assume !(1 == ~E_1~0); 230461#L778-1 assume !(1 == ~E_2~0); 230443#L783-1 assume !(1 == ~E_3~0); 230444#L788-1 assume !(1 == ~E_4~0); 230737#L793-1 assume !(1 == ~E_5~0); 230689#L798-1 assume !(1 == ~E_6~0); 230334#L803-1 assume { :end_inline_reset_delta_events } true; 230335#L1024-2 [2022-07-14 16:03:48,986 INFO L754 eck$LassoCheckResult]: Loop: 230335#L1024-2 assume !false; 241698#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 241692#L645 assume !false; 241690#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 241686#L504 assume !(0 == ~m_st~0); 241681#L508 assume !(0 == ~t1_st~0); 241682#L512 assume !(0 == ~t2_st~0); 241684#L516 assume !(0 == ~t3_st~0); 241679#L520 assume !(0 == ~t4_st~0); 241680#L524 assume !(0 == ~t5_st~0); 241683#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 241685#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 242718#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 242717#L556 assume !(0 != eval_~tmp~0#1); 242716#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 242714#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 242712#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 242710#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 242709#L675-3 assume !(0 == ~T2_E~0); 242708#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 242704#L685-3 assume !(0 == ~T4_E~0); 242702#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 242700#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 242698#L700-3 assume !(0 == ~E_1~0); 242696#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 242694#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 242692#L715-3 assume !(0 == ~E_4~0); 242690#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 242688#L725-3 assume !(0 == ~E_6~0); 242685#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242683#L320-21 assume !(1 == ~m_pc~0); 242681#L320-23 is_master_triggered_~__retres1~0#1 := 0; 242679#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 242677#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 242675#L825-21 assume !(0 != activate_threads_~tmp~1#1); 242673#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242669#L339-21 assume !(1 == ~t1_pc~0); 242667#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 242665#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 242663#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 242661#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 242659#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242657#L358-21 assume !(1 == ~t2_pc~0); 241488#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 242654#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242652#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 242650#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 242648#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242646#L377-21 assume !(1 == ~t3_pc~0); 242643#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 242641#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242639#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 242637#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 242635#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242633#L396-21 assume !(1 == ~t4_pc~0); 242632#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 242629#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 242627#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242625#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 242623#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 242621#L415-21 assume !(1 == ~t5_pc~0); 242619#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 242618#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242616#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242614#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 242612#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 242610#L434-21 assume !(1 == ~t6_pc~0); 242607#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 242604#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 242602#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 242600#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 242598#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242596#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 242594#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 242592#L748-3 assume !(1 == ~T2_E~0); 242590#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 242588#L758-3 assume !(1 == ~T4_E~0); 242586#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 242584#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 242546#L773-3 assume !(1 == ~E_1~0); 242544#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 242542#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 242541#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 242540#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 242539#L798-3 assume !(1 == ~E_6~0); 242538#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 242534#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 242530#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 242529#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 242413#L1043 assume !(0 == start_simulation_~tmp~3#1); 242411#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 242404#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 242398#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 242396#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 242393#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 242391#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 242389#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 242387#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 230335#L1024-2 [2022-07-14 16:03:48,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:48,987 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 4 times [2022-07-14 16:03:48,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:48,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670929854] [2022-07-14 16:03:48,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:48,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:48,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:48,993 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:48,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:49,008 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:49,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:49,008 INFO L85 PathProgramCache]: Analyzing trace with hash 2087164513, now seen corresponding path program 1 times [2022-07-14 16:03:49,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:49,009 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510054150] [2022-07-14 16:03:49,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:49,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:49,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:49,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:49,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:49,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510054150] [2022-07-14 16:03:49,027 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510054150] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:49,027 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:49,027 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:49,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564418571] [2022-07-14 16:03:49,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:49,028 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:49,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:49,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:49,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:49,029 INFO L87 Difference]: Start difference. First operand 12717 states and 17448 transitions. cyclomatic complexity: 4739 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:49,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:49,106 INFO L93 Difference]: Finished difference Result 22067 states and 29886 transitions. [2022-07-14 16:03:49,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:49,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22067 states and 29886 transitions. [2022-07-14 16:03:49,189 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21800 [2022-07-14 16:03:49,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22067 states to 22067 states and 29886 transitions. [2022-07-14 16:03:49,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22067 [2022-07-14 16:03:49,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22067 [2022-07-14 16:03:49,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22067 states and 29886 transitions. [2022-07-14 16:03:49,280 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:49,281 INFO L369 hiAutomatonCegarLoop]: Abstraction has 22067 states and 29886 transitions. [2022-07-14 16:03:49,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22067 states and 29886 transitions. [2022-07-14 16:03:49,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22067 to 21711. [2022-07-14 16:03:49,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21711 states, 21711 states have (on average 1.3557182994795265) internal successors, (29434), 21710 states have internal predecessors, (29434), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:49,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21711 states to 21711 states and 29434 transitions. [2022-07-14 16:03:49,479 INFO L392 hiAutomatonCegarLoop]: Abstraction has 21711 states and 29434 transitions. [2022-07-14 16:03:49,479 INFO L374 stractBuchiCegarLoop]: Abstraction has 21711 states and 29434 transitions. [2022-07-14 16:03:49,479 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-14 16:03:49,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21711 states and 29434 transitions. [2022-07-14 16:03:49,528 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21444 [2022-07-14 16:03:49,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:49,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:49,529 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:49,530 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:49,530 INFO L752 eck$LassoCheckResult]: Stem: 265748#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 265677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 265593#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264998#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264994#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 264995#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 265526#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 265706#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 265083#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265084#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265237#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 265102#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 265103#L670 assume !(0 == ~M_E~0); 265483#L670-2 assume !(0 == ~T1_E~0); 265428#L675-1 assume !(0 == ~T2_E~0); 265429#L680-1 assume !(0 == ~T3_E~0); 265525#L685-1 assume !(0 == ~T4_E~0); 265487#L690-1 assume !(0 == ~T5_E~0); 265488#L695-1 assume !(0 == ~T6_E~0); 265566#L700-1 assume !(0 == ~E_1~0); 265555#L705-1 assume !(0 == ~E_2~0); 265556#L710-1 assume !(0 == ~E_3~0); 265426#L715-1 assume !(0 == ~E_4~0); 265346#L720-1 assume !(0 == ~E_5~0); 265347#L725-1 assume !(0 == ~E_6~0); 265405#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 265453#L320 assume !(1 == ~m_pc~0); 265588#L320-2 is_master_triggered_~__retres1~0#1 := 0; 265282#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265283#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 265238#L825 assume !(0 != activate_threads_~tmp~1#1); 265239#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265244#L339 assume !(1 == ~t1_pc~0); 265245#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 265597#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265569#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 265105#L833 assume !(0 != activate_threads_~tmp___0~0#1); 265106#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265777#L358 assume !(1 == ~t2_pc~0); 265548#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 265549#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 265675#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 265775#L841 assume !(0 != activate_threads_~tmp___1~0#1); 265774#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265773#L377 assume !(1 == ~t3_pc~0); 265508#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 265509#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 265517#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 265242#L849 assume !(0 != activate_threads_~tmp___2~0#1); 265243#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265191#L396 assume !(1 == ~t4_pc~0); 265192#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 265021#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265022#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 265767#L857 assume !(0 != activate_threads_~tmp___3~0#1); 265766#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 265765#L415 assume !(1 == ~t5_pc~0); 265270#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 265271#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265724#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 265601#L865 assume !(0 != activate_threads_~tmp___4~0#1); 265061#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 265062#L434 assume !(1 == ~t6_pc~0); 265382#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 265383#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 265537#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 265758#L873 assume !(0 != activate_threads_~tmp___5~0#1); 265256#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 265257#L743 assume !(1 == ~M_E~0); 265151#L743-2 assume !(1 == ~T1_E~0); 265152#L748-1 assume !(1 == ~T2_E~0); 265661#L753-1 assume !(1 == ~T3_E~0); 265756#L758-1 assume !(1 == ~T4_E~0); 265755#L763-1 assume !(1 == ~T5_E~0); 265754#L768-1 assume !(1 == ~T6_E~0); 265753#L773-1 assume !(1 == ~E_1~0); 265253#L778-1 assume !(1 == ~E_2~0); 265230#L783-1 assume !(1 == ~E_3~0); 265231#L788-1 assume !(1 == ~E_4~0); 265523#L793-1 assume !(1 == ~E_5~0); 265477#L798-1 assume !(1 == ~E_6~0); 265122#L803-1 assume { :end_inline_reset_delta_events } true; 265123#L1024-2 assume !false; 279712#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279706#L645 [2022-07-14 16:03:49,530 INFO L754 eck$LassoCheckResult]: Loop: 279706#L645 assume !false; 279704#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 279701#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 279699#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 279697#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 279695#L556 assume 0 != eval_~tmp~0#1; 279692#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 279690#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 279688#L561 assume !(0 == ~t1_st~0); 279683#L575 assume !(0 == ~t2_st~0); 279681#L589 assume !(0 == ~t3_st~0); 279721#L603 assume !(0 == ~t4_st~0); 279718#L617 assume !(0 == ~t5_st~0); 279711#L631 assume !(0 == ~t6_st~0); 279706#L645 [2022-07-14 16:03:49,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:49,531 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 1 times [2022-07-14 16:03:49,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:49,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115771883] [2022-07-14 16:03:49,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:49,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:49,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:49,537 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:49,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:49,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:49,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:49,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1489034978, now seen corresponding path program 1 times [2022-07-14 16:03:49,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:49,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338924609] [2022-07-14 16:03:49,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:49,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:49,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:49,553 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:49,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:49,555 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:49,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:49,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1336774676, now seen corresponding path program 1 times [2022-07-14 16:03:49,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:49,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523143741] [2022-07-14 16:03:49,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:49,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:49,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:49,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:49,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:49,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523143741] [2022-07-14 16:03:49,575 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523143741] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:49,575 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:49,575 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:49,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000901300] [2022-07-14 16:03:49,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:49,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:49,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:49,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:49,640 INFO L87 Difference]: Start difference. First operand 21711 states and 29434 transitions. cyclomatic complexity: 7739 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:49,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:49,753 INFO L93 Difference]: Finished difference Result 40712 states and 54773 transitions. [2022-07-14 16:03:49,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:49,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40712 states and 54773 transitions. [2022-07-14 16:03:49,897 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40184 [2022-07-14 16:03:50,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40712 states to 40712 states and 54773 transitions. [2022-07-14 16:03:50,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40712 [2022-07-14 16:03:50,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40712 [2022-07-14 16:03:50,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40712 states and 54773 transitions. [2022-07-14 16:03:50,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:50,218 INFO L369 hiAutomatonCegarLoop]: Abstraction has 40712 states and 54773 transitions. [2022-07-14 16:03:50,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40712 states and 54773 transitions. [2022-07-14 16:03:50,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40712 to 38312. [2022-07-14 16:03:50,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38312 states, 38312 states have (on average 1.3503079974942578) internal successors, (51733), 38311 states have internal predecessors, (51733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:50,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38312 states to 38312 states and 51733 transitions. [2022-07-14 16:03:50,702 INFO L392 hiAutomatonCegarLoop]: Abstraction has 38312 states and 51733 transitions. [2022-07-14 16:03:50,703 INFO L374 stractBuchiCegarLoop]: Abstraction has 38312 states and 51733 transitions. [2022-07-14 16:03:50,703 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-14 16:03:50,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38312 states and 51733 transitions. [2022-07-14 16:03:50,810 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37784 [2022-07-14 16:03:50,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:50,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:50,811 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:50,811 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:50,812 INFO L752 eck$LassoCheckResult]: Stem: 328184#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 328115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 328030#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327429#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327425#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 327426#L461-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 327959#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 344401#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 344400#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 344399#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 344398#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 344397#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 344396#L670 assume !(0 == ~M_E~0); 344395#L670-2 assume !(0 == ~T1_E~0); 344394#L675-1 assume !(0 == ~T2_E~0); 344393#L680-1 assume !(0 == ~T3_E~0); 344392#L685-1 assume !(0 == ~T4_E~0); 344391#L690-1 assume !(0 == ~T5_E~0); 344390#L695-1 assume !(0 == ~T6_E~0); 344388#L700-1 assume !(0 == ~E_1~0); 344386#L705-1 assume !(0 == ~E_2~0); 344384#L710-1 assume !(0 == ~E_3~0); 344382#L715-1 assume !(0 == ~E_4~0); 344380#L720-1 assume !(0 == ~E_5~0); 344378#L725-1 assume !(0 == ~E_6~0); 344376#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 344374#L320 assume !(1 == ~m_pc~0); 344372#L320-2 is_master_triggered_~__retres1~0#1 := 0; 344369#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344367#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 344365#L825 assume !(0 != activate_threads_~tmp~1#1); 344362#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327679#L339 assume !(1 == ~t1_pc~0); 327680#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 328034#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 328007#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 327537#L833 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 327538#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343492#L358 assume !(1 == ~t2_pc~0); 343491#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 343490#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343489#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 343488#L841 assume !(0 != activate_threads_~tmp___1~0#1); 343487#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 343486#L377 assume !(1 == ~t3_pc~0); 343484#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 343483#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343482#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 343481#L849 assume !(0 != activate_threads_~tmp___2~0#1); 343480#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343479#L396 assume !(1 == ~t4_pc~0); 343478#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 343477#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 343476#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 343475#L857 assume !(0 != activate_threads_~tmp___3~0#1); 343474#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 343473#L415 assume !(1 == ~t5_pc~0); 343472#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 343471#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 343470#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 328037#L865 assume !(0 != activate_threads_~tmp___4~0#1); 327494#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 327495#L434 assume !(1 == ~t6_pc~0); 327815#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 327816#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 327973#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 328194#L873 assume !(0 != activate_threads_~tmp___5~0#1); 327691#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 327692#L743 assume !(1 == ~M_E~0); 327584#L743-2 assume !(1 == ~T1_E~0); 327585#L748-1 assume !(1 == ~T2_E~0); 328096#L753-1 assume !(1 == ~T3_E~0); 328191#L758-1 assume !(1 == ~T4_E~0); 328192#L763-1 assume !(1 == ~T5_E~0); 343453#L768-1 assume !(1 == ~T6_E~0); 343451#L773-1 assume !(1 == ~E_1~0); 328183#L778-1 assume !(1 == ~E_2~0); 327665#L783-1 assume !(1 == ~E_3~0); 327666#L788-1 assume !(1 == ~E_4~0); 328169#L793-1 assume !(1 == ~E_5~0); 327908#L798-1 assume !(1 == ~E_6~0); 327555#L803-1 assume { :end_inline_reset_delta_events } true; 327556#L1024-2 assume !false; 347986#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 347980#L645 [2022-07-14 16:03:50,812 INFO L754 eck$LassoCheckResult]: Loop: 347980#L645 assume !false; 347978#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 347975#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 347971#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 347969#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 347967#L556 assume 0 != eval_~tmp~0#1; 347962#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 347960#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 347957#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 341934#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 347952#L575 assume !(0 == ~t2_st~0); 347704#L589 assume !(0 == ~t3_st~0); 347700#L603 assume !(0 == ~t4_st~0); 347698#L617 assume !(0 == ~t5_st~0); 347985#L631 assume !(0 == ~t6_st~0); 347980#L645 [2022-07-14 16:03:50,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:50,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1610041797, now seen corresponding path program 1 times [2022-07-14 16:03:50,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:50,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319705220] [2022-07-14 16:03:50,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:50,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:50,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:50,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:50,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:50,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319705220] [2022-07-14 16:03:50,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319705220] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:50,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:50,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:50,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346528032] [2022-07-14 16:03:50,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:50,831 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:50,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:50,831 INFO L85 PathProgramCache]: Analyzing trace with hash 2146507872, now seen corresponding path program 1 times [2022-07-14 16:03:50,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:50,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882768105] [2022-07-14 16:03:50,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:50,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:50,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:50,835 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:50,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:50,837 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:50,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:50,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:50,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:50,926 INFO L87 Difference]: Start difference. First operand 38312 states and 51733 transitions. cyclomatic complexity: 13437 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:51,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:51,169 INFO L93 Difference]: Finished difference Result 38187 states and 51565 transitions. [2022-07-14 16:03:51,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:51,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38187 states and 51565 transitions. [2022-07-14 16:03:51,329 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37784 [2022-07-14 16:03:51,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38187 states to 38187 states and 51565 transitions. [2022-07-14 16:03:51,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38187 [2022-07-14 16:03:51,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38187 [2022-07-14 16:03:51,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38187 states and 51565 transitions. [2022-07-14 16:03:51,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:51,636 INFO L369 hiAutomatonCegarLoop]: Abstraction has 38187 states and 51565 transitions. [2022-07-14 16:03:51,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38187 states and 51565 transitions. [2022-07-14 16:03:51,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38187 to 38187. [2022-07-14 16:03:51,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38187 states, 38187 states have (on average 1.3503286458742505) internal successors, (51565), 38186 states have internal predecessors, (51565), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:52,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38187 states to 38187 states and 51565 transitions. [2022-07-14 16:03:52,117 INFO L392 hiAutomatonCegarLoop]: Abstraction has 38187 states and 51565 transitions. [2022-07-14 16:03:52,117 INFO L374 stractBuchiCegarLoop]: Abstraction has 38187 states and 51565 transitions. [2022-07-14 16:03:52,117 INFO L287 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-07-14 16:03:52,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38187 states and 51565 transitions. [2022-07-14 16:03:52,201 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37784 [2022-07-14 16:03:52,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:52,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:52,202 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:52,202 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:52,203 INFO L752 eck$LassoCheckResult]: Stem: 404689#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 404622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 404538#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 403934#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 403930#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 403931#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 404465#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 404650#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 404019#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 404020#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 404175#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 404039#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 404040#L670 assume !(0 == ~M_E~0); 404420#L670-2 assume !(0 == ~T1_E~0); 404362#L675-1 assume !(0 == ~T2_E~0); 404363#L680-1 assume !(0 == ~T3_E~0); 404463#L685-1 assume !(0 == ~T4_E~0); 404424#L690-1 assume !(0 == ~T5_E~0); 404425#L695-1 assume !(0 == ~T6_E~0); 404509#L700-1 assume !(0 == ~E_1~0); 404498#L705-1 assume !(0 == ~E_2~0); 404499#L710-1 assume !(0 == ~E_3~0); 404360#L715-1 assume !(0 == ~E_4~0); 404282#L720-1 assume !(0 == ~E_5~0); 404283#L725-1 assume !(0 == ~E_6~0); 404339#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 404389#L320 assume !(1 == ~m_pc~0); 404535#L320-2 is_master_triggered_~__retres1~0#1 := 0; 404215#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404216#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 404176#L825 assume !(0 != activate_threads_~tmp~1#1); 404177#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 404181#L339 assume !(1 == ~t1_pc~0); 404182#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 404161#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 404162#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 404719#L833 assume !(0 != activate_threads_~tmp___0~0#1); 404635#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 403955#L358 assume !(1 == ~t2_pc~0); 403956#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 404717#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 404421#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 404343#L841 assume !(0 != activate_threads_~tmp___1~0#1); 404173#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 404174#L377 assume !(1 == ~t3_pc~0); 404564#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 404452#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 404453#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 404179#L849 assume !(0 != activate_threads_~tmp___2~0#1); 404180#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404130#L396 assume !(1 == ~t4_pc~0); 404131#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 403957#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 403958#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 404709#L857 assume !(0 != activate_threads_~tmp___3~0#1); 404708#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 404707#L415 assume !(1 == ~t5_pc~0); 404205#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404206#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 404664#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 404543#L865 assume !(0 != activate_threads_~tmp___4~0#1); 403998#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 403999#L434 assume !(1 == ~t6_pc~0); 404316#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 404317#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 404481#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 404700#L873 assume !(0 != activate_threads_~tmp___5~0#1); 404191#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404192#L743 assume !(1 == ~M_E~0); 404088#L743-2 assume !(1 == ~T1_E~0); 404089#L748-1 assume !(1 == ~T2_E~0); 404601#L753-1 assume !(1 == ~T3_E~0); 404698#L758-1 assume !(1 == ~T4_E~0); 404697#L763-1 assume !(1 == ~T5_E~0); 404696#L768-1 assume !(1 == ~T6_E~0); 404695#L773-1 assume !(1 == ~E_1~0); 404190#L778-1 assume !(1 == ~E_2~0); 404168#L783-1 assume !(1 == ~E_3~0); 404169#L788-1 assume !(1 == ~E_4~0); 404461#L793-1 assume !(1 == ~E_5~0); 404413#L798-1 assume !(1 == ~E_6~0); 404059#L803-1 assume { :end_inline_reset_delta_events } true; 404060#L1024-2 assume !false; 414632#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 414633#L645 [2022-07-14 16:03:52,203 INFO L754 eck$LassoCheckResult]: Loop: 414633#L645 assume !false; 416034#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 416032#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 416031#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 416030#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 416029#L556 assume 0 != eval_~tmp~0#1; 416028#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 416026#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 416023#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 416009#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 416021#L575 assume !(0 == ~t2_st~0); 416040#L589 assume !(0 == ~t3_st~0); 417085#L603 assume !(0 == ~t4_st~0); 416474#L617 assume !(0 == ~t5_st~0); 416038#L631 assume !(0 == ~t6_st~0); 414633#L645 [2022-07-14 16:03:52,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:52,203 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 2 times [2022-07-14 16:03:52,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:52,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444265349] [2022-07-14 16:03:52,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:52,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:52,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:52,211 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:52,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:52,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:52,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:52,227 INFO L85 PathProgramCache]: Analyzing trace with hash 2146507872, now seen corresponding path program 2 times [2022-07-14 16:03:52,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:52,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347076896] [2022-07-14 16:03:52,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:52,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:52,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:52,232 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:52,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:52,235 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:52,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:52,235 INFO L85 PathProgramCache]: Analyzing trace with hash -447706070, now seen corresponding path program 1 times [2022-07-14 16:03:52,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:52,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404768258] [2022-07-14 16:03:52,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:52,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:52,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:52,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:52,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:52,254 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404768258] [2022-07-14 16:03:52,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404768258] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:52,254 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:52,254 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:52,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037988664] [2022-07-14 16:03:52,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:52,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:52,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:52,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:52,314 INFO L87 Difference]: Start difference. First operand 38187 states and 51565 transitions. cyclomatic complexity: 13394 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:52,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:52,618 INFO L93 Difference]: Finished difference Result 72339 states and 97157 transitions. [2022-07-14 16:03:52,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:52,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72339 states and 97157 transitions. [2022-07-14 16:03:52,897 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 71664 [2022-07-14 16:03:53,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72339 states to 72339 states and 97157 transitions. [2022-07-14 16:03:53,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72339 [2022-07-14 16:03:53,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72339 [2022-07-14 16:03:53,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72339 states and 97157 transitions. [2022-07-14 16:03:53,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:53,260 INFO L369 hiAutomatonCegarLoop]: Abstraction has 72339 states and 97157 transitions. [2022-07-14 16:03:53,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72339 states and 97157 transitions. [2022-07-14 16:03:53,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72339 to 70355. [2022-07-14 16:03:53,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70355 states, 70355 states have (on average 1.345476511974984) internal successors, (94661), 70354 states have internal predecessors, (94661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:53,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70355 states to 70355 states and 94661 transitions. [2022-07-14 16:03:53,952 INFO L392 hiAutomatonCegarLoop]: Abstraction has 70355 states and 94661 transitions. [2022-07-14 16:03:53,953 INFO L374 stractBuchiCegarLoop]: Abstraction has 70355 states and 94661 transitions. [2022-07-14 16:03:53,953 INFO L287 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-07-14 16:03:53,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70355 states and 94661 transitions. [2022-07-14 16:03:54,306 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 69680 [2022-07-14 16:03:54,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:54,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:54,307 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:54,307 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:54,307 INFO L752 eck$LassoCheckResult]: Stem: 515257#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 515183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 515100#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 514468#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 514464#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 514465#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 515020#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 515216#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 514553#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 514554#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 514712#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 514573#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 514574#L670 assume !(0 == ~M_E~0); 514968#L670-2 assume !(0 == ~T1_E~0); 514908#L675-1 assume !(0 == ~T2_E~0); 514909#L680-1 assume !(0 == ~T3_E~0); 515018#L685-1 assume !(0 == ~T4_E~0); 514973#L690-1 assume !(0 == ~T5_E~0); 514974#L695-1 assume !(0 == ~T6_E~0); 515069#L700-1 assume !(0 == ~E_1~0); 515058#L705-1 assume !(0 == ~E_2~0); 515059#L710-1 assume !(0 == ~E_3~0); 514905#L715-1 assume !(0 == ~E_4~0); 514824#L720-1 assume !(0 == ~E_5~0); 514825#L725-1 assume !(0 == ~E_6~0); 514884#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 514936#L320 assume !(1 == ~m_pc~0); 515095#L320-2 is_master_triggered_~__retres1~0#1 := 0; 514755#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 514756#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 514713#L825 assume !(0 != activate_threads_~tmp~1#1); 514714#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 514718#L339 assume !(1 == ~t1_pc~0); 514719#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 515104#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 515072#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 514576#L833 assume !(0 != activate_threads_~tmp___0~0#1); 514577#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 515287#L358 assume !(1 == ~t2_pc~0); 515050#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 515051#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 515181#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 515285#L841 assume !(0 != activate_threads_~tmp___1~0#1); 515284#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 515283#L377 assume !(1 == ~t3_pc~0); 514996#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 514997#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515008#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 514716#L849 assume !(0 != activate_threads_~tmp___2~0#1); 514717#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514664#L396 assume !(1 == ~t4_pc~0); 514665#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 514491#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 514492#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 515277#L857 assume !(0 != activate_threads_~tmp___3~0#1); 515276#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 515275#L415 assume !(1 == ~t5_pc~0); 514742#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 514743#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 515234#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 515106#L865 assume !(0 != activate_threads_~tmp___4~0#1); 514532#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 514533#L434 assume !(1 == ~t6_pc~0); 514859#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 514860#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515037#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 515268#L873 assume !(0 != activate_threads_~tmp___5~0#1); 514730#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 514731#L743 assume !(1 == ~M_E~0); 514623#L743-2 assume !(1 == ~T1_E~0); 514624#L748-1 assume !(1 == ~T2_E~0); 515163#L753-1 assume !(1 == ~T3_E~0); 515266#L758-1 assume !(1 == ~T4_E~0); 515265#L763-1 assume !(1 == ~T5_E~0); 515264#L768-1 assume !(1 == ~T6_E~0); 515263#L773-1 assume !(1 == ~E_1~0); 514725#L778-1 assume !(1 == ~E_2~0); 514705#L783-1 assume !(1 == ~E_3~0); 514706#L788-1 assume !(1 == ~E_4~0); 515015#L793-1 assume !(1 == ~E_5~0); 514961#L798-1 assume !(1 == ~E_6~0); 514593#L803-1 assume { :end_inline_reset_delta_events } true; 514594#L1024-2 assume !false; 530696#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530691#L645 [2022-07-14 16:03:54,313 INFO L754 eck$LassoCheckResult]: Loop: 530691#L645 assume !false; 530688#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 530682#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 530680#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 530678#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 530675#L556 assume 0 != eval_~tmp~0#1; 530672#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 530669#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 530667#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 530569#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 530664#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 530441#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 530705#L589 assume !(0 == ~t3_st~0); 530702#L603 assume !(0 == ~t4_st~0); 530699#L617 assume !(0 == ~t5_st~0); 530695#L631 assume !(0 == ~t6_st~0); 530691#L645 [2022-07-14 16:03:54,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:54,313 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 3 times [2022-07-14 16:03:54,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:54,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46265983] [2022-07-14 16:03:54,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:54,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:54,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:54,321 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:54,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:54,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:54,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:54,336 INFO L85 PathProgramCache]: Analyzing trace with hash 488929788, now seen corresponding path program 1 times [2022-07-14 16:03:54,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:54,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212330161] [2022-07-14 16:03:54,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:54,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:54,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:54,341 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:54,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:54,343 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:54,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:54,344 INFO L85 PathProgramCache]: Analyzing trace with hash 1672676210, now seen corresponding path program 1 times [2022-07-14 16:03:54,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:54,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511702606] [2022-07-14 16:03:54,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:54,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:54,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:54,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:54,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:54,365 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511702606] [2022-07-14 16:03:54,365 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511702606] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:54,365 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:54,365 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:54,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959608043] [2022-07-14 16:03:54,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:54,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:54,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:54,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:54,459 INFO L87 Difference]: Start difference. First operand 70355 states and 94661 transitions. cyclomatic complexity: 24322 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:55,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:55,061 INFO L93 Difference]: Finished difference Result 128931 states and 172661 transitions. [2022-07-14 16:03:55,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:55,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128931 states and 172661 transitions. [2022-07-14 16:03:55,537 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 127712 [2022-07-14 16:03:55,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128931 states to 128931 states and 172661 transitions. [2022-07-14 16:03:55,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128931 [2022-07-14 16:03:55,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128931 [2022-07-14 16:03:55,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128931 states and 172661 transitions. [2022-07-14 16:03:56,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:56,208 INFO L369 hiAutomatonCegarLoop]: Abstraction has 128931 states and 172661 transitions. [2022-07-14 16:03:56,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128931 states and 172661 transitions. [2022-07-14 16:03:57,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128931 to 122787. [2022-07-14 16:03:57,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122787 states, 122787 states have (on average 1.3457206381783087) internal successors, (165237), 122786 states have internal predecessors, (165237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:57,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122787 states to 122787 states and 165237 transitions. [2022-07-14 16:03:57,434 INFO L392 hiAutomatonCegarLoop]: Abstraction has 122787 states and 165237 transitions. [2022-07-14 16:03:57,434 INFO L374 stractBuchiCegarLoop]: Abstraction has 122787 states and 165237 transitions. [2022-07-14 16:03:57,434 INFO L287 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-07-14 16:03:57,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122787 states and 165237 transitions. [2022-07-14 16:03:58,062 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 121568 [2022-07-14 16:03:58,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:58,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:58,063 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:58,063 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:58,064 INFO L752 eck$LassoCheckResult]: Stem: 714557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 714470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 714382#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 713762#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 713758#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 713759#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 714311#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 714505#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 713849#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 713850#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 714003#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 713869#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713870#L670 assume !(0 == ~M_E~0); 714266#L670-2 assume !(0 == ~T1_E~0); 714199#L675-1 assume !(0 == ~T2_E~0); 714200#L680-1 assume !(0 == ~T3_E~0); 714309#L685-1 assume !(0 == ~T4_E~0); 714270#L690-1 assume !(0 == ~T5_E~0); 714271#L695-1 assume !(0 == ~T6_E~0); 714354#L700-1 assume !(0 == ~E_1~0); 714345#L705-1 assume !(0 == ~E_2~0); 714346#L710-1 assume !(0 == ~E_3~0); 714196#L715-1 assume !(0 == ~E_4~0); 714116#L720-1 assume !(0 == ~E_5~0); 714117#L725-1 assume !(0 == ~E_6~0); 714175#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 714231#L320 assume !(1 == ~m_pc~0); 714377#L320-2 is_master_triggered_~__retres1~0#1 := 0; 714047#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 714048#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 714004#L825 assume !(0 != activate_threads_~tmp~1#1); 714005#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 714010#L339 assume !(1 == ~t1_pc~0); 714011#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 714388#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714357#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 713872#L833 assume !(0 != activate_threads_~tmp___0~0#1); 713873#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 714588#L358 assume !(1 == ~t2_pc~0); 714337#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 714338#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 714467#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 714586#L841 assume !(0 != activate_threads_~tmp___1~0#1); 714585#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 714584#L377 assume !(1 == ~t3_pc~0); 714291#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 714292#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 714301#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 714008#L849 assume !(0 != activate_threads_~tmp___2~0#1); 714009#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713956#L396 assume !(1 == ~t4_pc~0); 713957#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 713785#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 713786#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 714578#L857 assume !(0 != activate_threads_~tmp___3~0#1); 714577#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 714576#L415 assume !(1 == ~t5_pc~0); 714034#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 714035#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 714531#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 714392#L865 assume !(0 != activate_threads_~tmp___4~0#1); 713827#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 713828#L434 assume !(1 == ~t6_pc~0); 714152#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 714153#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 714325#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 714569#L873 assume !(0 != activate_threads_~tmp___5~0#1); 714022#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 714023#L743 assume !(1 == ~M_E~0); 713917#L743-2 assume !(1 == ~T1_E~0); 713918#L748-1 assume !(1 == ~T2_E~0); 714450#L753-1 assume !(1 == ~T3_E~0); 714567#L758-1 assume !(1 == ~T4_E~0); 714566#L763-1 assume !(1 == ~T5_E~0); 714565#L768-1 assume !(1 == ~T6_E~0); 714564#L773-1 assume !(1 == ~E_1~0); 714017#L778-1 assume !(1 == ~E_2~0); 713996#L783-1 assume !(1 == ~E_3~0); 713997#L788-1 assume !(1 == ~E_4~0); 714307#L793-1 assume !(1 == ~E_5~0); 714257#L798-1 assume !(1 == ~E_6~0); 713889#L803-1 assume { :end_inline_reset_delta_events } true; 713890#L1024-2 assume !false; 783724#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 783717#L645 [2022-07-14 16:03:58,064 INFO L754 eck$LassoCheckResult]: Loop: 783717#L645 assume !false; 783714#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 783710#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 783709#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 783708#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 783707#L556 assume 0 != eval_~tmp~0#1; 783705#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 783703#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 783701#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 783638#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 783699#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 782489#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 783737#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 783735#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 783734#L603 assume !(0 == ~t4_st~0); 783731#L617 assume !(0 == ~t5_st~0); 783723#L631 assume !(0 == ~t6_st~0); 783717#L645 [2022-07-14 16:03:58,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:58,064 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 4 times [2022-07-14 16:03:58,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:58,065 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641538842] [2022-07-14 16:03:58,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:58,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:58,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:58,071 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:58,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:58,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:58,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:58,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2080854914, now seen corresponding path program 1 times [2022-07-14 16:03:58,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:58,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719816500] [2022-07-14 16:03:58,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:58,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:58,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:58,087 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:58,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:58,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:58,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:58,090 INFO L85 PathProgramCache]: Analyzing trace with hash 122288332, now seen corresponding path program 1 times [2022-07-14 16:03:58,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:58,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107706584] [2022-07-14 16:03:58,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:58,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:58,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:58,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:58,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:58,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107706584] [2022-07-14 16:03:58,108 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107706584] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:58,108 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:58,108 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:58,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172140843] [2022-07-14 16:03:58,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:58,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:58,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:58,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:58,221 INFO L87 Difference]: Start difference. First operand 122787 states and 165237 transitions. cyclomatic complexity: 42466 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:58,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:58,929 INFO L93 Difference]: Finished difference Result 158675 states and 212545 transitions. [2022-07-14 16:03:58,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:58,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158675 states and 212545 transitions. [2022-07-14 16:03:59,565 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 157168 [2022-07-14 16:03:59,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158675 states to 158675 states and 212545 transitions. [2022-07-14 16:03:59,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158675 [2022-07-14 16:03:59,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158675 [2022-07-14 16:03:59,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158675 states and 212545 transitions. [2022-07-14 16:04:00,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:04:00,062 INFO L369 hiAutomatonCegarLoop]: Abstraction has 158675 states and 212545 transitions. [2022-07-14 16:04:00,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158675 states and 212545 transitions. [2022-07-14 16:04:01,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158675 to 154195. [2022-07-14 16:04:01,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 154195 states, 154195 states have (on average 1.3443821135575083) internal successors, (207297), 154194 states have internal predecessors, (207297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:04:01,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154195 states to 154195 states and 207297 transitions. [2022-07-14 16:04:02,000 INFO L392 hiAutomatonCegarLoop]: Abstraction has 154195 states and 207297 transitions. [2022-07-14 16:04:02,000 INFO L374 stractBuchiCegarLoop]: Abstraction has 154195 states and 207297 transitions. [2022-07-14 16:04:02,000 INFO L287 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-07-14 16:04:02,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 154195 states and 207297 transitions. [2022-07-14 16:04:02,425 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 152688 [2022-07-14 16:04:02,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:04:02,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:04:02,426 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:04:02,426 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:04:02,426 INFO L752 eck$LassoCheckResult]: Stem: 996049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 995965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 995869#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 995232#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 995228#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 995229#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 995787#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 996001#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 995320#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 995321#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 995478#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 995339#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 995340#L670 assume !(0 == ~M_E~0); 995737#L670-2 assume !(0 == ~T1_E~0); 995673#L675-1 assume !(0 == ~T2_E~0); 995674#L680-1 assume !(0 == ~T3_E~0); 995786#L685-1 assume !(0 == ~T4_E~0); 995740#L690-1 assume !(0 == ~T5_E~0); 995741#L695-1 assume !(0 == ~T6_E~0); 995836#L700-1 assume !(0 == ~E_1~0); 995826#L705-1 assume !(0 == ~E_2~0); 995827#L710-1 assume !(0 == ~E_3~0); 995671#L715-1 assume !(0 == ~E_4~0); 995590#L720-1 assume !(0 == ~E_5~0); 995591#L725-1 assume !(0 == ~E_6~0); 995649#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 995704#L320 assume !(1 == ~m_pc~0); 995864#L320-2 is_master_triggered_~__retres1~0#1 := 0; 995522#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 995523#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 995479#L825 assume !(0 != activate_threads_~tmp~1#1); 995480#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 995485#L339 assume !(1 == ~t1_pc~0); 995486#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 995876#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 995839#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 995342#L833 assume !(0 != activate_threads_~tmp___0~0#1); 995343#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 996080#L358 assume !(1 == ~t2_pc~0); 995817#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 995818#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995963#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 996078#L841 assume !(0 != activate_threads_~tmp___1~0#1); 996077#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 996076#L377 assume !(1 == ~t3_pc~0); 995765#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 995766#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 995776#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 995483#L849 assume !(0 != activate_threads_~tmp___2~0#1); 995484#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 995428#L396 assume !(1 == ~t4_pc~0); 995429#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 995255#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 995256#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 996070#L857 assume !(0 != activate_threads_~tmp___3~0#1); 996069#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 996068#L415 assume !(1 == ~t5_pc~0); 995509#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 995510#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 996026#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 995880#L865 assume !(0 != activate_threads_~tmp___4~0#1); 995299#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 995300#L434 assume !(1 == ~t6_pc~0); 995623#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 995624#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 995802#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 996061#L873 assume !(0 != activate_threads_~tmp___5~0#1); 995497#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 995498#L743 assume !(1 == ~M_E~0); 995389#L743-2 assume !(1 == ~T1_E~0); 995390#L748-1 assume !(1 == ~T2_E~0); 995937#L753-1 assume !(1 == ~T3_E~0); 996059#L758-1 assume !(1 == ~T4_E~0); 996058#L763-1 assume !(1 == ~T5_E~0); 996057#L768-1 assume !(1 == ~T6_E~0); 996056#L773-1 assume !(1 == ~E_1~0); 995492#L778-1 assume !(1 == ~E_2~0); 995471#L783-1 assume !(1 == ~E_3~0); 995472#L788-1 assume !(1 == ~E_4~0); 995784#L793-1 assume !(1 == ~E_5~0); 995729#L798-1 assume !(1 == ~E_6~0); 995360#L803-1 assume { :end_inline_reset_delta_events } true; 995361#L1024-2 assume !false; 1066958#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1066952#L645 [2022-07-14 16:04:02,426 INFO L754 eck$LassoCheckResult]: Loop: 1066952#L645 assume !false; 1066950#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1066947#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1066945#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1066943#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1066941#L556 assume 0 != eval_~tmp~0#1; 1066938#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1066936#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1066934#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1066931#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1066929#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1066178#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1066926#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1066907#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1066923#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1066966#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1066963#L617 assume !(0 == ~t5_st~0); 1066957#L631 assume !(0 == ~t6_st~0); 1066952#L645 [2022-07-14 16:04:02,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:02,427 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 5 times [2022-07-14 16:04:02,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:02,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342738705] [2022-07-14 16:04:02,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:02,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:02,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:02,436 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:02,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:02,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:02,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:02,453 INFO L85 PathProgramCache]: Analyzing trace with hash 75836122, now seen corresponding path program 1 times [2022-07-14 16:04:02,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:02,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002826353] [2022-07-14 16:04:02,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:02,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:02,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:02,457 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:02,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:02,460 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:02,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:02,460 INFO L85 PathProgramCache]: Analyzing trace with hash -510185776, now seen corresponding path program 1 times [2022-07-14 16:04:02,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:02,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046301486] [2022-07-14 16:04:02,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:02,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:02,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:04:02,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:04:02,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:04:02,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046301486] [2022-07-14 16:04:02,481 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046301486] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:04:02,481 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:04:02,481 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:04:02,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188540475] [2022-07-14 16:04:02,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:04:02,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:04:02,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:04:02,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:04:02,612 INFO L87 Difference]: Start difference. First operand 154195 states and 207297 transitions. cyclomatic complexity: 53120 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:04:03,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:04:03,573 INFO L93 Difference]: Finished difference Result 203787 states and 272575 transitions. [2022-07-14 16:04:03,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:04:03,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203787 states and 272575 transitions. [2022-07-14 16:04:04,849 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 201976 [2022-07-14 16:04:05,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203787 states to 203787 states and 272575 transitions. [2022-07-14 16:04:05,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 203787 [2022-07-14 16:04:05,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 203787 [2022-07-14 16:04:05,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203787 states and 272575 transitions. [2022-07-14 16:04:05,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:04:05,677 INFO L369 hiAutomatonCegarLoop]: Abstraction has 203787 states and 272575 transitions. [2022-07-14 16:04:05,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203787 states and 272575 transitions. [2022-07-14 16:04:07,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203787 to 198411. [2022-07-14 16:04:07,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198411 states, 198411 states have (on average 1.3408883580043445) internal successors, (266047), 198410 states have internal predecessors, (266047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:04:08,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198411 states to 198411 states and 266047 transitions. [2022-07-14 16:04:08,523 INFO L392 hiAutomatonCegarLoop]: Abstraction has 198411 states and 266047 transitions. [2022-07-14 16:04:08,523 INFO L374 stractBuchiCegarLoop]: Abstraction has 198411 states and 266047 transitions. [2022-07-14 16:04:08,523 INFO L287 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-07-14 16:04:08,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198411 states and 266047 transitions. [2022-07-14 16:04:09,089 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 196600 [2022-07-14 16:04:09,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:04:09,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:04:09,090 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:04:09,090 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:04:09,091 INFO L752 eck$LassoCheckResult]: Stem: 1354100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1353995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1353881#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1353222#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1353218#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1353219#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1353791#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1354034#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1353309#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1353310#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1353463#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1353327#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1353328#L670 assume !(0 == ~M_E~0); 1353744#L670-2 assume !(0 == ~T1_E~0); 1353674#L675-1 assume !(0 == ~T2_E~0); 1353675#L680-1 assume !(0 == ~T3_E~0); 1353790#L685-1 assume !(0 == ~T4_E~0); 1353749#L690-1 assume !(0 == ~T5_E~0); 1353750#L695-1 assume !(0 == ~T6_E~0); 1353851#L700-1 assume !(0 == ~E_1~0); 1353839#L705-1 assume !(0 == ~E_2~0); 1353840#L710-1 assume !(0 == ~E_3~0); 1353672#L715-1 assume !(0 == ~E_4~0); 1353583#L720-1 assume !(0 == ~E_5~0); 1353584#L725-1 assume !(0 == ~E_6~0); 1353649#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1353709#L320 assume !(1 == ~m_pc~0); 1353875#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1353511#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1353512#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1353464#L825 assume !(0 != activate_threads_~tmp~1#1); 1353465#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1353471#L339 assume !(1 == ~t1_pc~0); 1353472#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1353887#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1353855#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1353330#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1353331#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1354130#L358 assume !(1 == ~t2_pc~0); 1353830#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1353831#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1353993#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1354128#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1354127#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1354126#L377 assume !(1 == ~t3_pc~0); 1353769#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1353770#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1353782#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1353469#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1353470#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1353416#L396 assume !(1 == ~t4_pc~0); 1353417#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1353245#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1353246#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1354120#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1354119#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1354118#L415 assume !(1 == ~t5_pc~0); 1353496#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1353497#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1354065#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1353891#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1353288#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1353289#L434 assume !(1 == ~t6_pc~0); 1353619#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1353620#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1353810#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1354111#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1353483#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1353484#L743 assume !(1 == ~M_E~0); 1353377#L743-2 assume !(1 == ~T1_E~0); 1353378#L748-1 assume !(1 == ~T2_E~0); 1353968#L753-1 assume !(1 == ~T3_E~0); 1354109#L758-1 assume !(1 == ~T4_E~0); 1354108#L763-1 assume !(1 == ~T5_E~0); 1354107#L768-1 assume !(1 == ~T6_E~0); 1354106#L773-1 assume !(1 == ~E_1~0); 1353478#L778-1 assume !(1 == ~E_2~0); 1353456#L783-1 assume !(1 == ~E_3~0); 1353457#L788-1 assume !(1 == ~E_4~0); 1353788#L793-1 assume !(1 == ~E_5~0); 1353734#L798-1 assume !(1 == ~E_6~0); 1353347#L803-1 assume { :end_inline_reset_delta_events } true; 1353348#L1024-2 assume !false; 1437683#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1437684#L645 [2022-07-14 16:04:09,091 INFO L754 eck$LassoCheckResult]: Loop: 1437684#L645 assume !false; 1438515#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1438513#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1438512#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1438509#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1438507#L556 assume 0 != eval_~tmp~0#1; 1438504#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1438502#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1438500#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1438053#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1438498#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1436837#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1438528#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1438526#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1438525#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1438523#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1438522#L617 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1438520#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1438519#L631 assume !(0 == ~t6_st~0); 1437684#L645 [2022-07-14 16:04:09,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:09,092 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 6 times [2022-07-14 16:04:09,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:09,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384380066] [2022-07-14 16:04:09,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:09,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:09,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:09,098 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:09,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:09,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:09,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:09,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1944239452, now seen corresponding path program 1 times [2022-07-14 16:04:09,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:09,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880833625] [2022-07-14 16:04:09,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:09,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:09,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:09,115 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:09,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:09,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:09,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:09,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1363918190, now seen corresponding path program 1 times [2022-07-14 16:04:09,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:09,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391777762] [2022-07-14 16:04:09,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:09,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:09,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:04:09,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:04:09,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:04:09,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391777762] [2022-07-14 16:04:09,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391777762] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:04:09,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:04:09,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:04:09,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018089410] [2022-07-14 16:04:09,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:04:09,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:04:09,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:04:09,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:04:09,289 INFO L87 Difference]: Start difference. First operand 198411 states and 266047 transitions. cyclomatic complexity: 67655 Second operand has 3 states, 2 states have (on average 51.5) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:04:10,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:04:10,649 INFO L93 Difference]: Finished difference Result 367107 states and 489757 transitions. [2022-07-14 16:04:10,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:04:10,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 367107 states and 489757 transitions. [2022-07-14 16:04:12,572 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 363616 [2022-07-14 16:04:13,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 367107 states to 367107 states and 489757 transitions. [2022-07-14 16:04:13,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 367107 [2022-07-14 16:04:13,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 367107 [2022-07-14 16:04:13,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 367107 states and 489757 transitions. [2022-07-14 16:04:14,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:04:14,204 INFO L369 hiAutomatonCegarLoop]: Abstraction has 367107 states and 489757 transitions. [2022-07-14 16:04:14,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367107 states and 489757 transitions. [2022-07-14 16:04:17,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367107 to 367107. [2022-07-14 16:04:17,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367107 states, 367107 states have (on average 1.3340987777405497) internal successors, (489757), 367106 states have internal predecessors, (489757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:04:17,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367107 states to 367107 states and 489757 transitions. [2022-07-14 16:04:17,998 INFO L392 hiAutomatonCegarLoop]: Abstraction has 367107 states and 489757 transitions. [2022-07-14 16:04:17,998 INFO L374 stractBuchiCegarLoop]: Abstraction has 367107 states and 489757 transitions. [2022-07-14 16:04:17,998 INFO L287 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-07-14 16:04:17,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 367107 states and 489757 transitions. [2022-07-14 16:04:19,674 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 363616 [2022-07-14 16:04:19,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:04:19,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:04:19,675 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:04:19,675 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:04:19,675 INFO L752 eck$LassoCheckResult]: Stem: 1919572#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1919480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1919388#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1918748#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1918744#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1918745#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1919304#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1919527#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1918838#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1918839#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1918992#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1918857#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1918858#L670 assume !(0 == ~M_E~0); 1919259#L670-2 assume !(0 == ~T1_E~0); 1919191#L675-1 assume !(0 == ~T2_E~0); 1919192#L680-1 assume !(0 == ~T3_E~0); 1919302#L685-1 assume !(0 == ~T4_E~0); 1919264#L690-1 assume !(0 == ~T5_E~0); 1919265#L695-1 assume !(0 == ~T6_E~0); 1919359#L700-1 assume !(0 == ~E_1~0); 1919346#L705-1 assume !(0 == ~E_2~0); 1919347#L710-1 assume !(0 == ~E_3~0); 1919190#L715-1 assume !(0 == ~E_4~0); 1919108#L720-1 assume !(0 == ~E_5~0); 1919109#L725-1 assume !(0 == ~E_6~0); 1919167#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1919224#L320 assume !(1 == ~m_pc~0); 1919380#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1919036#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1919037#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1918993#L825 assume !(0 != activate_threads_~tmp~1#1); 1918994#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1919002#L339 assume !(1 == ~t1_pc~0); 1919003#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1919396#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1919362#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1918859#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1918860#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1919600#L358 assume !(1 == ~t2_pc~0); 1919335#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1919336#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1919478#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1919598#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1919597#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1919596#L377 assume !(1 == ~t3_pc~0); 1919281#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1919282#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1919279#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1919280#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1919595#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1918944#L396 assume !(1 == ~t4_pc~0); 1918945#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1918771#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1918772#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1919592#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1919591#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1919590#L415 assume !(1 == ~t5_pc~0); 1919025#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1919026#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1919550#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1919399#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1918814#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1918815#L434 assume !(1 == ~t6_pc~0); 1919144#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1919145#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1919318#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1919583#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1919011#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1919012#L743 assume !(1 == ~M_E~0); 1918904#L743-2 assume !(1 == ~T1_E~0); 1918905#L748-1 assume !(1 == ~T2_E~0); 1919460#L753-1 assume !(1 == ~T3_E~0); 1919581#L758-1 assume !(1 == ~T4_E~0); 1919580#L763-1 assume !(1 == ~T5_E~0); 1919579#L768-1 assume !(1 == ~T6_E~0); 1919578#L773-1 assume !(1 == ~E_1~0); 1919010#L778-1 assume !(1 == ~E_2~0); 1918985#L783-1 assume !(1 == ~E_3~0); 1918986#L788-1 assume !(1 == ~E_4~0); 1919300#L793-1 assume !(1 == ~E_5~0); 1919249#L798-1 assume !(1 == ~E_6~0); 1918878#L803-1 assume { :end_inline_reset_delta_events } true; 1918879#L1024-2 assume !false; 2081374#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2081137#L645 [2022-07-14 16:04:19,675 INFO L754 eck$LassoCheckResult]: Loop: 2081137#L645 assume !false; 2081371#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2081369#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2081368#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2081366#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2081364#L556 assume 0 != eval_~tmp~0#1; 2081361#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2081358#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 2081168#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2081165#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 2081163#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2062481#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 2081160#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2081156#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 2081154#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2081151#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 2081149#L617 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2081145#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 2081142#L631 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 2081105#L648 assume !(0 != eval_~tmp_ndt_7~0#1); 2081137#L645 [2022-07-14 16:04:19,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:19,676 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 7 times [2022-07-14 16:04:19,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:19,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198589955] [2022-07-14 16:04:19,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:19,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:19,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:19,682 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:19,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:19,695 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:19,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:19,696 INFO L85 PathProgramCache]: Analyzing trace with hash -141880392, now seen corresponding path program 1 times [2022-07-14 16:04:19,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:19,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649044445] [2022-07-14 16:04:19,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:19,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:19,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:19,699 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:19,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:19,701 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:19,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:04:19,702 INFO L85 PathProgramCache]: Analyzing trace with hash -668208594, now seen corresponding path program 1 times [2022-07-14 16:04:19,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:04:19,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74520144] [2022-07-14 16:04:19,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:04:19,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:04:19,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:19,708 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:04:19,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:04:19,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:04:21,183 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 14.07 04:04:21 BoogieIcfgContainer [2022-07-14 16:04:21,186 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-14 16:04:21,186 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-14 16:04:21,187 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-14 16:04:21,187 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-14 16:04:21,187 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:03:42" (3/4) ... [2022-07-14 16:04:21,189 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-14 16:04:21,253 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-14 16:04:21,253 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-14 16:04:21,253 INFO L158 Benchmark]: Toolchain (without parser) took 40063.69ms. Allocated memory was 100.7MB in the beginning and 14.5GB in the end (delta: 14.4GB). Free memory was 71.3MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 4.8GB. Max. memory is 16.1GB. [2022-07-14 16:04:21,263 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 100.7MB. Free memory was 57.0MB in the beginning and 57.0MB in the end (delta: 48.0kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-14 16:04:21,264 INFO L158 Benchmark]: CACSL2BoogieTranslator took 300.93ms. Allocated memory was 100.7MB in the beginning and 136.3MB in the end (delta: 35.7MB). Free memory was 71.1MB in the beginning and 106.7MB in the end (delta: -35.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-07-14 16:04:21,264 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.40ms. Allocated memory is still 136.3MB. Free memory was 106.7MB in the beginning and 101.3MB in the end (delta: 5.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-07-14 16:04:21,264 INFO L158 Benchmark]: Boogie Preprocessor took 62.60ms. Allocated memory is still 136.3MB. Free memory was 101.3MB in the beginning and 96.3MB in the end (delta: 5.0MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-07-14 16:04:21,264 INFO L158 Benchmark]: RCFGBuilder took 787.21ms. Allocated memory is still 136.3MB. Free memory was 96.3MB in the beginning and 76.4MB in the end (delta: 19.9MB). Peak memory consumption was 27.2MB. Max. memory is 16.1GB. [2022-07-14 16:04:21,264 INFO L158 Benchmark]: BuchiAutomizer took 38770.57ms. Allocated memory was 136.3MB in the beginning and 14.5GB in the end (delta: 14.3GB). Free memory was 76.2MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 4.8GB. Max. memory is 16.1GB. [2022-07-14 16:04:21,264 INFO L158 Benchmark]: Witness Printer took 66.56ms. Allocated memory is still 14.5GB. Free memory was 9.6GB in the beginning and 9.6GB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-07-14 16:04:21,266 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 100.7MB. Free memory was 57.0MB in the beginning and 57.0MB in the end (delta: 48.0kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 300.93ms. Allocated memory was 100.7MB in the beginning and 136.3MB in the end (delta: 35.7MB). Free memory was 71.1MB in the beginning and 106.7MB in the end (delta: -35.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.40ms. Allocated memory is still 136.3MB. Free memory was 106.7MB in the beginning and 101.3MB in the end (delta: 5.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 62.60ms. Allocated memory is still 136.3MB. Free memory was 101.3MB in the beginning and 96.3MB in the end (delta: 5.0MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 787.21ms. Allocated memory is still 136.3MB. Free memory was 96.3MB in the beginning and 76.4MB in the end (delta: 19.9MB). Peak memory consumption was 27.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 38770.57ms. Allocated memory was 136.3MB in the beginning and 14.5GB in the end (delta: 14.3GB). Free memory was 76.2MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 4.8GB. Max. memory is 16.1GB. * Witness Printer took 66.56ms. Allocated memory is still 14.5GB. Free memory was 9.6GB in the beginning and 9.6GB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 28 terminating modules (28 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.28 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 367107 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 38.7s and 29 iterations. TraceHistogramMax:1. Analysis of lassos took 4.1s. Construction of modules took 0.6s. Büchi inclusion checks took 5.3s. Highest rank in rank-based complementation 0. Minimization of det autom 28. Minimization of nondet autom 0. Automata minimization 13.3s AutomataMinimizationTime, 28 MinimizatonAttempts, 65924 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 8.7s Buchi closure took 0.9s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 33340 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 33340 mSDsluCounter, 52310 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 23593 mSDsCounter, 350 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 836 IncrementalHoareTripleChecker+Invalid, 1186 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 350 mSolverCounterUnsat, 28717 mSDtfsCounter, 836 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc6 concLT0 SILN1 SILU0 SILI17 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 551]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, NULL=1, tmp=0, \result=0, t5_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@fbb41a5=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@67f82687=0, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@29abf0ea=0, tmp_ndt_2=0, \result=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_5=2, T6_E=2, E_1=2, tmp_ndt_1=0, tmp___4=0, __retres1=1, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c0ae42c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6ecc8da2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@604b12e6=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@186646ed=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@75f3a95b=0, t6_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a5791b2=0, tmp___2=0, m_pc=0, \result=0, \result=1, __retres1=0, t6_st=0, __retres1=0, tmp_ndt_7=0, E_6=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4842a91b=0, \result=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d53db86=0, tmp_ndt_6=0, tmp=0, t1_pc=0, t5_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@fc1338b=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, T5_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6eba43d6=0, t1_st=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49f1fba=0, __retres1=0, t2_pc=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b2e5aa7=0, __retres1=0, tmp_ndt_4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f344534=0, kernel_st=1, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@752317c2=0, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 551]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) [L675] COND FALSE !(T1_E == 0) [L680] COND FALSE !(T2_E == 0) [L685] COND FALSE !(T3_E == 0) [L690] COND FALSE !(T4_E == 0) [L695] COND FALSE !(T5_E == 0) [L700] COND FALSE !(T6_E == 0) [L705] COND FALSE !(E_1 == 0) [L710] COND FALSE !(E_2 == 0) [L715] COND FALSE !(E_3 == 0) [L720] COND FALSE !(E_4 == 0) [L725] COND FALSE !(E_5 == 0) [L730] COND FALSE !(E_6 == 0) [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; [L320] COND FALSE !(m_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; [L339] COND FALSE !(t1_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; [L358] COND FALSE !(t2_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; [L377] COND FALSE !(t3_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; [L396] COND FALSE !(t4_pc == 1) [L406] __retres1 = 0 [L408] return (__retres1); [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; [L415] COND FALSE !(t5_pc == 1) [L425] __retres1 = 0 [L427] return (__retres1); [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; [L434] COND FALSE !(t6_pc == 1) [L444] __retres1 = 0 [L446] return (__retres1); [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) [L748] COND FALSE !(T1_E == 1) [L753] COND FALSE !(T2_E == 1) [L758] COND FALSE !(T3_E == 1) [L763] COND FALSE !(T4_E == 1) [L768] COND FALSE !(T5_E == 1) [L773] COND FALSE !(T6_E == 1) [L778] COND FALSE !(E_1 == 1) [L783] COND FALSE !(E_2 == 1) [L788] COND FALSE !(E_3 == 1) [L793] COND FALSE !(E_4 == 1) [L798] COND FALSE !(E_5 == 1) [L803] COND FALSE !(E_6 == 1) [L1021] RET reset_delta_events() [L1024] COND TRUE 1 [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_1)) [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_2)) [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_3)) [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_4)) [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_5)) [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_6)) [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-14 16:04:21,315 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)