./Ultimate.py --spec ../../sv-benchmarks/c/Systems_DeviceDriversLinux64_ReachSafety.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default-EXP.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-26 23:22:01,525 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 23:22:01,526 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 23:22:01,537 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 23:22:01,537 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 23:22:01,538 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 23:22:01,539 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 23:22:01,542 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 23:22:01,543 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 23:22:01,544 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 23:22:01,545 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 23:22:01,545 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 23:22:01,546 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 23:22:01,547 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 23:22:01,549 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 23:22:01,550 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 23:22:01,550 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 23:22:01,552 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 23:22:01,554 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 23:22:01,556 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 23:22:01,557 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 23:22:01,558 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 23:22:01,561 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 23:22:01,561 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 23:22:01,561 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 23:22:01,562 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 23:22:01,563 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 23:22:01,564 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 23:22:01,565 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 23:22:01,567 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 23:22:01,567 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 23:22:01,567 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 23:22:01,568 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 23:22:01,568 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 23:22:01,570 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 23:22:01,570 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 23:22:01,571 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default-EXP.epf [2018-10-26 23:22:01,585 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 23:22:01,585 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 23:22:01,586 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 23:22:01,586 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-26 23:22:01,586 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-26 23:22:01,586 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-26 23:22:01,587 INFO L133 SettingsManager]: * Explicit value domain=true [2018-10-26 23:22:01,587 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-10-26 23:22:01,587 INFO L133 SettingsManager]: * Octagon Domain=false [2018-10-26 23:22:01,587 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-26 23:22:01,587 INFO L133 SettingsManager]: * Log string format=TERM [2018-10-26 23:22:01,588 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-10-26 23:22:01,588 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-10-26 23:22:01,588 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-26 23:22:01,590 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 23:22:01,590 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-26 23:22:01,591 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 23:22:01,591 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 23:22:01,591 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 23:22:01,591 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 23:22:01,591 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 23:22:01,592 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 23:22:01,592 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 23:22:01,592 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-26 23:22:01,592 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 23:22:01,592 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-26 23:22:01,593 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:22:01,593 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 23:22:01,593 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 23:22:01,593 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 23:22:01,593 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-10-26 23:22:01,593 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 23:22:01,594 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-26 23:22:01,594 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-26 23:22:01,594 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-10-26 23:22:01,594 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-10-26 23:22:01,628 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 23:22:01,639 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 23:22:01,643 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 23:22:01,645 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 23:22:01,645 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 23:22:01,646 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 23:22:01,704 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/52c4941cf/e704e2eefd574deda09b0e4569c5592e/FLAGca7e88443 [2018-10-26 23:22:02,301 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 23:22:02,303 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 23:22:02,327 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/52c4941cf/e704e2eefd574deda09b0e4569c5592e/FLAGca7e88443 [2018-10-26 23:22:02,340 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/52c4941cf/e704e2eefd574deda09b0e4569c5592e [2018-10-26 23:22:02,342 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 23:22:02,343 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 23:22:02,345 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 23:22:02,345 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 23:22:02,349 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 23:22:02,350 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:22:02" (1/1) ... [2018-10-26 23:22:02,353 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4bd1c1a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:02, skipping insertion in model container [2018-10-26 23:22:02,353 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:22:02" (1/1) ... [2018-10-26 23:22:02,365 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 23:22:02,435 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 23:22:03,364 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:22:03,403 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 23:22:03,875 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:22:03,947 INFO L193 MainTranslator]: Completed translation [2018-10-26 23:22:03,948 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03 WrapperNode [2018-10-26 23:22:03,948 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 23:22:03,949 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 23:22:03,949 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 23:22:03,950 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 23:22:03,959 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:03,988 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,045 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 23:22:04,046 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 23:22:04,046 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 23:22:04,046 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 23:22:04,057 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,057 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,071 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,072 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,103 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,113 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,122 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... [2018-10-26 23:22:04,132 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 23:22:04,132 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 23:22:04,133 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 23:22:04,133 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 23:22:04,134 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:22:04,192 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-10-26 23:22:04,192 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-10-26 23:22:04,192 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-10-26 23:22:04,192 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-10-26 23:22:04,192 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-10-26 23:22:04,193 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-10-26 23:22:04,193 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-10-26 23:22:04,193 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-10-26 23:22:04,193 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-10-26 23:22:04,193 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-10-26 23:22:04,193 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-10-26 23:22:04,193 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-10-26 23:22:04,194 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-10-26 23:22:04,195 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-10-26 23:22:04,195 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-10-26 23:22:04,196 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-10-26 23:22:04,196 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-10-26 23:22:04,196 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-10-26 23:22:04,196 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-10-26 23:22:04,196 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-10-26 23:22:04,196 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-10-26 23:22:04,196 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-10-26 23:22:04,197 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-10-26 23:22:04,197 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-10-26 23:22:04,197 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-10-26 23:22:04,197 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-10-26 23:22:04,197 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-10-26 23:22:04,197 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-10-26 23:22:04,197 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-10-26 23:22:04,197 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-10-26 23:22:04,198 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-10-26 23:22:04,198 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-10-26 23:22:04,198 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-10-26 23:22:04,198 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-10-26 23:22:04,198 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-26 23:22:04,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-26 23:22:04,198 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-10-26 23:22:04,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-10-26 23:22:04,199 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-10-26 23:22:04,199 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-10-26 23:22:04,199 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-10-26 23:22:04,199 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-10-26 23:22:04,199 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-26 23:22:04,199 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-26 23:22:04,199 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-10-26 23:22:04,200 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-10-26 23:22:04,200 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-10-26 23:22:04,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-10-26 23:22:04,200 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-10-26 23:22:04,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-10-26 23:22:04,204 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-10-26 23:22:04,204 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-10-26 23:22:04,205 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-10-26 23:22:04,205 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-10-26 23:22:04,205 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-10-26 23:22:04,205 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-10-26 23:22:04,205 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-10-26 23:22:04,205 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-10-26 23:22:04,205 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-10-26 23:22:04,205 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-10-26 23:22:04,206 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-10-26 23:22:04,206 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-10-26 23:22:04,206 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-10-26 23:22:04,206 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-10-26 23:22:04,206 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-10-26 23:22:04,206 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-10-26 23:22:04,206 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-10-26 23:22:04,206 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-10-26 23:22:04,207 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-10-26 23:22:04,207 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-10-26 23:22:04,207 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-10-26 23:22:04,207 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-10-26 23:22:04,207 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-10-26 23:22:04,207 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-10-26 23:22:04,207 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-10-26 23:22:04,207 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-10-26 23:22:04,208 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-10-26 23:22:04,208 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-10-26 23:22:04,208 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-10-26 23:22:04,208 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-10-26 23:22:04,208 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-10-26 23:22:04,211 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-10-26 23:22:04,212 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 23:22:04,212 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 23:22:07,546 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 23:22:07,547 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:22:07 BoogieIcfgContainer [2018-10-26 23:22:07,547 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 23:22:07,548 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-26 23:22:07,548 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-26 23:22:07,552 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-26 23:22:07,552 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.10 11:22:02" (1/3) ... [2018-10-26 23:22:07,553 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@28f802a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:22:07, skipping insertion in model container [2018-10-26 23:22:07,553 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:22:03" (2/3) ... [2018-10-26 23:22:07,554 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@28f802a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:22:07, skipping insertion in model container [2018-10-26 23:22:07,554 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:22:07" (3/3) ... [2018-10-26 23:22:07,556 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 23:22:07,567 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-26 23:22:07,576 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-10-26 23:22:07,590 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-10-26 23:22:07,625 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-26 23:22:07,625 INFO L383 AbstractCegarLoop]: Hoare is true [2018-10-26 23:22:07,625 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-26 23:22:07,626 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-26 23:22:07,626 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-26 23:22:07,626 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-26 23:22:07,626 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-26 23:22:07,626 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-26 23:22:07,653 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states. [2018-10-26 23:22:07,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 23:22:07,664 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:07,665 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:07,668 INFO L424 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:07,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:07,674 INFO L82 PathProgramCache]: Analyzing trace with hash 273110255, now seen corresponding path program 1 times [2018-10-26 23:22:07,677 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:07,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:07,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:07,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:07,745 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:07,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:08,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:22:08,049 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:22:08,049 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:22:08,049 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:08,054 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:22:08,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:22:08,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:22:08,065 INFO L87 Difference]: Start difference. First operand 362 states. Second operand 3 states. [2018-10-26 23:22:08,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:08,164 INFO L93 Difference]: Finished difference Result 612 states and 814 transitions. [2018-10-26 23:22:08,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:22:08,166 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-10-26 23:22:08,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:08,177 INFO L225 Difference]: With dead ends: 612 [2018-10-26 23:22:08,177 INFO L226 Difference]: Without dead ends: 248 [2018-10-26 23:22:08,183 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:22:08,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-10-26 23:22:08,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 248. [2018-10-26 23:22:08,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-10-26 23:22:08,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 314 transitions. [2018-10-26 23:22:08,253 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 314 transitions. Word has length 34 [2018-10-26 23:22:08,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:08,255 INFO L481 AbstractCegarLoop]: Abstraction has 248 states and 314 transitions. [2018-10-26 23:22:08,255 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:22:08,255 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 314 transitions. [2018-10-26 23:22:08,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 23:22:08,258 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:08,258 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:08,258 INFO L424 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:08,259 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:08,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1454992326, now seen corresponding path program 1 times [2018-10-26 23:22:08,259 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:08,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:08,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:08,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:08,263 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:08,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:08,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:22:08,432 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:22:08,432 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:22:08,432 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:08,433 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:22:08,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:22:08,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:22:08,434 INFO L87 Difference]: Start difference. First operand 248 states and 314 transitions. Second operand 5 states. [2018-10-26 23:22:08,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:08,982 INFO L93 Difference]: Finished difference Result 727 states and 939 transitions. [2018-10-26 23:22:08,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:22:08,985 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-10-26 23:22:08,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:08,992 INFO L225 Difference]: With dead ends: 727 [2018-10-26 23:22:08,994 INFO L226 Difference]: Without dead ends: 493 [2018-10-26 23:22:08,996 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:22:08,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493 states. [2018-10-26 23:22:09,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493 to 480. [2018-10-26 23:22:09,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2018-10-26 23:22:09,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 615 transitions. [2018-10-26 23:22:09,061 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 615 transitions. Word has length 47 [2018-10-26 23:22:09,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:09,061 INFO L481 AbstractCegarLoop]: Abstraction has 480 states and 615 transitions. [2018-10-26 23:22:09,061 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:22:09,061 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 615 transitions. [2018-10-26 23:22:09,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 23:22:09,063 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:09,063 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:09,064 INFO L424 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:09,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:09,064 INFO L82 PathProgramCache]: Analyzing trace with hash -1690200814, now seen corresponding path program 1 times [2018-10-26 23:22:09,064 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:09,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:09,071 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:09,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:09,071 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:09,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:09,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:22:09,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:22:09,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:22:09,250 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:09,250 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:22:09,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:22:09,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:22:09,251 INFO L87 Difference]: Start difference. First operand 480 states and 615 transitions. Second operand 5 states. [2018-10-26 23:22:09,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:09,440 INFO L93 Difference]: Finished difference Result 962 states and 1247 transitions. [2018-10-26 23:22:09,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:22:09,442 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-10-26 23:22:09,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:09,445 INFO L225 Difference]: With dead ends: 962 [2018-10-26 23:22:09,446 INFO L226 Difference]: Without dead ends: 496 [2018-10-26 23:22:09,447 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:22:09,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-10-26 23:22:09,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 484. [2018-10-26 23:22:09,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-10-26 23:22:09,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 615 transitions. [2018-10-26 23:22:09,499 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 615 transitions. Word has length 48 [2018-10-26 23:22:09,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:09,499 INFO L481 AbstractCegarLoop]: Abstraction has 484 states and 615 transitions. [2018-10-26 23:22:09,499 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:22:09,500 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 615 transitions. [2018-10-26 23:22:09,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 23:22:09,501 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:09,501 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:09,502 INFO L424 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:09,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:09,502 INFO L82 PathProgramCache]: Analyzing trace with hash 284618944, now seen corresponding path program 1 times [2018-10-26 23:22:09,502 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:09,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:09,504 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:09,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:09,505 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:09,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:09,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:22:09,614 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:22:09,614 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:22:09,614 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:09,614 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:22:09,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:22:09,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:22:09,615 INFO L87 Difference]: Start difference. First operand 484 states and 615 transitions. Second operand 3 states. [2018-10-26 23:22:09,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:09,990 INFO L93 Difference]: Finished difference Result 1146 states and 1460 transitions. [2018-10-26 23:22:09,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:22:09,991 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-10-26 23:22:09,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:09,995 INFO L225 Difference]: With dead ends: 1146 [2018-10-26 23:22:09,995 INFO L226 Difference]: Without dead ends: 676 [2018-10-26 23:22:09,999 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:22:10,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states. [2018-10-26 23:22:10,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 673. [2018-10-26 23:22:10,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2018-10-26 23:22:10,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 857 transitions. [2018-10-26 23:22:10,047 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 857 transitions. Word has length 45 [2018-10-26 23:22:10,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:10,052 INFO L481 AbstractCegarLoop]: Abstraction has 673 states and 857 transitions. [2018-10-26 23:22:10,052 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:22:10,052 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 857 transitions. [2018-10-26 23:22:10,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 23:22:10,053 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:10,053 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:10,054 INFO L424 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:10,054 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:10,054 INFO L82 PathProgramCache]: Analyzing trace with hash 1747554851, now seen corresponding path program 1 times [2018-10-26 23:22:10,054 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:10,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:10,056 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:10,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:10,056 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:10,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:10,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:22:10,204 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:22:10,204 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:22:10,204 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:10,204 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:22:10,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:22:10,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:22:10,205 INFO L87 Difference]: Start difference. First operand 673 states and 857 transitions. Second operand 5 states. [2018-10-26 23:22:10,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:10,795 INFO L93 Difference]: Finished difference Result 1354 states and 1739 transitions. [2018-10-26 23:22:10,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:22:10,796 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-10-26 23:22:10,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:10,799 INFO L225 Difference]: With dead ends: 1354 [2018-10-26 23:22:10,799 INFO L226 Difference]: Without dead ends: 705 [2018-10-26 23:22:10,802 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:22:10,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states. [2018-10-26 23:22:10,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 681. [2018-10-26 23:22:10,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2018-10-26 23:22:10,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 859 transitions. [2018-10-26 23:22:10,837 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 859 transitions. Word has length 49 [2018-10-26 23:22:10,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:10,837 INFO L481 AbstractCegarLoop]: Abstraction has 681 states and 859 transitions. [2018-10-26 23:22:10,837 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:22:10,838 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 859 transitions. [2018-10-26 23:22:10,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 23:22:10,838 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:10,839 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:10,839 INFO L424 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:10,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:10,839 INFO L82 PathProgramCache]: Analyzing trace with hash -1196674033, now seen corresponding path program 1 times [2018-10-26 23:22:10,839 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:10,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:10,843 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:10,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:10,843 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:10,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:10,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:22:10,962 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:22:10,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:22:10,962 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:10,962 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:22:10,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:22:10,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:22:10,963 INFO L87 Difference]: Start difference. First operand 681 states and 859 transitions. Second operand 5 states. [2018-10-26 23:22:11,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:11,509 INFO L93 Difference]: Finished difference Result 1297 states and 1651 transitions. [2018-10-26 23:22:11,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:22:11,510 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-10-26 23:22:11,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:11,512 INFO L225 Difference]: With dead ends: 1297 [2018-10-26 23:22:11,512 INFO L226 Difference]: Without dead ends: 640 [2018-10-26 23:22:11,514 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:22:11,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-10-26 23:22:11,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 622. [2018-10-26 23:22:11,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-10-26 23:22:11,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 777 transitions. [2018-10-26 23:22:11,546 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 777 transitions. Word has length 50 [2018-10-26 23:22:11,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:11,547 INFO L481 AbstractCegarLoop]: Abstraction has 622 states and 777 transitions. [2018-10-26 23:22:11,547 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:22:11,547 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 777 transitions. [2018-10-26 23:22:11,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-10-26 23:22:11,548 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:11,548 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:11,549 INFO L424 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:11,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:11,549 INFO L82 PathProgramCache]: Analyzing trace with hash -922844006, now seen corresponding path program 1 times [2018-10-26 23:22:11,549 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:11,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:11,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:11,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:11,553 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:11,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:12,277 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 23:22:12,277 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:22:12,277 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:22:12,278 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 63 with the following transitions: [2018-10-26 23:22:12,279 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [540], [555], [573], [583], [588], [590], [617], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [830], [834], [835], [878], [879], [880] [2018-10-26 23:22:12,315 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:22:12,315 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:22:12,650 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:22:12,651 INFO L272 AbstractInterpreter]: Visited 15 different actions 15 times. Never merged. Never widened. Never found a fixpoint. Largest state had 182 variables. [2018-10-26 23:22:12,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:12,693 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:22:12,886 INFO L227 lantSequenceWeakener]: Weakened 13 states. On average, predicates are now at 94.58% of their original sizes. [2018-10-26 23:22:12,887 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:22:13,337 INFO L415 sIntCurrentIteration]: We unified 61 AI predicates to 61 [2018-10-26 23:22:13,338 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:22:13,338 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:22:13,338 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [9] total 15 [2018-10-26 23:22:13,338 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:13,339 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:22:13,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:22:13,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:22:13,339 INFO L87 Difference]: Start difference. First operand 622 states and 777 transitions. Second operand 8 states. [2018-10-26 23:22:19,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:19,961 INFO L93 Difference]: Finished difference Result 1492 states and 1864 transitions. [2018-10-26 23:22:19,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:22:19,961 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 62 [2018-10-26 23:22:19,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:19,966 INFO L225 Difference]: With dead ends: 1492 [2018-10-26 23:22:19,966 INFO L226 Difference]: Without dead ends: 891 [2018-10-26 23:22:19,967 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 62 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:22:19,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 891 states. [2018-10-26 23:22:20,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 891 to 827. [2018-10-26 23:22:20,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 827 states. [2018-10-26 23:22:20,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1042 transitions. [2018-10-26 23:22:20,010 INFO L78 Accepts]: Start accepts. Automaton has 827 states and 1042 transitions. Word has length 62 [2018-10-26 23:22:20,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:20,010 INFO L481 AbstractCegarLoop]: Abstraction has 827 states and 1042 transitions. [2018-10-26 23:22:20,010 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:22:20,010 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1042 transitions. [2018-10-26 23:22:20,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-10-26 23:22:20,011 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:20,012 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:20,012 INFO L424 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:20,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:20,012 INFO L82 PathProgramCache]: Analyzing trace with hash -1234114431, now seen corresponding path program 1 times [2018-10-26 23:22:20,015 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:20,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:20,017 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:20,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:20,017 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:20,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:20,959 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 23:22:20,960 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:22:20,960 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:22:20,960 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 64 with the following transitions: [2018-10-26 23:22:20,960 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [830], [834], [835], [878], [879], [880] [2018-10-26 23:22:20,964 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:22:20,979 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:22:21,162 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:22:21,162 INFO L272 AbstractInterpreter]: Visited 35 different actions 39 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:22:21,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:21,205 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:22:21,442 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:22:21,443 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:22:22,944 INFO L415 sIntCurrentIteration]: We unified 62 AI predicates to 62 [2018-10-26 23:22:22,944 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:22:22,945 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:22:22,945 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [25] imperfect sequences [9] total 32 [2018-10-26 23:22:22,945 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:22,945 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-10-26 23:22:22,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-10-26 23:22:22,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=492, Unknown=0, NotChecked=0, Total=600 [2018-10-26 23:22:22,946 INFO L87 Difference]: Start difference. First operand 827 states and 1042 transitions. Second operand 25 states. [2018-10-26 23:22:40,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:22:40,379 INFO L93 Difference]: Finished difference Result 2011 states and 2547 transitions. [2018-10-26 23:22:40,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-10-26 23:22:40,379 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 63 [2018-10-26 23:22:40,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:22:40,384 INFO L225 Difference]: With dead ends: 2011 [2018-10-26 23:22:40,384 INFO L226 Difference]: Without dead ends: 1209 [2018-10-26 23:22:40,387 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 64 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 264 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=123, Invalid=579, Unknown=0, NotChecked=0, Total=702 [2018-10-26 23:22:40,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states. [2018-10-26 23:22:40,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 866. [2018-10-26 23:22:40,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 866 states. [2018-10-26 23:22:40,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 866 states to 866 states and 1093 transitions. [2018-10-26 23:22:40,472 INFO L78 Accepts]: Start accepts. Automaton has 866 states and 1093 transitions. Word has length 63 [2018-10-26 23:22:40,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:22:40,472 INFO L481 AbstractCegarLoop]: Abstraction has 866 states and 1093 transitions. [2018-10-26 23:22:40,473 INFO L482 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-10-26 23:22:40,474 INFO L276 IsEmpty]: Start isEmpty. Operand 866 states and 1093 transitions. [2018-10-26 23:22:40,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-10-26 23:22:40,475 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:22:40,475 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:22:40,475 INFO L424 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:22:40,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:40,476 INFO L82 PathProgramCache]: Analyzing trace with hash -1389860382, now seen corresponding path program 1 times [2018-10-26 23:22:40,476 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:22:40,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:40,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:22:40,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:22:40,478 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:22:40,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:22:40,839 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 23:22:40,839 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:22:40,839 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:22:40,839 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 65 with the following transitions: [2018-10-26 23:22:40,840 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [830], [834], [835], [878], [879], [880] [2018-10-26 23:22:40,843 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:22:40,843 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:22:40,984 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:22:40,985 INFO L272 AbstractInterpreter]: Visited 38 different actions 47 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:22:40,992 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:22:40,992 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:22:41,219 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:22:41,220 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:22:42,375 INFO L415 sIntCurrentIteration]: We unified 63 AI predicates to 63 [2018-10-26 23:22:42,375 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:22:42,375 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:22:42,375 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [10] total 34 [2018-10-26 23:22:42,375 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:22:42,376 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-10-26 23:22:42,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-10-26 23:22:42,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=538, Unknown=0, NotChecked=0, Total=650 [2018-10-26 23:22:42,376 INFO L87 Difference]: Start difference. First operand 866 states and 1093 transitions. Second operand 26 states. [2018-10-26 23:23:13,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:23:13,790 INFO L93 Difference]: Finished difference Result 2046 states and 2591 transitions. [2018-10-26 23:23:13,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-10-26 23:23:13,791 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 64 [2018-10-26 23:23:13,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:23:13,797 INFO L225 Difference]: With dead ends: 2046 [2018-10-26 23:23:13,797 INFO L226 Difference]: Without dead ends: 1448 [2018-10-26 23:23:13,799 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 65 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 283 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-10-26 23:23:13,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states. [2018-10-26 23:23:13,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 927. [2018-10-26 23:23:13,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 927 states. [2018-10-26 23:23:13,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 927 states to 927 states and 1178 transitions. [2018-10-26 23:23:13,886 INFO L78 Accepts]: Start accepts. Automaton has 927 states and 1178 transitions. Word has length 64 [2018-10-26 23:23:13,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:23:13,886 INFO L481 AbstractCegarLoop]: Abstraction has 927 states and 1178 transitions. [2018-10-26 23:23:13,886 INFO L482 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-10-26 23:23:13,886 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 1178 transitions. [2018-10-26 23:23:13,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-10-26 23:23:13,887 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:23:13,888 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:23:13,888 INFO L424 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:23:13,888 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:23:13,888 INFO L82 PathProgramCache]: Analyzing trace with hash 115780858, now seen corresponding path program 1 times [2018-10-26 23:23:13,888 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:23:13,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:23:13,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:23:13,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:23:13,892 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:23:13,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:23:14,226 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 23:23:14,226 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:23:14,226 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:23:14,226 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 66 with the following transitions: [2018-10-26 23:23:14,227 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [519], [521], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [824], [825], [830], [834], [835], [878], [879], [880] [2018-10-26 23:23:14,229 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:23:14,229 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:23:14,356 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:23:14,356 INFO L272 AbstractInterpreter]: Visited 39 different actions 48 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:23:14,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:23:14,357 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:23:14,549 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:23:14,549 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:23:15,692 INFO L415 sIntCurrentIteration]: We unified 64 AI predicates to 64 [2018-10-26 23:23:15,693 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:23:15,693 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:23:15,693 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-10-26 23:23:15,693 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:23:15,693 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-10-26 23:23:15,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-10-26 23:23:15,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-10-26 23:23:15,694 INFO L87 Difference]: Start difference. First operand 927 states and 1178 transitions. Second operand 27 states. [2018-10-26 23:23:38,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:23:38,560 INFO L93 Difference]: Finished difference Result 2088 states and 2645 transitions. [2018-10-26 23:23:38,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-10-26 23:23:38,561 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 65 [2018-10-26 23:23:38,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:23:38,567 INFO L225 Difference]: With dead ends: 2088 [2018-10-26 23:23:38,567 INFO L226 Difference]: Without dead ends: 1490 [2018-10-26 23:23:38,569 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 66 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 302 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=131, Invalid=681, Unknown=0, NotChecked=0, Total=812 [2018-10-26 23:23:38,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states. [2018-10-26 23:23:38,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 962. [2018-10-26 23:23:38,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 962 states. [2018-10-26 23:23:38,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 962 states to 962 states and 1225 transitions. [2018-10-26 23:23:38,659 INFO L78 Accepts]: Start accepts. Automaton has 962 states and 1225 transitions. Word has length 65 [2018-10-26 23:23:38,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:23:38,659 INFO L481 AbstractCegarLoop]: Abstraction has 962 states and 1225 transitions. [2018-10-26 23:23:38,659 INFO L482 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-10-26 23:23:38,659 INFO L276 IsEmpty]: Start isEmpty. Operand 962 states and 1225 transitions. [2018-10-26 23:23:38,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-26 23:23:38,662 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:23:38,662 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:23:38,662 INFO L424 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:23:38,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:23:38,662 INFO L82 PathProgramCache]: Analyzing trace with hash 1584817467, now seen corresponding path program 1 times [2018-10-26 23:23:38,663 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:23:38,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:23:38,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:23:38,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:23:38,664 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:23:38,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:23:38,812 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 23:23:38,812 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:23:38,812 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:23:38,813 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 67 with the following transitions: [2018-10-26 23:23:38,813 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [826], [827], [830], [834], [835], [878], [879], [880] [2018-10-26 23:23:38,815 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:23:38,815 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:23:38,903 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:23:38,903 INFO L272 AbstractInterpreter]: Visited 40 different actions 49 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:23:38,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:23:38,908 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:23:39,037 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:23:39,037 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:23:40,217 INFO L415 sIntCurrentIteration]: We unified 65 AI predicates to 65 [2018-10-26 23:23:40,217 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:23:40,218 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:23:40,218 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-10-26 23:23:40,218 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:23:40,218 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-10-26 23:23:40,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-10-26 23:23:40,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=636, Unknown=0, NotChecked=0, Total=756 [2018-10-26 23:23:40,219 INFO L87 Difference]: Start difference. First operand 962 states and 1225 transitions. Second operand 28 states. [2018-10-26 23:23:59,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:23:59,806 INFO L93 Difference]: Finished difference Result 2130 states and 2698 transitions. [2018-10-26 23:23:59,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-10-26 23:23:59,806 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 66 [2018-10-26 23:23:59,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:23:59,810 INFO L225 Difference]: With dead ends: 2130 [2018-10-26 23:23:59,810 INFO L226 Difference]: Without dead ends: 1532 [2018-10-26 23:23:59,811 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 67 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-10-26 23:23:59,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1532 states. [2018-10-26 23:23:59,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1532 to 997. [2018-10-26 23:23:59,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 997 states. [2018-10-26 23:23:59,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 997 states to 997 states and 1271 transitions. [2018-10-26 23:23:59,912 INFO L78 Accepts]: Start accepts. Automaton has 997 states and 1271 transitions. Word has length 66 [2018-10-26 23:23:59,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:23:59,913 INFO L481 AbstractCegarLoop]: Abstraction has 997 states and 1271 transitions. [2018-10-26 23:23:59,913 INFO L482 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-10-26 23:23:59,913 INFO L276 IsEmpty]: Start isEmpty. Operand 997 states and 1271 transitions. [2018-10-26 23:23:59,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-10-26 23:23:59,916 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:23:59,916 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:23:59,916 INFO L424 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:23:59,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:23:59,916 INFO L82 PathProgramCache]: Analyzing trace with hash -821331501, now seen corresponding path program 1 times [2018-10-26 23:23:59,917 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:23:59,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:23:59,918 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:23:59,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:23:59,918 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:23:59,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:24:00,357 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 23:24:00,357 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:24:00,358 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:24:00,358 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 70 with the following transitions: [2018-10-26 23:24:00,358 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:24:00,360 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:24:00,360 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:24:00,463 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:24:00,463 INFO L272 AbstractInterpreter]: Visited 41 different actions 45 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:24:00,465 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:00,465 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:24:00,667 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:24:00,667 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:24:01,603 INFO L415 sIntCurrentIteration]: We unified 68 AI predicates to 68 [2018-10-26 23:24:01,603 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:24:01,603 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:24:01,603 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-10-26 23:24:01,603 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:24:01,603 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-10-26 23:24:01,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-10-26 23:24:01,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=535, Unknown=0, NotChecked=0, Total=650 [2018-10-26 23:24:01,604 INFO L87 Difference]: Start difference. First operand 997 states and 1271 transitions. Second operand 26 states. [2018-10-26 23:24:11,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:24:11,048 INFO L93 Difference]: Finished difference Result 2409 states and 3064 transitions. [2018-10-26 23:24:11,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-10-26 23:24:11,048 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 69 [2018-10-26 23:24:11,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:24:11,054 INFO L225 Difference]: With dead ends: 2409 [2018-10-26 23:24:11,054 INFO L226 Difference]: Without dead ends: 1607 [2018-10-26 23:24:11,056 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 70 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 284 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=130, Invalid=626, Unknown=0, NotChecked=0, Total=756 [2018-10-26 23:24:11,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states. [2018-10-26 23:24:11,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1032. [2018-10-26 23:24:11,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1032 states. [2018-10-26 23:24:11,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1032 states to 1032 states and 1317 transitions. [2018-10-26 23:24:11,175 INFO L78 Accepts]: Start accepts. Automaton has 1032 states and 1317 transitions. Word has length 69 [2018-10-26 23:24:11,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:24:11,175 INFO L481 AbstractCegarLoop]: Abstraction has 1032 states and 1317 transitions. [2018-10-26 23:24:11,175 INFO L482 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-10-26 23:24:11,175 INFO L276 IsEmpty]: Start isEmpty. Operand 1032 states and 1317 transitions. [2018-10-26 23:24:11,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-10-26 23:24:11,178 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:24:11,178 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:24:11,178 INFO L424 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:24:11,178 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:11,178 INFO L82 PathProgramCache]: Analyzing trace with hash -1478491440, now seen corresponding path program 1 times [2018-10-26 23:24:11,179 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:24:11,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:11,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:24:11,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:11,182 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:24:11,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:24:11,620 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 23:24:11,621 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:24:11,621 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:24:11,621 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 71 with the following transitions: [2018-10-26 23:24:11,621 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:24:11,623 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:24:11,623 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:24:11,719 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:24:11,719 INFO L272 AbstractInterpreter]: Visited 44 different actions 53 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:24:11,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:11,724 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:24:11,883 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:24:11,883 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:24:12,850 INFO L415 sIntCurrentIteration]: We unified 69 AI predicates to 69 [2018-10-26 23:24:12,850 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:24:12,850 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:24:12,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-10-26 23:24:12,850 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:24:12,850 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-10-26 23:24:12,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-10-26 23:24:12,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=119, Invalid=583, Unknown=0, NotChecked=0, Total=702 [2018-10-26 23:24:12,851 INFO L87 Difference]: Start difference. First operand 1032 states and 1317 transitions. Second operand 27 states. [2018-10-26 23:24:23,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:24:23,582 INFO L93 Difference]: Finished difference Result 2244 states and 2848 transitions. [2018-10-26 23:24:23,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-10-26 23:24:23,582 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 70 [2018-10-26 23:24:23,582 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:24:23,586 INFO L225 Difference]: With dead ends: 2244 [2018-10-26 23:24:23,586 INFO L226 Difference]: Without dead ends: 1646 [2018-10-26 23:24:23,589 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 71 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 304 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=134, Invalid=678, Unknown=0, NotChecked=0, Total=812 [2018-10-26 23:24:23,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1646 states. [2018-10-26 23:24:23,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1646 to 1093. [2018-10-26 23:24:23,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1093 states. [2018-10-26 23:24:23,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1093 states to 1093 states and 1402 transitions. [2018-10-26 23:24:23,723 INFO L78 Accepts]: Start accepts. Automaton has 1093 states and 1402 transitions. Word has length 70 [2018-10-26 23:24:23,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:24:23,723 INFO L481 AbstractCegarLoop]: Abstraction has 1093 states and 1402 transitions. [2018-10-26 23:24:23,723 INFO L482 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-10-26 23:24:23,723 INFO L276 IsEmpty]: Start isEmpty. Operand 1093 states and 1402 transitions. [2018-10-26 23:24:23,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-10-26 23:24:23,727 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:24:23,727 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:24:23,727 INFO L424 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:24:23,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:23,727 INFO L82 PathProgramCache]: Analyzing trace with hash 789073739, now seen corresponding path program 1 times [2018-10-26 23:24:23,727 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:24:23,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:23,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:24:23,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:23,729 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:24:23,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:24:23,834 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 23:24:23,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:24:23,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:24:23,835 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:24:23,835 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:24:23,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:24:23,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:24:23,836 INFO L87 Difference]: Start difference. First operand 1093 states and 1402 transitions. Second operand 3 states. [2018-10-26 23:24:24,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:24:24,386 INFO L93 Difference]: Finished difference Result 2119 states and 2735 transitions. [2018-10-26 23:24:24,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:24:24,387 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2018-10-26 23:24:24,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:24:24,390 INFO L225 Difference]: With dead ends: 2119 [2018-10-26 23:24:24,390 INFO L226 Difference]: Without dead ends: 1317 [2018-10-26 23:24:24,391 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:24:24,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1317 states. [2018-10-26 23:24:24,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1317 to 1314. [2018-10-26 23:24:24,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1314 states. [2018-10-26 23:24:24,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1314 states to 1314 states and 1692 transitions. [2018-10-26 23:24:24,523 INFO L78 Accepts]: Start accepts. Automaton has 1314 states and 1692 transitions. Word has length 70 [2018-10-26 23:24:24,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:24:24,523 INFO L481 AbstractCegarLoop]: Abstraction has 1314 states and 1692 transitions. [2018-10-26 23:24:24,523 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:24:24,523 INFO L276 IsEmpty]: Start isEmpty. Operand 1314 states and 1692 transitions. [2018-10-26 23:24:24,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-10-26 23:24:24,526 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:24:24,526 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:24:24,526 INFO L424 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:24:24,526 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:24,527 INFO L82 PathProgramCache]: Analyzing trace with hash 1663185356, now seen corresponding path program 1 times [2018-10-26 23:24:24,527 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:24:24,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:24,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:24:24,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:24,528 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:24:24,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:24:25,239 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 23:24:25,240 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:24:25,240 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:24:25,240 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 72 with the following transitions: [2018-10-26 23:24:25,240 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [519], [521], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [824], [825], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:24:25,242 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:24:25,242 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:24:25,340 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:24:25,340 INFO L272 AbstractInterpreter]: Visited 45 different actions 54 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:24:25,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:25,348 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:24:25,487 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:24:25,487 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:24:26,713 INFO L415 sIntCurrentIteration]: We unified 70 AI predicates to 70 [2018-10-26 23:24:26,713 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:24:26,713 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:24:26,713 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-10-26 23:24:26,714 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:24:26,714 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-10-26 23:24:26,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-10-26 23:24:26,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=633, Unknown=0, NotChecked=0, Total=756 [2018-10-26 23:24:26,715 INFO L87 Difference]: Start difference. First operand 1314 states and 1692 transitions. Second operand 28 states. [2018-10-26 23:24:43,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:24:43,960 INFO L93 Difference]: Finished difference Result 2811 states and 3588 transitions. [2018-10-26 23:24:43,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-10-26 23:24:43,960 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 71 [2018-10-26 23:24:43,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:24:43,965 INFO L225 Difference]: With dead ends: 2811 [2018-10-26 23:24:43,965 INFO L226 Difference]: Without dead ends: 2041 [2018-10-26 23:24:43,967 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 72 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 324 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=138, Invalid=732, Unknown=0, NotChecked=0, Total=870 [2018-10-26 23:24:43,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2041 states. [2018-10-26 23:24:44,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2041 to 1349. [2018-10-26 23:24:44,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1349 states. [2018-10-26 23:24:44,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1349 states to 1349 states and 1739 transitions. [2018-10-26 23:24:44,128 INFO L78 Accepts]: Start accepts. Automaton has 1349 states and 1739 transitions. Word has length 71 [2018-10-26 23:24:44,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:24:44,129 INFO L481 AbstractCegarLoop]: Abstraction has 1349 states and 1739 transitions. [2018-10-26 23:24:44,129 INFO L482 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-10-26 23:24:44,129 INFO L276 IsEmpty]: Start isEmpty. Operand 1349 states and 1739 transitions. [2018-10-26 23:24:44,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-10-26 23:24:44,131 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:24:44,132 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:24:44,132 INFO L424 AbstractCegarLoop]: === Iteration 16 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:24:44,132 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:44,132 INFO L82 PathProgramCache]: Analyzing trace with hash -1985250647, now seen corresponding path program 1 times [2018-10-26 23:24:44,132 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:24:44,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:44,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:24:44,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:44,134 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:24:44,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:24:44,445 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 23:24:44,445 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:24:44,445 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:24:44,445 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 73 with the following transitions: [2018-10-26 23:24:44,445 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [523], [526], [528], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [826], [827], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:24:44,447 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:24:44,447 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:24:44,560 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:24:44,560 INFO L272 AbstractInterpreter]: Visited 46 different actions 55 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:24:44,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:44,568 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:24:44,728 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:24:44,728 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:24:45,958 INFO L415 sIntCurrentIteration]: We unified 71 AI predicates to 71 [2018-10-26 23:24:45,958 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:24:45,959 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:24:45,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-10-26 23:24:45,959 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:24:45,959 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-10-26 23:24:45,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-10-26 23:24:45,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=685, Unknown=0, NotChecked=0, Total=812 [2018-10-26 23:24:45,960 INFO L87 Difference]: Start difference. First operand 1349 states and 1739 transitions. Second operand 29 states. [2018-10-26 23:24:59,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:24:59,241 INFO L93 Difference]: Finished difference Result 2853 states and 3641 transitions. [2018-10-26 23:24:59,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-10-26 23:24:59,241 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 72 [2018-10-26 23:24:59,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:24:59,245 INFO L225 Difference]: With dead ends: 2853 [2018-10-26 23:24:59,245 INFO L226 Difference]: Without dead ends: 2083 [2018-10-26 23:24:59,246 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 73 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 344 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=142, Invalid=788, Unknown=0, NotChecked=0, Total=930 [2018-10-26 23:24:59,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states. [2018-10-26 23:24:59,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 1384. [2018-10-26 23:24:59,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1384 states. [2018-10-26 23:24:59,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1384 states to 1384 states and 1785 transitions. [2018-10-26 23:24:59,421 INFO L78 Accepts]: Start accepts. Automaton has 1384 states and 1785 transitions. Word has length 72 [2018-10-26 23:24:59,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:24:59,421 INFO L481 AbstractCegarLoop]: Abstraction has 1384 states and 1785 transitions. [2018-10-26 23:24:59,421 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-10-26 23:24:59,421 INFO L276 IsEmpty]: Start isEmpty. Operand 1384 states and 1785 transitions. [2018-10-26 23:24:59,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-10-26 23:24:59,423 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:24:59,423 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:24:59,424 INFO L424 AbstractCegarLoop]: === Iteration 17 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:24:59,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:24:59,424 INFO L82 PathProgramCache]: Analyzing trace with hash -198691610, now seen corresponding path program 1 times [2018-10-26 23:24:59,424 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:24:59,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:59,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:24:59,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:24:59,429 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:24:59,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:25:00,011 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 15 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 23:25:00,012 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:25:00,012 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:25:00,012 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 81 with the following transitions: [2018-10-26 23:25:00,012 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [516], [519], [521], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [824], [825], [830], [834], [835], [878], [879], [880] [2018-10-26 23:25:00,014 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:25:00,014 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:25:00,130 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:25:00,131 INFO L272 AbstractInterpreter]: Visited 41 different actions 52 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:25:00,180 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:00,180 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:25:00,450 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:25:00,450 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:25:01,781 INFO L415 sIntCurrentIteration]: We unified 79 AI predicates to 79 [2018-10-26 23:25:01,781 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:25:01,781 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:25:01,782 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [12] total 40 [2018-10-26 23:25:01,782 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:25:01,782 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-10-26 23:25:01,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-10-26 23:25:01,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-10-26 23:25:01,783 INFO L87 Difference]: Start difference. First operand 1384 states and 1785 transitions. Second operand 30 states. [2018-10-26 23:25:20,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:25:20,120 INFO L93 Difference]: Finished difference Result 2888 states and 3688 transitions. [2018-10-26 23:25:20,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-10-26 23:25:20,121 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 80 [2018-10-26 23:25:20,121 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:25:20,125 INFO L225 Difference]: With dead ends: 2888 [2018-10-26 23:25:20,125 INFO L226 Difference]: Without dead ends: 2118 [2018-10-26 23:25:20,127 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 81 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-10-26 23:25:20,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2118 states. [2018-10-26 23:25:20,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2118 to 1428. [2018-10-26 23:25:20,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1428 states. [2018-10-26 23:25:20,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1428 states to 1428 states and 1842 transitions. [2018-10-26 23:25:20,323 INFO L78 Accepts]: Start accepts. Automaton has 1428 states and 1842 transitions. Word has length 80 [2018-10-26 23:25:20,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:25:20,323 INFO L481 AbstractCegarLoop]: Abstraction has 1428 states and 1842 transitions. [2018-10-26 23:25:20,323 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-10-26 23:25:20,323 INFO L276 IsEmpty]: Start isEmpty. Operand 1428 states and 1842 transitions. [2018-10-26 23:25:20,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-10-26 23:25:20,327 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:25:20,327 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:25:20,327 INFO L424 AbstractCegarLoop]: === Iteration 18 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:25:20,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:20,327 INFO L82 PathProgramCache]: Analyzing trace with hash 2019719707, now seen corresponding path program 1 times [2018-10-26 23:25:20,327 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:25:20,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:20,329 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:25:20,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:20,329 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:25:20,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:25:20,431 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 23:25:20,431 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:25:20,431 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:25:20,431 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:25:20,431 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:25:20,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:25:20,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:25:20,432 INFO L87 Difference]: Start difference. First operand 1428 states and 1842 transitions. Second operand 3 states. [2018-10-26 23:25:20,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:25:20,773 INFO L93 Difference]: Finished difference Result 2454 states and 3149 transitions. [2018-10-26 23:25:20,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:25:20,777 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 77 [2018-10-26 23:25:20,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:25:20,781 INFO L225 Difference]: With dead ends: 2454 [2018-10-26 23:25:20,782 INFO L226 Difference]: Without dead ends: 1422 [2018-10-26 23:25:20,783 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:25:20,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1422 states. [2018-10-26 23:25:20,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1422 to 1386. [2018-10-26 23:25:20,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1386 states. [2018-10-26 23:25:20,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1386 states to 1386 states and 1791 transitions. [2018-10-26 23:25:20,925 INFO L78 Accepts]: Start accepts. Automaton has 1386 states and 1791 transitions. Word has length 77 [2018-10-26 23:25:20,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:25:20,925 INFO L481 AbstractCegarLoop]: Abstraction has 1386 states and 1791 transitions. [2018-10-26 23:25:20,925 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:25:20,925 INFO L276 IsEmpty]: Start isEmpty. Operand 1386 states and 1791 transitions. [2018-10-26 23:25:20,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-10-26 23:25:20,927 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:25:20,927 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:25:20,927 INFO L424 AbstractCegarLoop]: === Iteration 19 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:25:20,927 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:20,927 INFO L82 PathProgramCache]: Analyzing trace with hash 643475997, now seen corresponding path program 1 times [2018-10-26 23:25:20,928 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:25:20,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:20,931 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:25:20,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:20,931 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:25:20,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:25:21,218 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 23:25:21,219 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:25:21,219 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:25:21,219 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 82 with the following transitions: [2018-10-26 23:25:21,219 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [516], [519], [521], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [824], [825], [830], [834], [835], [878], [879], [880] [2018-10-26 23:25:21,220 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:25:21,220 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:25:21,383 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:25:21,384 INFO L272 AbstractInterpreter]: Visited 43 different actions 59 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:25:21,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:21,429 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:25:21,597 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:25:21,598 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:25:22,806 INFO L415 sIntCurrentIteration]: We unified 80 AI predicates to 80 [2018-10-26 23:25:22,806 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:25:22,807 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:25:22,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-10-26 23:25:22,807 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:25:22,807 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-10-26 23:25:22,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-10-26 23:25:22,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-10-26 23:25:22,808 INFO L87 Difference]: Start difference. First operand 1386 states and 1791 transitions. Second operand 30 states. [2018-10-26 23:25:34,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:25:34,986 INFO L93 Difference]: Finished difference Result 2841 states and 3633 transitions. [2018-10-26 23:25:34,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-10-26 23:25:34,986 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 81 [2018-10-26 23:25:34,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:25:34,990 INFO L225 Difference]: With dead ends: 2841 [2018-10-26 23:25:34,990 INFO L226 Difference]: Without dead ends: 2099 [2018-10-26 23:25:34,992 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 82 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-10-26 23:25:34,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2099 states. [2018-10-26 23:25:35,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2099 to 1430. [2018-10-26 23:25:35,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1430 states. [2018-10-26 23:25:35,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1430 states to 1430 states and 1848 transitions. [2018-10-26 23:25:35,155 INFO L78 Accepts]: Start accepts. Automaton has 1430 states and 1848 transitions. Word has length 81 [2018-10-26 23:25:35,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:25:35,155 INFO L481 AbstractCegarLoop]: Abstraction has 1430 states and 1848 transitions. [2018-10-26 23:25:35,155 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-10-26 23:25:35,155 INFO L276 IsEmpty]: Start isEmpty. Operand 1430 states and 1848 transitions. [2018-10-26 23:25:35,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-10-26 23:25:35,157 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:25:35,157 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:25:35,158 INFO L424 AbstractCegarLoop]: === Iteration 20 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:25:35,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:35,158 INFO L82 PathProgramCache]: Analyzing trace with hash 832763812, now seen corresponding path program 1 times [2018-10-26 23:25:35,158 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:25:35,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:35,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:25:35,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:35,160 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:25:35,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:25:35,341 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:25:35,342 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:25:35,342 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:25:35,342 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 80 with the following transitions: [2018-10-26 23:25:35,342 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [512], [514], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [822], [823], [830], [834], [835], [878], [879], [880] [2018-10-26 23:25:35,343 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:25:35,344 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:25:35,458 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:25:35,459 INFO L272 AbstractInterpreter]: Visited 40 different actions 51 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:25:35,460 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:35,460 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:25:35,633 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:25:35,633 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:25:36,742 INFO L415 sIntCurrentIteration]: We unified 78 AI predicates to 78 [2018-10-26 23:25:36,742 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:25:36,742 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:25:36,742 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-10-26 23:25:36,742 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:25:36,743 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-10-26 23:25:36,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-10-26 23:25:36,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=681, Unknown=0, NotChecked=0, Total=812 [2018-10-26 23:25:36,743 INFO L87 Difference]: Start difference. First operand 1430 states and 1848 transitions. Second operand 29 states. [2018-10-26 23:25:55,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:25:55,357 INFO L93 Difference]: Finished difference Result 2892 states and 3697 transitions. [2018-10-26 23:25:55,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-10-26 23:25:55,357 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 79 [2018-10-26 23:25:55,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:25:55,360 INFO L225 Difference]: With dead ends: 2892 [2018-10-26 23:25:55,360 INFO L226 Difference]: Without dead ends: 2150 [2018-10-26 23:25:55,361 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 80 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 362 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=146, Invalid=784, Unknown=0, NotChecked=0, Total=930 [2018-10-26 23:25:55,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2150 states. [2018-10-26 23:25:55,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2150 to 1474. [2018-10-26 23:25:55,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1474 states. [2018-10-26 23:25:55,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1474 states to 1474 states and 1905 transitions. [2018-10-26 23:25:55,525 INFO L78 Accepts]: Start accepts. Automaton has 1474 states and 1905 transitions. Word has length 79 [2018-10-26 23:25:55,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:25:55,525 INFO L481 AbstractCegarLoop]: Abstraction has 1474 states and 1905 transitions. [2018-10-26 23:25:55,525 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-10-26 23:25:55,525 INFO L276 IsEmpty]: Start isEmpty. Operand 1474 states and 1905 transitions. [2018-10-26 23:25:55,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-10-26 23:25:55,528 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:25:55,528 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:25:55,528 INFO L424 AbstractCegarLoop]: === Iteration 21 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:25:55,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:55,528 INFO L82 PathProgramCache]: Analyzing trace with hash -1367045507, now seen corresponding path program 1 times [2018-10-26 23:25:55,531 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:25:55,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:55,532 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:25:55,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:25:55,533 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:25:55,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:25:55,798 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:25:55,798 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:25:55,798 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:25:55,798 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 82 with the following transitions: [2018-10-26 23:25:55,798 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [516], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [826], [827], [830], [834], [835], [878], [879], [880] [2018-10-26 23:25:55,800 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:25:55,800 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:25:55,891 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:25:55,891 INFO L272 AbstractInterpreter]: Visited 42 different actions 53 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:25:55,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:25:55,893 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:25:56,048 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:25:56,048 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:25:57,311 INFO L415 sIntCurrentIteration]: We unified 80 AI predicates to 80 [2018-10-26 23:25:57,311 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:25:57,311 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:25:57,311 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-10-26 23:25:57,311 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:25:57,311 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-10-26 23:25:57,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-10-26 23:25:57,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=791, Unknown=0, NotChecked=0, Total=930 [2018-10-26 23:25:57,312 INFO L87 Difference]: Start difference. First operand 1474 states and 1905 transitions. Second operand 31 states. [2018-10-26 23:26:20,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:26:20,396 INFO L93 Difference]: Finished difference Result 2936 states and 3753 transitions. [2018-10-26 23:26:20,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-10-26 23:26:20,397 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 81 [2018-10-26 23:26:20,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:26:20,401 INFO L225 Difference]: With dead ends: 2936 [2018-10-26 23:26:20,401 INFO L226 Difference]: Without dead ends: 2194 [2018-10-26 23:26:20,403 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 82 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 410 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-10-26 23:26:20,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2194 states. [2018-10-26 23:26:20,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2194 to 1518. [2018-10-26 23:26:20,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1518 states. [2018-10-26 23:26:20,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1518 states to 1518 states and 1961 transitions. [2018-10-26 23:26:20,559 INFO L78 Accepts]: Start accepts. Automaton has 1518 states and 1961 transitions. Word has length 81 [2018-10-26 23:26:20,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:26:20,559 INFO L481 AbstractCegarLoop]: Abstraction has 1518 states and 1961 transitions. [2018-10-26 23:26:20,559 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-10-26 23:26:20,559 INFO L276 IsEmpty]: Start isEmpty. Operand 1518 states and 1961 transitions. [2018-10-26 23:26:20,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-10-26 23:26:20,561 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:26:20,561 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:26:20,561 INFO L424 AbstractCegarLoop]: === Iteration 22 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:26:20,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:26:20,561 INFO L82 PathProgramCache]: Analyzing trace with hash 1410958006, now seen corresponding path program 1 times [2018-10-26 23:26:20,561 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:26:20,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:26:20,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:26:20,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:26:20,563 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:26:20,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:26:20,762 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 23:26:20,762 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:26:20,762 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:26:20,763 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 84 with the following transitions: [2018-10-26 23:26:20,763 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [519], [521], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [824], [825], [826], [827], [830], [834], [835], [878], [879], [880] [2018-10-26 23:26:20,764 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:26:20,765 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:26:20,864 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:26:20,864 INFO L272 AbstractInterpreter]: Visited 44 different actions 60 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:26:20,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:26:20,872 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:26:21,085 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:26:21,086 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:26:22,519 INFO L415 sIntCurrentIteration]: We unified 82 AI predicates to 82 [2018-10-26 23:26:22,519 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:26:22,519 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:26:22,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-10-26 23:26:22,519 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:26:22,520 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-10-26 23:26:22,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-10-26 23:26:22,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=791, Unknown=0, NotChecked=0, Total=930 [2018-10-26 23:26:22,520 INFO L87 Difference]: Start difference. First operand 1518 states and 1961 transitions. Second operand 31 states. [2018-10-26 23:26:45,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:26:45,018 INFO L93 Difference]: Finished difference Result 2981 states and 3810 transitions. [2018-10-26 23:26:45,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-10-26 23:26:45,018 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 83 [2018-10-26 23:26:45,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:26:45,024 INFO L225 Difference]: With dead ends: 2981 [2018-10-26 23:26:45,024 INFO L226 Difference]: Without dead ends: 2239 [2018-10-26 23:26:45,025 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 84 GetRequests, 52 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-10-26 23:26:45,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2239 states. [2018-10-26 23:26:45,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2239 to 1562. [2018-10-26 23:26:45,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1562 states. [2018-10-26 23:26:45,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1562 states to 1562 states and 2017 transitions. [2018-10-26 23:26:45,217 INFO L78 Accepts]: Start accepts. Automaton has 1562 states and 2017 transitions. Word has length 83 [2018-10-26 23:26:45,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:26:45,218 INFO L481 AbstractCegarLoop]: Abstraction has 1562 states and 2017 transitions. [2018-10-26 23:26:45,218 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-10-26 23:26:45,218 INFO L276 IsEmpty]: Start isEmpty. Operand 1562 states and 2017 transitions. [2018-10-26 23:26:45,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-10-26 23:26:45,219 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:26:45,219 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:26:45,220 INFO L424 AbstractCegarLoop]: === Iteration 23 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:26:45,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:26:45,220 INFO L82 PathProgramCache]: Analyzing trace with hash -158323889, now seen corresponding path program 1 times [2018-10-26 23:26:45,220 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:26:45,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:26:45,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:26:45,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:26:45,221 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:26:45,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:26:45,486 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:26:45,486 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:26:45,487 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:26:45,487 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-10-26 23:26:45,487 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [516], [523], [526], [528], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [826], [827], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:26:45,488 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:26:45,488 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:26:45,583 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:26:45,583 INFO L272 AbstractInterpreter]: Visited 48 different actions 59 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:26:45,592 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:26:45,592 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:26:45,756 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:26:45,756 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:26:47,073 INFO L415 sIntCurrentIteration]: We unified 86 AI predicates to 86 [2018-10-26 23:26:47,073 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:26:47,073 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:26:47,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-10-26 23:26:47,073 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:26:47,074 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-10-26 23:26:47,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-10-26 23:26:47,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=846, Unknown=0, NotChecked=0, Total=992 [2018-10-26 23:26:47,074 INFO L87 Difference]: Start difference. First operand 1562 states and 2017 transitions. Second operand 32 states. [2018-10-26 23:27:09,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:27:09,500 INFO L93 Difference]: Finished difference Result 3025 states and 3868 transitions. [2018-10-26 23:27:09,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-10-26 23:27:09,500 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 87 [2018-10-26 23:27:09,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:27:09,504 INFO L225 Difference]: With dead ends: 3025 [2018-10-26 23:27:09,504 INFO L226 Difference]: Without dead ends: 2283 [2018-10-26 23:27:09,506 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 88 GetRequests, 55 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=161, Invalid=961, Unknown=0, NotChecked=0, Total=1122 [2018-10-26 23:27:09,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2283 states. [2018-10-26 23:27:09,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2283 to 1608. [2018-10-26 23:27:09,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1608 states. [2018-10-26 23:27:09,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1608 states to 1608 states and 2076 transitions. [2018-10-26 23:27:09,715 INFO L78 Accepts]: Start accepts. Automaton has 1608 states and 2076 transitions. Word has length 87 [2018-10-26 23:27:09,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:27:09,715 INFO L481 AbstractCegarLoop]: Abstraction has 1608 states and 2076 transitions. [2018-10-26 23:27:09,715 INFO L482 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-10-26 23:27:09,715 INFO L276 IsEmpty]: Start isEmpty. Operand 1608 states and 2076 transitions. [2018-10-26 23:27:09,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-10-26 23:27:09,718 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:27:09,719 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:27:09,719 INFO L424 AbstractCegarLoop]: === Iteration 24 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:27:09,719 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:09,719 INFO L82 PathProgramCache]: Analyzing trace with hash -833825378, now seen corresponding path program 1 times [2018-10-26 23:27:09,719 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:27:09,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:09,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:09,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:09,721 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:27:09,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:09,982 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 23:27:09,983 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:09,983 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:27:09,983 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 83 with the following transitions: [2018-10-26 23:27:09,983 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [516], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [826], [827], [830], [834], [835], [878], [879], [880] [2018-10-26 23:27:09,984 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:27:09,984 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:27:10,079 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:27:10,079 INFO L272 AbstractInterpreter]: Visited 44 different actions 60 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:27:10,084 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:10,085 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:27:10,241 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:27:10,242 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:27:11,665 INFO L415 sIntCurrentIteration]: We unified 81 AI predicates to 81 [2018-10-26 23:27:11,665 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:27:11,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:27:11,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-10-26 23:27:11,666 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:27:11,666 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-10-26 23:27:11,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-10-26 23:27:11,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=791, Unknown=0, NotChecked=0, Total=930 [2018-10-26 23:27:11,667 INFO L87 Difference]: Start difference. First operand 1608 states and 2076 transitions. Second operand 31 states. [2018-10-26 23:27:24,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:27:24,366 INFO L93 Difference]: Finished difference Result 3078 states and 3931 transitions. [2018-10-26 23:27:24,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-10-26 23:27:24,366 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 82 [2018-10-26 23:27:24,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:27:24,372 INFO L225 Difference]: With dead ends: 3078 [2018-10-26 23:27:24,372 INFO L226 Difference]: Without dead ends: 2336 [2018-10-26 23:27:24,373 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 83 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 405 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-10-26 23:27:24,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2336 states. [2018-10-26 23:27:24,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2336 to 1652. [2018-10-26 23:27:24,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1652 states. [2018-10-26 23:27:24,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1652 states to 1652 states and 2131 transitions. [2018-10-26 23:27:24,559 INFO L78 Accepts]: Start accepts. Automaton has 1652 states and 2131 transitions. Word has length 82 [2018-10-26 23:27:24,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:27:24,559 INFO L481 AbstractCegarLoop]: Abstraction has 1652 states and 2131 transitions. [2018-10-26 23:27:24,559 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-10-26 23:27:24,559 INFO L276 IsEmpty]: Start isEmpty. Operand 1652 states and 2131 transitions. [2018-10-26 23:27:24,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-10-26 23:27:24,561 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:27:24,561 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:27:24,561 INFO L424 AbstractCegarLoop]: === Iteration 25 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:27:24,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:24,562 INFO L82 PathProgramCache]: Analyzing trace with hash -1968261165, now seen corresponding path program 1 times [2018-10-26 23:27:24,562 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:27:24,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:24,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:24,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:24,563 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:27:24,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:24,655 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:27:24,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:27:24,656 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:27:24,656 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:27:24,656 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:27:24,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:27:24,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:27:24,657 INFO L87 Difference]: Start difference. First operand 1652 states and 2131 transitions. Second operand 3 states. [2018-10-26 23:27:25,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:27:25,355 INFO L93 Difference]: Finished difference Result 3072 states and 3929 transitions. [2018-10-26 23:27:25,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:27:25,356 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2018-10-26 23:27:25,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:27:25,360 INFO L225 Difference]: With dead ends: 3072 [2018-10-26 23:27:25,361 INFO L226 Difference]: Without dead ends: 2091 [2018-10-26 23:27:25,362 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:27:25,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2091 states. [2018-10-26 23:27:25,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2091 to 2067. [2018-10-26 23:27:25,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2067 states. [2018-10-26 23:27:25,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2067 states to 2067 states and 2626 transitions. [2018-10-26 23:27:25,568 INFO L78 Accepts]: Start accepts. Automaton has 2067 states and 2626 transitions. Word has length 82 [2018-10-26 23:27:25,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:27:25,569 INFO L481 AbstractCegarLoop]: Abstraction has 2067 states and 2626 transitions. [2018-10-26 23:27:25,569 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:27:25,569 INFO L276 IsEmpty]: Start isEmpty. Operand 2067 states and 2626 transitions. [2018-10-26 23:27:25,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-10-26 23:27:25,571 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:27:25,571 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:27:25,571 INFO L424 AbstractCegarLoop]: === Iteration 26 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:27:25,571 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:25,571 INFO L82 PathProgramCache]: Analyzing trace with hash 1852197615, now seen corresponding path program 1 times [2018-10-26 23:27:25,571 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:27:25,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:25,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:25,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:25,573 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:27:25,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:26,161 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 23:27:26,162 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:26,162 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:27:26,162 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-10-26 23:27:26,162 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [516], [519], [521], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [824], [825], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:27:26,163 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:27:26,164 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:27:26,288 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:27:26,288 INFO L272 AbstractInterpreter]: Visited 49 different actions 65 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:27:26,296 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:26,296 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:27:26,460 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:27:26,460 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:27:27,695 INFO L415 sIntCurrentIteration]: We unified 86 AI predicates to 86 [2018-10-26 23:27:27,695 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:27:27,695 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:27:27,695 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-10-26 23:27:27,695 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:27:27,696 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-10-26 23:27:27,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-10-26 23:27:27,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=788, Unknown=0, NotChecked=0, Total=930 [2018-10-26 23:27:27,696 INFO L87 Difference]: Start difference. First operand 2067 states and 2626 transitions. Second operand 31 states. [2018-10-26 23:27:40,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:27:40,245 INFO L93 Difference]: Finished difference Result 4087 states and 5144 transitions. [2018-10-26 23:27:40,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-10-26 23:27:40,246 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 87 [2018-10-26 23:27:40,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:27:40,253 INFO L225 Difference]: With dead ends: 4087 [2018-10-26 23:27:40,253 INFO L226 Difference]: Without dead ends: 3030 [2018-10-26 23:27:40,255 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 88 GetRequests, 56 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 401 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=157, Invalid=899, Unknown=0, NotChecked=0, Total=1056 [2018-10-26 23:27:40,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3030 states. [2018-10-26 23:27:40,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3030 to 2111. [2018-10-26 23:27:40,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2111 states. [2018-10-26 23:27:40,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2111 states to 2111 states and 2683 transitions. [2018-10-26 23:27:40,541 INFO L78 Accepts]: Start accepts. Automaton has 2111 states and 2683 transitions. Word has length 87 [2018-10-26 23:27:40,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:27:40,541 INFO L481 AbstractCegarLoop]: Abstraction has 2111 states and 2683 transitions. [2018-10-26 23:27:40,542 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-10-26 23:27:40,542 INFO L276 IsEmpty]: Start isEmpty. Operand 2111 states and 2683 transitions. [2018-10-26 23:27:40,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-10-26 23:27:40,543 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:27:40,543 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:27:40,544 INFO L424 AbstractCegarLoop]: === Iteration 27 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:27:40,544 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:40,544 INFO L82 PathProgramCache]: Analyzing trace with hash -479943434, now seen corresponding path program 1 times [2018-10-26 23:27:40,544 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:27:40,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:40,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:40,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:40,545 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:27:40,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:40,975 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:27:40,976 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:40,976 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:27:40,976 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 86 with the following transitions: [2018-10-26 23:27:40,976 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [512], [514], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [822], [823], [830], [834], [835], [872], [873], [878], [879], [880] [2018-10-26 23:27:40,977 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:27:40,978 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:27:41,071 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 23:27:41,071 INFO L272 AbstractInterpreter]: Visited 46 different actions 57 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-10-26 23:27:41,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:41,076 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 23:27:41,241 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-10-26 23:27:41,241 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 23:27:42,589 INFO L415 sIntCurrentIteration]: We unified 84 AI predicates to 84 [2018-10-26 23:27:42,589 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 23:27:42,589 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:27:42,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-10-26 23:27:42,589 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:27:42,590 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-10-26 23:27:42,590 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-10-26 23:27:42,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=732, Unknown=0, NotChecked=0, Total=870 [2018-10-26 23:27:42,590 INFO L87 Difference]: Start difference. First operand 2111 states and 2683 transitions. Second operand 30 states. [2018-10-26 23:27:55,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:27:55,450 INFO L93 Difference]: Finished difference Result 4145 states and 5215 transitions. [2018-10-26 23:27:55,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-10-26 23:27:55,451 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 85 [2018-10-26 23:27:55,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:27:55,457 INFO L225 Difference]: With dead ends: 4145 [2018-10-26 23:27:55,457 INFO L226 Difference]: Without dead ends: 3088 [2018-10-26 23:27:55,459 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 86 GetRequests, 55 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 386 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=153, Invalid=839, Unknown=0, NotChecked=0, Total=992 [2018-10-26 23:27:55,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3088 states. [2018-10-26 23:27:55,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3088 to 2155. [2018-10-26 23:27:55,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2155 states. [2018-10-26 23:27:55,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2155 states to 2155 states and 2740 transitions. [2018-10-26 23:27:55,741 INFO L78 Accepts]: Start accepts. Automaton has 2155 states and 2740 transitions. Word has length 85 [2018-10-26 23:27:55,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:27:55,741 INFO L481 AbstractCegarLoop]: Abstraction has 2155 states and 2740 transitions. [2018-10-26 23:27:55,741 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-10-26 23:27:55,741 INFO L276 IsEmpty]: Start isEmpty. Operand 2155 states and 2740 transitions. [2018-10-26 23:27:55,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-10-26 23:27:55,743 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:27:55,743 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:27:55,743 INFO L424 AbstractCegarLoop]: === Iteration 28 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:27:55,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:55,743 INFO L82 PathProgramCache]: Analyzing trace with hash 913353771, now seen corresponding path program 1 times [2018-10-26 23:27:55,743 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:27:55,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:55,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:55,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:55,745 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:27:55,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:55,994 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:27:55,994 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:55,994 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:27:55,995 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 84 with the following transitions: [2018-10-26 23:27:55,995 INFO L202 CegarAbsIntRunner]: [19], [20], [21], [23], [25], [27], [39], [42], [45], [57], [60], [63], [65], [68], [77], [96], [256], [259], [262], [265], [272], [276], [283], [302], [331], [350], [353], [356], [444], [498], [500], [501], [555], [573], [583], [588], [590], [601], [603], [617], [621], [623], [624], [672], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [750], [751], [752], [753], [782], [818], [819], [830], [834], [835], [838], [839], [840], [860], [878], [879], [880] [2018-10-26 23:27:55,996 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-10-26 23:27:55,996 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:27:56,657 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 23:27:56,657 INFO L272 AbstractInterpreter]: Visited 72 different actions 255 times. Merged at 26 different actions 87 times. Never widened. Found 6 fixpoints after 4 different actions. Largest state had 191 variables. [2018-10-26 23:27:56,704 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:56,705 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 23:27:56,706 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:56,706 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:27:56,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:56,726 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 23:27:56,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:56,872 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:27:57,061 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 23:27:57,061 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:27:57,281 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:27:57,300 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 23:27:57,300 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2018-10-26 23:27:57,300 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 23:27:57,300 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:27:57,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:27:57,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-10-26 23:27:57,301 INFO L87 Difference]: Start difference. First operand 2155 states and 2740 transitions. Second operand 8 states. [2018-10-26 23:27:57,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:27:57,808 INFO L93 Difference]: Finished difference Result 4285 states and 5453 transitions. [2018-10-26 23:27:57,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:27:57,809 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 83 [2018-10-26 23:27:57,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:27:57,815 INFO L225 Difference]: With dead ends: 4285 [2018-10-26 23:27:57,817 INFO L226 Difference]: Without dead ends: 2156 [2018-10-26 23:27:57,822 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 160 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=51, Invalid=81, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:27:57,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2156 states. [2018-10-26 23:27:58,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2156 to 2156. [2018-10-26 23:27:58,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2156 states. [2018-10-26 23:27:58,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2156 states to 2156 states and 2741 transitions. [2018-10-26 23:27:58,255 INFO L78 Accepts]: Start accepts. Automaton has 2156 states and 2741 transitions. Word has length 83 [2018-10-26 23:27:58,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:27:58,255 INFO L481 AbstractCegarLoop]: Abstraction has 2156 states and 2741 transitions. [2018-10-26 23:27:58,255 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:27:58,255 INFO L276 IsEmpty]: Start isEmpty. Operand 2156 states and 2741 transitions. [2018-10-26 23:27:58,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-10-26 23:27:58,260 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:27:58,260 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:27:58,260 INFO L424 AbstractCegarLoop]: === Iteration 29 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:27:58,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:27:58,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1642754396, now seen corresponding path program 2 times [2018-10-26 23:27:58,261 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:27:58,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:58,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:27:58,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:27:58,269 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:27:58,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:27:58,828 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:27:58,829 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:58,829 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:27:58,829 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 23:27:58,829 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 23:27:58,829 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:27:58,829 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:27:58,845 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 23:27:58,845 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 23:27:59,846 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-10-26 23:27:59,846 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 23:27:59,851 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:27:59,910 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 23:27:59,910 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:00,064 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:28:00,084 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 23:28:00,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 14 [2018-10-26 23:28:00,084 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 23:28:00,085 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 23:28:00,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 23:28:00,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2018-10-26 23:28:00,085 INFO L87 Difference]: Start difference. First operand 2156 states and 2741 transitions. Second operand 10 states. [2018-10-26 23:28:00,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:00,415 INFO L93 Difference]: Finished difference Result 4286 states and 5454 transitions. [2018-10-26 23:28:00,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:28:00,416 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 84 [2018-10-26 23:28:00,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:00,422 INFO L225 Difference]: With dead ends: 4286 [2018-10-26 23:28:00,423 INFO L226 Difference]: Without dead ends: 2157 [2018-10-26 23:28:00,426 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 160 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=82, Invalid=128, Unknown=0, NotChecked=0, Total=210 [2018-10-26 23:28:00,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2157 states. [2018-10-26 23:28:00,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2157 to 2157. [2018-10-26 23:28:00,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2157 states. [2018-10-26 23:28:00,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2157 states to 2157 states and 2742 transitions. [2018-10-26 23:28:00,822 INFO L78 Accepts]: Start accepts. Automaton has 2157 states and 2742 transitions. Word has length 84 [2018-10-26 23:28:00,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:00,822 INFO L481 AbstractCegarLoop]: Abstraction has 2157 states and 2742 transitions. [2018-10-26 23:28:00,822 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 23:28:00,822 INFO L276 IsEmpty]: Start isEmpty. Operand 2157 states and 2742 transitions. [2018-10-26 23:28:00,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-10-26 23:28:00,824 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:00,824 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:00,824 INFO L424 AbstractCegarLoop]: === Iteration 30 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:00,825 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:00,825 INFO L82 PathProgramCache]: Analyzing trace with hash 722271051, now seen corresponding path program 3 times [2018-10-26 23:28:00,825 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:28:00,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:28:00,826 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 23:28:00,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:28:00,826 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:28:00,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:01,115 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:28:01,115 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:28:01,115 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:28:01,115 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 23:28:01,115 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 23:28:01,115 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:28:01,116 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:28:01,129 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 23:28:01,129 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-10-26 23:28:01,246 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 23:28:01,247 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 23:28:01,252 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:01,356 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 23:28:01,356 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:01,441 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:28:01,458 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 23:28:01,458 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 16 [2018-10-26 23:28:01,458 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 23:28:01,459 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-26 23:28:01,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-26 23:28:01,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-10-26 23:28:01,459 INFO L87 Difference]: Start difference. First operand 2157 states and 2742 transitions. Second operand 12 states. [2018-10-26 23:28:01,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:01,752 INFO L93 Difference]: Finished difference Result 4287 states and 5455 transitions. [2018-10-26 23:28:01,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:28:01,753 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-10-26 23:28:01,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:01,757 INFO L225 Difference]: With dead ends: 4287 [2018-10-26 23:28:01,757 INFO L226 Difference]: Without dead ends: 2158 [2018-10-26 23:28:01,762 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 177 GetRequests, 160 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=106, Invalid=166, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:28:01,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2158 states. [2018-10-26 23:28:02,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2158 to 2158. [2018-10-26 23:28:02,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2158 states. [2018-10-26 23:28:02,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2158 states to 2158 states and 2743 transitions. [2018-10-26 23:28:02,156 INFO L78 Accepts]: Start accepts. Automaton has 2158 states and 2743 transitions. Word has length 85 [2018-10-26 23:28:02,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:02,156 INFO L481 AbstractCegarLoop]: Abstraction has 2158 states and 2743 transitions. [2018-10-26 23:28:02,156 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-26 23:28:02,156 INFO L276 IsEmpty]: Start isEmpty. Operand 2158 states and 2743 transitions. [2018-10-26 23:28:02,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-10-26 23:28:02,160 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:02,160 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:02,160 INFO L424 AbstractCegarLoop]: === Iteration 31 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:02,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:02,160 INFO L82 PathProgramCache]: Analyzing trace with hash 1023615876, now seen corresponding path program 4 times [2018-10-26 23:28:02,160 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:28:02,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:28:02,162 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 23:28:02,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:28:02,162 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:28:02,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 23:28:02,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 23:28:02,278 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-10-26 23:28:02,301 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,302 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,303 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,304 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,307 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,312 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,314 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,315 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,315 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,315 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,325 WARN L387 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-10-26 23:28:02,326 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,326 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,326 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,327 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,327 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,327 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,327 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,327 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,328 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,328 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,328 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,328 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,328 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,329 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,329 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,329 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,329 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,330 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,330 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,330 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,331 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,331 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,331 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,331 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,334 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,334 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,334 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,334 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,335 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,335 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,335 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,335 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,335 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,336 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,336 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,336 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,337 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,337 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,337 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,337 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,337 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,338 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,338 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,338 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,338 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,338 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,339 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,339 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,339 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,339 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,339 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,340 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,340 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,340 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,342 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,342 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,342 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,343 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,343 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,343 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,343 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,343 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,344 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,344 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,344 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,344 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,344 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,345 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,345 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,345 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:28:02,418 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 23:28:02,445 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:28:02,447 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:28:02,448 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:28:02,449 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:28:02,449 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:28:02,483 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.10 11:28:02 BoogieIcfgContainer [2018-10-26 23:28:02,483 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-10-26 23:28:02,483 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-26 23:28:02,483 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-26 23:28:02,483 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-26 23:28:02,484 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:22:07" (3/4) ... [2018-10-26 23:28:02,487 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-10-26 23:28:02,487 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-26 23:28:02,487 INFO L168 Benchmark]: Toolchain (without parser) took 360144.65 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 955.3 MB in the beginning and 1.4 GB in the end (delta: -413.6 MB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2018-10-26 23:28:02,490 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:28:02,490 INFO L168 Benchmark]: CACSL2BoogieTranslator took 1603.92 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 150.5 MB). Free memory was 955.3 MB in the beginning and 1.1 GB in the end (delta: -114.4 MB). Peak memory consumption was 104.7 MB. Max. memory is 11.5 GB. [2018-10-26 23:28:02,491 INFO L168 Benchmark]: Boogie Procedure Inliner took 96.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-10-26 23:28:02,491 INFO L168 Benchmark]: Boogie Preprocessor took 86.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-10-26 23:28:02,491 INFO L168 Benchmark]: RCFGBuilder took 3414.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.3 MB). Peak memory consumption was 184.1 MB. Max. memory is 11.5 GB. [2018-10-26 23:28:02,492 INFO L168 Benchmark]: TraceAbstraction took 354935.40 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.8 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -317.6 MB). Peak memory consumption was 3.5 GB. Max. memory is 11.5 GB. [2018-10-26 23:28:02,492 INFO L168 Benchmark]: Witness Printer took 3.63 ms. Allocated memory is still 5.0 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:28:02,494 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 1603.92 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 150.5 MB). Free memory was 955.3 MB in the beginning and 1.1 GB in the end (delta: -114.4 MB). Peak memory consumption was 104.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 96.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 86.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 3414.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.3 MB). Peak memory consumption was 184.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 354935.40 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.8 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -317.6 MB). Peak memory consumption was 3.5 GB. Max. memory is 11.5 GB. * Witness Printer took 3.63 ms. Allocated memory is still 5.0 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1684]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseAnd at line 1870. Possible FailurePath: [L1905] CALL "write failed:retry count exceeded.\n" [L1905] RET "write failed:retry count exceeded.\n" [L2072] CALL "name\t\t: %s\n" [L2072] RET "name\t\t: %s\n" [L2150] CALL "Unable to allocate resources for device.\n" [L2150] RET "Unable to allocate resources for device.\n" [L2159] CALL "Unable to request mem region for device.\n" [L2159] RET "Unable to request mem region for device.\n" [L2175] CALL "Unable to grab IOs for device.\n" [L2175] RET "Unable to grab IOs for device.\n" [L2189] CALL "info->tegra_rtc_lock" [L2189] RET "info->tegra_rtc_lock" [L2211] CALL "Unable to register device (err=%d).\n" [L2211] RET "Unable to register device (err=%d).\n" [L2218] CALL "rtc alarm" [L2218] RET "rtc alarm" [L2220] CALL "Unable to request interrupt for device (err=%d).\n" [L2220] RET "Unable to request interrupt for device (err=%d).\n" [L2226] CALL "Tegra internal Real Time Clock\n" [L2226] RET "Tegra internal Real Time Clock\n" [L2323] CALL, EXPR "tegra_rtc" [L2323] RET, EXPR "tegra_rtc" [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] CALL static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] CALL static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] CALL pm_message_t ldvarg2 ; [L2522] RET pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2533] FCALL ldv_initialize() [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] CALL, EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] EXPR, FCALL platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] RET return (tmp); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2569] CALL ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] RET tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2766] FCALL ldv_probe_2() [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={156:219}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={167:-16}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] CALL, EXPR info->rtc_base [L1867] RET, EXPR info->rtc_base [L1867] CALL, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] RET, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] RET return (__v & 1U); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={167:-16}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] RET return (0); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={167:-16}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={156:219}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2017] CALL ldv_spin_lock_check() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 42 procedures, 364 locations, 1 error locations. UNSAFE Result, 354.8s OverallTime, 31 OverallIterations, 4 TraceHistogramMax, 309.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9868 SDtfs, 7395 SDslu, 28485 SDs, 0 SdLazy, 10594 SolverSat, 1138 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 115.7s Time, PredicateUnifierStatistics: 36 DeclaredPredicates, 1938 GetRequests, 1352 SyntacticMatches, 21 SemanticMatches, 565 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6119 ImplicationChecksByTransitivity, 24.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=2158occurred in iteration=30, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 3.3s AbstIntTime, 19 AbstIntIterations, 18 AbstIntStrong, 0.9898314720298689 AbsIntWeakeningRatio, 3.441685477802859 AbsIntAvgWeakeningVarsNumRemoved, 65.40105342362679 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 4.7s AutomataMinimizationTime, 30 MinimizatonAttempts, 11242 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 1.7s SatisfiabilityAnalysisTime, 9.9s InterpolantComputationTime, 2439 NumberOfCodeBlocks, 2439 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 2569 ConstructedInterpolants, 0 QuantifiedInterpolants, 298915 SizeOfPredicates, 3 NumberOfNonLiveVariables, 2679 ConjunctsInSsa, 15 ConjunctsInUnsatCore, 36 InterpolantComputations, 9 PerfectInterpolantSequences, 427/586 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-1dbac8b [2018-10-26 23:28:04,548 INFO L170 SettingsManager]: Resetting all preferences to default values... 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[2018-10-26 23:28:04,587 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 23:28:04,587 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 23:28:04,588 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 23:28:04,592 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 23:28:04,593 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 23:28:04,594 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 23:28:04,595 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 23:28:04,596 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 23:28:04,597 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 23:28:04,597 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 23:28:04,597 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 23:28:04,598 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 23:28:04,598 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 23:28:04,598 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2018-10-26 23:28:04,610 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 23:28:04,611 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 23:28:04,611 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 23:28:04,611 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-26 23:28:04,611 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-26 23:28:04,612 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-26 23:28:04,612 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-26 23:28:04,612 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-26 23:28:04,613 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 23:28:04,613 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 23:28:04,613 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 23:28:04,614 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 23:28:04,614 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:28:04,615 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-10-26 23:28:04,615 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 23:28:04,616 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-10-26 23:28:04,616 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-10-26 23:28:04,616 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-10-26 23:28:04,649 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 23:28:04,662 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 23:28:04,665 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 23:28:04,666 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 23:28:04,666 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 23:28:04,667 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 23:28:04,714 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/19b362187/740d170263fb49719890530366c76a07/FLAGbcb85b5a6 [2018-10-26 23:28:05,229 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 23:28:05,230 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 23:28:05,249 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/19b362187/740d170263fb49719890530366c76a07/FLAGbcb85b5a6 [2018-10-26 23:28:05,261 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/data/19b362187/740d170263fb49719890530366c76a07 [2018-10-26 23:28:05,264 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 23:28:05,266 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 23:28:05,266 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 23:28:05,267 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 23:28:05,273 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 23:28:05,274 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:28:05" (1/1) ... [2018-10-26 23:28:05,276 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@101cf2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:05, skipping insertion in model container [2018-10-26 23:28:05,277 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:28:05" (1/1) ... [2018-10-26 23:28:05,285 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 23:28:05,374 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 23:28:06,856 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:28:06,879 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 23:28:07,757 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:28:07,953 INFO L193 MainTranslator]: Completed translation [2018-10-26 23:28:07,954 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07 WrapperNode [2018-10-26 23:28:07,954 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 23:28:07,955 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 23:28:07,956 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 23:28:07,956 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 23:28:07,963 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,004 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,091 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 23:28:08,095 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 23:28:08,095 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 23:28:08,096 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 23:28:08,104 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,104 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,118 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,119 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,151 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,158 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,167 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... [2018-10-26 23:28:08,177 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 23:28:08,177 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 23:28:08,177 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 23:28:08,177 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 23:28:08,178 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:28:08,246 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-10-26 23:28:08,247 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-10-26 23:28:08,248 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-10-26 23:28:08,248 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-10-26 23:28:08,248 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-10-26 23:28:08,248 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-10-26 23:28:08,248 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-10-26 23:28:08,249 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-10-26 23:28:08,249 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-10-26 23:28:08,249 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-10-26 23:28:08,249 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-10-26 23:28:08,249 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-10-26 23:28:08,249 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-10-26 23:28:08,250 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-10-26 23:28:08,250 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-10-26 23:28:08,251 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-10-26 23:28:08,251 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-10-26 23:28:08,252 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-10-26 23:28:08,252 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-10-26 23:28:08,252 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-10-26 23:28:08,252 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-10-26 23:28:08,252 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-10-26 23:28:08,253 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-10-26 23:28:08,253 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-10-26 23:28:08,253 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-10-26 23:28:08,253 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-10-26 23:28:08,253 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-10-26 23:28:08,253 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-10-26 23:28:08,253 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-10-26 23:28:08,254 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-10-26 23:28:08,254 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-10-26 23:28:08,254 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-10-26 23:28:08,254 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-10-26 23:28:08,254 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-10-26 23:28:08,254 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-26 23:28:08,254 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-26 23:28:08,254 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-10-26 23:28:08,254 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-10-26 23:28:08,254 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-10-26 23:28:08,254 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-10-26 23:28:08,255 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-10-26 23:28:08,255 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-10-26 23:28:08,255 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-26 23:28:08,255 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-26 23:28:08,255 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-10-26 23:28:08,255 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-10-26 23:28:08,255 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-10-26 23:28:08,255 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-10-26 23:28:08,255 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-10-26 23:28:08,255 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-10-26 23:28:08,256 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-10-26 23:28:08,256 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-10-26 23:28:08,256 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-10-26 23:28:08,256 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-10-26 23:28:08,256 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-10-26 23:28:08,256 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-10-26 23:28:08,262 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-10-26 23:28:08,262 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-10-26 23:28:08,262 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-10-26 23:28:08,262 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-10-26 23:28:08,262 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-10-26 23:28:08,262 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-10-26 23:28:08,263 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-10-26 23:28:08,263 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-10-26 23:28:08,263 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-10-26 23:28:08,263 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-10-26 23:28:08,263 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-10-26 23:28:08,263 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-10-26 23:28:08,263 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-10-26 23:28:08,263 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-10-26 23:28:08,263 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-10-26 23:28:08,263 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-10-26 23:28:08,263 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-10-26 23:28:08,264 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-10-26 23:28:08,264 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-10-26 23:28:08,264 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-10-26 23:28:08,264 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-10-26 23:28:08,264 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-10-26 23:28:08,264 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-10-26 23:28:08,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-10-26 23:28:08,264 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-10-26 23:28:08,264 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-10-26 23:28:08,264 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 23:28:08,265 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 23:28:12,884 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 23:28:12,884 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:28:12 BoogieIcfgContainer [2018-10-26 23:28:12,884 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 23:28:12,885 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-26 23:28:12,885 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-26 23:28:12,888 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-26 23:28:12,889 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.10 11:28:05" (1/3) ... [2018-10-26 23:28:12,889 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@18f9ee26 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:28:12, skipping insertion in model container [2018-10-26 23:28:12,889 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:28:07" (2/3) ... [2018-10-26 23:28:12,889 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@18f9ee26 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:28:12, skipping insertion in model container [2018-10-26 23:28:12,890 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:28:12" (3/3) ... [2018-10-26 23:28:12,891 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 23:28:12,900 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-26 23:28:12,907 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-10-26 23:28:12,919 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-10-26 23:28:12,945 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-26 23:28:12,946 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-26 23:28:12,946 INFO L383 AbstractCegarLoop]: Hoare is true [2018-10-26 23:28:12,946 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-26 23:28:12,946 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-26 23:28:12,946 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-26 23:28:12,946 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-26 23:28:12,946 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-26 23:28:12,946 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-26 23:28:12,967 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states. [2018-10-26 23:28:12,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 23:28:12,975 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:12,976 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:12,978 INFO L424 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:12,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:12,983 INFO L82 PathProgramCache]: Analyzing trace with hash 273110255, now seen corresponding path program 1 times [2018-10-26 23:28:12,988 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:12,988 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:13,021 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:13,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:13,206 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:13,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:13,295 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:28:13,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:28:13,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:28:13,306 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:28:13,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:28:13,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:28:13,320 INFO L87 Difference]: Start difference. First operand 362 states. Second operand 3 states. [2018-10-26 23:28:13,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:13,454 INFO L93 Difference]: Finished difference Result 612 states and 814 transitions. [2018-10-26 23:28:13,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:28:13,456 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-10-26 23:28:13,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:13,469 INFO L225 Difference]: With dead ends: 612 [2018-10-26 23:28:13,470 INFO L226 Difference]: Without dead ends: 248 [2018-10-26 23:28:13,475 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:28:13,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-10-26 23:28:13,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 248. [2018-10-26 23:28:13,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-10-26 23:28:13,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 314 transitions. [2018-10-26 23:28:13,545 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 314 transitions. Word has length 34 [2018-10-26 23:28:13,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:13,546 INFO L481 AbstractCegarLoop]: Abstraction has 248 states and 314 transitions. [2018-10-26 23:28:13,547 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:28:13,547 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 314 transitions. [2018-10-26 23:28:13,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 23:28:13,551 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:13,551 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:13,551 INFO L424 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:13,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:13,551 INFO L82 PathProgramCache]: Analyzing trace with hash 284618944, now seen corresponding path program 1 times [2018-10-26 23:28:13,552 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:13,552 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:13,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:13,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:13,732 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:13,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:13,785 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:28:13,789 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:28:13,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:28:13,790 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:28:13,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:28:13,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:28:13,791 INFO L87 Difference]: Start difference. First operand 248 states and 314 transitions. Second operand 3 states. [2018-10-26 23:28:14,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:14,173 INFO L93 Difference]: Finished difference Result 582 states and 740 transitions. [2018-10-26 23:28:14,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:28:14,173 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-10-26 23:28:14,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:14,176 INFO L225 Difference]: With dead ends: 582 [2018-10-26 23:28:14,176 INFO L226 Difference]: Without dead ends: 348 [2018-10-26 23:28:14,178 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:28:14,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 348 states. [2018-10-26 23:28:14,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 348 to 345. [2018-10-26 23:28:14,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 345 states. [2018-10-26 23:28:14,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 345 states to 345 states and 439 transitions. [2018-10-26 23:28:14,208 INFO L78 Accepts]: Start accepts. Automaton has 345 states and 439 transitions. Word has length 45 [2018-10-26 23:28:14,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:14,209 INFO L481 AbstractCegarLoop]: Abstraction has 345 states and 439 transitions. [2018-10-26 23:28:14,209 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:28:14,209 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 439 transitions. [2018-10-26 23:28:14,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 23:28:14,210 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:14,210 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:14,211 INFO L424 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:14,211 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:14,211 INFO L82 PathProgramCache]: Analyzing trace with hash 1454992326, now seen corresponding path program 1 times [2018-10-26 23:28:14,211 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:14,211 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:14,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:14,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:14,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:14,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:14,526 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:28:14,530 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:28:14,530 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:28:14,530 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:28:14,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:28:14,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:28:14,531 INFO L87 Difference]: Start difference. First operand 345 states and 439 transitions. Second operand 5 states. [2018-10-26 23:28:15,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:15,041 INFO L93 Difference]: Finished difference Result 1009 states and 1311 transitions. [2018-10-26 23:28:15,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:28:15,041 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-10-26 23:28:15,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:15,046 INFO L225 Difference]: With dead ends: 1009 [2018-10-26 23:28:15,046 INFO L226 Difference]: Without dead ends: 688 [2018-10-26 23:28:15,047 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:28:15,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states. [2018-10-26 23:28:15,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 665. [2018-10-26 23:28:15,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-10-26 23:28:15,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 855 transitions. [2018-10-26 23:28:15,108 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 855 transitions. Word has length 47 [2018-10-26 23:28:15,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:15,108 INFO L481 AbstractCegarLoop]: Abstraction has 665 states and 855 transitions. [2018-10-26 23:28:15,108 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:28:15,109 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 855 transitions. [2018-10-26 23:28:15,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 23:28:15,110 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:15,110 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:15,110 INFO L424 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:15,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:15,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1690200814, now seen corresponding path program 1 times [2018-10-26 23:28:15,111 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:15,111 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:15,132 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:15,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:15,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:15,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:15,386 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:28:15,397 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:28:15,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:28:15,397 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:28:15,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:28:15,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:28:15,398 INFO L87 Difference]: Start difference. First operand 665 states and 855 transitions. Second operand 5 states. [2018-10-26 23:28:15,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:15,627 INFO L93 Difference]: Finished difference Result 1338 states and 1739 transitions. [2018-10-26 23:28:15,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:28:15,628 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-10-26 23:28:15,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:15,632 INFO L225 Difference]: With dead ends: 1338 [2018-10-26 23:28:15,632 INFO L226 Difference]: Without dead ends: 697 [2018-10-26 23:28:15,634 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:28:15,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 697 states. [2018-10-26 23:28:15,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 697 to 673. [2018-10-26 23:28:15,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2018-10-26 23:28:15,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 857 transitions. [2018-10-26 23:28:15,692 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 857 transitions. Word has length 48 [2018-10-26 23:28:15,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:15,693 INFO L481 AbstractCegarLoop]: Abstraction has 673 states and 857 transitions. [2018-10-26 23:28:15,693 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:28:15,693 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 857 transitions. [2018-10-26 23:28:15,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 23:28:15,695 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:15,695 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:15,696 INFO L424 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:15,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:15,696 INFO L82 PathProgramCache]: Analyzing trace with hash 1747554851, now seen corresponding path program 1 times [2018-10-26 23:28:15,697 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:15,697 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:15,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:15,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:15,916 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:16,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:16,159 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:28:16,164 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:28:16,165 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:28:16,165 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:28:16,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:28:16,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:28:16,165 INFO L87 Difference]: Start difference. First operand 673 states and 857 transitions. Second operand 5 states. [2018-10-26 23:28:16,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:16,560 INFO L93 Difference]: Finished difference Result 1354 states and 1739 transitions. [2018-10-26 23:28:16,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:28:16,561 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-10-26 23:28:16,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:16,564 INFO L225 Difference]: With dead ends: 1354 [2018-10-26 23:28:16,564 INFO L226 Difference]: Without dead ends: 705 [2018-10-26 23:28:16,569 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:28:16,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states. [2018-10-26 23:28:16,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 681. [2018-10-26 23:28:16,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2018-10-26 23:28:16,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 859 transitions. [2018-10-26 23:28:16,619 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 859 transitions. Word has length 49 [2018-10-26 23:28:16,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:16,619 INFO L481 AbstractCegarLoop]: Abstraction has 681 states and 859 transitions. [2018-10-26 23:28:16,619 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:28:16,619 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 859 transitions. [2018-10-26 23:28:16,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 23:28:16,620 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:16,620 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:16,620 INFO L424 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:16,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:16,621 INFO L82 PathProgramCache]: Analyzing trace with hash -1196674033, now seen corresponding path program 1 times [2018-10-26 23:28:16,621 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:16,621 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:16,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:16,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:16,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:17,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:17,016 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:28:17,019 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:28:17,019 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:28:17,019 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:28:17,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:28:17,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:28:17,020 INFO L87 Difference]: Start difference. First operand 681 states and 859 transitions. Second operand 5 states. [2018-10-26 23:28:17,513 WARN L179 SmtUtils]: Spent 107.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 23:28:17,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:17,725 INFO L93 Difference]: Finished difference Result 1297 states and 1651 transitions. [2018-10-26 23:28:17,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 23:28:17,726 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-10-26 23:28:17,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:17,729 INFO L225 Difference]: With dead ends: 1297 [2018-10-26 23:28:17,729 INFO L226 Difference]: Without dead ends: 640 [2018-10-26 23:28:17,730 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:28:17,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-10-26 23:28:17,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 622. [2018-10-26 23:28:17,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-10-26 23:28:17,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 777 transitions. [2018-10-26 23:28:17,762 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 777 transitions. Word has length 50 [2018-10-26 23:28:17,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:17,763 INFO L481 AbstractCegarLoop]: Abstraction has 622 states and 777 transitions. [2018-10-26 23:28:17,763 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:28:17,763 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 777 transitions. [2018-10-26 23:28:17,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-10-26 23:28:17,764 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:17,764 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:17,764 INFO L424 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:17,765 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:17,765 INFO L82 PathProgramCache]: Analyzing trace with hash -922844006, now seen corresponding path program 1 times [2018-10-26 23:28:17,765 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:17,765 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:17,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:17,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:17,927 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:18,042 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 23:28:18,042 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:18,441 WARN L179 SmtUtils]: Spent 101.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-10-26 23:28:18,521 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 23:28:18,523 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 23:28:18,523 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 13 [2018-10-26 23:28:18,524 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-10-26 23:28:18,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-10-26 23:28:18,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-10-26 23:28:18,524 INFO L87 Difference]: Start difference. First operand 622 states and 777 transitions. Second operand 13 states. [2018-10-26 23:28:27,334 WARN L179 SmtUtils]: Spent 201.00 ms on a formula simplification. DAG size of input: 13 DAG size of output: 12 [2018-10-26 23:28:31,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:31,640 INFO L93 Difference]: Finished difference Result 1689 states and 2183 transitions. [2018-10-26 23:28:31,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-10-26 23:28:31,645 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 62 [2018-10-26 23:28:31,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:31,651 INFO L225 Difference]: With dead ends: 1689 [2018-10-26 23:28:31,651 INFO L226 Difference]: Without dead ends: 1091 [2018-10-26 23:28:31,653 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 112 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=152, Invalid=498, Unknown=0, NotChecked=0, Total=650 [2018-10-26 23:28:31,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1091 states. [2018-10-26 23:28:31,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1091 to 882. [2018-10-26 23:28:31,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 882 states. [2018-10-26 23:28:31,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 882 states to 882 states and 1106 transitions. [2018-10-26 23:28:31,707 INFO L78 Accepts]: Start accepts. Automaton has 882 states and 1106 transitions. Word has length 62 [2018-10-26 23:28:31,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:31,708 INFO L481 AbstractCegarLoop]: Abstraction has 882 states and 1106 transitions. [2018-10-26 23:28:31,708 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-10-26 23:28:31,708 INFO L276 IsEmpty]: Start isEmpty. Operand 882 states and 1106 transitions. [2018-10-26 23:28:31,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-10-26 23:28:31,710 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:31,710 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:31,710 INFO L424 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:31,710 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:31,710 INFO L82 PathProgramCache]: Analyzing trace with hash -330411799, now seen corresponding path program 1 times [2018-10-26 23:28:31,711 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:31,711 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:31,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:31,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:31,853 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:31,964 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:31,964 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:32,177 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:32,179 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:28:32,179 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:28:32,189 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:32,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:32,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:32,284 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:32,284 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:32,470 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:32,491 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:28:32,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-10-26 23:28:32,491 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-10-26 23:28:32,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-10-26 23:28:32,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-10-26 23:28:32,492 INFO L87 Difference]: Start difference. First operand 882 states and 1106 transitions. Second operand 14 states. [2018-10-26 23:28:44,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:44,085 INFO L93 Difference]: Finished difference Result 2048 states and 2577 transitions. [2018-10-26 23:28:44,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-10-26 23:28:44,086 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-10-26 23:28:44,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:44,090 INFO L225 Difference]: With dead ends: 2048 [2018-10-26 23:28:44,090 INFO L226 Difference]: Without dead ends: 1190 [2018-10-26 23:28:44,093 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-10-26 23:28:44,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1190 states. [2018-10-26 23:28:44,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1190 to 1121. [2018-10-26 23:28:44,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-10-26 23:28:44,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1418 transitions. [2018-10-26 23:28:44,148 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1418 transitions. Word has length 63 [2018-10-26 23:28:44,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:44,148 INFO L481 AbstractCegarLoop]: Abstraction has 1121 states and 1418 transitions. [2018-10-26 23:28:44,148 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-10-26 23:28:44,148 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1418 transitions. [2018-10-26 23:28:44,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-10-26 23:28:44,149 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:44,150 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:44,150 INFO L424 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:44,150 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:44,150 INFO L82 PathProgramCache]: Analyzing trace with hash -1401051437, now seen corresponding path program 1 times [2018-10-26 23:28:44,150 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:44,151 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:44,174 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:44,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:44,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:44,458 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:44,458 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:44,604 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:44,606 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:28:44,606 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:28:44,613 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:44,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:44,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:44,715 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:44,715 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:44,812 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:44,829 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:28:44,829 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-10-26 23:28:44,829 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-10-26 23:28:44,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-10-26 23:28:44,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-10-26 23:28:44,830 INFO L87 Difference]: Start difference. First operand 1121 states and 1418 transitions. Second operand 14 states. [2018-10-26 23:28:56,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:28:56,357 INFO L93 Difference]: Finished difference Result 2526 states and 3205 transitions. [2018-10-26 23:28:56,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-10-26 23:28:56,358 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 64 [2018-10-26 23:28:56,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:28:56,364 INFO L225 Difference]: With dead ends: 2526 [2018-10-26 23:28:56,364 INFO L226 Difference]: Without dead ends: 1429 [2018-10-26 23:28:56,367 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 241 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-10-26 23:28:56,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1429 states. [2018-10-26 23:28:56,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1429 to 1121. [2018-10-26 23:28:56,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-10-26 23:28:56,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1418 transitions. [2018-10-26 23:28:56,427 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1418 transitions. Word has length 64 [2018-10-26 23:28:56,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:28:56,428 INFO L481 AbstractCegarLoop]: Abstraction has 1121 states and 1418 transitions. [2018-10-26 23:28:56,428 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-10-26 23:28:56,428 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1418 transitions. [2018-10-26 23:28:56,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-10-26 23:28:56,431 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:28:56,431 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:28:56,431 INFO L424 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:28:56,431 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:28:56,431 INFO L82 PathProgramCache]: Analyzing trace with hash 1807656578, now seen corresponding path program 1 times [2018-10-26 23:28:56,432 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:28:56,433 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:28:56,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:56,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:56,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:57,177 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:57,177 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:57,563 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:57,564 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:28:57,564 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:28:57,572 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:28:57,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:28:57,657 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:28:57,666 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:57,667 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:28:57,975 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:28:57,994 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:28:57,994 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-10-26 23:28:57,994 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-10-26 23:28:57,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-10-26 23:28:57,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-10-26 23:28:57,995 INFO L87 Difference]: Start difference. First operand 1121 states and 1418 transitions. Second operand 14 states. [2018-10-26 23:29:06,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:29:06,467 INFO L93 Difference]: Finished difference Result 2197 states and 2774 transitions. [2018-10-26 23:29:06,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-10-26 23:29:06,467 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 65 [2018-10-26 23:29:06,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:29:06,471 INFO L225 Difference]: With dead ends: 2197 [2018-10-26 23:29:06,471 INFO L226 Difference]: Without dead ends: 1100 [2018-10-26 23:29:06,474 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 245 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2018-10-26 23:29:06,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1100 states. [2018-10-26 23:29:06,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1100 to 318. [2018-10-26 23:29:06,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 318 states. [2018-10-26 23:29:06,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 383 transitions. [2018-10-26 23:29:06,517 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 383 transitions. Word has length 65 [2018-10-26 23:29:06,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:29:06,518 INFO L481 AbstractCegarLoop]: Abstraction has 318 states and 383 transitions. [2018-10-26 23:29:06,518 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-10-26 23:29:06,518 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 383 transitions. [2018-10-26 23:29:06,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-10-26 23:29:06,519 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:29:06,519 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:29:06,519 INFO L424 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:29:06,519 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:29:06,520 INFO L82 PathProgramCache]: Analyzing trace with hash -265251566, now seen corresponding path program 1 times [2018-10-26 23:29:06,520 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:29:06,522 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:29:06,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:29:06,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:29:06,701 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:29:06,756 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:29:06,756 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:29:06,758 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:29:06,758 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:29:06,758 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:29:06,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:29:06,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:29:06,758 INFO L87 Difference]: Start difference. First operand 318 states and 383 transitions. Second operand 3 states. [2018-10-26 23:29:08,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:29:08,985 INFO L93 Difference]: Finished difference Result 689 states and 844 transitions. [2018-10-26 23:29:08,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:29:08,985 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2018-10-26 23:29:08,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:29:08,986 INFO L225 Difference]: With dead ends: 689 [2018-10-26 23:29:08,987 INFO L226 Difference]: Without dead ends: 395 [2018-10-26 23:29:08,987 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:29:08,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states. [2018-10-26 23:29:09,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2018-10-26 23:29:09,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395 states. [2018-10-26 23:29:09,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 479 transitions. [2018-10-26 23:29:09,022 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 479 transitions. Word has length 69 [2018-10-26 23:29:09,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:29:09,023 INFO L481 AbstractCegarLoop]: Abstraction has 395 states and 479 transitions. [2018-10-26 23:29:09,023 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:29:09,023 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 479 transitions. [2018-10-26 23:29:09,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-10-26 23:29:09,024 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:29:09,024 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:29:09,026 INFO L424 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:29:09,026 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:29:09,026 INFO L82 PathProgramCache]: Analyzing trace with hash -2005824742, now seen corresponding path program 1 times [2018-10-26 23:29:09,026 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:29:09,026 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:29:09,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:29:09,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:29:09,166 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:29:09,224 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 23:29:09,226 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:29:09,228 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:29:09,228 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:29:09,229 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:29:09,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:29:09,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:29:09,229 INFO L87 Difference]: Start difference. First operand 395 states and 479 transitions. Second operand 3 states. [2018-10-26 23:29:11,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:29:11,440 INFO L93 Difference]: Finished difference Result 936 states and 1133 transitions. [2018-10-26 23:29:11,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:29:11,441 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2018-10-26 23:29:11,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:29:11,443 INFO L225 Difference]: With dead ends: 936 [2018-10-26 23:29:11,443 INFO L226 Difference]: Without dead ends: 565 [2018-10-26 23:29:11,444 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:29:11,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 565 states. [2018-10-26 23:29:11,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 565 to 562. [2018-10-26 23:29:11,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-10-26 23:29:11,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 670 transitions. [2018-10-26 23:29:11,494 INFO L78 Accepts]: Start accepts. Automaton has 562 states and 670 transitions. Word has length 81 [2018-10-26 23:29:11,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:29:11,495 INFO L481 AbstractCegarLoop]: Abstraction has 562 states and 670 transitions. [2018-10-26 23:29:11,495 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:29:11,495 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 670 transitions. [2018-10-26 23:29:11,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-10-26 23:29:11,496 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:29:11,496 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:29:11,498 INFO L424 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:29:11,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:29:11,498 INFO L82 PathProgramCache]: Analyzing trace with hash -251117116, now seen corresponding path program 1 times [2018-10-26 23:29:11,498 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:29:11,498 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:29:11,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:29:11,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:29:11,825 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:29:11,855 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 23:29:11,855 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:29:11,857 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:29:11,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:29:11,858 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:29:11,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:29:11,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:29:11,858 INFO L87 Difference]: Start difference. First operand 562 states and 670 transitions. Second operand 4 states. [2018-10-26 23:29:11,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:29:11,908 INFO L93 Difference]: Finished difference Result 1104 states and 1318 transitions. [2018-10-26 23:29:11,909 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:29:11,909 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2018-10-26 23:29:11,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:29:11,910 INFO L225 Difference]: With dead ends: 1104 [2018-10-26 23:29:11,910 INFO L226 Difference]: Without dead ends: 563 [2018-10-26 23:29:11,911 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:29:11,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-10-26 23:29:11,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 563. [2018-10-26 23:29:11,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 563 states. [2018-10-26 23:29:11,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 671 transitions. [2018-10-26 23:29:11,961 INFO L78 Accepts]: Start accepts. Automaton has 563 states and 671 transitions. Word has length 82 [2018-10-26 23:29:11,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:29:11,961 INFO L481 AbstractCegarLoop]: Abstraction has 563 states and 671 transitions. [2018-10-26 23:29:11,961 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:29:11,961 INFO L276 IsEmpty]: Start isEmpty. Operand 563 states and 671 transitions. [2018-10-26 23:29:11,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-10-26 23:29:11,962 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:29:11,962 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:29:11,962 INFO L424 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:29:11,962 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:29:11,963 INFO L82 PathProgramCache]: Analyzing trace with hash 913353771, now seen corresponding path program 1 times [2018-10-26 23:29:11,963 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:29:11,963 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:29:11,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:29:12,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:29:12,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:29:12,283 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 23:29:12,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:29:12,346 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:29:12,348 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:29:12,349 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:29:12,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:29:12,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:29:12,458 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:29:12,462 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 23:29:12,462 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:29:12,545 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 23:29:12,563 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:29:12,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5] total 8 [2018-10-26 23:29:12,563 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:29:12,563 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:29:12,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:29:12,564 INFO L87 Difference]: Start difference. First operand 563 states and 671 transitions. Second operand 8 states. [2018-10-26 23:29:12,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:29:12,763 INFO L93 Difference]: Finished difference Result 1109 states and 1325 transitions. [2018-10-26 23:29:12,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-26 23:29:12,764 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 83 [2018-10-26 23:29:12,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:29:12,765 INFO L225 Difference]: With dead ends: 1109 [2018-10-26 23:29:12,765 INFO L226 Difference]: Without dead ends: 566 [2018-10-26 23:29:12,765 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-10-26 23:29:12,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 566 states. [2018-10-26 23:29:12,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 566 to 566. [2018-10-26 23:29:12,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 566 states. [2018-10-26 23:29:12,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 566 states to 566 states and 674 transitions. [2018-10-26 23:29:12,814 INFO L78 Accepts]: Start accepts. Automaton has 566 states and 674 transitions. Word has length 83 [2018-10-26 23:29:12,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:29:12,814 INFO L481 AbstractCegarLoop]: Abstraction has 566 states and 674 transitions. [2018-10-26 23:29:12,814 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:29:12,814 INFO L276 IsEmpty]: Start isEmpty. Operand 566 states and 674 transitions. [2018-10-26 23:29:12,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-10-26 23:29:12,815 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:29:12,815 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:29:12,816 INFO L424 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:29:12,816 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:29:12,816 INFO L82 PathProgramCache]: Analyzing trace with hash 1023615876, now seen corresponding path program 2 times [2018-10-26 23:29:12,818 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:29:12,818 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:29:12,848 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-10-26 23:29:14,329 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-26 23:29:14,329 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-10-26 23:29:15,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 23:29:15,769 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-10-26 23:29:15,804 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,808 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,811 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,814 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,817 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,817 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,819 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,821 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,822 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,822 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,824 WARN L387 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-10-26 23:29:15,824 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,825 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,825 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,825 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,825 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,826 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,826 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,826 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,826 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,827 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,827 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,827 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,827 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,828 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,828 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,830 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,831 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,831 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,832 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,832 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,832 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,833 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,833 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,833 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,835 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,835 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,836 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,836 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,836 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,838 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,839 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,839 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,839 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,839 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,840 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,840 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,840 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,840 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,841 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,841 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,841 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,841 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,842 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,842 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,842 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,842 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,843 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,843 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,843 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,843 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,844 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,844 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,844 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,848 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,848 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,848 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,849 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,849 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,849 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,849 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,850 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,850 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,850 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,850 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,851 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,851 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,851 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,851 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,852 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,852 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:15,892 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,892 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,895 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,895 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,898 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,898 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,901 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,901 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,903 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,903 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,905 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,905 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,907 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,907 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,908 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,909 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,910 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,910 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,911 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,912 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,920 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,920 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,921 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 23:29:15,922 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,922 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,923 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,924 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,932 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,932 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,933 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,933 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,934 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,934 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,935 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,935 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,936 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,941 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,942 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,942 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,943 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,943 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,944 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,944 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,946 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,946 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,947 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,947 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,947 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,948 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,948 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,948 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,949 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,949 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,950 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,950 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,951 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,951 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,952 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,952 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,958 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,959 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,960 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,960 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:15,961 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,961 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,961 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,962 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:15,962 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,962 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,963 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,963 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,964 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,964 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,966 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,966 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:15,967 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,968 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:15,969 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,969 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,970 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:15,973 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,974 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,974 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,975 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,975 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,975 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,976 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,976 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,977 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:15,977 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,003 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.10 11:29:16 BoogieIcfgContainer [2018-10-26 23:29:16,003 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-10-26 23:29:16,003 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-26 23:29:16,003 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-26 23:29:16,003 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-26 23:29:16,004 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:28:12" (3/4) ... [2018-10-26 23:29:16,009 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-10-26 23:29:16,015 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,016 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,017 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,018 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,018 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,018 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,019 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,019 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,020 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,020 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,021 WARN L387 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-10-26 23:29:16,021 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,022 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,022 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,022 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,022 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,022 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,023 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,023 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,023 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,023 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,023 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,027 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,028 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,028 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,029 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,029 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,029 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,029 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,030 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,030 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,030 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,030 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,031 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,031 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,034 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,037 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,037 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,037 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,037 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,038 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,038 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,038 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,038 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,038 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,039 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,039 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,039 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,039 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,039 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,040 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,040 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,040 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,043 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,043 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,043 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,043 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,044 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,044 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,044 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,044 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,045 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,045 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,045 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,045 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,045 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,046 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,046 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,046 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,046 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,046 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,047 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,047 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,047 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,047 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,047 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,048 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,048 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,048 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,052 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,052 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-10-26 23:29:16,085 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,087 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,088 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,089 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,090 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,091 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,091 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,092 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,092 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,092 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,093 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,093 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,094 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,094 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,095 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,095 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,095 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,096 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,098 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,098 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,099 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,099 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 23:29:16,099 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,100 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,100 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,101 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,101 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,102 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,102 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,102 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,102 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,103 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,103 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,104 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,104 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,107 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,107 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,108 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,108 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,109 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,110 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,111 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,111 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,112 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,112 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,112 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,113 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,113 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,113 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,114 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,114 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,115 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,115 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,116 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,116 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,118 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,118 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,119 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,119 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,120 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,120 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,121 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:16,121 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,121 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,122 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,122 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,122 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:16,123 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,123 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,123 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,124 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,127 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,127 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,128 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:16,128 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,128 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,129 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,129 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:16,129 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,130 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,130 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-10-26 23:29:16,130 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,131 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,131 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,131 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,132 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,132 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,135 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,135 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,136 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-10-26 23:29:16,221 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_786abda5-1ded-4cfb-8a8e-85aa70e507b8/bin-2019/utaipan/witness.graphml [2018-10-26 23:29:16,222 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-26 23:29:16,222 INFO L168 Benchmark]: Toolchain (without parser) took 70957.35 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 784.9 MB). Free memory was 949.2 MB in the beginning and 1.1 GB in the end (delta: -198.2 MB). Peak memory consumption was 586.6 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,223 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:29:16,223 INFO L168 Benchmark]: CACSL2BoogieTranslator took 2688.38 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 410.0 MB). Free memory was 949.2 MB in the beginning and 1.4 GB in the end (delta: -435.4 MB). Peak memory consumption was 451.4 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,223 INFO L168 Benchmark]: Boogie Procedure Inliner took 139.82 ms. Allocated memory is still 1.4 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 4.6 MB). Peak memory consumption was 4.6 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,225 INFO L168 Benchmark]: Boogie Preprocessor took 81.50 ms. Allocated memory is still 1.4 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 13.7 MB). Peak memory consumption was 13.7 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,225 INFO L168 Benchmark]: RCFGBuilder took 4707.52 ms. Allocated memory is still 1.4 GB. Free memory was 1.4 GB in the beginning and 1.1 GB in the end (delta: 275.3 MB). Peak memory consumption was 275.3 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,225 INFO L168 Benchmark]: TraceAbstraction took 63117.67 ms. Allocated memory was 1.4 GB in the beginning and 1.8 GB in the end (delta: 374.9 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -115.1 MB). Peak memory consumption was 259.8 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,225 INFO L168 Benchmark]: Witness Printer took 218.56 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 58.6 MB). Peak memory consumption was 58.6 MB. Max. memory is 11.5 GB. [2018-10-26 23:29:16,228 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 2688.38 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 410.0 MB). Free memory was 949.2 MB in the beginning and 1.4 GB in the end (delta: -435.4 MB). Peak memory consumption was 451.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 139.82 ms. Allocated memory is still 1.4 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 4.6 MB). Peak memory consumption was 4.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 81.50 ms. Allocated memory is still 1.4 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 13.7 MB). Peak memory consumption was 13.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 4707.52 ms. Allocated memory is still 1.4 GB. Free memory was 1.4 GB in the beginning and 1.1 GB in the end (delta: 275.3 MB). Peak memory consumption was 275.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 63117.67 ms. Allocated memory was 1.4 GB in the beginning and 1.8 GB in the end (delta: 374.9 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -115.1 MB). Peak memory consumption was 259.8 MB. Max. memory is 11.5 GB. * Witness Printer took 218.56 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 58.6 MB). Peak memory consumption was 58.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 1684]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L1905] CALL "write failed:retry count exceeded.\n" [L1905] RET "write failed:retry count exceeded.\n" [L2072] CALL "name\t\t: %s\n" [L2072] RET "name\t\t: %s\n" [L2150] CALL "Unable to allocate resources for device.\n" [L2150] RET "Unable to allocate resources for device.\n" [L2159] CALL "Unable to request mem region for device.\n" [L2159] RET "Unable to request mem region for device.\n" [L2175] CALL "Unable to grab IOs for device.\n" [L2175] RET "Unable to grab IOs for device.\n" [L2189] CALL "info->tegra_rtc_lock" [L2189] RET "info->tegra_rtc_lock" [L2211] CALL "Unable to register device (err=%d).\n" [L2211] RET "Unable to register device (err=%d).\n" [L2218] CALL "rtc alarm" [L2218] RET "rtc alarm" [L2220] CALL "Unable to request interrupt for device (err=%d).\n" [L2220] RET "Unable to request interrupt for device (err=%d).\n" [L2226] CALL "Tegra internal Real Time Clock\n" [L2226] RET "Tegra internal Real Time Clock\n" [L2323] CALL, EXPR "tegra_rtc" [L2323] RET, EXPR "tegra_rtc" [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] CALL static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] CALL static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] CALL pm_message_t ldvarg2 ; [L2522] RET pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2533] FCALL ldv_initialize() [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] CALL, EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] EXPR, FCALL platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] RET return (tmp); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2569] CALL ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] RET tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2766] FCALL ldv_probe_2() [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={1195909131:129}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] CALL, EXPR info->rtc_base [L1867] RET, EXPR info->rtc_base [L1867] CALL, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] RET, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] RET return (__v & 1U); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={1195909131:129}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] RET return (0); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={1195909131:129}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2017] CALL ldv_spin_lock_check() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 42 procedures, 364 locations, 1 error locations. UNSAFE Result, 63.0s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 51.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4553 SDtfs, 4949 SDslu, 11973 SDs, 0 SdLazy, 4927 SolverSat, 642 SolverUnsat, 18 SolverUnknown, 0 SolverNotchecked, 47.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1771 GetRequests, 1635 SyntacticMatches, 9 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 4.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1121occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 14 MinimizatonAttempts, 1463 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.8s SsaConstructionTime, 3.0s SatisfiabilityAnalysisTime, 4.2s InterpolantComputationTime, 1203 NumberOfCodeBlocks, 1203 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 1702 ConstructedInterpolants, 0 QuantifiedInterpolants, 231860 SizeOfPredicates, 60 NumberOfNonLiveVariables, 8478 ConjunctsInSsa, 138 ConjunctsInUnsatCore, 27 InterpolantComputations, 10 PerfectInterpolantSequences, 147/227 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...