./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-26 23:36:12,688 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 23:36:12,690 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 23:36:12,699 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 23:36:12,699 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 23:36:12,700 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 23:36:12,701 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 23:36:12,702 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 23:36:12,704 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 23:36:12,704 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 23:36:12,705 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 23:36:12,706 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 23:36:12,706 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 23:36:12,707 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 23:36:12,708 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 23:36:12,708 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 23:36:12,709 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 23:36:12,711 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 23:36:12,712 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 23:36:12,714 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 23:36:12,714 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 23:36:12,715 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 23:36:12,717 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 23:36:12,717 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 23:36:12,717 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 23:36:12,720 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 23:36:12,721 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 23:36:12,721 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 23:36:12,722 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 23:36:12,722 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 23:36:12,723 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 23:36:12,723 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 23:36:12,723 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 23:36:12,723 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 23:36:12,724 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 23:36:12,724 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 23:36:12,725 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-10-26 23:36:12,738 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 23:36:12,740 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 23:36:12,743 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 23:36:12,744 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-26 23:36:12,744 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-26 23:36:12,744 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-26 23:36:12,745 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-10-26 23:36:12,745 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-26 23:36:12,745 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-10-26 23:36:12,745 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-10-26 23:36:12,745 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-26 23:36:12,746 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 23:36:12,746 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-26 23:36:12,746 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-26 23:36:12,746 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-26 23:36:12,746 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 23:36:12,746 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 23:36:12,746 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 23:36:12,747 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 23:36:12,747 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-26 23:36:12,747 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 23:36:12,747 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 23:36:12,747 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 23:36:12,747 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-26 23:36:12,747 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 23:36:12,748 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-26 23:36:12,748 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:36:12,748 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 23:36:12,748 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 23:36:12,748 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 23:36:12,748 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-10-26 23:36:12,748 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 23:36:12,749 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-26 23:36:12,749 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-26 23:36:12,749 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 [2018-10-26 23:36:12,785 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 23:36:12,795 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 23:36:12,798 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 23:36:12,799 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 23:36:12,799 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 23:36:12,800 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c [2018-10-26 23:36:12,848 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/b68a2f905/4d149620fbda4248820a4ead1c12d5f4/FLAGf01d69640 [2018-10-26 23:36:13,247 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 23:36:13,248 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c [2018-10-26 23:36:13,256 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/b68a2f905/4d149620fbda4248820a4ead1c12d5f4/FLAGf01d69640 [2018-10-26 23:36:13,268 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/b68a2f905/4d149620fbda4248820a4ead1c12d5f4 [2018-10-26 23:36:13,272 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 23:36:13,274 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 23:36:13,275 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 23:36:13,275 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 23:36:13,279 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 23:36:13,279 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,281 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45c90e0c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13, skipping insertion in model container [2018-10-26 23:36:13,281 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,288 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 23:36:13,327 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 23:36:13,513 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:36:13,519 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 23:36:13,592 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:36:13,623 INFO L193 MainTranslator]: Completed translation [2018-10-26 23:36:13,624 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13 WrapperNode [2018-10-26 23:36:13,624 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 23:36:13,624 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 23:36:13,624 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 23:36:13,625 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 23:36:13,632 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,646 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,664 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 23:36:13,665 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 23:36:13,665 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 23:36:13,665 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 23:36:13,753 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,755 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,758 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,759 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,786 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,808 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,812 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... [2018-10-26 23:36:13,825 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 23:36:13,825 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 23:36:13,826 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 23:36:13,826 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 23:36:13,826 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:36:13,888 INFO L130 BoogieDeclarations]: Found specification of procedure read_manual_selection_history [2018-10-26 23:36:13,889 INFO L138 BoogieDeclarations]: Found implementation of procedure read_manual_selection_history [2018-10-26 23:36:13,889 INFO L130 BoogieDeclarations]: Found specification of procedure Side1_activestandby_task_each_pals_period [2018-10-26 23:36:13,889 INFO L138 BoogieDeclarations]: Found implementation of procedure Side1_activestandby_task_each_pals_period [2018-10-26 23:36:13,889 INFO L130 BoogieDeclarations]: Found specification of procedure write_active_side_history [2018-10-26 23:36:13,889 INFO L138 BoogieDeclarations]: Found implementation of procedure write_active_side_history [2018-10-26 23:36:13,890 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-26 23:36:13,890 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-26 23:36:13,890 INFO L130 BoogieDeclarations]: Found specification of procedure Console_task_each_pals_period [2018-10-26 23:36:13,890 INFO L138 BoogieDeclarations]: Found implementation of procedure Console_task_each_pals_period [2018-10-26 23:36:13,890 INFO L130 BoogieDeclarations]: Found specification of procedure read_side2_failed_history [2018-10-26 23:36:13,890 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side2_failed_history [2018-10-26 23:36:13,890 INFO L130 BoogieDeclarations]: Found specification of procedure assert [2018-10-26 23:36:13,890 INFO L138 BoogieDeclarations]: Found implementation of procedure assert [2018-10-26 23:36:13,890 INFO L130 BoogieDeclarations]: Found specification of procedure Pendulum_prism_task_each_pals_period [2018-10-26 23:36:13,890 INFO L138 BoogieDeclarations]: Found implementation of procedure Pendulum_prism_task_each_pals_period [2018-10-26 23:36:13,891 INFO L130 BoogieDeclarations]: Found specification of procedure write_manual_selection_history [2018-10-26 23:36:13,891 INFO L138 BoogieDeclarations]: Found implementation of procedure write_manual_selection_history [2018-10-26 23:36:13,891 INFO L130 BoogieDeclarations]: Found specification of procedure init [2018-10-26 23:36:13,891 INFO L138 BoogieDeclarations]: Found implementation of procedure init [2018-10-26 23:36:13,891 INFO L130 BoogieDeclarations]: Found specification of procedure flip_the_side [2018-10-26 23:36:13,891 INFO L138 BoogieDeclarations]: Found implementation of procedure flip_the_side [2018-10-26 23:36:13,891 INFO L130 BoogieDeclarations]: Found specification of procedure Side2_activestandby_task_each_pals_period [2018-10-26 23:36:13,891 INFO L138 BoogieDeclarations]: Found implementation of procedure Side2_activestandby_task_each_pals_period [2018-10-26 23:36:13,891 INFO L130 BoogieDeclarations]: Found specification of procedure check [2018-10-26 23:36:13,891 INFO L138 BoogieDeclarations]: Found implementation of procedure check [2018-10-26 23:36:13,892 INFO L130 BoogieDeclarations]: Found specification of procedure write_side1_failed_history [2018-10-26 23:36:13,892 INFO L138 BoogieDeclarations]: Found implementation of procedure write_side1_failed_history [2018-10-26 23:36:13,892 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-26 23:36:13,892 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-26 23:36:13,892 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 23:36:13,892 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 23:36:13,892 INFO L130 BoogieDeclarations]: Found specification of procedure read_side1_failed_history [2018-10-26 23:36:13,892 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side1_failed_history [2018-10-26 23:36:13,892 INFO L130 BoogieDeclarations]: Found specification of procedure read_active_side_history [2018-10-26 23:36:13,892 INFO L138 BoogieDeclarations]: Found implementation of procedure read_active_side_history [2018-10-26 23:36:13,893 INFO L130 BoogieDeclarations]: Found specification of procedure write_side2_failed_history [2018-10-26 23:36:13,893 INFO L138 BoogieDeclarations]: Found implementation of procedure write_side2_failed_history [2018-10-26 23:36:15,060 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 23:36:15,060 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:36:15 BoogieIcfgContainer [2018-10-26 23:36:15,060 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 23:36:15,061 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-26 23:36:15,061 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-26 23:36:15,064 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-26 23:36:15,065 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.10 11:36:13" (1/3) ... [2018-10-26 23:36:15,066 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f45b63e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:36:15, skipping insertion in model container [2018-10-26 23:36:15,066 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:13" (2/3) ... [2018-10-26 23:36:15,066 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f45b63e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:36:15, skipping insertion in model container [2018-10-26 23:36:15,066 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:36:15" (3/3) ... [2018-10-26 23:36:15,069 INFO L112 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c [2018-10-26 23:36:15,075 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-26 23:36:15,082 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-10-26 23:36:15,095 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-10-26 23:36:15,124 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-26 23:36:15,124 INFO L383 AbstractCegarLoop]: Hoare is true [2018-10-26 23:36:15,124 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-26 23:36:15,124 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-26 23:36:15,124 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-26 23:36:15,125 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-26 23:36:15,125 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-26 23:36:15,125 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-26 23:36:15,145 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states. [2018-10-26 23:36:15,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-26 23:36:15,152 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:15,153 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:15,155 INFO L424 AbstractCegarLoop]: === Iteration 1 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:15,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:15,160 INFO L82 PathProgramCache]: Analyzing trace with hash 586372410, now seen corresponding path program 1 times [2018-10-26 23:36:15,162 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:15,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:15,209 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:15,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:15,209 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:15,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:15,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:15,512 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:15,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:15,512 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:15,518 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:15,526 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:15,527 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:15,528 INFO L87 Difference]: Start difference. First operand 237 states. Second operand 4 states. [2018-10-26 23:36:15,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:15,628 INFO L93 Difference]: Finished difference Result 450 states and 694 transitions. [2018-10-26 23:36:15,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:15,629 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2018-10-26 23:36:15,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:15,640 INFO L225 Difference]: With dead ends: 450 [2018-10-26 23:36:15,640 INFO L226 Difference]: Without dead ends: 232 [2018-10-26 23:36:15,645 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:15,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-10-26 23:36:15,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 232. [2018-10-26 23:36:15,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-10-26 23:36:15,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 324 transitions. [2018-10-26 23:36:15,695 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 324 transitions. Word has length 66 [2018-10-26 23:36:15,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:15,696 INFO L481 AbstractCegarLoop]: Abstraction has 232 states and 324 transitions. [2018-10-26 23:36:15,696 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:15,696 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 324 transitions. [2018-10-26 23:36:15,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-10-26 23:36:15,699 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:15,699 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:15,699 INFO L424 AbstractCegarLoop]: === Iteration 2 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:15,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:15,700 INFO L82 PathProgramCache]: Analyzing trace with hash -417093478, now seen corresponding path program 1 times [2018-10-26 23:36:15,700 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:15,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:15,706 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:15,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:15,707 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:15,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:15,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:15,942 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:15,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:15,942 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:15,943 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:15,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:15,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:15,944 INFO L87 Difference]: Start difference. First operand 232 states and 324 transitions. Second operand 4 states. [2018-10-26 23:36:16,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:16,338 INFO L93 Difference]: Finished difference Result 446 states and 636 transitions. [2018-10-26 23:36:16,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:16,339 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2018-10-26 23:36:16,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:16,341 INFO L225 Difference]: With dead ends: 446 [2018-10-26 23:36:16,341 INFO L226 Difference]: Without dead ends: 236 [2018-10-26 23:36:16,343 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:16,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-10-26 23:36:16,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 236. [2018-10-26 23:36:16,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-10-26 23:36:16,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 327 transitions. [2018-10-26 23:36:16,366 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 327 transitions. Word has length 77 [2018-10-26 23:36:16,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:16,366 INFO L481 AbstractCegarLoop]: Abstraction has 236 states and 327 transitions. [2018-10-26 23:36:16,366 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:16,366 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 327 transitions. [2018-10-26 23:36:16,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-10-26 23:36:16,368 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:16,368 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:16,368 INFO L424 AbstractCegarLoop]: === Iteration 3 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:16,368 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:16,368 INFO L82 PathProgramCache]: Analyzing trace with hash -1243317975, now seen corresponding path program 1 times [2018-10-26 23:36:16,368 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:16,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:16,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:16,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:16,373 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:16,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:16,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:16,708 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:16,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:36:16,709 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:16,709 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:36:16,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:36:16,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:16,710 INFO L87 Difference]: Start difference. First operand 236 states and 327 transitions. Second operand 7 states. [2018-10-26 23:36:18,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:18,342 INFO L93 Difference]: Finished difference Result 538 states and 747 transitions. [2018-10-26 23:36:18,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:36:18,343 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 95 [2018-10-26 23:36:18,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:18,347 INFO L225 Difference]: With dead ends: 538 [2018-10-26 23:36:18,347 INFO L226 Difference]: Without dead ends: 324 [2018-10-26 23:36:18,348 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:36:18,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states. [2018-10-26 23:36:18,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 323. [2018-10-26 23:36:18,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 323 states. [2018-10-26 23:36:18,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 440 transitions. [2018-10-26 23:36:18,374 INFO L78 Accepts]: Start accepts. Automaton has 323 states and 440 transitions. Word has length 95 [2018-10-26 23:36:18,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:18,374 INFO L481 AbstractCegarLoop]: Abstraction has 323 states and 440 transitions. [2018-10-26 23:36:18,374 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:36:18,374 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 440 transitions. [2018-10-26 23:36:18,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-26 23:36:18,376 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:18,376 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:18,376 INFO L424 AbstractCegarLoop]: === Iteration 4 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:18,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:18,377 INFO L82 PathProgramCache]: Analyzing trace with hash -55255230, now seen corresponding path program 1 times [2018-10-26 23:36:18,377 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:18,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:18,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:18,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:18,378 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:18,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:18,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:18,477 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:18,478 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:36:18,478 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:18,478 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:36:18,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:36:18,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:18,479 INFO L87 Difference]: Start difference. First operand 323 states and 440 transitions. Second operand 7 states. [2018-10-26 23:36:19,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:19,528 INFO L93 Difference]: Finished difference Result 544 states and 755 transitions. [2018-10-26 23:36:19,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:36:19,528 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 96 [2018-10-26 23:36:19,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:19,530 INFO L225 Difference]: With dead ends: 544 [2018-10-26 23:36:19,530 INFO L226 Difference]: Without dead ends: 327 [2018-10-26 23:36:19,531 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:36:19,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-10-26 23:36:19,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 323. [2018-10-26 23:36:19,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 323 states. [2018-10-26 23:36:19,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 440 transitions. [2018-10-26 23:36:19,553 INFO L78 Accepts]: Start accepts. Automaton has 323 states and 440 transitions. Word has length 96 [2018-10-26 23:36:19,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:19,554 INFO L481 AbstractCegarLoop]: Abstraction has 323 states and 440 transitions. [2018-10-26 23:36:19,554 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:36:19,554 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 440 transitions. [2018-10-26 23:36:19,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-10-26 23:36:19,555 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:19,555 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:19,556 INFO L424 AbstractCegarLoop]: === Iteration 5 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:19,556 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:19,556 INFO L82 PathProgramCache]: Analyzing trace with hash 1553554439, now seen corresponding path program 1 times [2018-10-26 23:36:19,556 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:19,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:19,557 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:19,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:19,558 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:19,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:19,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:19,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:19,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:36:19,767 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:19,768 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:36:19,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:36:19,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:19,768 INFO L87 Difference]: Start difference. First operand 323 states and 440 transitions. Second operand 7 states. [2018-10-26 23:36:21,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:21,499 INFO L93 Difference]: Finished difference Result 545 states and 759 transitions. [2018-10-26 23:36:21,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:36:21,500 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 98 [2018-10-26 23:36:21,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:21,501 INFO L225 Difference]: With dead ends: 545 [2018-10-26 23:36:21,501 INFO L226 Difference]: Without dead ends: 328 [2018-10-26 23:36:21,502 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:36:21,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states. [2018-10-26 23:36:21,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 324. [2018-10-26 23:36:21,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2018-10-26 23:36:21,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 441 transitions. [2018-10-26 23:36:21,522 INFO L78 Accepts]: Start accepts. Automaton has 324 states and 441 transitions. Word has length 98 [2018-10-26 23:36:21,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:21,522 INFO L481 AbstractCegarLoop]: Abstraction has 324 states and 441 transitions. [2018-10-26 23:36:21,522 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:36:21,522 INFO L276 IsEmpty]: Start isEmpty. Operand 324 states and 441 transitions. [2018-10-26 23:36:21,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-10-26 23:36:21,524 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:21,524 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:21,524 INFO L424 AbstractCegarLoop]: === Iteration 6 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:21,524 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:21,524 INFO L82 PathProgramCache]: Analyzing trace with hash 1726971536, now seen corresponding path program 1 times [2018-10-26 23:36:21,525 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:21,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:21,526 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:21,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:21,526 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:21,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:21,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:21,680 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:21,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:36:21,680 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:21,681 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:36:21,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:36:21,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:21,688 INFO L87 Difference]: Start difference. First operand 324 states and 441 transitions. Second operand 3 states. [2018-10-26 23:36:21,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:21,822 INFO L93 Difference]: Finished difference Result 777 states and 1082 transitions. [2018-10-26 23:36:21,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:36:21,823 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2018-10-26 23:36:21,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:21,827 INFO L225 Difference]: With dead ends: 777 [2018-10-26 23:36:21,829 INFO L226 Difference]: Without dead ends: 559 [2018-10-26 23:36:21,830 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:21,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states. [2018-10-26 23:36:21,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 541. [2018-10-26 23:36:21,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 541 states. [2018-10-26 23:36:21,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541 states to 541 states and 749 transitions. [2018-10-26 23:36:21,873 INFO L78 Accepts]: Start accepts. Automaton has 541 states and 749 transitions. Word has length 98 [2018-10-26 23:36:21,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:21,875 INFO L481 AbstractCegarLoop]: Abstraction has 541 states and 749 transitions. [2018-10-26 23:36:21,875 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:36:21,875 INFO L276 IsEmpty]: Start isEmpty. Operand 541 states and 749 transitions. [2018-10-26 23:36:21,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-10-26 23:36:21,878 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:21,878 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:21,878 INFO L424 AbstractCegarLoop]: === Iteration 7 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:21,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:21,879 INFO L82 PathProgramCache]: Analyzing trace with hash -1766145080, now seen corresponding path program 1 times [2018-10-26 23:36:21,880 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:21,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:21,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:21,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:21,881 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:21,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:22,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:22,026 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:22,026 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:36:22,026 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:22,027 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:36:22,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:36:22,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:22,027 INFO L87 Difference]: Start difference. First operand 541 states and 749 transitions. Second operand 3 states. [2018-10-26 23:36:22,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:22,173 INFO L93 Difference]: Finished difference Result 1288 states and 1826 transitions. [2018-10-26 23:36:22,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:36:22,174 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2018-10-26 23:36:22,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:22,178 INFO L225 Difference]: With dead ends: 1288 [2018-10-26 23:36:22,179 INFO L226 Difference]: Without dead ends: 896 [2018-10-26 23:36:22,180 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:22,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 896 states. [2018-10-26 23:36:22,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 896 to 890. [2018-10-26 23:36:22,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 890 states. [2018-10-26 23:36:22,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 1251 transitions. [2018-10-26 23:36:22,240 INFO L78 Accepts]: Start accepts. Automaton has 890 states and 1251 transitions. Word has length 99 [2018-10-26 23:36:22,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:22,240 INFO L481 AbstractCegarLoop]: Abstraction has 890 states and 1251 transitions. [2018-10-26 23:36:22,240 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:36:22,240 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 1251 transitions. [2018-10-26 23:36:22,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-10-26 23:36:22,243 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:22,243 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:22,243 INFO L424 AbstractCegarLoop]: === Iteration 8 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:22,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:22,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1065080502, now seen corresponding path program 1 times [2018-10-26 23:36:22,243 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:22,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:22,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:22,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:22,245 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:22,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:22,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:22,366 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:22,366 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:36:22,366 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:22,366 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:36:22,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:36:22,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:22,367 INFO L87 Difference]: Start difference. First operand 890 states and 1251 transitions. Second operand 3 states. [2018-10-26 23:36:22,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:22,479 INFO L93 Difference]: Finished difference Result 1504 states and 2128 transitions. [2018-10-26 23:36:22,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:36:22,479 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2018-10-26 23:36:22,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:22,482 INFO L225 Difference]: With dead ends: 1504 [2018-10-26 23:36:22,482 INFO L226 Difference]: Without dead ends: 728 [2018-10-26 23:36:22,485 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:22,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 728 states. [2018-10-26 23:36:22,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 728 to 728. [2018-10-26 23:36:22,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 728 states. [2018-10-26 23:36:22,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 728 states to 728 states and 1014 transitions. [2018-10-26 23:36:22,525 INFO L78 Accepts]: Start accepts. Automaton has 728 states and 1014 transitions. Word has length 99 [2018-10-26 23:36:22,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:22,526 INFO L481 AbstractCegarLoop]: Abstraction has 728 states and 1014 transitions. [2018-10-26 23:36:22,526 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:36:22,526 INFO L276 IsEmpty]: Start isEmpty. Operand 728 states and 1014 transitions. [2018-10-26 23:36:22,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-10-26 23:36:22,527 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:22,527 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:22,527 INFO L424 AbstractCegarLoop]: === Iteration 9 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:22,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:22,528 INFO L82 PathProgramCache]: Analyzing trace with hash -420325951, now seen corresponding path program 1 times [2018-10-26 23:36:22,528 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:22,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:22,529 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:22,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:22,529 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:22,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:22,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:22,696 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:22,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:22,696 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:22,696 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:22,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:22,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:22,697 INFO L87 Difference]: Start difference. First operand 728 states and 1014 transitions. Second operand 4 states. [2018-10-26 23:36:23,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:23,038 INFO L93 Difference]: Finished difference Result 1319 states and 1864 transitions. [2018-10-26 23:36:23,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:23,043 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 99 [2018-10-26 23:36:23,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:23,047 INFO L225 Difference]: With dead ends: 1319 [2018-10-26 23:36:23,047 INFO L226 Difference]: Without dead ends: 743 [2018-10-26 23:36:23,049 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:23,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 743 states. [2018-10-26 23:36:23,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 743 to 743. [2018-10-26 23:36:23,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 743 states. [2018-10-26 23:36:23,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 743 states to 743 states and 1026 transitions. [2018-10-26 23:36:23,088 INFO L78 Accepts]: Start accepts. Automaton has 743 states and 1026 transitions. Word has length 99 [2018-10-26 23:36:23,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:23,088 INFO L481 AbstractCegarLoop]: Abstraction has 743 states and 1026 transitions. [2018-10-26 23:36:23,088 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:23,088 INFO L276 IsEmpty]: Start isEmpty. Operand 743 states and 1026 transitions. [2018-10-26 23:36:23,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-10-26 23:36:23,093 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:23,093 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:23,093 INFO L424 AbstractCegarLoop]: === Iteration 10 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:23,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:23,093 INFO L82 PathProgramCache]: Analyzing trace with hash 561581181, now seen corresponding path program 1 times [2018-10-26 23:36:23,093 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:23,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:23,096 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:23,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:23,096 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:23,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:23,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:23,396 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:23,396 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:23,396 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:23,397 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:23,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:23,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:23,397 INFO L87 Difference]: Start difference. First operand 743 states and 1026 transitions. Second operand 4 states. [2018-10-26 23:36:23,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:23,914 INFO L93 Difference]: Finished difference Result 1349 states and 1897 transitions. [2018-10-26 23:36:23,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:23,914 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2018-10-26 23:36:23,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:23,918 INFO L225 Difference]: With dead ends: 1349 [2018-10-26 23:36:23,918 INFO L226 Difference]: Without dead ends: 758 [2018-10-26 23:36:23,920 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:23,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 758 states. [2018-10-26 23:36:23,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 758 to 758. [2018-10-26 23:36:23,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 758 states. [2018-10-26 23:36:23,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 758 states to 758 states and 1038 transitions. [2018-10-26 23:36:23,961 INFO L78 Accepts]: Start accepts. Automaton has 758 states and 1038 transitions. Word has length 107 [2018-10-26 23:36:23,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:23,962 INFO L481 AbstractCegarLoop]: Abstraction has 758 states and 1038 transitions. [2018-10-26 23:36:23,962 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:23,962 INFO L276 IsEmpty]: Start isEmpty. Operand 758 states and 1038 transitions. [2018-10-26 23:36:23,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-10-26 23:36:23,966 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:23,966 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:23,966 INFO L424 AbstractCegarLoop]: === Iteration 11 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:23,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:23,967 INFO L82 PathProgramCache]: Analyzing trace with hash -1931624345, now seen corresponding path program 1 times [2018-10-26 23:36:23,967 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:23,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:23,970 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:23,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:23,970 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:23,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:24,164 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:24,165 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:24,165 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:24,165 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:24,165 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:24,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:24,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:24,166 INFO L87 Difference]: Start difference. First operand 758 states and 1038 transitions. Second operand 4 states. [2018-10-26 23:36:24,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:24,568 INFO L93 Difference]: Finished difference Result 1376 states and 1909 transitions. [2018-10-26 23:36:24,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:24,569 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 115 [2018-10-26 23:36:24,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:24,573 INFO L225 Difference]: With dead ends: 1376 [2018-10-26 23:36:24,574 INFO L226 Difference]: Without dead ends: 770 [2018-10-26 23:36:24,576 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:24,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 770 states. [2018-10-26 23:36:24,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 770 to 770. [2018-10-26 23:36:24,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 770 states. [2018-10-26 23:36:24,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 770 states to 770 states and 1047 transitions. [2018-10-26 23:36:24,613 INFO L78 Accepts]: Start accepts. Automaton has 770 states and 1047 transitions. Word has length 115 [2018-10-26 23:36:24,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:24,613 INFO L481 AbstractCegarLoop]: Abstraction has 770 states and 1047 transitions. [2018-10-26 23:36:24,613 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:24,613 INFO L276 IsEmpty]: Start isEmpty. Operand 770 states and 1047 transitions. [2018-10-26 23:36:24,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-10-26 23:36:24,616 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:24,616 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:24,617 INFO L424 AbstractCegarLoop]: === Iteration 12 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:24,617 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:24,617 INFO L82 PathProgramCache]: Analyzing trace with hash 801022489, now seen corresponding path program 1 times [2018-10-26 23:36:24,617 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:24,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:24,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:24,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:24,620 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:24,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:24,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:36:24,952 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:24,952 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:24,952 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:24,952 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:24,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:24,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:24,954 INFO L87 Difference]: Start difference. First operand 770 states and 1047 transitions. Second operand 4 states. [2018-10-26 23:36:25,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:25,471 INFO L93 Difference]: Finished difference Result 1403 states and 1939 transitions. [2018-10-26 23:36:25,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:25,472 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 115 [2018-10-26 23:36:25,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:25,476 INFO L225 Difference]: With dead ends: 1403 [2018-10-26 23:36:25,476 INFO L226 Difference]: Without dead ends: 785 [2018-10-26 23:36:25,479 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:25,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 785 states. [2018-10-26 23:36:25,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 785 to 785. [2018-10-26 23:36:25,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 785 states. [2018-10-26 23:36:25,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 785 states to 785 states and 1059 transitions. [2018-10-26 23:36:25,521 INFO L78 Accepts]: Start accepts. Automaton has 785 states and 1059 transitions. Word has length 115 [2018-10-26 23:36:25,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:25,523 INFO L481 AbstractCegarLoop]: Abstraction has 785 states and 1059 transitions. [2018-10-26 23:36:25,523 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:25,523 INFO L276 IsEmpty]: Start isEmpty. Operand 785 states and 1059 transitions. [2018-10-26 23:36:25,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-10-26 23:36:25,525 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:25,525 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:25,525 INFO L424 AbstractCegarLoop]: === Iteration 13 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:25,525 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:25,525 INFO L82 PathProgramCache]: Analyzing trace with hash 2053207083, now seen corresponding path program 1 times [2018-10-26 23:36:25,526 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:25,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:25,526 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:25,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:25,527 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:25,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:25,681 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 23:36:25,681 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:25,681 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:25,681 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:25,682 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:25,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:25,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:25,682 INFO L87 Difference]: Start difference. First operand 785 states and 1059 transitions. Second operand 4 states. [2018-10-26 23:36:26,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:26,087 INFO L93 Difference]: Finished difference Result 1436 states and 1960 transitions. [2018-10-26 23:36:26,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:26,087 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 123 [2018-10-26 23:36:26,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:26,091 INFO L225 Difference]: With dead ends: 1436 [2018-10-26 23:36:26,091 INFO L226 Difference]: Without dead ends: 803 [2018-10-26 23:36:26,093 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:26,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 803 states. [2018-10-26 23:36:26,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 803 to 803. [2018-10-26 23:36:26,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 803 states. [2018-10-26 23:36:26,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 803 states to 803 states and 1074 transitions. [2018-10-26 23:36:26,131 INFO L78 Accepts]: Start accepts. Automaton has 803 states and 1074 transitions. Word has length 123 [2018-10-26 23:36:26,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:26,131 INFO L481 AbstractCegarLoop]: Abstraction has 803 states and 1074 transitions. [2018-10-26 23:36:26,131 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:26,131 INFO L276 IsEmpty]: Start isEmpty. Operand 803 states and 1074 transitions. [2018-10-26 23:36:26,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-10-26 23:36:26,133 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:26,133 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:26,135 INFO L424 AbstractCegarLoop]: === Iteration 14 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:26,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:26,136 INFO L82 PathProgramCache]: Analyzing trace with hash 695243234, now seen corresponding path program 1 times [2018-10-26 23:36:26,136 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:26,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:26,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:26,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:26,138 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:26,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:26,659 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 23:36:26,659 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:26,659 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-10-26 23:36:26,659 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:26,659 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 23:36:26,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 23:36:26,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-10-26 23:36:26,660 INFO L87 Difference]: Start difference. First operand 803 states and 1074 transitions. Second operand 10 states. [2018-10-26 23:36:29,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:29,674 INFO L93 Difference]: Finished difference Result 2101 states and 2792 transitions. [2018-10-26 23:36:29,675 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-10-26 23:36:29,675 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 128 [2018-10-26 23:36:29,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:29,681 INFO L225 Difference]: With dead ends: 2101 [2018-10-26 23:36:29,682 INFO L226 Difference]: Without dead ends: 1435 [2018-10-26 23:36:29,684 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=92, Invalid=460, Unknown=0, NotChecked=0, Total=552 [2018-10-26 23:36:29,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1435 states. [2018-10-26 23:36:29,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1435 to 1338. [2018-10-26 23:36:29,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1338 states. [2018-10-26 23:36:29,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1338 states to 1338 states and 1755 transitions. [2018-10-26 23:36:29,751 INFO L78 Accepts]: Start accepts. Automaton has 1338 states and 1755 transitions. Word has length 128 [2018-10-26 23:36:29,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:29,751 INFO L481 AbstractCegarLoop]: Abstraction has 1338 states and 1755 transitions. [2018-10-26 23:36:29,751 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 23:36:29,751 INFO L276 IsEmpty]: Start isEmpty. Operand 1338 states and 1755 transitions. [2018-10-26 23:36:29,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-10-26 23:36:29,753 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:29,755 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:29,755 INFO L424 AbstractCegarLoop]: === Iteration 15 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:29,755 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:29,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1530516526, now seen corresponding path program 1 times [2018-10-26 23:36:29,756 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:29,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:29,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:29,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:29,757 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:29,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:29,963 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 23:36:29,964 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:29,964 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:29,964 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:29,965 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:29,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:29,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:29,965 INFO L87 Difference]: Start difference. First operand 1338 states and 1755 transitions. Second operand 4 states. [2018-10-26 23:36:30,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:30,081 INFO L93 Difference]: Finished difference Result 2430 states and 3211 transitions. [2018-10-26 23:36:30,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:30,094 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 130 [2018-10-26 23:36:30,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:30,100 INFO L225 Difference]: With dead ends: 2430 [2018-10-26 23:36:30,100 INFO L226 Difference]: Without dead ends: 1350 [2018-10-26 23:36:30,104 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:30,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1350 states. [2018-10-26 23:36:30,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1350 to 1344. [2018-10-26 23:36:30,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1344 states. [2018-10-26 23:36:30,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1344 states to 1344 states and 1742 transitions. [2018-10-26 23:36:30,163 INFO L78 Accepts]: Start accepts. Automaton has 1344 states and 1742 transitions. Word has length 130 [2018-10-26 23:36:30,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:30,163 INFO L481 AbstractCegarLoop]: Abstraction has 1344 states and 1742 transitions. [2018-10-26 23:36:30,163 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:30,163 INFO L276 IsEmpty]: Start isEmpty. Operand 1344 states and 1742 transitions. [2018-10-26 23:36:30,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-10-26 23:36:30,165 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:30,167 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:30,167 INFO L424 AbstractCegarLoop]: === Iteration 16 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:30,168 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:30,168 INFO L82 PathProgramCache]: Analyzing trace with hash 1068429319, now seen corresponding path program 1 times [2018-10-26 23:36:30,168 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:30,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:30,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:30,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:30,171 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:30,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:30,395 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 23:36:30,395 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:30,395 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:36:30,395 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:30,395 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:36:30,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:36:30,396 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:30,396 INFO L87 Difference]: Start difference. First operand 1344 states and 1742 transitions. Second operand 7 states. [2018-10-26 23:36:30,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:30,615 INFO L93 Difference]: Finished difference Result 1427 states and 1868 transitions. [2018-10-26 23:36:30,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-26 23:36:30,616 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 131 [2018-10-26 23:36:30,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:30,622 INFO L225 Difference]: With dead ends: 1427 [2018-10-26 23:36:30,622 INFO L226 Difference]: Without dead ends: 1425 [2018-10-26 23:36:30,623 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:36:30,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1425 states. [2018-10-26 23:36:30,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1425 to 1368. [2018-10-26 23:36:30,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1368 states. [2018-10-26 23:36:30,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1368 states to 1368 states and 1772 transitions. [2018-10-26 23:36:30,692 INFO L78 Accepts]: Start accepts. Automaton has 1368 states and 1772 transitions. Word has length 131 [2018-10-26 23:36:30,692 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:30,692 INFO L481 AbstractCegarLoop]: Abstraction has 1368 states and 1772 transitions. [2018-10-26 23:36:30,692 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:36:30,692 INFO L276 IsEmpty]: Start isEmpty. Operand 1368 states and 1772 transitions. [2018-10-26 23:36:30,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-10-26 23:36:30,696 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:30,696 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:30,697 INFO L424 AbstractCegarLoop]: === Iteration 17 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:30,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:30,697 INFO L82 PathProgramCache]: Analyzing trace with hash 1083399022, now seen corresponding path program 1 times [2018-10-26 23:36:30,697 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:30,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:30,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:30,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:30,698 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:30,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:31,700 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 23:36:31,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:31,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:36:31,700 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:31,702 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:36:31,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:36:31,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:36:31,702 INFO L87 Difference]: Start difference. First operand 1368 states and 1772 transitions. Second operand 9 states. [2018-10-26 23:36:33,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:33,002 INFO L93 Difference]: Finished difference Result 2834 states and 3642 transitions. [2018-10-26 23:36:33,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-10-26 23:36:33,002 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 132 [2018-10-26 23:36:33,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:33,009 INFO L225 Difference]: With dead ends: 2834 [2018-10-26 23:36:33,009 INFO L226 Difference]: Without dead ends: 1775 [2018-10-26 23:36:33,012 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=67, Invalid=275, Unknown=0, NotChecked=0, Total=342 [2018-10-26 23:36:33,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1775 states. [2018-10-26 23:36:33,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1775 to 1488. [2018-10-26 23:36:33,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1488 states. [2018-10-26 23:36:33,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 1488 states and 1899 transitions. [2018-10-26 23:36:33,084 INFO L78 Accepts]: Start accepts. Automaton has 1488 states and 1899 transitions. Word has length 132 [2018-10-26 23:36:33,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:33,084 INFO L481 AbstractCegarLoop]: Abstraction has 1488 states and 1899 transitions. [2018-10-26 23:36:33,085 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:36:33,085 INFO L276 IsEmpty]: Start isEmpty. Operand 1488 states and 1899 transitions. [2018-10-26 23:36:33,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-10-26 23:36:33,088 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:33,088 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:33,088 INFO L424 AbstractCegarLoop]: === Iteration 18 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:33,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:33,089 INFO L82 PathProgramCache]: Analyzing trace with hash 1829270886, now seen corresponding path program 1 times [2018-10-26 23:36:33,089 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:33,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:33,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:33,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:33,090 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:33,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:33,359 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 23:36:33,359 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:33,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-10-26 23:36:33,359 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:33,360 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 23:36:33,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 23:36:33,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-10-26 23:36:33,360 INFO L87 Difference]: Start difference. First operand 1488 states and 1899 transitions. Second operand 10 states. [2018-10-26 23:36:36,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:36,449 INFO L93 Difference]: Finished difference Result 3897 states and 4951 transitions. [2018-10-26 23:36:36,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-10-26 23:36:36,449 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 136 [2018-10-26 23:36:36,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:36,459 INFO L225 Difference]: With dead ends: 3897 [2018-10-26 23:36:36,459 INFO L226 Difference]: Without dead ends: 2760 [2018-10-26 23:36:36,462 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=92, Invalid=460, Unknown=0, NotChecked=0, Total=552 [2018-10-26 23:36:36,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states. [2018-10-26 23:36:36,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 1913. [2018-10-26 23:36:36,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1913 states. [2018-10-26 23:36:36,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1913 states to 1913 states and 2429 transitions. [2018-10-26 23:36:36,566 INFO L78 Accepts]: Start accepts. Automaton has 1913 states and 2429 transitions. Word has length 136 [2018-10-26 23:36:36,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:36,566 INFO L481 AbstractCegarLoop]: Abstraction has 1913 states and 2429 transitions. [2018-10-26 23:36:36,566 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 23:36:36,566 INFO L276 IsEmpty]: Start isEmpty. Operand 1913 states and 2429 transitions. [2018-10-26 23:36:36,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-10-26 23:36:36,568 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:36,568 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:36,569 INFO L424 AbstractCegarLoop]: === Iteration 19 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:36,569 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:36,569 INFO L82 PathProgramCache]: Analyzing trace with hash -536691835, now seen corresponding path program 1 times [2018-10-26 23:36:36,569 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:36,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:36,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:36,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:36,573 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:36,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:36,854 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:36,854 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:36,854 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:36:36,854 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:36,855 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:36:36,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:36:36,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:36,855 INFO L87 Difference]: Start difference. First operand 1913 states and 2429 transitions. Second operand 5 states. [2018-10-26 23:36:37,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:37,534 INFO L93 Difference]: Finished difference Result 6604 states and 8496 transitions. [2018-10-26 23:36:37,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:36:37,538 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 137 [2018-10-26 23:36:37,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:37,556 INFO L225 Difference]: With dead ends: 6604 [2018-10-26 23:36:37,556 INFO L226 Difference]: Without dead ends: 4987 [2018-10-26 23:36:37,562 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:37,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4987 states. [2018-10-26 23:36:37,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4987 to 4529. [2018-10-26 23:36:37,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4529 states. [2018-10-26 23:36:37,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4529 states to 4529 states and 5769 transitions. [2018-10-26 23:36:37,830 INFO L78 Accepts]: Start accepts. Automaton has 4529 states and 5769 transitions. Word has length 137 [2018-10-26 23:36:37,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:37,831 INFO L481 AbstractCegarLoop]: Abstraction has 4529 states and 5769 transitions. [2018-10-26 23:36:37,832 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:36:37,832 INFO L276 IsEmpty]: Start isEmpty. Operand 4529 states and 5769 transitions. [2018-10-26 23:36:37,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-10-26 23:36:37,834 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:37,834 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:37,834 INFO L424 AbstractCegarLoop]: === Iteration 20 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:37,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:37,835 INFO L82 PathProgramCache]: Analyzing trace with hash 850568995, now seen corresponding path program 1 times [2018-10-26 23:36:37,835 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:37,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:37,836 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:37,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:37,836 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:37,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:38,009 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:38,009 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:38,009 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:38,009 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:38,010 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:38,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:38,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:38,010 INFO L87 Difference]: Start difference. First operand 4529 states and 5769 transitions. Second operand 4 states. [2018-10-26 23:36:38,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:38,340 INFO L93 Difference]: Finished difference Result 8504 states and 10869 transitions. [2018-10-26 23:36:38,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:38,346 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 141 [2018-10-26 23:36:38,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:38,362 INFO L225 Difference]: With dead ends: 8504 [2018-10-26 23:36:38,362 INFO L226 Difference]: Without dead ends: 4570 [2018-10-26 23:36:38,371 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:38,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4570 states. [2018-10-26 23:36:38,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4570 to 4145. [2018-10-26 23:36:38,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4145 states. [2018-10-26 23:36:38,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4145 states to 4145 states and 5282 transitions. [2018-10-26 23:36:38,589 INFO L78 Accepts]: Start accepts. Automaton has 4145 states and 5282 transitions. Word has length 141 [2018-10-26 23:36:38,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:38,589 INFO L481 AbstractCegarLoop]: Abstraction has 4145 states and 5282 transitions. [2018-10-26 23:36:38,589 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:38,590 INFO L276 IsEmpty]: Start isEmpty. Operand 4145 states and 5282 transitions. [2018-10-26 23:36:38,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-10-26 23:36:38,592 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:38,592 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:38,592 INFO L424 AbstractCegarLoop]: === Iteration 21 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:38,593 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:38,593 INFO L82 PathProgramCache]: Analyzing trace with hash 904153943, now seen corresponding path program 1 times [2018-10-26 23:36:38,593 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:38,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:38,594 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:38,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:38,594 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:38,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:38,846 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 23:36:38,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:38,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:36:38,846 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:38,847 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:36:38,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:36:38,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:36:38,847 INFO L87 Difference]: Start difference. First operand 4145 states and 5282 transitions. Second operand 9 states. [2018-10-26 23:36:39,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:39,870 INFO L93 Difference]: Finished difference Result 8196 states and 10700 transitions. [2018-10-26 23:36:39,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 23:36:39,871 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 138 [2018-10-26 23:36:39,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:39,887 INFO L225 Difference]: With dead ends: 8196 [2018-10-26 23:36:39,887 INFO L226 Difference]: Without dead ends: 4404 [2018-10-26 23:36:39,896 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=187, Unknown=0, NotChecked=0, Total=240 [2018-10-26 23:36:39,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4404 states. [2018-10-26 23:36:40,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4404 to 3707. [2018-10-26 23:36:40,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3707 states. [2018-10-26 23:36:40,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3707 states to 3707 states and 4768 transitions. [2018-10-26 23:36:40,108 INFO L78 Accepts]: Start accepts. Automaton has 3707 states and 4768 transitions. Word has length 138 [2018-10-26 23:36:40,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:40,110 INFO L481 AbstractCegarLoop]: Abstraction has 3707 states and 4768 transitions. [2018-10-26 23:36:40,110 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:36:40,110 INFO L276 IsEmpty]: Start isEmpty. Operand 3707 states and 4768 transitions. [2018-10-26 23:36:40,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2018-10-26 23:36:40,113 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:40,114 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:40,115 INFO L424 AbstractCegarLoop]: === Iteration 22 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:40,115 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:40,115 INFO L82 PathProgramCache]: Analyzing trace with hash -392368965, now seen corresponding path program 1 times [2018-10-26 23:36:40,115 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:40,117 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:40,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:40,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:40,119 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:40,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:41,032 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 23:36:41,032 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:41,032 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:36:41,032 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:41,033 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:36:41,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:36:41,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:36:41,033 INFO L87 Difference]: Start difference. First operand 3707 states and 4768 transitions. Second operand 9 states. [2018-10-26 23:36:42,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:42,550 INFO L93 Difference]: Finished difference Result 7524 states and 9831 transitions. [2018-10-26 23:36:42,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-10-26 23:36:42,551 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 139 [2018-10-26 23:36:42,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:42,565 INFO L225 Difference]: With dead ends: 7524 [2018-10-26 23:36:42,565 INFO L226 Difference]: Without dead ends: 4186 [2018-10-26 23:36:42,573 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:36:42,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4186 states. [2018-10-26 23:36:42,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4186 to 3405. [2018-10-26 23:36:42,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3405 states. [2018-10-26 23:36:42,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3405 states to 3405 states and 4322 transitions. [2018-10-26 23:36:42,838 INFO L78 Accepts]: Start accepts. Automaton has 3405 states and 4322 transitions. Word has length 139 [2018-10-26 23:36:42,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:42,838 INFO L481 AbstractCegarLoop]: Abstraction has 3405 states and 4322 transitions. [2018-10-26 23:36:42,838 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:36:42,838 INFO L276 IsEmpty]: Start isEmpty. Operand 3405 states and 4322 transitions. [2018-10-26 23:36:42,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-10-26 23:36:42,840 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:42,840 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:42,840 INFO L424 AbstractCegarLoop]: === Iteration 23 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:42,840 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:42,840 INFO L82 PathProgramCache]: Analyzing trace with hash 2144735438, now seen corresponding path program 1 times [2018-10-26 23:36:42,840 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:42,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:42,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:42,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:42,846 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:42,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:43,121 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:43,121 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:43,121 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:36:43,121 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:43,123 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:36:43,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:36:43,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:43,123 INFO L87 Difference]: Start difference. First operand 3405 states and 4322 transitions. Second operand 5 states. [2018-10-26 23:36:43,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:43,773 INFO L93 Difference]: Finished difference Result 10476 states and 13429 transitions. [2018-10-26 23:36:43,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:36:43,774 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 140 [2018-10-26 23:36:43,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:43,798 INFO L225 Difference]: With dead ends: 10476 [2018-10-26 23:36:43,798 INFO L226 Difference]: Without dead ends: 7585 [2018-10-26 23:36:43,806 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:43,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7585 states. [2018-10-26 23:36:44,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7585 to 5223. [2018-10-26 23:36:44,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5223 states. [2018-10-26 23:36:44,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5223 states to 5223 states and 6621 transitions. [2018-10-26 23:36:44,081 INFO L78 Accepts]: Start accepts. Automaton has 5223 states and 6621 transitions. Word has length 140 [2018-10-26 23:36:44,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:44,082 INFO L481 AbstractCegarLoop]: Abstraction has 5223 states and 6621 transitions. [2018-10-26 23:36:44,082 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:36:44,082 INFO L276 IsEmpty]: Start isEmpty. Operand 5223 states and 6621 transitions. [2018-10-26 23:36:44,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-10-26 23:36:44,084 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:44,084 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:44,085 INFO L424 AbstractCegarLoop]: === Iteration 24 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:44,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:44,085 INFO L82 PathProgramCache]: Analyzing trace with hash 517496669, now seen corresponding path program 1 times [2018-10-26 23:36:44,085 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:44,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:44,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:44,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:44,089 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:44,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:44,279 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:44,279 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:44,279 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 23:36:44,279 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:44,279 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 23:36:44,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 23:36:44,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:44,280 INFO L87 Difference]: Start difference. First operand 5223 states and 6621 transitions. Second operand 5 states. [2018-10-26 23:36:44,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:44,952 INFO L93 Difference]: Finished difference Result 12119 states and 15434 transitions. [2018-10-26 23:36:44,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:36:44,953 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 140 [2018-10-26 23:36:44,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:44,973 INFO L225 Difference]: With dead ends: 12119 [2018-10-26 23:36:44,973 INFO L226 Difference]: Without dead ends: 7547 [2018-10-26 23:36:44,984 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:36:44,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7547 states. [2018-10-26 23:36:45,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7547 to 6998. [2018-10-26 23:36:45,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6998 states. [2018-10-26 23:36:45,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6998 states to 6998 states and 8824 transitions. [2018-10-26 23:36:45,457 INFO L78 Accepts]: Start accepts. Automaton has 6998 states and 8824 transitions. Word has length 140 [2018-10-26 23:36:45,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:45,458 INFO L481 AbstractCegarLoop]: Abstraction has 6998 states and 8824 transitions. [2018-10-26 23:36:45,458 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 23:36:45,458 INFO L276 IsEmpty]: Start isEmpty. Operand 6998 states and 8824 transitions. [2018-10-26 23:36:45,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-10-26 23:36:45,460 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:45,460 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:45,460 INFO L424 AbstractCegarLoop]: === Iteration 25 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:45,461 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:45,461 INFO L82 PathProgramCache]: Analyzing trace with hash 543382104, now seen corresponding path program 1 times [2018-10-26 23:36:45,461 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:45,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:45,464 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:45,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:45,464 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:45,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:45,553 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:45,553 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:45,553 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:36:45,553 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:45,555 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:36:45,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:36:45,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:45,555 INFO L87 Difference]: Start difference. First operand 6998 states and 8824 transitions. Second operand 3 states. [2018-10-26 23:36:46,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:46,275 INFO L93 Difference]: Finished difference Result 13479 states and 17077 transitions. [2018-10-26 23:36:46,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:36:46,276 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 141 [2018-10-26 23:36:46,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:46,298 INFO L225 Difference]: With dead ends: 13479 [2018-10-26 23:36:46,298 INFO L226 Difference]: Without dead ends: 7067 [2018-10-26 23:36:46,313 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:36:46,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7067 states. [2018-10-26 23:36:46,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7067 to 7004. [2018-10-26 23:36:46,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7004 states. [2018-10-26 23:36:46,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7004 states to 7004 states and 8830 transitions. [2018-10-26 23:36:46,747 INFO L78 Accepts]: Start accepts. Automaton has 7004 states and 8830 transitions. Word has length 141 [2018-10-26 23:36:46,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:46,748 INFO L481 AbstractCegarLoop]: Abstraction has 7004 states and 8830 transitions. [2018-10-26 23:36:46,748 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:36:46,748 INFO L276 IsEmpty]: Start isEmpty. Operand 7004 states and 8830 transitions. [2018-10-26 23:36:46,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-10-26 23:36:46,752 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:46,752 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:46,752 INFO L424 AbstractCegarLoop]: === Iteration 26 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:46,753 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:46,753 INFO L82 PathProgramCache]: Analyzing trace with hash -28088871, now seen corresponding path program 1 times [2018-10-26 23:36:46,753 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:46,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:46,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:46,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:46,754 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:46,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:46,982 WARN L179 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 10 DAG size of output: 7 [2018-10-26 23:36:47,107 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:47,107 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:47,107 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-10-26 23:36:47,107 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:47,108 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-10-26 23:36:47,108 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-10-26 23:36:47,108 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-10-26 23:36:47,108 INFO L87 Difference]: Start difference. First operand 7004 states and 8830 transitions. Second operand 11 states. [2018-10-26 23:36:49,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:49,175 INFO L93 Difference]: Finished difference Result 13412 states and 16977 transitions. [2018-10-26 23:36:49,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-10-26 23:36:49,180 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 142 [2018-10-26 23:36:49,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:49,198 INFO L225 Difference]: With dead ends: 13412 [2018-10-26 23:36:49,198 INFO L226 Difference]: Without dead ends: 6564 [2018-10-26 23:36:49,209 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=140, Invalid=460, Unknown=0, NotChecked=0, Total=600 [2018-10-26 23:36:49,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6564 states. [2018-10-26 23:36:49,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6564 to 6512. [2018-10-26 23:36:49,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6512 states. [2018-10-26 23:36:49,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6512 states to 6512 states and 8239 transitions. [2018-10-26 23:36:49,732 INFO L78 Accepts]: Start accepts. Automaton has 6512 states and 8239 transitions. Word has length 142 [2018-10-26 23:36:49,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:49,733 INFO L481 AbstractCegarLoop]: Abstraction has 6512 states and 8239 transitions. [2018-10-26 23:36:49,733 INFO L482 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-10-26 23:36:49,733 INFO L276 IsEmpty]: Start isEmpty. Operand 6512 states and 8239 transitions. [2018-10-26 23:36:49,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-10-26 23:36:49,734 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:49,734 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:49,734 INFO L424 AbstractCegarLoop]: === Iteration 27 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:49,734 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:49,735 INFO L82 PathProgramCache]: Analyzing trace with hash 918203045, now seen corresponding path program 1 times [2018-10-26 23:36:49,735 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:49,735 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:49,736 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:49,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:49,736 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:49,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:50,010 WARN L179 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 10 DAG size of output: 7 [2018-10-26 23:36:50,115 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:50,116 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:50,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-10-26 23:36:50,116 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:50,116 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 23:36:50,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 23:36:50,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-10-26 23:36:50,117 INFO L87 Difference]: Start difference. First operand 6512 states and 8239 transitions. Second operand 10 states. [2018-10-26 23:36:53,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:53,741 INFO L93 Difference]: Finished difference Result 12873 states and 16334 transitions. [2018-10-26 23:36:53,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-10-26 23:36:53,742 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 143 [2018-10-26 23:36:53,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:53,757 INFO L225 Difference]: With dead ends: 12873 [2018-10-26 23:36:53,757 INFO L226 Difference]: Without dead ends: 6630 [2018-10-26 23:36:53,767 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=113, Invalid=349, Unknown=0, NotChecked=0, Total=462 [2018-10-26 23:36:53,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6630 states. [2018-10-26 23:36:54,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6630 to 6306. [2018-10-26 23:36:54,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6306 states. [2018-10-26 23:36:54,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6306 states to 6306 states and 7965 transitions. [2018-10-26 23:36:54,306 INFO L78 Accepts]: Start accepts. Automaton has 6306 states and 7965 transitions. Word has length 143 [2018-10-26 23:36:54,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:54,307 INFO L481 AbstractCegarLoop]: Abstraction has 6306 states and 7965 transitions. [2018-10-26 23:36:54,307 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 23:36:54,307 INFO L276 IsEmpty]: Start isEmpty. Operand 6306 states and 7965 transitions. [2018-10-26 23:36:54,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-10-26 23:36:54,308 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:54,308 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:54,308 INFO L424 AbstractCegarLoop]: === Iteration 28 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:54,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:54,309 INFO L82 PathProgramCache]: Analyzing trace with hash 269992605, now seen corresponding path program 1 times [2018-10-26 23:36:54,309 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:54,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:54,313 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:54,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:54,313 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:54,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:54,469 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:36:54,470 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:36:54,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:36:54,470 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 23:36:54,470 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:36:54,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:36:54,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:36:54,471 INFO L87 Difference]: Start difference. First operand 6306 states and 7965 transitions. Second operand 4 states. [2018-10-26 23:36:54,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:36:54,902 INFO L93 Difference]: Finished difference Result 12304 states and 15604 transitions. [2018-10-26 23:36:54,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:36:54,903 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 144 [2018-10-26 23:36:54,903 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:36:54,916 INFO L225 Difference]: With dead ends: 12304 [2018-10-26 23:36:54,917 INFO L226 Difference]: Without dead ends: 6267 [2018-10-26 23:36:54,926 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:36:54,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6267 states. [2018-10-26 23:36:55,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6267 to 6173. [2018-10-26 23:36:55,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6173 states. [2018-10-26 23:36:55,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6173 states to 6173 states and 7808 transitions. [2018-10-26 23:36:55,255 INFO L78 Accepts]: Start accepts. Automaton has 6173 states and 7808 transitions. Word has length 144 [2018-10-26 23:36:55,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:36:55,255 INFO L481 AbstractCegarLoop]: Abstraction has 6173 states and 7808 transitions. [2018-10-26 23:36:55,255 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:36:55,255 INFO L276 IsEmpty]: Start isEmpty. Operand 6173 states and 7808 transitions. [2018-10-26 23:36:55,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 236 [2018-10-26 23:36:55,258 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:36:55,258 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:36:55,258 INFO L424 AbstractCegarLoop]: === Iteration 29 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:36:55,259 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:36:55,259 INFO L82 PathProgramCache]: Analyzing trace with hash 430731799, now seen corresponding path program 1 times [2018-10-26 23:36:55,259 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 23:36:55,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:55,260 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:36:55,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 23:36:55,260 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 23:36:55,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:36:56,105 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 12 proven. 23 refuted. 0 times theorem prover too weak. 82 trivial. 0 not checked. [2018-10-26 23:36:56,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:36:56,105 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 23:36:56,106 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 236 with the following transitions: [2018-10-26 23:36:56,108 INFO L202 CegarAbsIntRunner]: [0], [4], [7], [15], [16], [42], [45], [82], [86], [89], [93], [96], [100], [101], [105], [109], [113], [117], [121], [125], [129], [133], [137], [141], [145], [149], [150], [160], [161], [162], [166], [171], [173], [178], [180], [185], [187], [247], [248], [250], [254], [260], [265], [267], [274], [277], [286], [288], [355], [358], [361], [363], [366], [368], [371], [389], [392], [423], [426], [467], [469], [470], [471], [475], [479], [482], [486], [487], [488], [489], [490], [491], [492], [496], [499], [507], [508], [511], [513], [516], [518], [519], [521], [524], [526], [531], [542], [554], [557], [561], [565], [568], [576], [577], [580], [581], [585], [588], [592], [593], [594], [595], [596], [599], [600], [603], [604], [607], [608], [609], [610], [611], [612], [613], [614], [615], [616], [617], [618], [619], [620], [621], [622], [631], [632], [633], [634], [635], [636], [639], [640], [647], [648], [663], [664], [667], [668], [669], [670], [671], [672], [673] [2018-10-26 23:36:56,155 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 23:36:56,156 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 23:36:56,218 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.AssertionError: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Sort ~port_t~0 not declared at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.extractInterpolants(BaseRefinementStrategy.java:391) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.handleInfeasibleCase(BaseRefinementStrategy.java:296) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:206) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:429) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:435) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:312) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:154) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:123) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Sort ~port_t~0 not declared at de.uni_freiburg.informatik.ultimate.logic.NoopScript.sort(NoopScript.java:289) at de.uni_freiburg.informatik.ultimate.logic.NoopScript.sort(NoopScript.java:278) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SmtSortUtils.getNamedSort(SmtSortUtils.java:118) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.TypeSortTranslator.constructSort(TypeSortTranslator.java:253) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.util.FakeBoogieVar.(FakeBoogieVar.java:60) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.util.AbsIntUtil.createTemporaryIBoogieVar(AbsIntUtil.java:347) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.relational.octagon.OctStatementProcessor.processAssignmentStatement(OctStatementProcessor.java:105) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.relational.octagon.OctStatementProcessor.processStatement(OctStatementProcessor.java:65) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.relational.octagon.OctPostOperator.applyCall(OctPostOperator.java:251) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.relational.octagon.OctPostOperator.apply(OctPostOperator.java:214) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.relational.octagon.OctPostOperator.apply(OctPostOperator.java:1) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.compound.CompoundDomainPostOperator.applyInternally(CompoundDomainPostOperator.java:311) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.compound.CompoundDomainPostOperator.apply(CompoundDomainPostOperator.java:276) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.compound.CompoundDomainPostOperator.apply(CompoundDomainPostOperator.java:1) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormansAbstractPostOperator.handleCallTransition(PoormansAbstractPostOperator.java:185) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormansAbstractPostOperator.apply(PoormansAbstractPostOperator.java:165) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormansAbstractPostOperator.apply(PoormansAbstractPostOperator.java:1) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.absint.DisjunctiveAbstractState.lambda$18(DisjunctiveAbstractState.java:339) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.absint.DisjunctiveAbstractState.crossProductCollection(DisjunctiveAbstractState.java:507) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.absint.DisjunctiveAbstractState.apply(DisjunctiveAbstractState.java:339) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.algorithm.FixpointEngine.calculateAbstractPost(FixpointEngine.java:243) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.algorithm.FixpointEngine.calculateFixpoint(FixpointEngine.java:134) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.algorithm.FixpointEngine.run(FixpointEngine.java:105) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.tool.AbstractInterpreter.runWithoutTimeoutAndResults(AbstractInterpreter.java:149) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.CegarAbsIntRunner.generateFixpoints(CegarAbsIntRunner.java:217) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseTaipanRefinementStrategy.constructInterpolantGenerator(BaseTaipanRefinementStrategy.java:385) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseTaipanRefinementStrategy.getInterpolantGenerator(BaseTaipanRefinementStrategy.java:226) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.extractInterpolants(BaseRefinementStrategy.java:380) ... 20 more [2018-10-26 23:36:56,222 INFO L168 Benchmark]: Toolchain (without parser) took 42947.83 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 843.6 MB). Free memory was 953.1 MB in the beginning and 1.6 GB in the end (delta: -636.2 MB). Peak memory consumption was 207.4 MB. Max. memory is 11.5 GB. [2018-10-26 23:36:56,222 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 980.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:36:56,223 INFO L168 Benchmark]: CACSL2BoogieTranslator took 348.94 ms. Allocated memory is still 1.0 GB. Free memory was 950.4 MB in the beginning and 931.6 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-10-26 23:36:56,223 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.30 ms. Allocated memory is still 1.0 GB. Free memory is still 931.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:36:56,223 INFO L168 Benchmark]: Boogie Preprocessor took 160.15 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 161.0 MB). Free memory was 931.6 MB in the beginning and 1.2 GB in the end (delta: -224.7 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. [2018-10-26 23:36:56,224 INFO L168 Benchmark]: RCFGBuilder took 1234.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 64.1 MB). Peak memory consumption was 64.1 MB. Max. memory is 11.5 GB. [2018-10-26 23:36:56,224 INFO L168 Benchmark]: TraceAbstraction took 41160.10 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 682.6 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -497.0 MB). Peak memory consumption was 185.6 MB. Max. memory is 11.5 GB. [2018-10-26 23:36:56,242 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 980.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 348.94 ms. Allocated memory is still 1.0 GB. Free memory was 950.4 MB in the beginning and 931.6 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.30 ms. Allocated memory is still 1.0 GB. Free memory is still 931.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 160.15 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 161.0 MB). Free memory was 931.6 MB in the beginning and 1.2 GB in the end (delta: -224.7 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1234.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 64.1 MB). Peak memory consumption was 64.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 41160.10 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 682.6 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -497.0 MB). Peak memory consumption was 185.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: AssertionError: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Sort ~port_t~0 not declared de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: AssertionError: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Sort ~port_t~0 not declared: de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.extractInterpolants(BaseRefinementStrategy.java:391) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-1dbac8b [2018-10-26 23:36:58,118 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 23:36:58,120 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 23:36:58,129 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 23:36:58,129 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 23:36:58,130 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 23:36:58,131 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 23:36:58,132 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 23:36:58,134 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 23:36:58,135 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 23:36:58,135 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 23:36:58,135 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 23:36:58,136 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 23:36:58,137 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 23:36:58,138 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 23:36:58,139 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 23:36:58,139 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 23:36:58,141 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 23:36:58,143 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 23:36:58,144 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 23:36:58,145 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 23:36:58,146 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 23:36:58,148 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 23:36:58,148 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 23:36:58,148 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 23:36:58,149 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 23:36:58,150 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 23:36:58,151 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 23:36:58,152 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 23:36:58,152 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 23:36:58,153 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 23:36:58,153 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 23:36:58,154 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 23:36:58,154 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 23:36:58,155 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 23:36:58,156 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 23:36:58,156 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Bitvector.epf [2018-10-26 23:36:58,167 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 23:36:58,167 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 23:36:58,168 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 23:36:58,168 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-26 23:36:58,168 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-26 23:36:58,168 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-26 23:36:58,168 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-26 23:36:58,168 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-26 23:36:58,169 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 23:36:58,169 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-26 23:36:58,169 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-26 23:36:58,169 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 23:36:58,170 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 23:36:58,170 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 23:36:58,171 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 23:36:58,171 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-10-26 23:36:58,171 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-10-26 23:36:58,171 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-26 23:36:58,171 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 23:36:58,171 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 23:36:58,171 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 23:36:58,172 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-26 23:36:58,172 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 23:36:58,172 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-26 23:36:58,172 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:36:58,172 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 23:36:58,172 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 23:36:58,172 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 23:36:58,173 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-10-26 23:36:58,173 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 23:36:58,173 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-10-26 23:36:58,173 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-10-26 23:36:58,173 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 [2018-10-26 23:36:58,206 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 23:36:58,216 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 23:36:58,219 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 23:36:58,220 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 23:36:58,221 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 23:36:58,221 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c [2018-10-26 23:36:58,264 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/c7cb71d48/4a5adb0616f949368c2d1438557ec50f/FLAGddae353ff [2018-10-26 23:36:58,696 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 23:36:58,696 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c [2018-10-26 23:36:58,705 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/c7cb71d48/4a5adb0616f949368c2d1438557ec50f/FLAGddae353ff [2018-10-26 23:36:58,716 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/data/c7cb71d48/4a5adb0616f949368c2d1438557ec50f [2018-10-26 23:36:58,719 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 23:36:58,722 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 23:36:58,722 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 23:36:58,723 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 23:36:58,728 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 23:36:58,729 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:36:58" (1/1) ... [2018-10-26 23:36:58,731 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6d80c46c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:58, skipping insertion in model container [2018-10-26 23:36:58,732 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 11:36:58" (1/1) ... [2018-10-26 23:36:58,740 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 23:36:58,778 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 23:36:58,991 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:36:59,001 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 23:36:59,095 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 23:36:59,119 INFO L193 MainTranslator]: Completed translation [2018-10-26 23:36:59,119 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59 WrapperNode [2018-10-26 23:36:59,120 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 23:36:59,120 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 23:36:59,120 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 23:36:59,120 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 23:36:59,128 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,140 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,149 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 23:36:59,150 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 23:36:59,150 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 23:36:59,150 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 23:36:59,161 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,162 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,166 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,175 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,193 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,208 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,211 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... [2018-10-26 23:36:59,304 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 23:36:59,304 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 23:36:59,304 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 23:36:59,304 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 23:36:59,305 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 23:36:59,368 INFO L130 BoogieDeclarations]: Found specification of procedure read_manual_selection_history [2018-10-26 23:36:59,368 INFO L138 BoogieDeclarations]: Found implementation of procedure read_manual_selection_history [2018-10-26 23:36:59,369 INFO L130 BoogieDeclarations]: Found specification of procedure Side1_activestandby_task_each_pals_period [2018-10-26 23:36:59,369 INFO L138 BoogieDeclarations]: Found implementation of procedure Side1_activestandby_task_each_pals_period [2018-10-26 23:36:59,369 INFO L130 BoogieDeclarations]: Found specification of procedure write_active_side_history [2018-10-26 23:36:59,369 INFO L138 BoogieDeclarations]: Found implementation of procedure write_active_side_history [2018-10-26 23:36:59,369 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-26 23:36:59,369 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-26 23:36:59,369 INFO L130 BoogieDeclarations]: Found specification of procedure Console_task_each_pals_period [2018-10-26 23:36:59,369 INFO L138 BoogieDeclarations]: Found implementation of procedure Console_task_each_pals_period [2018-10-26 23:36:59,370 INFO L130 BoogieDeclarations]: Found specification of procedure read_side2_failed_history [2018-10-26 23:36:59,372 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side2_failed_history [2018-10-26 23:36:59,372 INFO L130 BoogieDeclarations]: Found specification of procedure assert [2018-10-26 23:36:59,372 INFO L138 BoogieDeclarations]: Found implementation of procedure assert [2018-10-26 23:36:59,373 INFO L130 BoogieDeclarations]: Found specification of procedure Pendulum_prism_task_each_pals_period [2018-10-26 23:36:59,373 INFO L138 BoogieDeclarations]: Found implementation of procedure Pendulum_prism_task_each_pals_period [2018-10-26 23:36:59,373 INFO L130 BoogieDeclarations]: Found specification of procedure write_manual_selection_history [2018-10-26 23:36:59,373 INFO L138 BoogieDeclarations]: Found implementation of procedure write_manual_selection_history [2018-10-26 23:36:59,373 INFO L130 BoogieDeclarations]: Found specification of procedure init [2018-10-26 23:36:59,373 INFO L138 BoogieDeclarations]: Found implementation of procedure init [2018-10-26 23:36:59,373 INFO L130 BoogieDeclarations]: Found specification of procedure flip_the_side [2018-10-26 23:36:59,373 INFO L138 BoogieDeclarations]: Found implementation of procedure flip_the_side [2018-10-26 23:36:59,374 INFO L130 BoogieDeclarations]: Found specification of procedure Side2_activestandby_task_each_pals_period [2018-10-26 23:36:59,374 INFO L138 BoogieDeclarations]: Found implementation of procedure Side2_activestandby_task_each_pals_period [2018-10-26 23:36:59,374 INFO L130 BoogieDeclarations]: Found specification of procedure check [2018-10-26 23:36:59,374 INFO L138 BoogieDeclarations]: Found implementation of procedure check [2018-10-26 23:36:59,374 INFO L130 BoogieDeclarations]: Found specification of procedure write_side1_failed_history [2018-10-26 23:36:59,374 INFO L138 BoogieDeclarations]: Found implementation of procedure write_side1_failed_history [2018-10-26 23:36:59,374 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-26 23:36:59,374 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-26 23:36:59,375 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 23:36:59,375 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 23:36:59,375 INFO L130 BoogieDeclarations]: Found specification of procedure read_side1_failed_history [2018-10-26 23:36:59,375 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side1_failed_history [2018-10-26 23:36:59,375 INFO L130 BoogieDeclarations]: Found specification of procedure read_active_side_history [2018-10-26 23:36:59,375 INFO L138 BoogieDeclarations]: Found implementation of procedure read_active_side_history [2018-10-26 23:36:59,375 INFO L130 BoogieDeclarations]: Found specification of procedure write_side2_failed_history [2018-10-26 23:36:59,375 INFO L138 BoogieDeclarations]: Found implementation of procedure write_side2_failed_history [2018-10-26 23:37:00,634 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 23:37:00,635 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:37:00 BoogieIcfgContainer [2018-10-26 23:37:00,635 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 23:37:00,636 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-26 23:37:00,636 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-26 23:37:00,639 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-26 23:37:00,640 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.10 11:36:58" (1/3) ... [2018-10-26 23:37:00,640 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@169964d1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:37:00, skipping insertion in model container [2018-10-26 23:37:00,640 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 11:36:59" (2/3) ... [2018-10-26 23:37:00,641 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@169964d1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 11:37:00, skipping insertion in model container [2018-10-26 23:37:00,641 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:37:00" (3/3) ... [2018-10-26 23:37:00,643 INFO L112 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby_false-unreach-call.4_2.ufo.UNBOUNDED.pals.c [2018-10-26 23:37:00,652 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-26 23:37:00,659 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-10-26 23:37:00,673 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-10-26 23:37:00,700 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-26 23:37:00,700 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-26 23:37:00,701 INFO L383 AbstractCegarLoop]: Hoare is true [2018-10-26 23:37:00,701 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-26 23:37:00,701 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-26 23:37:00,701 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-26 23:37:00,701 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-26 23:37:00,701 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-26 23:37:00,701 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-26 23:37:00,722 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states. [2018-10-26 23:37:00,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-26 23:37:00,730 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:00,730 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:00,733 INFO L424 AbstractCegarLoop]: === Iteration 1 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:00,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:00,738 INFO L82 PathProgramCache]: Analyzing trace with hash 586372410, now seen corresponding path program 1 times [2018-10-26 23:37:00,744 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:00,744 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:00,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:00,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:00,954 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:00,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:00,989 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (2)] Exception during sending of exit command (exit): Broken pipe [2018-10-26 23:37:00,994 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:00,995 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-26 23:37:00,999 INFO L460 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-10-26 23:37:01,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-10-26 23:37:01,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-10-26 23:37:01,015 INFO L87 Difference]: Start difference. First operand 237 states. Second operand 2 states. [2018-10-26 23:37:01,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:01,094 INFO L93 Difference]: Finished difference Result 447 states and 691 transitions. [2018-10-26 23:37:01,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-10-26 23:37:01,095 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 66 [2018-10-26 23:37:01,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:01,113 INFO L225 Difference]: With dead ends: 447 [2018-10-26 23:37:01,113 INFO L226 Difference]: Without dead ends: 232 [2018-10-26 23:37:01,118 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-10-26 23:37:01,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-10-26 23:37:01,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 232. [2018-10-26 23:37:01,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-10-26 23:37:01,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 336 transitions. [2018-10-26 23:37:01,181 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 336 transitions. Word has length 66 [2018-10-26 23:37:01,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:01,183 INFO L481 AbstractCegarLoop]: Abstraction has 232 states and 336 transitions. [2018-10-26 23:37:01,183 INFO L482 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-10-26 23:37:01,183 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 336 transitions. [2018-10-26 23:37:01,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-26 23:37:01,185 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:01,186 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:01,186 INFO L424 AbstractCegarLoop]: === Iteration 2 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:01,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:01,186 INFO L82 PathProgramCache]: Analyzing trace with hash -1897166660, now seen corresponding path program 1 times [2018-10-26 23:37:01,187 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:01,187 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:01,211 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:01,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:01,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:01,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:01,493 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:01,495 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:01,495 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:01,496 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:01,497 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:01,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:01,497 INFO L87 Difference]: Start difference. First operand 232 states and 336 transitions. Second operand 4 states. [2018-10-26 23:37:01,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:01,623 INFO L93 Difference]: Finished difference Result 445 states and 641 transitions. [2018-10-26 23:37:01,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:37:01,626 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2018-10-26 23:37:01,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:01,628 INFO L225 Difference]: With dead ends: 445 [2018-10-26 23:37:01,629 INFO L226 Difference]: Without dead ends: 232 [2018-10-26 23:37:01,630 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:01,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states. [2018-10-26 23:37:01,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 232. [2018-10-26 23:37:01,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-10-26 23:37:01,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 324 transitions. [2018-10-26 23:37:01,657 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 324 transitions. Word has length 66 [2018-10-26 23:37:01,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:01,657 INFO L481 AbstractCegarLoop]: Abstraction has 232 states and 324 transitions. [2018-10-26 23:37:01,658 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:01,658 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 324 transitions. [2018-10-26 23:37:01,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-10-26 23:37:01,659 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:01,659 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:01,660 INFO L424 AbstractCegarLoop]: === Iteration 3 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:01,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:01,660 INFO L82 PathProgramCache]: Analyzing trace with hash -417093478, now seen corresponding path program 1 times [2018-10-26 23:37:01,661 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:01,661 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:01,687 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:01,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:01,830 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:01,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:01,993 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:01,998 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:01,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:01,999 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:01,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:01,999 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:01,999 INFO L87 Difference]: Start difference. First operand 232 states and 324 transitions. Second operand 4 states. [2018-10-26 23:37:02,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:02,322 INFO L93 Difference]: Finished difference Result 448 states and 639 transitions. [2018-10-26 23:37:02,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:02,322 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2018-10-26 23:37:02,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:02,325 INFO L225 Difference]: With dead ends: 448 [2018-10-26 23:37:02,325 INFO L226 Difference]: Without dead ends: 238 [2018-10-26 23:37:02,326 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 74 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:02,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 238 states. [2018-10-26 23:37:02,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 238 to 236. [2018-10-26 23:37:02,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-10-26 23:37:02,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 327 transitions. [2018-10-26 23:37:02,349 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 327 transitions. Word has length 77 [2018-10-26 23:37:02,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:02,351 INFO L481 AbstractCegarLoop]: Abstraction has 236 states and 327 transitions. [2018-10-26 23:37:02,351 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:02,351 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 327 transitions. [2018-10-26 23:37:02,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-10-26 23:37:02,353 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:02,354 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:02,354 INFO L424 AbstractCegarLoop]: === Iteration 4 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:02,354 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:02,354 INFO L82 PathProgramCache]: Analyzing trace with hash -1243317975, now seen corresponding path program 1 times [2018-10-26 23:37:02,355 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:02,355 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:02,375 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:02,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:02,511 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:02,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:02,546 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:02,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:02,550 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:37:02,551 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:37:02,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:37:02,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:02,551 INFO L87 Difference]: Start difference. First operand 236 states and 327 transitions. Second operand 3 states. [2018-10-26 23:37:02,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:02,695 INFO L93 Difference]: Finished difference Result 638 states and 903 transitions. [2018-10-26 23:37:02,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:37:02,698 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 95 [2018-10-26 23:37:02,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:02,701 INFO L225 Difference]: With dead ends: 638 [2018-10-26 23:37:02,701 INFO L226 Difference]: Without dead ends: 424 [2018-10-26 23:37:02,707 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:02,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states. [2018-10-26 23:37:02,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 406. [2018-10-26 23:37:02,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2018-10-26 23:37:02,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 575 transitions. [2018-10-26 23:37:02,763 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 575 transitions. Word has length 95 [2018-10-26 23:37:02,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:02,763 INFO L481 AbstractCegarLoop]: Abstraction has 406 states and 575 transitions. [2018-10-26 23:37:02,763 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:37:02,764 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 575 transitions. [2018-10-26 23:37:02,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-26 23:37:02,766 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:02,766 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:02,766 INFO L424 AbstractCegarLoop]: === Iteration 5 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:02,766 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:02,767 INFO L82 PathProgramCache]: Analyzing trace with hash 644160591, now seen corresponding path program 1 times [2018-10-26 23:37:02,767 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:02,767 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:02,784 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:02,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:02,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:03,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:03,002 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (6)] Exception during sending of exit command (exit): Broken pipe [2018-10-26 23:37:03,004 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:03,006 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:37:03,006 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:37:03,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:37:03,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:03,007 INFO L87 Difference]: Start difference. First operand 406 states and 575 transitions. Second operand 3 states. [2018-10-26 23:37:03,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:03,171 INFO L93 Difference]: Finished difference Result 1119 states and 1612 transitions. [2018-10-26 23:37:03,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:37:03,171 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 96 [2018-10-26 23:37:03,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:03,177 INFO L225 Difference]: With dead ends: 1119 [2018-10-26 23:37:03,177 INFO L226 Difference]: Without dead ends: 735 [2018-10-26 23:37:03,181 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:03,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735 states. [2018-10-26 23:37:03,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735 to 729. [2018-10-26 23:37:03,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 729 states. [2018-10-26 23:37:03,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1047 transitions. [2018-10-26 23:37:03,231 INFO L78 Accepts]: Start accepts. Automaton has 729 states and 1047 transitions. Word has length 96 [2018-10-26 23:37:03,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:03,232 INFO L481 AbstractCegarLoop]: Abstraction has 729 states and 1047 transitions. [2018-10-26 23:37:03,232 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:37:03,232 INFO L276 IsEmpty]: Start isEmpty. Operand 729 states and 1047 transitions. [2018-10-26 23:37:03,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-26 23:37:03,234 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:03,234 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:03,235 INFO L424 AbstractCegarLoop]: === Iteration 6 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:03,235 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:03,235 INFO L82 PathProgramCache]: Analyzing trace with hash 1345225169, now seen corresponding path program 1 times [2018-10-26 23:37:03,235 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:03,235 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:03,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:03,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:03,372 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:03,397 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:03,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:03,398 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:37:03,399 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:37:03,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:37:03,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:03,399 INFO L87 Difference]: Start difference. First operand 729 states and 1047 transitions. Second operand 3 states. [2018-10-26 23:37:03,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:03,437 INFO L93 Difference]: Finished difference Result 1327 states and 1904 transitions. [2018-10-26 23:37:03,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:37:03,446 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 96 [2018-10-26 23:37:03,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:03,456 INFO L225 Difference]: With dead ends: 1327 [2018-10-26 23:37:03,457 INFO L226 Difference]: Without dead ends: 586 [2018-10-26 23:37:03,460 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:03,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 586 states. [2018-10-26 23:37:03,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 586 to 586. [2018-10-26 23:37:03,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 586 states. [2018-10-26 23:37:03,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 586 states to 586 states and 832 transitions. [2018-10-26 23:37:03,506 INFO L78 Accepts]: Start accepts. Automaton has 586 states and 832 transitions. Word has length 96 [2018-10-26 23:37:03,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:03,510 INFO L481 AbstractCegarLoop]: Abstraction has 586 states and 832 transitions. [2018-10-26 23:37:03,510 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:37:03,510 INFO L276 IsEmpty]: Start isEmpty. Operand 586 states and 832 transitions. [2018-10-26 23:37:03,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-26 23:37:03,511 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:03,512 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:03,512 INFO L424 AbstractCegarLoop]: === Iteration 7 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:03,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:03,512 INFO L82 PathProgramCache]: Analyzing trace with hash -188786792, now seen corresponding path program 1 times [2018-10-26 23:37:03,512 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:03,513 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:03,537 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:03,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:03,663 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:03,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:03,814 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:03,818 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:03,818 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:03,819 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:03,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:03,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:03,819 INFO L87 Difference]: Start difference. First operand 586 states and 832 transitions. Second operand 4 states. [2018-10-26 23:37:04,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:04,057 INFO L93 Difference]: Finished difference Result 1171 states and 1673 transitions. [2018-10-26 23:37:04,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:04,062 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 96 [2018-10-26 23:37:04,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:04,065 INFO L225 Difference]: With dead ends: 1171 [2018-10-26 23:37:04,065 INFO L226 Difference]: Without dead ends: 607 [2018-10-26 23:37:04,068 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:04,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-10-26 23:37:04,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 601. [2018-10-26 23:37:04,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 601 states. [2018-10-26 23:37:04,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 601 states to 601 states and 844 transitions. [2018-10-26 23:37:04,094 INFO L78 Accepts]: Start accepts. Automaton has 601 states and 844 transitions. Word has length 96 [2018-10-26 23:37:04,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:04,094 INFO L481 AbstractCegarLoop]: Abstraction has 601 states and 844 transitions. [2018-10-26 23:37:04,095 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:04,095 INFO L276 IsEmpty]: Start isEmpty. Operand 601 states and 844 transitions. [2018-10-26 23:37:04,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-10-26 23:37:04,096 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:04,096 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:04,097 INFO L424 AbstractCegarLoop]: === Iteration 8 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:04,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:04,097 INFO L82 PathProgramCache]: Analyzing trace with hash -600946860, now seen corresponding path program 1 times [2018-10-26 23:37:04,099 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:04,099 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:04,125 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:04,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:04,249 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:04,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:04,396 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:04,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:04,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:04,399 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:04,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:04,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:04,400 INFO L87 Difference]: Start difference. First operand 601 states and 844 transitions. Second operand 4 states. [2018-10-26 23:37:04,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:04,921 INFO L93 Difference]: Finished difference Result 1201 states and 1712 transitions. [2018-10-26 23:37:04,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:04,921 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 104 [2018-10-26 23:37:04,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:04,924 INFO L225 Difference]: With dead ends: 1201 [2018-10-26 23:37:04,924 INFO L226 Difference]: Without dead ends: 622 [2018-10-26 23:37:04,927 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 101 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:04,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 622 states. [2018-10-26 23:37:04,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 622 to 616. [2018-10-26 23:37:04,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. [2018-10-26 23:37:04,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 856 transitions. [2018-10-26 23:37:04,950 INFO L78 Accepts]: Start accepts. Automaton has 616 states and 856 transitions. Word has length 104 [2018-10-26 23:37:04,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:04,950 INFO L481 AbstractCegarLoop]: Abstraction has 616 states and 856 transitions. [2018-10-26 23:37:04,950 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:04,951 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 856 transitions. [2018-10-26 23:37:04,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-10-26 23:37:04,952 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:04,952 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:04,952 INFO L424 AbstractCegarLoop]: === Iteration 9 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:04,953 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:04,953 INFO L82 PathProgramCache]: Analyzing trace with hash -919456706, now seen corresponding path program 1 times [2018-10-26 23:37:04,953 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:04,953 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:04,978 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:05,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:05,107 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:05,263 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:05,263 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:05,265 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:05,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:05,266 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:05,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:05,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:05,266 INFO L87 Difference]: Start difference. First operand 616 states and 856 transitions. Second operand 4 states. [2018-10-26 23:37:05,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:05,680 INFO L93 Difference]: Finished difference Result 1228 states and 1718 transitions. [2018-10-26 23:37:05,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:05,681 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 112 [2018-10-26 23:37:05,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:05,684 INFO L225 Difference]: With dead ends: 1228 [2018-10-26 23:37:05,684 INFO L226 Difference]: Without dead ends: 634 [2018-10-26 23:37:05,687 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:05,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 634 states. [2018-10-26 23:37:05,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 634 to 628. [2018-10-26 23:37:05,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 628 states. [2018-10-26 23:37:05,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 628 states and 865 transitions. [2018-10-26 23:37:05,709 INFO L78 Accepts]: Start accepts. Automaton has 628 states and 865 transitions. Word has length 112 [2018-10-26 23:37:05,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:05,710 INFO L481 AbstractCegarLoop]: Abstraction has 628 states and 865 transitions. [2018-10-26 23:37:05,710 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:05,710 INFO L276 IsEmpty]: Start isEmpty. Operand 628 states and 865 transitions. [2018-10-26 23:37:05,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-10-26 23:37:05,712 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:05,712 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:05,712 INFO L424 AbstractCegarLoop]: === Iteration 10 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:05,712 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:05,712 INFO L82 PathProgramCache]: Analyzing trace with hash 1813190128, now seen corresponding path program 1 times [2018-10-26 23:37:05,712 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:05,713 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:05,735 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:05,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:05,863 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:05,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:05,978 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:05,980 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:05,980 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:05,981 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:05,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:05,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:05,981 INFO L87 Difference]: Start difference. First operand 628 states and 865 transitions. Second operand 4 states. [2018-10-26 23:37:06,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:06,449 INFO L93 Difference]: Finished difference Result 1255 states and 1754 transitions. [2018-10-26 23:37:06,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:06,450 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 112 [2018-10-26 23:37:06,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:06,453 INFO L225 Difference]: With dead ends: 1255 [2018-10-26 23:37:06,454 INFO L226 Difference]: Without dead ends: 649 [2018-10-26 23:37:06,455 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:06,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2018-10-26 23:37:06,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 643. [2018-10-26 23:37:06,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 643 states. [2018-10-26 23:37:06,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 877 transitions. [2018-10-26 23:37:06,480 INFO L78 Accepts]: Start accepts. Automaton has 643 states and 877 transitions. Word has length 112 [2018-10-26 23:37:06,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:06,481 INFO L481 AbstractCegarLoop]: Abstraction has 643 states and 877 transitions. [2018-10-26 23:37:06,481 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:06,481 INFO L276 IsEmpty]: Start isEmpty. Operand 643 states and 877 transitions. [2018-10-26 23:37:06,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-10-26 23:37:06,484 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:06,484 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:06,484 INFO L424 AbstractCegarLoop]: === Iteration 11 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:06,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:06,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1712070914, now seen corresponding path program 1 times [2018-10-26 23:37:06,485 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:06,485 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:06,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:06,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:06,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:07,603 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:07,603 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:07,607 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:07,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:37:07,608 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:37:07,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:37:07,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:37:07,608 INFO L87 Difference]: Start difference. First operand 643 states and 877 transitions. Second operand 9 states. [2018-10-26 23:37:09,502 WARN L179 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 23:37:10,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:10,992 INFO L93 Difference]: Finished difference Result 1671 states and 2290 transitions. [2018-10-26 23:37:10,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-10-26 23:37:10,992 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 120 [2018-10-26 23:37:10,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:10,997 INFO L225 Difference]: With dead ends: 1671 [2018-10-26 23:37:10,997 INFO L226 Difference]: Without dead ends: 1050 [2018-10-26 23:37:10,999 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-10-26 23:37:11,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1050 states. [2018-10-26 23:37:11,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1050 to 922. [2018-10-26 23:37:11,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 922 states. [2018-10-26 23:37:11,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 922 states to 922 states and 1247 transitions. [2018-10-26 23:37:11,035 INFO L78 Accepts]: Start accepts. Automaton has 922 states and 1247 transitions. Word has length 120 [2018-10-26 23:37:11,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:11,036 INFO L481 AbstractCegarLoop]: Abstraction has 922 states and 1247 transitions. [2018-10-26 23:37:11,036 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:37:11,036 INFO L276 IsEmpty]: Start isEmpty. Operand 922 states and 1247 transitions. [2018-10-26 23:37:11,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-10-26 23:37:11,039 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:11,039 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:11,039 INFO L424 AbstractCegarLoop]: === Iteration 12 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:11,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:11,039 INFO L82 PathProgramCache]: Analyzing trace with hash -395095189, now seen corresponding path program 1 times [2018-10-26 23:37:11,040 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:11,040 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:11,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:11,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:11,262 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:11,359 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:11,360 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:11,362 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:11,362 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:37:11,363 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:37:11,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:37:11,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:37:11,364 INFO L87 Difference]: Start difference. First operand 922 states and 1247 transitions. Second operand 7 states. [2018-10-26 23:37:13,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:13,360 INFO L93 Difference]: Finished difference Result 1985 states and 2693 transitions. [2018-10-26 23:37:13,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 23:37:13,361 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 125 [2018-10-26 23:37:13,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:13,364 INFO L225 Difference]: With dead ends: 1985 [2018-10-26 23:37:13,365 INFO L226 Difference]: Without dead ends: 1085 [2018-10-26 23:37:13,368 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 120 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-10-26 23:37:13,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1085 states. [2018-10-26 23:37:13,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1085 to 1076. [2018-10-26 23:37:13,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1076 states. [2018-10-26 23:37:13,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1076 states to 1076 states and 1444 transitions. [2018-10-26 23:37:13,414 INFO L78 Accepts]: Start accepts. Automaton has 1076 states and 1444 transitions. Word has length 125 [2018-10-26 23:37:13,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:13,415 INFO L481 AbstractCegarLoop]: Abstraction has 1076 states and 1444 transitions. [2018-10-26 23:37:13,415 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:37:13,415 INFO L276 IsEmpty]: Start isEmpty. Operand 1076 states and 1444 transitions. [2018-10-26 23:37:13,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-10-26 23:37:13,417 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:13,417 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:13,417 INFO L424 AbstractCegarLoop]: === Iteration 13 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:13,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:13,419 INFO L82 PathProgramCache]: Analyzing trace with hash 901404208, now seen corresponding path program 1 times [2018-10-26 23:37:13,419 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:13,419 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:13,444 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:13,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:13,616 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:13,687 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:13,687 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:13,689 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:13,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:37:13,690 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:37:13,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:37:13,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:37:13,693 INFO L87 Difference]: Start difference. First operand 1076 states and 1444 transitions. Second operand 7 states. [2018-10-26 23:37:15,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:15,665 INFO L93 Difference]: Finished difference Result 2015 states and 2723 transitions. [2018-10-26 23:37:15,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 23:37:15,667 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 126 [2018-10-26 23:37:15,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:15,671 INFO L225 Difference]: With dead ends: 2015 [2018-10-26 23:37:15,672 INFO L226 Difference]: Without dead ends: 1106 [2018-10-26 23:37:15,674 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 121 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-10-26 23:37:15,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1106 states. [2018-10-26 23:37:15,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1106 to 1079. [2018-10-26 23:37:15,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1079 states. [2018-10-26 23:37:15,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1079 states to 1079 states and 1441 transitions. [2018-10-26 23:37:15,725 INFO L78 Accepts]: Start accepts. Automaton has 1079 states and 1441 transitions. Word has length 126 [2018-10-26 23:37:15,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:15,725 INFO L481 AbstractCegarLoop]: Abstraction has 1079 states and 1441 transitions. [2018-10-26 23:37:15,725 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:37:15,726 INFO L276 IsEmpty]: Start isEmpty. Operand 1079 states and 1441 transitions. [2018-10-26 23:37:15,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-10-26 23:37:15,728 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:15,728 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:15,728 INFO L424 AbstractCegarLoop]: === Iteration 14 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:15,728 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:15,728 INFO L82 PathProgramCache]: Analyzing trace with hash 898237369, now seen corresponding path program 1 times [2018-10-26 23:37:15,729 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:15,729 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:15,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:15,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:15,970 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:16,329 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:16,330 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:16,331 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:16,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:37:16,332 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:37:16,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:37:16,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:37:16,332 INFO L87 Difference]: Start difference. First operand 1079 states and 1441 transitions. Second operand 9 states. [2018-10-26 23:37:18,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:18,569 INFO L93 Difference]: Finished difference Result 2705 states and 3658 transitions. [2018-10-26 23:37:18,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 23:37:18,570 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 129 [2018-10-26 23:37:18,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:18,577 INFO L225 Difference]: With dead ends: 2705 [2018-10-26 23:37:18,577 INFO L226 Difference]: Without dead ends: 1805 [2018-10-26 23:37:18,580 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 122 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:37:18,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1805 states. [2018-10-26 23:37:18,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1805 to 1779. [2018-10-26 23:37:18,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1779 states. [2018-10-26 23:37:18,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1779 states to 1779 states and 2393 transitions. [2018-10-26 23:37:18,659 INFO L78 Accepts]: Start accepts. Automaton has 1779 states and 2393 transitions. Word has length 129 [2018-10-26 23:37:18,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:18,660 INFO L481 AbstractCegarLoop]: Abstraction has 1779 states and 2393 transitions. [2018-10-26 23:37:18,660 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:37:18,660 INFO L276 IsEmpty]: Start isEmpty. Operand 1779 states and 2393 transitions. [2018-10-26 23:37:18,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-10-26 23:37:18,662 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:18,663 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:18,663 INFO L424 AbstractCegarLoop]: === Iteration 15 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:18,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:18,663 INFO L82 PathProgramCache]: Analyzing trace with hash -960615355, now seen corresponding path program 1 times [2018-10-26 23:37:18,663 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:18,664 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:18,690 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:18,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:18,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:18,936 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 23:37:18,936 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (16)] Exception during sending of exit command (exit): Broken pipe [2018-10-26 23:37:18,942 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:18,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:18,942 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:18,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:18,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:18,943 INFO L87 Difference]: Start difference. First operand 1779 states and 2393 transitions. Second operand 4 states. [2018-10-26 23:37:19,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:19,137 INFO L93 Difference]: Finished difference Result 3348 states and 4540 transitions. [2018-10-26 23:37:19,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:19,142 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 131 [2018-10-26 23:37:19,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:19,149 INFO L225 Difference]: With dead ends: 3348 [2018-10-26 23:37:19,149 INFO L226 Difference]: Without dead ends: 1827 [2018-10-26 23:37:19,153 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:19,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1827 states. [2018-10-26 23:37:19,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1827 to 1803. [2018-10-26 23:37:19,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1803 states. [2018-10-26 23:37:19,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2411 transitions. [2018-10-26 23:37:19,227 INFO L78 Accepts]: Start accepts. Automaton has 1803 states and 2411 transitions. Word has length 131 [2018-10-26 23:37:19,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:19,227 INFO L481 AbstractCegarLoop]: Abstraction has 1803 states and 2411 transitions. [2018-10-26 23:37:19,227 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:19,227 INFO L276 IsEmpty]: Start isEmpty. Operand 1803 states and 2411 transitions. [2018-10-26 23:37:19,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-10-26 23:37:19,229 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:19,230 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:19,230 INFO L424 AbstractCegarLoop]: === Iteration 16 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:19,231 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:19,231 INFO L82 PathProgramCache]: Analyzing trace with hash -247962167, now seen corresponding path program 1 times [2018-10-26 23:37:19,231 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:19,231 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:19,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:19,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:19,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:19,481 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 23:37:19,481 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:19,483 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:19,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:37:19,484 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:37:19,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:37:19,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:37:19,484 INFO L87 Difference]: Start difference. First operand 1803 states and 2411 transitions. Second operand 9 states. [2018-10-26 23:37:22,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:22,129 INFO L93 Difference]: Finished difference Result 3374 states and 4522 transitions. [2018-10-26 23:37:22,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 23:37:22,129 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 137 [2018-10-26 23:37:22,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:22,136 INFO L225 Difference]: With dead ends: 3374 [2018-10-26 23:37:22,136 INFO L226 Difference]: Without dead ends: 1853 [2018-10-26 23:37:22,139 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 130 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:37:22,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1853 states. [2018-10-26 23:37:22,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1853 to 1803. [2018-10-26 23:37:22,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1803 states. [2018-10-26 23:37:22,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2408 transitions. [2018-10-26 23:37:22,220 INFO L78 Accepts]: Start accepts. Automaton has 1803 states and 2408 transitions. Word has length 137 [2018-10-26 23:37:22,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:22,221 INFO L481 AbstractCegarLoop]: Abstraction has 1803 states and 2408 transitions. [2018-10-26 23:37:22,221 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:37:22,221 INFO L276 IsEmpty]: Start isEmpty. Operand 1803 states and 2408 transitions. [2018-10-26 23:37:22,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-10-26 23:37:22,223 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:22,224 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:22,224 INFO L424 AbstractCegarLoop]: === Iteration 17 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:22,224 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:22,224 INFO L82 PathProgramCache]: Analyzing trace with hash -190420082, now seen corresponding path program 1 times [2018-10-26 23:37:22,224 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:22,225 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:22,250 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:22,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:22,379 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:22,671 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 23:37:22,671 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:22,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:22,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-26 23:37:22,673 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:37:22,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:37:22,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:37:22,674 INFO L87 Difference]: Start difference. First operand 1803 states and 2408 transitions. Second operand 8 states. [2018-10-26 23:37:23,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:23,559 INFO L93 Difference]: Finished difference Result 3109 states and 4213 transitions. [2018-10-26 23:37:23,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:37:23,560 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 138 [2018-10-26 23:37:23,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:23,567 INFO L225 Difference]: With dead ends: 3109 [2018-10-26 23:37:23,568 INFO L226 Difference]: Without dead ends: 1988 [2018-10-26 23:37:23,571 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:37:23,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1988 states. [2018-10-26 23:37:23,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1988 to 1796. [2018-10-26 23:37:23,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-10-26 23:37:23,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 2387 transitions. [2018-10-26 23:37:23,701 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 2387 transitions. Word has length 138 [2018-10-26 23:37:23,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:23,702 INFO L481 AbstractCegarLoop]: Abstraction has 1796 states and 2387 transitions. [2018-10-26 23:37:23,702 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:37:23,702 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 2387 transitions. [2018-10-26 23:37:23,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-10-26 23:37:23,704 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:23,704 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:23,704 INFO L424 AbstractCegarLoop]: === Iteration 18 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:23,704 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:23,704 INFO L82 PathProgramCache]: Analyzing trace with hash -1377876699, now seen corresponding path program 1 times [2018-10-26 23:37:23,705 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:23,705 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:23,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:23,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:23,852 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:23,916 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:37:23,916 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:23,919 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:23,919 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 23:37:23,920 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 23:37:23,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 23:37:23,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:23,923 INFO L87 Difference]: Start difference. First operand 1796 states and 2387 transitions. Second operand 3 states. [2018-10-26 23:37:24,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:24,085 INFO L93 Difference]: Finished difference Result 2951 states and 3940 transitions. [2018-10-26 23:37:24,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 23:37:24,086 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 140 [2018-10-26 23:37:24,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:24,093 INFO L225 Difference]: With dead ends: 2951 [2018-10-26 23:37:24,093 INFO L226 Difference]: Without dead ends: 1814 [2018-10-26 23:37:24,096 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 23:37:24,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1814 states. [2018-10-26 23:37:24,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1814 to 1796. [2018-10-26 23:37:24,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-10-26 23:37:24,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 2381 transitions. [2018-10-26 23:37:24,185 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 2381 transitions. Word has length 140 [2018-10-26 23:37:24,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:24,186 INFO L481 AbstractCegarLoop]: Abstraction has 1796 states and 2381 transitions. [2018-10-26 23:37:24,186 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 23:37:24,186 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 2381 transitions. [2018-10-26 23:37:24,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2018-10-26 23:37:24,188 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:24,188 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:24,188 INFO L424 AbstractCegarLoop]: === Iteration 19 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:24,189 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:24,189 INFO L82 PathProgramCache]: Analyzing trace with hash 1503990070, now seen corresponding path program 1 times [2018-10-26 23:37:24,189 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:24,189 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:24,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:24,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:24,340 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:24,396 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 23:37:24,396 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:24,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:24,398 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-26 23:37:24,398 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:37:24,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:37:24,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:37:24,398 INFO L87 Difference]: Start difference. First operand 1796 states and 2381 transitions. Second operand 8 states. [2018-10-26 23:37:25,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:25,092 INFO L93 Difference]: Finished difference Result 3008 states and 4024 transitions. [2018-10-26 23:37:25,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:37:25,094 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 139 [2018-10-26 23:37:25,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:25,099 INFO L225 Difference]: With dead ends: 3008 [2018-10-26 23:37:25,100 INFO L226 Difference]: Without dead ends: 1887 [2018-10-26 23:37:25,103 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 133 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:37:25,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1887 states. [2018-10-26 23:37:25,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1887 to 1772. [2018-10-26 23:37:25,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1772 states. [2018-10-26 23:37:25,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1772 states to 1772 states and 2335 transitions. [2018-10-26 23:37:25,194 INFO L78 Accepts]: Start accepts. Automaton has 1772 states and 2335 transitions. Word has length 139 [2018-10-26 23:37:25,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:25,194 INFO L481 AbstractCegarLoop]: Abstraction has 1772 states and 2335 transitions. [2018-10-26 23:37:25,195 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:37:25,195 INFO L276 IsEmpty]: Start isEmpty. Operand 1772 states and 2335 transitions. [2018-10-26 23:37:25,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2018-10-26 23:37:25,196 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:25,197 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:25,197 INFO L424 AbstractCegarLoop]: === Iteration 20 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:25,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:25,197 INFO L82 PathProgramCache]: Analyzing trace with hash -662767333, now seen corresponding path program 1 times [2018-10-26 23:37:25,199 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:25,199 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:25,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:25,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:25,447 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:25,600 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:37:25,600 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (21)] Exception during sending of exit command (exit): Broken pipe [2018-10-26 23:37:25,603 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:25,604 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:25,604 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:25,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:25,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:25,605 INFO L87 Difference]: Start difference. First operand 1772 states and 2335 transitions. Second operand 4 states. [2018-10-26 23:37:25,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:25,939 INFO L93 Difference]: Finished difference Result 4379 states and 5821 transitions. [2018-10-26 23:37:25,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:25,940 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 139 [2018-10-26 23:37:25,940 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:25,952 INFO L225 Difference]: With dead ends: 4379 [2018-10-26 23:37:25,952 INFO L226 Difference]: Without dead ends: 3261 [2018-10-26 23:37:25,955 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 135 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:25,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3261 states. [2018-10-26 23:37:26,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3261 to 3036. [2018-10-26 23:37:26,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3036 states. [2018-10-26 23:37:26,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3036 states to 3036 states and 4009 transitions. [2018-10-26 23:37:26,108 INFO L78 Accepts]: Start accepts. Automaton has 3036 states and 4009 transitions. Word has length 139 [2018-10-26 23:37:26,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:26,108 INFO L481 AbstractCegarLoop]: Abstraction has 3036 states and 4009 transitions. [2018-10-26 23:37:26,108 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:26,109 INFO L276 IsEmpty]: Start isEmpty. Operand 3036 states and 4009 transitions. [2018-10-26 23:37:26,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-10-26 23:37:26,112 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:26,112 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:26,112 INFO L424 AbstractCegarLoop]: === Iteration 21 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:26,112 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:26,112 INFO L82 PathProgramCache]: Analyzing trace with hash -1291838255, now seen corresponding path program 1 times [2018-10-26 23:37:26,113 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:26,113 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:26,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:26,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:26,356 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:26,513 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:37:26,513 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:26,518 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:26,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:26,518 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:26,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:26,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:26,518 INFO L87 Difference]: Start difference. First operand 3036 states and 4009 transitions. Second operand 4 states. [2018-10-26 23:37:27,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:27,122 INFO L93 Difference]: Finished difference Result 7026 states and 9360 transitions. [2018-10-26 23:37:27,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:27,122 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 141 [2018-10-26 23:37:27,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:27,135 INFO L225 Difference]: With dead ends: 7026 [2018-10-26 23:37:27,135 INFO L226 Difference]: Without dead ends: 4908 [2018-10-26 23:37:27,139 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 137 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:27,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4908 states. [2018-10-26 23:37:27,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4908 to 4717. [2018-10-26 23:37:27,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4717 states. [2018-10-26 23:37:27,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4717 states to 4717 states and 6237 transitions. [2018-10-26 23:37:27,373 INFO L78 Accepts]: Start accepts. Automaton has 4717 states and 6237 transitions. Word has length 141 [2018-10-26 23:37:27,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:27,374 INFO L481 AbstractCegarLoop]: Abstraction has 4717 states and 6237 transitions. [2018-10-26 23:37:27,374 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:27,374 INFO L276 IsEmpty]: Start isEmpty. Operand 4717 states and 6237 transitions. [2018-10-26 23:37:27,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-10-26 23:37:27,377 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:27,377 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:27,377 INFO L424 AbstractCegarLoop]: === Iteration 22 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:27,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:27,379 INFO L82 PathProgramCache]: Analyzing trace with hash -1870314826, now seen corresponding path program 1 times [2018-10-26 23:37:27,379 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:27,379 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) [2018-10-26 23:37:27,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:27,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:27,660 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:27,786 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:37:27,786 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:27,788 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:27,788 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:37:27,789 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:37:27,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:37:27,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:37:27,789 INFO L87 Difference]: Start difference. First operand 4717 states and 6237 transitions. Second operand 7 states. [2018-10-26 23:37:28,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:28,835 INFO L93 Difference]: Finished difference Result 7935 states and 10506 transitions. [2018-10-26 23:37:28,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 23:37:28,838 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 141 [2018-10-26 23:37:28,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:28,849 INFO L225 Difference]: With dead ends: 7935 [2018-10-26 23:37:28,849 INFO L226 Difference]: Without dead ends: 3942 [2018-10-26 23:37:28,857 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 137 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-10-26 23:37:28,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3942 states. [2018-10-26 23:37:29,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3942 to 3926. [2018-10-26 23:37:29,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3926 states. [2018-10-26 23:37:29,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3926 states to 3926 states and 5173 transitions. [2018-10-26 23:37:29,056 INFO L78 Accepts]: Start accepts. Automaton has 3926 states and 5173 transitions. Word has length 141 [2018-10-26 23:37:29,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:29,057 INFO L481 AbstractCegarLoop]: Abstraction has 3926 states and 5173 transitions. [2018-10-26 23:37:29,057 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:37:29,057 INFO L276 IsEmpty]: Start isEmpty. Operand 3926 states and 5173 transitions. [2018-10-26 23:37:29,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-10-26 23:37:29,060 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:29,060 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:29,060 INFO L424 AbstractCegarLoop]: === Iteration 23 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:29,060 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:29,060 INFO L82 PathProgramCache]: Analyzing trace with hash -1256561150, now seen corresponding path program 1 times [2018-10-26 23:37:29,061 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:29,061 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:29,085 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:29,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:29,214 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:29,862 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 23:37:29,862 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:29,864 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:29,864 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-26 23:37:29,864 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:37:29,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:37:29,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:37:29,865 INFO L87 Difference]: Start difference. First operand 3926 states and 5173 transitions. Second operand 8 states. [2018-10-26 23:37:30,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:30,505 INFO L93 Difference]: Finished difference Result 7532 states and 10134 transitions. [2018-10-26 23:37:30,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:37:30,506 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 144 [2018-10-26 23:37:30,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:30,519 INFO L225 Difference]: With dead ends: 7532 [2018-10-26 23:37:30,519 INFO L226 Difference]: Without dead ends: 4522 [2018-10-26 23:37:30,527 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:37:30,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4522 states. [2018-10-26 23:37:30,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4522 to 4051. [2018-10-26 23:37:30,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4051 states. [2018-10-26 23:37:30,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4051 states to 4051 states and 5365 transitions. [2018-10-26 23:37:30,745 INFO L78 Accepts]: Start accepts. Automaton has 4051 states and 5365 transitions. Word has length 144 [2018-10-26 23:37:30,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:30,746 INFO L481 AbstractCegarLoop]: Abstraction has 4051 states and 5365 transitions. [2018-10-26 23:37:30,746 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:37:30,746 INFO L276 IsEmpty]: Start isEmpty. Operand 4051 states and 5365 transitions. [2018-10-26 23:37:30,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-10-26 23:37:30,748 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:30,748 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:30,748 INFO L424 AbstractCegarLoop]: === Iteration 24 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:30,748 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:30,748 INFO L82 PathProgramCache]: Analyzing trace with hash -18862678, now seen corresponding path program 1 times [2018-10-26 23:37:30,749 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:30,749 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:30,774 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:30,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:30,901 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:31,070 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 23:37:31,070 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:37:31,235 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 23:37:31,242 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:37:31,242 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:37:31,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:31,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:31,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:31,564 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 23:37:31,565 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:31,581 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-10-26 23:37:31,581 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9, 9] total 18 [2018-10-26 23:37:31,582 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-10-26 23:37:31,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-10-26 23:37:31,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=250, Unknown=0, NotChecked=0, Total=306 [2018-10-26 23:37:31,582 INFO L87 Difference]: Start difference. First operand 4051 states and 5365 transitions. Second operand 18 states. [2018-10-26 23:37:34,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:34,805 INFO L93 Difference]: Finished difference Result 8756 states and 11742 transitions. [2018-10-26 23:37:34,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-10-26 23:37:34,806 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 145 [2018-10-26 23:37:34,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:34,822 INFO L225 Difference]: With dead ends: 8756 [2018-10-26 23:37:34,823 INFO L226 Difference]: Without dead ends: 5543 [2018-10-26 23:37:34,829 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 456 GetRequests, 422 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=198, Invalid=992, Unknown=0, NotChecked=0, Total=1190 [2018-10-26 23:37:34,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5543 states. [2018-10-26 23:37:35,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5543 to 3591. [2018-10-26 23:37:35,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3591 states. [2018-10-26 23:37:35,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3591 states to 3591 states and 4611 transitions. [2018-10-26 23:37:35,057 INFO L78 Accepts]: Start accepts. Automaton has 3591 states and 4611 transitions. Word has length 145 [2018-10-26 23:37:35,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:35,058 INFO L481 AbstractCegarLoop]: Abstraction has 3591 states and 4611 transitions. [2018-10-26 23:37:35,058 INFO L482 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-10-26 23:37:35,058 INFO L276 IsEmpty]: Start isEmpty. Operand 3591 states and 4611 transitions. [2018-10-26 23:37:35,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-10-26 23:37:35,059 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:35,059 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:35,060 INFO L424 AbstractCegarLoop]: === Iteration 25 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:35,060 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:35,060 INFO L82 PathProgramCache]: Analyzing trace with hash -659636774, now seen corresponding path program 1 times [2018-10-26 23:37:35,060 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:35,060 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:35,085 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:35,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:35,259 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:35,321 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 23:37:35,322 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:35,323 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:35,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:37:35,324 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:37:35,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:37:35,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:37:35,324 INFO L87 Difference]: Start difference. First operand 3591 states and 4611 transitions. Second operand 7 states. [2018-10-26 23:37:36,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:36,289 INFO L93 Difference]: Finished difference Result 6786 states and 8744 transitions. [2018-10-26 23:37:36,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 23:37:36,290 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 144 [2018-10-26 23:37:36,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:36,299 INFO L225 Difference]: With dead ends: 6786 [2018-10-26 23:37:36,299 INFO L226 Difference]: Without dead ends: 3437 [2018-10-26 23:37:36,306 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 140 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-10-26 23:37:36,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states. [2018-10-26 23:37:36,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3316. [2018-10-26 23:37:36,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3316 states. [2018-10-26 23:37:36,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3316 states to 3316 states and 4253 transitions. [2018-10-26 23:37:36,532 INFO L78 Accepts]: Start accepts. Automaton has 3316 states and 4253 transitions. Word has length 144 [2018-10-26 23:37:36,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:36,533 INFO L481 AbstractCegarLoop]: Abstraction has 3316 states and 4253 transitions. [2018-10-26 23:37:36,533 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:37:36,533 INFO L276 IsEmpty]: Start isEmpty. Operand 3316 states and 4253 transitions. [2018-10-26 23:37:36,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-10-26 23:37:36,535 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:36,535 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:36,535 INFO L424 AbstractCegarLoop]: === Iteration 26 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:36,535 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:36,536 INFO L82 PathProgramCache]: Analyzing trace with hash 917750483, now seen corresponding path program 1 times [2018-10-26 23:37:36,536 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:36,536 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:36,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:36,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:36,678 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:36,699 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:37:36,699 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:36,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:36,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:36,701 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:36,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:36,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:36,701 INFO L87 Difference]: Start difference. First operand 3316 states and 4253 transitions. Second operand 4 states. [2018-10-26 23:37:36,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:36,846 INFO L93 Difference]: Finished difference Result 6484 states and 8417 transitions. [2018-10-26 23:37:36,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 23:37:36,846 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 148 [2018-10-26 23:37:36,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:36,853 INFO L225 Difference]: With dead ends: 6484 [2018-10-26 23:37:36,853 INFO L226 Difference]: Without dead ends: 3508 [2018-10-26 23:37:36,858 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 146 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:36,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3508 states. [2018-10-26 23:37:37,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3508 to 3460. [2018-10-26 23:37:37,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3460 states. [2018-10-26 23:37:37,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4373 transitions. [2018-10-26 23:37:37,024 INFO L78 Accepts]: Start accepts. Automaton has 3460 states and 4373 transitions. Word has length 148 [2018-10-26 23:37:37,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:37,024 INFO L481 AbstractCegarLoop]: Abstraction has 3460 states and 4373 transitions. [2018-10-26 23:37:37,024 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:37,024 INFO L276 IsEmpty]: Start isEmpty. Operand 3460 states and 4373 transitions. [2018-10-26 23:37:37,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2018-10-26 23:37:37,026 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:37,026 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:37,026 INFO L424 AbstractCegarLoop]: === Iteration 27 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:37,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:37,027 INFO L82 PathProgramCache]: Analyzing trace with hash -1474049746, now seen corresponding path program 1 times [2018-10-26 23:37:37,027 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:37,027 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:37,054 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:37,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:37,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:38,249 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:37:38,250 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:38,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:38,251 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:37:38,254 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:37:38,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:37:38,254 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:37:38,254 INFO L87 Difference]: Start difference. First operand 3460 states and 4373 transitions. Second operand 9 states. [2018-10-26 23:37:39,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:39,602 INFO L93 Difference]: Finished difference Result 6580 states and 8372 transitions. [2018-10-26 23:37:39,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 23:37:39,603 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 153 [2018-10-26 23:37:39,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:39,611 INFO L225 Difference]: With dead ends: 6580 [2018-10-26 23:37:39,611 INFO L226 Difference]: Without dead ends: 3423 [2018-10-26 23:37:39,616 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 146 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:37:39,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3423 states. [2018-10-26 23:37:39,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3423 to 3345. [2018-10-26 23:37:39,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3345 states. [2018-10-26 23:37:39,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3345 states to 3345 states and 4223 transitions. [2018-10-26 23:37:39,824 INFO L78 Accepts]: Start accepts. Automaton has 3345 states and 4223 transitions. Word has length 153 [2018-10-26 23:37:39,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:39,824 INFO L481 AbstractCegarLoop]: Abstraction has 3345 states and 4223 transitions. [2018-10-26 23:37:39,824 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:37:39,824 INFO L276 IsEmpty]: Start isEmpty. Operand 3345 states and 4223 transitions. [2018-10-26 23:37:39,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-10-26 23:37:39,826 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:39,827 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:39,827 INFO L424 AbstractCegarLoop]: === Iteration 28 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:39,827 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:39,827 INFO L82 PathProgramCache]: Analyzing trace with hash -1329850705, now seen corresponding path program 1 times [2018-10-26 23:37:39,827 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:39,828 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:39,848 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:39,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:40,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:40,100 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-10-26 23:37:40,101 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:40,102 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:40,102 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-26 23:37:40,102 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:37:40,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:37:40,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:37:40,103 INFO L87 Difference]: Start difference. First operand 3345 states and 4223 transitions. Second operand 8 states. [2018-10-26 23:37:40,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:40,290 INFO L93 Difference]: Finished difference Result 3603 states and 4594 transitions. [2018-10-26 23:37:40,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:37:40,290 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 156 [2018-10-26 23:37:40,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:40,298 INFO L225 Difference]: With dead ends: 3603 [2018-10-26 23:37:40,298 INFO L226 Difference]: Without dead ends: 3601 [2018-10-26 23:37:40,300 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-10-26 23:37:40,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3601 states. [2018-10-26 23:37:40,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3601 to 3364. [2018-10-26 23:37:40,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3364 states. [2018-10-26 23:37:40,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3364 states to 3364 states and 4248 transitions. [2018-10-26 23:37:40,518 INFO L78 Accepts]: Start accepts. Automaton has 3364 states and 4248 transitions. Word has length 156 [2018-10-26 23:37:40,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:40,518 INFO L481 AbstractCegarLoop]: Abstraction has 3364 states and 4248 transitions. [2018-10-26 23:37:40,518 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:37:40,518 INFO L276 IsEmpty]: Start isEmpty. Operand 3364 states and 4248 transitions. [2018-10-26 23:37:40,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2018-10-26 23:37:40,519 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:40,520 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:40,520 INFO L424 AbstractCegarLoop]: === Iteration 29 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:40,520 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:40,520 INFO L82 PathProgramCache]: Analyzing trace with hash -248837690, now seen corresponding path program 1 times [2018-10-26 23:37:40,520 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:40,520 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:40,541 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:40,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:40,679 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:40,719 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-10-26 23:37:40,719 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:40,720 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:40,721 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:40,762 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:40,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:40,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:40,762 INFO L87 Difference]: Start difference. First operand 3364 states and 4248 transitions. Second operand 4 states. [2018-10-26 23:37:40,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:40,936 INFO L93 Difference]: Finished difference Result 6337 states and 8109 transitions. [2018-10-26 23:37:40,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:37:40,937 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 157 [2018-10-26 23:37:40,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:40,944 INFO L225 Difference]: With dead ends: 6337 [2018-10-26 23:37:40,945 INFO L226 Difference]: Without dead ends: 3318 [2018-10-26 23:37:40,950 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:40,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3318 states. [2018-10-26 23:37:41,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3318 to 3318. [2018-10-26 23:37:41,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3318 states. [2018-10-26 23:37:41,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3318 states to 3318 states and 4110 transitions. [2018-10-26 23:37:41,157 INFO L78 Accepts]: Start accepts. Automaton has 3318 states and 4110 transitions. Word has length 157 [2018-10-26 23:37:41,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:41,158 INFO L481 AbstractCegarLoop]: Abstraction has 3318 states and 4110 transitions. [2018-10-26 23:37:41,158 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:41,158 INFO L276 IsEmpty]: Start isEmpty. Operand 3318 states and 4110 transitions. [2018-10-26 23:37:41,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-10-26 23:37:41,159 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:41,159 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:41,159 INFO L424 AbstractCegarLoop]: === Iteration 30 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:41,159 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:41,159 INFO L82 PathProgramCache]: Analyzing trace with hash 1241184532, now seen corresponding path program 1 times [2018-10-26 23:37:41,160 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:41,160 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:41,185 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:41,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:41,302 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:41,336 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-10-26 23:37:41,337 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:41,338 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:41,339 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:41,339 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:41,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:41,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:41,339 INFO L87 Difference]: Start difference. First operand 3318 states and 4110 transitions. Second operand 4 states. [2018-10-26 23:37:41,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:41,491 INFO L93 Difference]: Finished difference Result 6218 states and 7803 transitions. [2018-10-26 23:37:41,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:37:41,501 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 166 [2018-10-26 23:37:41,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:41,510 INFO L225 Difference]: With dead ends: 6218 [2018-10-26 23:37:41,510 INFO L226 Difference]: Without dead ends: 3272 [2018-10-26 23:37:41,516 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:41,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3272 states. [2018-10-26 23:37:41,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3272 to 3272. [2018-10-26 23:37:41,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3272 states. [2018-10-26 23:37:41,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3272 states to 3272 states and 3972 transitions. [2018-10-26 23:37:41,720 INFO L78 Accepts]: Start accepts. Automaton has 3272 states and 3972 transitions. Word has length 166 [2018-10-26 23:37:41,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:41,721 INFO L481 AbstractCegarLoop]: Abstraction has 3272 states and 3972 transitions. [2018-10-26 23:37:41,721 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:41,721 INFO L276 IsEmpty]: Start isEmpty. Operand 3272 states and 3972 transitions. [2018-10-26 23:37:41,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-10-26 23:37:41,724 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:41,725 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 5, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:41,725 INFO L424 AbstractCegarLoop]: === Iteration 31 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:41,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:41,725 INFO L82 PathProgramCache]: Analyzing trace with hash -930618732, now seen corresponding path program 1 times [2018-10-26 23:37:41,725 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:41,725 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:41,743 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:41,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:41,843 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:41,991 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-10-26 23:37:41,991 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (33)] Exception during sending of exit command (exit): Broken pipe [2018-10-26 23:37:41,997 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:41,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:41,999 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:41,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:42,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:42,000 INFO L87 Difference]: Start difference. First operand 3272 states and 3972 transitions. Second operand 4 states. [2018-10-26 23:37:42,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:42,332 INFO L93 Difference]: Finished difference Result 6078 states and 7476 transitions. [2018-10-26 23:37:42,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:37:42,333 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 182 [2018-10-26 23:37:42,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:42,339 INFO L225 Difference]: With dead ends: 6078 [2018-10-26 23:37:42,339 INFO L226 Difference]: Without dead ends: 3226 [2018-10-26 23:37:42,343 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 180 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:42,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3226 states. [2018-10-26 23:37:42,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3226 to 3226. [2018-10-26 23:37:42,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3226 states. [2018-10-26 23:37:42,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3226 states to 3226 states and 3834 transitions. [2018-10-26 23:37:42,532 INFO L78 Accepts]: Start accepts. Automaton has 3226 states and 3834 transitions. Word has length 182 [2018-10-26 23:37:42,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:42,532 INFO L481 AbstractCegarLoop]: Abstraction has 3226 states and 3834 transitions. [2018-10-26 23:37:42,532 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:42,532 INFO L276 IsEmpty]: Start isEmpty. Operand 3226 states and 3834 transitions. [2018-10-26 23:37:42,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-10-26 23:37:42,536 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:42,536 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:42,536 INFO L424 AbstractCegarLoop]: === Iteration 32 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:42,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:42,536 INFO L82 PathProgramCache]: Analyzing trace with hash -1147726044, now seen corresponding path program 1 times [2018-10-26 23:37:42,537 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:42,537 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:42,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:42,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:42,703 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:42,780 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 94 trivial. 0 not checked. [2018-10-26 23:37:42,780 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:42,781 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:42,782 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 23:37:42,782 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 23:37:42,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 23:37:42,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 23:37:42,782 INFO L87 Difference]: Start difference. First operand 3226 states and 3834 transitions. Second operand 4 states. [2018-10-26 23:37:42,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:42,912 INFO L93 Difference]: Finished difference Result 5918 states and 7109 transitions. [2018-10-26 23:37:42,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 23:37:42,913 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 198 [2018-10-26 23:37:42,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:42,919 INFO L225 Difference]: With dead ends: 5918 [2018-10-26 23:37:42,919 INFO L226 Difference]: Without dead ends: 3157 [2018-10-26 23:37:42,923 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 196 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-26 23:37:42,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3157 states. [2018-10-26 23:37:43,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3157 to 2967. [2018-10-26 23:37:43,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2967 states. [2018-10-26 23:37:43,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2967 states to 2967 states and 3443 transitions. [2018-10-26 23:37:43,036 INFO L78 Accepts]: Start accepts. Automaton has 2967 states and 3443 transitions. Word has length 198 [2018-10-26 23:37:43,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:43,036 INFO L481 AbstractCegarLoop]: Abstraction has 2967 states and 3443 transitions. [2018-10-26 23:37:43,036 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 23:37:43,036 INFO L276 IsEmpty]: Start isEmpty. Operand 2967 states and 3443 transitions. [2018-10-26 23:37:43,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-10-26 23:37:43,038 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:43,038 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 5, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:43,038 INFO L424 AbstractCegarLoop]: === Iteration 33 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:43,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:43,039 INFO L82 PathProgramCache]: Analyzing trace with hash 1564069126, now seen corresponding path program 1 times [2018-10-26 23:37:43,039 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:43,039 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:43,077 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:43,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:43,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:43,368 INFO L134 CoverageAnalysis]: Checked inductivity of 115 backedges. 74 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-10-26 23:37:43,369 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:37:43,370 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:37:43,370 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:37:43,371 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:37:43,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:37:43,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:37:43,371 INFO L87 Difference]: Start difference. First operand 2967 states and 3443 transitions. Second operand 9 states. [2018-10-26 23:37:48,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:48,060 INFO L93 Difference]: Finished difference Result 5779 states and 6806 transitions. [2018-10-26 23:37:48,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 23:37:48,061 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 210 [2018-10-26 23:37:48,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:48,066 INFO L225 Difference]: With dead ends: 5779 [2018-10-26 23:37:48,066 INFO L226 Difference]: Without dead ends: 3142 [2018-10-26 23:37:48,070 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 204 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:37:48,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3142 states. [2018-10-26 23:37:48,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3142 to 2826. [2018-10-26 23:37:48,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2826 states. [2018-10-26 23:37:48,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2826 states to 2826 states and 3281 transitions. [2018-10-26 23:37:48,194 INFO L78 Accepts]: Start accepts. Automaton has 2826 states and 3281 transitions. Word has length 210 [2018-10-26 23:37:48,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:48,195 INFO L481 AbstractCegarLoop]: Abstraction has 2826 states and 3281 transitions. [2018-10-26 23:37:48,195 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:37:48,195 INFO L276 IsEmpty]: Start isEmpty. Operand 2826 states and 3281 transitions. [2018-10-26 23:37:48,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2018-10-26 23:37:48,198 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:48,199 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:48,199 INFO L424 AbstractCegarLoop]: === Iteration 34 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:48,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:48,199 INFO L82 PathProgramCache]: Analyzing trace with hash 1156485311, now seen corresponding path program 1 times [2018-10-26 23:37:48,199 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:48,199 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:48,237 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:48,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:48,484 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:48,627 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 82 proven. 24 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-10-26 23:37:48,627 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:37:49,163 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2018-10-26 23:37:49,165 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:37:49,165 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:37:49,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:49,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:49,275 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:49,333 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 82 proven. 24 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-10-26 23:37:49,333 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:37:49,537 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 8 proven. 11 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2018-10-26 23:37:49,553 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:37:49,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13, 14] total 24 [2018-10-26 23:37:49,554 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-10-26 23:37:49,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-10-26 23:37:49,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=480, Unknown=0, NotChecked=0, Total=552 [2018-10-26 23:37:49,555 INFO L87 Difference]: Start difference. First operand 2826 states and 3281 transitions. Second operand 24 states. [2018-10-26 23:37:55,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:37:55,357 INFO L93 Difference]: Finished difference Result 6439 states and 7545 transitions. [2018-10-26 23:37:55,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-10-26 23:37:55,359 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 260 [2018-10-26 23:37:55,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:37:55,368 INFO L225 Difference]: With dead ends: 6439 [2018-10-26 23:37:55,368 INFO L226 Difference]: Without dead ends: 3982 [2018-10-26 23:37:55,375 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1123 GetRequests, 1029 SyntacticMatches, 12 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1674 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1457, Invalid=5515, Unknown=0, NotChecked=0, Total=6972 [2018-10-26 23:37:55,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3982 states. [2018-10-26 23:37:55,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3982 to 3178. [2018-10-26 23:37:55,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3178 states. [2018-10-26 23:37:55,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3178 states to 3178 states and 3689 transitions. [2018-10-26 23:37:55,632 INFO L78 Accepts]: Start accepts. Automaton has 3178 states and 3689 transitions. Word has length 260 [2018-10-26 23:37:55,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:37:55,633 INFO L481 AbstractCegarLoop]: Abstraction has 3178 states and 3689 transitions. [2018-10-26 23:37:55,633 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-10-26 23:37:55,633 INFO L276 IsEmpty]: Start isEmpty. Operand 3178 states and 3689 transitions. [2018-10-26 23:37:55,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 262 [2018-10-26 23:37:55,637 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:37:55,637 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:37:55,637 INFO L424 AbstractCegarLoop]: === Iteration 35 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:37:55,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:37:55,638 INFO L82 PathProgramCache]: Analyzing trace with hash -1528167733, now seen corresponding path program 1 times [2018-10-26 23:37:55,638 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:37:55,638 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:37:55,652 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:55,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:55,892 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:56,049 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 77 proven. 46 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-10-26 23:37:56,050 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:37:56,468 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 11 proven. 24 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-10-26 23:37:56,470 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:37:56,470 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:37:56,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:37:56,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:37:56,565 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:37:56,648 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 77 proven. 46 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-10-26 23:37:56,649 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:37:56,918 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 11 proven. 24 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-10-26 23:37:56,935 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:37:56,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13, 14] total 24 [2018-10-26 23:37:56,936 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-10-26 23:37:56,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-10-26 23:37:56,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=480, Unknown=0, NotChecked=0, Total=552 [2018-10-26 23:37:56,936 INFO L87 Difference]: Start difference. First operand 3178 states and 3689 transitions. Second operand 24 states. [2018-10-26 23:38:02,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:02,385 INFO L93 Difference]: Finished difference Result 7109 states and 8331 transitions. [2018-10-26 23:38:02,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-10-26 23:38:02,386 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 261 [2018-10-26 23:38:02,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:02,394 INFO L225 Difference]: With dead ends: 7109 [2018-10-26 23:38:02,394 INFO L226 Difference]: Without dead ends: 4292 [2018-10-26 23:38:02,400 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1103 GetRequests, 1021 SyntacticMatches, 13 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1208 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=870, Invalid=4100, Unknown=0, NotChecked=0, Total=4970 [2018-10-26 23:38:02,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4292 states. [2018-10-26 23:38:02,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4292 to 4062. [2018-10-26 23:38:02,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4062 states. [2018-10-26 23:38:02,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4062 states to 4062 states and 4718 transitions. [2018-10-26 23:38:02,776 INFO L78 Accepts]: Start accepts. Automaton has 4062 states and 4718 transitions. Word has length 261 [2018-10-26 23:38:02,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:02,777 INFO L481 AbstractCegarLoop]: Abstraction has 4062 states and 4718 transitions. [2018-10-26 23:38:02,777 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-10-26 23:38:02,777 INFO L276 IsEmpty]: Start isEmpty. Operand 4062 states and 4718 transitions. [2018-10-26 23:38:02,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 263 [2018-10-26 23:38:02,786 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:02,786 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:02,787 INFO L424 AbstractCegarLoop]: === Iteration 36 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:02,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:02,787 INFO L82 PathProgramCache]: Analyzing trace with hash -928649062, now seen corresponding path program 1 times [2018-10-26 23:38:02,787 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:02,787 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:02,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:03,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:03,162 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:03,290 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 61 proven. 52 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:03,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:03,656 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 13 proven. 11 refuted. 0 times theorem prover too weak. 116 trivial. 0 not checked. [2018-10-26 23:38:03,658 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:38:03,658 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:38:03,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:03,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:03,746 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:03,795 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 61 proven. 52 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:03,795 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:03,936 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 13 proven. 11 refuted. 0 times theorem prover too weak. 116 trivial. 0 not checked. [2018-10-26 23:38:03,953 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:38:03,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 17 [2018-10-26 23:38:03,954 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-10-26 23:38:03,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-10-26 23:38:03,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2018-10-26 23:38:03,954 INFO L87 Difference]: Start difference. First operand 4062 states and 4718 transitions. Second operand 17 states. [2018-10-26 23:38:05,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:05,941 INFO L93 Difference]: Finished difference Result 8112 states and 9563 transitions. [2018-10-26 23:38:05,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-10-26 23:38:05,941 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 262 [2018-10-26 23:38:05,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:05,949 INFO L225 Difference]: With dead ends: 8112 [2018-10-26 23:38:05,949 INFO L226 Difference]: Without dead ends: 4503 [2018-10-26 23:38:05,955 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1077 GetRequests, 1030 SyntacticMatches, 12 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 215 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=334, Invalid=998, Unknown=0, NotChecked=0, Total=1332 [2018-10-26 23:38:05,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4503 states. [2018-10-26 23:38:06,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4503 to 4439. [2018-10-26 23:38:06,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4439 states. [2018-10-26 23:38:06,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4439 states to 4439 states and 5191 transitions. [2018-10-26 23:38:06,379 INFO L78 Accepts]: Start accepts. Automaton has 4439 states and 5191 transitions. Word has length 262 [2018-10-26 23:38:06,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:06,379 INFO L481 AbstractCegarLoop]: Abstraction has 4439 states and 5191 transitions. [2018-10-26 23:38:06,380 INFO L482 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-10-26 23:38:06,380 INFO L276 IsEmpty]: Start isEmpty. Operand 4439 states and 5191 transitions. [2018-10-26 23:38:06,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 264 [2018-10-26 23:38:06,386 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:06,386 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:06,386 INFO L424 AbstractCegarLoop]: === Iteration 37 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:06,386 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:06,386 INFO L82 PathProgramCache]: Analyzing trace with hash 1541103329, now seen corresponding path program 1 times [2018-10-26 23:38:06,387 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:06,387 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:06,409 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:06,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:06,749 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:06,853 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 88 proven. 26 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:06,853 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:07,278 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 19 proven. 3 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-10-26 23:38:07,281 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:38:07,281 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:38:07,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:07,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:07,441 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:07,539 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 88 proven. 26 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:07,539 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:08,198 WARN L179 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-10-26 23:38:08,347 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 19 proven. 3 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-10-26 23:38:08,363 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:38:08,364 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9] total 15 [2018-10-26 23:38:08,364 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-10-26 23:38:08,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-10-26 23:38:08,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-10-26 23:38:08,365 INFO L87 Difference]: Start difference. First operand 4439 states and 5191 transitions. Second operand 15 states. [2018-10-26 23:38:10,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:10,735 INFO L93 Difference]: Finished difference Result 10944 states and 12896 transitions. [2018-10-26 23:38:10,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-10-26 23:38:10,736 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 263 [2018-10-26 23:38:10,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:10,747 INFO L225 Difference]: With dead ends: 10944 [2018-10-26 23:38:10,747 INFO L226 Difference]: Without dead ends: 6909 [2018-10-26 23:38:10,753 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1072 GetRequests, 1037 SyntacticMatches, 9 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=155, Invalid=601, Unknown=0, NotChecked=0, Total=756 [2018-10-26 23:38:10,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6909 states. [2018-10-26 23:38:11,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6909 to 6047. [2018-10-26 23:38:11,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6047 states. [2018-10-26 23:38:11,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6047 states to 6047 states and 7138 transitions. [2018-10-26 23:38:11,232 INFO L78 Accepts]: Start accepts. Automaton has 6047 states and 7138 transitions. Word has length 263 [2018-10-26 23:38:11,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:11,233 INFO L481 AbstractCegarLoop]: Abstraction has 6047 states and 7138 transitions. [2018-10-26 23:38:11,233 INFO L482 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-10-26 23:38:11,233 INFO L276 IsEmpty]: Start isEmpty. Operand 6047 states and 7138 transitions. [2018-10-26 23:38:11,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 264 [2018-10-26 23:38:11,238 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:11,238 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:11,238 INFO L424 AbstractCegarLoop]: === Iteration 38 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:11,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:11,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1754720415, now seen corresponding path program 1 times [2018-10-26 23:38:11,239 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:11,239 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:11,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:11,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:11,487 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:11,582 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 32 proven. 0 refuted. 0 times theorem prover too weak. 109 trivial. 0 not checked. [2018-10-26 23:38:11,582 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:38:11,584 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:38:11,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-26 23:38:11,584 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 23:38:11,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 23:38:11,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-10-26 23:38:11,585 INFO L87 Difference]: Start difference. First operand 6047 states and 7138 transitions. Second operand 7 states. [2018-10-26 23:38:12,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:12,339 INFO L93 Difference]: Finished difference Result 10123 states and 12107 transitions. [2018-10-26 23:38:12,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 23:38:12,340 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 263 [2018-10-26 23:38:12,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:12,350 INFO L225 Difference]: With dead ends: 10123 [2018-10-26 23:38:12,350 INFO L226 Difference]: Without dead ends: 4447 [2018-10-26 23:38:12,356 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 264 GetRequests, 257 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:38:12,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4447 states. [2018-10-26 23:38:12,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4447 to 4329. [2018-10-26 23:38:12,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4329 states. [2018-10-26 23:38:12,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4329 states to 4329 states and 5146 transitions. [2018-10-26 23:38:12,641 INFO L78 Accepts]: Start accepts. Automaton has 4329 states and 5146 transitions. Word has length 263 [2018-10-26 23:38:12,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:12,641 INFO L481 AbstractCegarLoop]: Abstraction has 4329 states and 5146 transitions. [2018-10-26 23:38:12,641 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 23:38:12,642 INFO L276 IsEmpty]: Start isEmpty. Operand 4329 states and 5146 transitions. [2018-10-26 23:38:12,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-10-26 23:38:12,645 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:12,645 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:12,645 INFO L424 AbstractCegarLoop]: === Iteration 39 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:12,645 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:12,645 INFO L82 PathProgramCache]: Analyzing trace with hash 1885938986, now seen corresponding path program 1 times [2018-10-26 23:38:12,646 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:12,646 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:12,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:12,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:12,898 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:13,034 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2018-10-26 23:38:13,035 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:38:13,036 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:38:13,037 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-26 23:38:13,037 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:38:13,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:38:13,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:38:13,037 INFO L87 Difference]: Start difference. First operand 4329 states and 5146 transitions. Second operand 8 states. [2018-10-26 23:38:14,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:14,100 INFO L93 Difference]: Finished difference Result 12685 states and 15513 transitions. [2018-10-26 23:38:14,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 23:38:14,101 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 266 [2018-10-26 23:38:14,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:14,119 INFO L225 Difference]: With dead ends: 12685 [2018-10-26 23:38:14,119 INFO L226 Difference]: Without dead ends: 8725 [2018-10-26 23:38:14,127 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 259 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-10-26 23:38:14,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8725 states. [2018-10-26 23:38:14,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8725 to 8227. [2018-10-26 23:38:14,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8227 states. [2018-10-26 23:38:14,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8227 states to 8227 states and 9945 transitions. [2018-10-26 23:38:14,695 INFO L78 Accepts]: Start accepts. Automaton has 8227 states and 9945 transitions. Word has length 266 [2018-10-26 23:38:14,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:14,696 INFO L481 AbstractCegarLoop]: Abstraction has 8227 states and 9945 transitions. [2018-10-26 23:38:14,696 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:38:14,696 INFO L276 IsEmpty]: Start isEmpty. Operand 8227 states and 9945 transitions. [2018-10-26 23:38:14,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-10-26 23:38:14,702 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:14,702 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:14,702 INFO L424 AbstractCegarLoop]: === Iteration 40 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:14,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:14,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1404858728, now seen corresponding path program 1 times [2018-10-26 23:38:14,703 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:14,703 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:14,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:14,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:14,958 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:15,082 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 88 proven. 29 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:15,082 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:15,355 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 22 proven. 3 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-10-26 23:38:15,357 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:38:15,357 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:38:15,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:15,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:15,452 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:15,538 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 88 proven. 29 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:15,538 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:16,371 WARN L179 SmtUtils]: Spent 128.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-10-26 23:38:16,559 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 22 proven. 3 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-10-26 23:38:16,581 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:38:16,581 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9] total 12 [2018-10-26 23:38:16,582 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-26 23:38:16,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-26 23:38:16,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:38:16,582 INFO L87 Difference]: Start difference. First operand 8227 states and 9945 transitions. Second operand 12 states. [2018-10-26 23:38:18,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:18,729 INFO L93 Difference]: Finished difference Result 16367 states and 19785 transitions. [2018-10-26 23:38:18,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-10-26 23:38:18,730 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 266 [2018-10-26 23:38:18,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:18,745 INFO L225 Difference]: With dead ends: 16367 [2018-10-26 23:38:18,745 INFO L226 Difference]: Without dead ends: 8509 [2018-10-26 23:38:18,753 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1082 GetRequests, 1051 SyntacticMatches, 8 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 73 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=126, Invalid=474, Unknown=0, NotChecked=0, Total=600 [2018-10-26 23:38:18,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8509 states. [2018-10-26 23:38:19,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8509 to 8227. [2018-10-26 23:38:19,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8227 states. [2018-10-26 23:38:19,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8227 states to 8227 states and 9905 transitions. [2018-10-26 23:38:19,399 INFO L78 Accepts]: Start accepts. Automaton has 8227 states and 9905 transitions. Word has length 266 [2018-10-26 23:38:19,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:19,399 INFO L481 AbstractCegarLoop]: Abstraction has 8227 states and 9905 transitions. [2018-10-26 23:38:19,399 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-26 23:38:19,399 INFO L276 IsEmpty]: Start isEmpty. Operand 8227 states and 9905 transitions. [2018-10-26 23:38:19,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 268 [2018-10-26 23:38:19,405 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:19,405 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:19,407 INFO L424 AbstractCegarLoop]: === Iteration 41 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:19,407 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:19,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1222091095, now seen corresponding path program 1 times [2018-10-26 23:38:19,407 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:19,408 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:19,420 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:19,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:19,552 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:19,621 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 136 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-10-26 23:38:19,621 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:38:19,623 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:38:19,623 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 23:38:19,623 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 23:38:19,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 23:38:19,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-10-26 23:38:19,623 INFO L87 Difference]: Start difference. First operand 8227 states and 9905 transitions. Second operand 9 states. [2018-10-26 23:38:20,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:20,596 INFO L93 Difference]: Finished difference Result 18083 states and 21973 transitions. [2018-10-26 23:38:20,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 23:38:20,597 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 267 [2018-10-26 23:38:20,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:20,614 INFO L225 Difference]: With dead ends: 18083 [2018-10-26 23:38:20,615 INFO L226 Difference]: Without dead ends: 10153 [2018-10-26 23:38:20,623 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 269 GetRequests, 259 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:38:20,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10153 states. [2018-10-26 23:38:21,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10153 to 9271. [2018-10-26 23:38:21,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9271 states. [2018-10-26 23:38:21,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9271 states to 9271 states and 11061 transitions. [2018-10-26 23:38:21,390 INFO L78 Accepts]: Start accepts. Automaton has 9271 states and 11061 transitions. Word has length 267 [2018-10-26 23:38:21,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:21,390 INFO L481 AbstractCegarLoop]: Abstraction has 9271 states and 11061 transitions. [2018-10-26 23:38:21,390 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 23:38:21,390 INFO L276 IsEmpty]: Start isEmpty. Operand 9271 states and 11061 transitions. [2018-10-26 23:38:21,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-10-26 23:38:21,395 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:21,395 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:21,396 INFO L424 AbstractCegarLoop]: === Iteration 42 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:21,396 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:21,396 INFO L82 PathProgramCache]: Analyzing trace with hash 922625315, now seen corresponding path program 1 times [2018-10-26 23:38:21,396 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:21,396 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:21,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:21,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:21,550 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:21,632 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 50 proven. 81 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-10-26 23:38:21,632 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:21,873 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 23 proven. 16 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-10-26 23:38:21,874 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:38:21,874 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:38:21,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:21,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:21,962 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:21,994 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 50 proven. 81 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-10-26 23:38:21,994 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:22,163 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 23 proven. 16 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-10-26 23:38:22,179 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:38:22,179 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 11, 12] total 19 [2018-10-26 23:38:22,180 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-10-26 23:38:22,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-10-26 23:38:22,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=287, Unknown=0, NotChecked=0, Total=342 [2018-10-26 23:38:22,180 INFO L87 Difference]: Start difference. First operand 9271 states and 11061 transitions. Second operand 19 states. [2018-10-26 23:38:23,230 WARN L179 SmtUtils]: Spent 124.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-26 23:38:27,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:27,554 INFO L93 Difference]: Finished difference Result 24085 states and 28447 transitions. [2018-10-26 23:38:27,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-10-26 23:38:27,555 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 274 [2018-10-26 23:38:27,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:27,586 INFO L225 Difference]: With dead ends: 24085 [2018-10-26 23:38:27,586 INFO L226 Difference]: Without dead ends: 15183 [2018-10-26 23:38:27,598 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1148 GetRequests, 1095 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 714 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=524, Invalid=2446, Unknown=0, NotChecked=0, Total=2970 [2018-10-26 23:38:27,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15183 states. [2018-10-26 23:38:28,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15183 to 13745. [2018-10-26 23:38:28,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13745 states. [2018-10-26 23:38:28,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13745 states to 13745 states and 16017 transitions. [2018-10-26 23:38:28,675 INFO L78 Accepts]: Start accepts. Automaton has 13745 states and 16017 transitions. Word has length 274 [2018-10-26 23:38:28,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:28,675 INFO L481 AbstractCegarLoop]: Abstraction has 13745 states and 16017 transitions. [2018-10-26 23:38:28,675 INFO L482 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-10-26 23:38:28,675 INFO L276 IsEmpty]: Start isEmpty. Operand 13745 states and 16017 transitions. [2018-10-26 23:38:28,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-10-26 23:38:28,680 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:28,680 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:28,681 INFO L424 AbstractCegarLoop]: === Iteration 43 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:28,681 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:28,681 INFO L82 PathProgramCache]: Analyzing trace with hash 989675694, now seen corresponding path program 1 times [2018-10-26 23:38:28,681 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:28,681 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:28,696 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:28,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:28,831 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:29,976 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 71 proven. 72 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-10-26 23:38:29,977 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:30,225 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 29 proven. 11 refuted. 0 times theorem prover too weak. 134 trivial. 0 not checked. [2018-10-26 23:38:30,226 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 23:38:30,226 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 23:38:30,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:30,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:30,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:30,351 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 71 proven. 72 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-10-26 23:38:30,351 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 23:38:30,515 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 29 proven. 11 refuted. 0 times theorem prover too weak. 134 trivial. 0 not checked. [2018-10-26 23:38:30,531 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-10-26 23:38:30,531 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 11, 12] total 19 [2018-10-26 23:38:30,532 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-10-26 23:38:30,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-10-26 23:38:30,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=287, Unknown=0, NotChecked=0, Total=342 [2018-10-26 23:38:30,532 INFO L87 Difference]: Start difference. First operand 13745 states and 16017 transitions. Second operand 19 states. [2018-10-26 23:38:32,486 WARN L179 SmtUtils]: Spent 147.00 ms on a formula simplification that was a NOOP. DAG size: 10 [2018-10-26 23:38:35,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:35,029 INFO L93 Difference]: Finished difference Result 25089 states and 29464 transitions. [2018-10-26 23:38:35,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-10-26 23:38:35,030 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 274 [2018-10-26 23:38:35,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:35,057 INFO L225 Difference]: With dead ends: 25089 [2018-10-26 23:38:35,057 INFO L226 Difference]: Without dead ends: 11259 [2018-10-26 23:38:35,070 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1147 GetRequests, 1092 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 723 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=551, Invalid=2641, Unknown=0, NotChecked=0, Total=3192 [2018-10-26 23:38:35,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11259 states. [2018-10-26 23:38:35,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11259 to 10769. [2018-10-26 23:38:35,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10769 states. [2018-10-26 23:38:35,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10769 states to 10769 states and 12657 transitions. [2018-10-26 23:38:35,856 INFO L78 Accepts]: Start accepts. Automaton has 10769 states and 12657 transitions. Word has length 274 [2018-10-26 23:38:35,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:35,856 INFO L481 AbstractCegarLoop]: Abstraction has 10769 states and 12657 transitions. [2018-10-26 23:38:35,856 INFO L482 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-10-26 23:38:35,856 INFO L276 IsEmpty]: Start isEmpty. Operand 10769 states and 12657 transitions. [2018-10-26 23:38:35,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-10-26 23:38:35,861 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:35,861 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:35,861 INFO L424 AbstractCegarLoop]: === Iteration 44 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:35,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:35,861 INFO L82 PathProgramCache]: Analyzing trace with hash 771944115, now seen corresponding path program 1 times [2018-10-26 23:38:35,862 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:35,862 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:36,102 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:36,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 23:38:36,240 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 23:38:36,295 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2018-10-26 23:38:36,296 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-26 23:38:36,297 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 23:38:36,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-26 23:38:36,298 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 23:38:36,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 23:38:36,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 23:38:36,298 INFO L87 Difference]: Start difference. First operand 10769 states and 12657 transitions. Second operand 8 states. [2018-10-26 23:38:37,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 23:38:37,580 INFO L93 Difference]: Finished difference Result 21487 states and 25405 transitions. [2018-10-26 23:38:37,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 23:38:37,581 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 274 [2018-10-26 23:38:37,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 23:38:37,608 INFO L225 Difference]: With dead ends: 21487 [2018-10-26 23:38:37,608 INFO L226 Difference]: Without dead ends: 11087 [2018-10-26 23:38:37,622 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2018-10-26 23:38:37,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11087 states. [2018-10-26 23:38:38,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11087 to 10765. [2018-10-26 23:38:38,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10765 states. [2018-10-26 23:38:38,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10765 states to 10765 states and 12645 transitions. [2018-10-26 23:38:38,370 INFO L78 Accepts]: Start accepts. Automaton has 10765 states and 12645 transitions. Word has length 274 [2018-10-26 23:38:38,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 23:38:38,370 INFO L481 AbstractCegarLoop]: Abstraction has 10765 states and 12645 transitions. [2018-10-26 23:38:38,370 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 23:38:38,370 INFO L276 IsEmpty]: Start isEmpty. Operand 10765 states and 12645 transitions. [2018-10-26 23:38:38,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 276 [2018-10-26 23:38:38,375 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 23:38:38,375 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 23:38:38,375 INFO L424 AbstractCegarLoop]: === Iteration 45 === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 23:38:38,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 23:38:38,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1682118303, now seen corresponding path program 1 times [2018-10-26 23:38:38,376 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-26 23:38:38,376 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/cvc4nyu Starting monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-26 23:38:38,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 23:38:38,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 23:38:38,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 23:38:39,323 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-10-26 23:38:39,839 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.10 11:38:39 BoogieIcfgContainer [2018-10-26 23:38:39,841 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-10-26 23:38:39,842 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-26 23:38:39,842 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-26 23:38:39,842 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-26 23:38:39,842 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 11:37:00" (3/4) ... [2018-10-26 23:38:39,844 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-10-26 23:38:40,127 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_210c05c0-b991-4196-bfb2-4395bde5b23b/bin-2019/utaipan/witness.graphml [2018-10-26 23:38:40,130 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-26 23:38:40,131 INFO L168 Benchmark]: Toolchain (without parser) took 101411.72 ms. Allocated memory was 1.0 GB in the beginning and 3.3 GB in the end (delta: 2.2 GB). Free memory was 953.2 MB in the beginning and 2.9 GB in the end (delta: -1.9 GB). Peak memory consumption was 323.3 MB. Max. memory is 11.5 GB. [2018-10-26 23:38:40,132 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:38:40,132 INFO L168 Benchmark]: CACSL2BoogieTranslator took 397.44 ms. Allocated memory is still 1.0 GB. Free memory was 947.9 MB in the beginning and 925.1 MB in the end (delta: 22.8 MB). Peak memory consumption was 22.8 MB. Max. memory is 11.5 GB. [2018-10-26 23:38:40,132 INFO L168 Benchmark]: Boogie Procedure Inliner took 29.06 ms. Allocated memory is still 1.0 GB. Free memory is still 925.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 23:38:40,132 INFO L168 Benchmark]: Boogie Preprocessor took 154.29 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 181.4 MB). Free memory was 925.1 MB in the beginning and 1.2 GB in the end (delta: -248.1 MB). Peak memory consumption was 17.5 MB. Max. memory is 11.5 GB. [2018-10-26 23:38:40,132 INFO L168 Benchmark]: RCFGBuilder took 1331.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 67.5 MB). Peak memory consumption was 67.5 MB. Max. memory is 11.5 GB. [2018-10-26 23:38:40,133 INFO L168 Benchmark]: TraceAbstraction took 99205.34 ms. Allocated memory was 1.2 GB in the beginning and 3.3 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 2.9 GB in the end (delta: -1.8 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2018-10-26 23:38:40,133 INFO L168 Benchmark]: Witness Printer took 288.78 ms. Allocated memory is still 3.3 GB. Free memory was 2.9 GB in the beginning and 2.9 GB in the end (delta: 42.6 MB). Peak memory consumption was 42.6 MB. Max. memory is 11.5 GB. [2018-10-26 23:38:40,141 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 397.44 ms. Allocated memory is still 1.0 GB. Free memory was 947.9 MB in the beginning and 925.1 MB in the end (delta: 22.8 MB). Peak memory consumption was 22.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 29.06 ms. Allocated memory is still 1.0 GB. Free memory is still 925.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 154.29 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 181.4 MB). Free memory was 925.1 MB in the beginning and 1.2 GB in the end (delta: -248.1 MB). Peak memory consumption was 17.5 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1331.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 67.5 MB). Peak memory consumption was 67.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 99205.34 ms. Allocated memory was 1.2 GB in the beginning and 3.3 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 2.9 GB in the end (delta: -1.8 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. * Witness Printer took 288.78 ms. Allocated memory is still 3.3 GB. Free memory was 2.9 GB in the beginning and 2.9 GB in the end (delta: 42.6 MB). Peak memory consumption was 42.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 661]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(nomsg)=0, \old(s1p)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L606] CALL, EXPR init() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] RET return (1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=1, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] EXPR init() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, init()=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, i2=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, i2=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L627] CALL Console_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L299] CALL write_manual_selection_history(manual_selection) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=1, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] RET manual_selection_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=1, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=1] [L299] write_manual_selection_history(manual_selection) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L300] COND TRUE, EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection=1, manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] COND TRUE, EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=255, cs2_old=255, manual_selection=1, manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] RET manual_selection = (msg_t )0 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L627] Console_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L628] CALL Side1_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L318] CALL write_side1_failed_history(side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=1, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] RET side1Failed_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=1, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=1] [L318] write_side1_failed_history(side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] COND FALSE, EXPR !(nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new=-1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] COND FALSE, EXPR !(nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new=-1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] COND FALSE, EXPR !(nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new=-1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] RET side1_written = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=255, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=255, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L628] Side1_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L629] CALL Side2_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L375] CALL write_side2_failed_history(side2Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] RET side2Failed_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=0] [L375] write_side2_failed_history(side2Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] COND TRUE, EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=255, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] COND TRUE, EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] COND TRUE, EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] RET side2_written = next_state VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=255, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=255, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L629] Side2_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L630] CALL Pendulum_prism_task_each_pals_period() VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND TRUE (int )index == 0 [L191] RET return (active_side_History_0); VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=-2, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, index=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] EXPR read_active_side_history((unsigned char)0) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_active_side_history((unsigned char)0)=-2, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=254, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L436] COND FALSE !((int )side1 == 1) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=254, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L439] COND FALSE !((int )side2 == 1) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=254, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L442] COND FALSE !((int )side1 == 0) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=254, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L450] COND TRUE (int )side1 == (int )nomsg VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=254, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L459] CALL write_active_side_history(active_side) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=254, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] RET active_side_History_0 = val VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=0] [L459] RET write_active_side_history(active_side) VAL [\old(active_side_History_0)=254, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=255, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=254] [L630] Pendulum_prism_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=1, cs1_old=255, cs2=0, cs2_new=1, cs2_old=255, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=255, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=0, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] CALL, EXPR check() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L499] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] RET return (manual_selection_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] EXPR read_manual_selection_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_manual_selection_history((unsigned char)1)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0] [L501] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] RET return (side1Failed_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_side1_failed_history((unsigned char)1)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0] [L503] CALL, EXPR read_side1_failed_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND TRUE (int )index == 0 [L131] RET return (side1Failed_History_0); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=1, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] EXPR read_side1_failed_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_side1_failed_history((unsigned char)0)=1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND FALSE !(! tmp___2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___2=1] [L529] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] RET return (side1Failed_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_side1_failed_history((unsigned char)1)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___2=1] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND FALSE !(\read(tmp___7)) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___2=1, tmp___7=0] [L545] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] RET return (side1Failed_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L545] EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_side1_failed_history((unsigned char)1)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___2=1, tmp___7=0] [L545] tmp___11 = read_side1_failed_history((unsigned char)1) [L546] COND TRUE ! tmp___11 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___11=0, tmp___2=1, tmp___7=0] [L547] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L160] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] RET return (side2Failed_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L547] EXPR read_side2_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_side2_failed_history((unsigned char)1)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___11=0, tmp___2=1, tmp___7=0] [L547] tmp___12 = read_side2_failed_history((unsigned char)1) [L548] COND FALSE !(\read(tmp___12)) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___11=0, tmp___12=0, tmp___2=1, tmp___7=0] [L561] CALL, EXPR read_active_side_history((unsigned char)2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=2, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=2, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=2, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=2, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=2, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] RET return (active_side_History_2); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=2, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=-2, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, index=2, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L561] EXPR read_active_side_history((unsigned char)2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, read_active_side_history((unsigned char)2)=-2, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___11=0, tmp___12=0, tmp___2=1, tmp___7=0] [L561] tmp___20 = read_active_side_history((unsigned char)2) [L562] COND FALSE !((int )tmp___20 > -2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___11=0, tmp___12=0, tmp___2=1, tmp___20=254, tmp___7=0] [L580] RET return (1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=1, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=0, tmp___1=0, tmp___11=0, tmp___12=0, tmp___2=1, tmp___20=254, tmp___7=0] [L647] EXPR check() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=0, check()=1, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L648] CALL assert(c1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(arg)=1, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L659] COND FALSE, RET !(! arg) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(arg)=1, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, arg=1, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L648] assert(c1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=1, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=1, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, i2=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L627] CALL Console_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection=0, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L299] CALL write_manual_selection_history(manual_selection) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] RET manual_selection_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=0] [L299] write_manual_selection_history(manual_selection) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L300] COND TRUE, EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection=0, manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] COND TRUE, EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=255, cs2_old=1, manual_selection=0, manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] RET manual_selection = (msg_t )0 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=255, \old(cs1_old)=0, \old(cs2_new)=255, \old(cs2_old)=0, \old(manual_selection_History_0)=1, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L627] Console_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=1, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, i2=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L628] CALL Side1_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L318] CALL write_side1_failed_history(side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=1, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] RET side1Failed_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=1, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=1] [L318] write_side1_failed_history(side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] COND FALSE, EXPR !(nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new=-1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] COND FALSE, EXPR !(nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new=-1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] COND FALSE, EXPR !(nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new=-1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] RET side1_written = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=1, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=255, \old(s1p_old)=0, \old(s1s1_new)=255, \old(s1s1_old)=255, \old(s1s2_new)=255, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=255, \old(side1Failed)=1, \old(side1Failed_History_0)=1, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L628] Side1_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=1, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, i2=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L629] CALL Side2_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L375] CALL write_side2_failed_history(side2Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] RET side2Failed_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=0] [L375] write_side2_failed_history(side2Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=1, manual_selection=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=255, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND FALSE !((int )side1 == (int )side2) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L392] COND TRUE (int )side1 == (int )nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L393] COND TRUE (int )side2 != (int )nomsg [L394] next_state = (int8_t )0 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, next_state=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] COND TRUE, EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, next_state=0, next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] COND TRUE, EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, next_state=0, next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] COND TRUE, EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, next_state=0, next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] RET side2_written = next_state VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=255, \old(s2p_new)=255, \old(s2p_old)=0, \old(s2s1_new)=255, \old(s2s1_old)=0, \old(s2s2_new)=255, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, next_state=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L629] Side2_activestandby_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, c1=1, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, i2=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L630] CALL Pendulum_prism_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND TRUE (int )index == 0 [L191] RET return (active_side_History_0); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, index=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] EXPR read_active_side_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, read_active_side_history((unsigned char)0)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L436] COND FALSE !((int )side1 == 1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L439] COND FALSE !((int )side2 == 1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L442] COND FALSE !((int )side1 == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=0, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L451] COND TRUE (int )side2 == 0 [L452] active_side = (int8_t )2 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=2, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L459] CALL write_active_side_history(active_side) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=2, active_side_History_0=0, active_side_History_1=254, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] RET active_side_History_0 = val VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \old(val)=2, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, val=2] [L459] RET write_active_side_history(active_side) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=254, \old(active_side_History_2)=254, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=255, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side=2, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=0] [L630] Pendulum_prism_task_each_pals_period() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, c1=1, cs1=0, cs1_new=0, cs1_old=1, cs2=0, cs2_new=0, cs2_old=255, i2=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=0, s2p_old=255, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=255, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, c1=1, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, i2=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] CALL, EXPR check() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L499] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] RET return (manual_selection_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] EXPR read_manual_selection_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, read_manual_selection_history((unsigned char)1)=1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND FALSE !(! tmp___0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1] [L529] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] RET return (side1Failed_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] EXPR read_side1_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, read_side1_failed_history((unsigned char)1)=1, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND TRUE \read(tmp___7) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___7=1] [L531] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L160] COND FALSE !((int )index == 0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] RET return (side2Failed_History_1); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=1, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L531] EXPR read_side2_failed_history((unsigned char)1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, read_side2_failed_history((unsigned char)1)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___7=1] [L531] tmp___8 = read_side2_failed_history((unsigned char)1) [L532] COND TRUE ! tmp___8 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___7=1, tmp___8=0] [L533] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND TRUE (int )index == 0 [L191] RET return (active_side_History_0); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=2, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L533] EXPR read_active_side_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, read_active_side_history((unsigned char)0)=2, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___7=1, tmp___8=0] [L533] tmp___5 = read_active_side_history((unsigned char)0) [L534] COND FALSE !(! ((int )tmp___5 == 2)) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___5=2, tmp___7=1, tmp___8=0] [L537] CALL, EXPR read_side2_failed_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L160] COND TRUE (int )index == 0 [L161] RET return (side2Failed_History_0); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(index)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, index=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] EXPR read_side2_failed_history((unsigned char)0) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, read_side2_failed_history((unsigned char)0)=0, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___5=2, tmp___7=1, tmp___8=0] [L537] tmp___6 = read_side2_failed_history((unsigned char)0) [L538] COND TRUE ! tmp___6 VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___5=2, tmp___6=0, tmp___7=1, tmp___8=0] [L539] COND TRUE ! ((int )side2_written == 1) [L540] RET return (0); VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, \result=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, tmp=1, tmp___0=1, tmp___5=2, tmp___6=0, tmp___7=1, tmp___8=0] [L647] EXPR check() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, c1=1, check()=0, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, i2=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L648] CALL assert(c1) VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(arg)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L659] COND TRUE ! arg VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(arg)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, arg=0, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L661] __VERIFIER_error() VAL [\old(active_side_History_0)=0, \old(active_side_History_1)=0, \old(active_side_History_2)=0, \old(arg)=0, \old(cs1_new)=0, \old(cs1_old)=0, \old(cs2_new)=0, \old(cs2_old)=0, \old(manual_selection_History_0)=0, \old(manual_selection_History_1)=0, \old(manual_selection_History_2)=0, \old(s1p_new)=0, \old(s1p_old)=0, \old(s1s1_new)=0, \old(s1s1_old)=0, \old(s1s2_new)=0, \old(s1s2_old)=0, \old(s2p_new)=0, \old(s2p_old)=0, \old(s2s1_new)=0, \old(s2s1_old)=0, \old(s2s2_new)=0, \old(s2s2_old)=0, \old(side1_written)=0, \old(side1Failed)=0, \old(side1Failed_History_0)=0, \old(side1Failed_History_1)=0, \old(side1Failed_History_2)=0, \old(side2_written)=0, \old(side2Failed)=0, \old(side2Failed_History_0)=0, \old(side2Failed_History_1)=0, \old(side2Failed_History_2)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=254, arg=0, cs1=0, cs1_new=255, cs1_old=0, cs2=0, cs2_new=255, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=1, manual_selection_History_2=0, nomsg=255, s1p=0, s1p_new=255, s1p_old=255, s1s1=0, s1s1_new=255, s1s1_old=255, s1s2=0, s1s2_new=255, s1s2_old=255, s2p=0, s2p_new=255, s2p_old=0, s2s1=0, s2s1_new=255, s2s1_old=0, s2s2=0, s2s2_new=255, s2s2_old=0, side1_written=255, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 19 procedures, 237 locations, 1 error locations. UNSAFE Result, 99.1s OverallTime, 45 OverallIterations, 6 TraceHistogramMax, 63.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 16633 SDtfs, 28398 SDslu, 30109 SDs, 0 SdLazy, 51024 SolverSat, 9643 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 40.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 13555 GetRequests, 12882 SyntacticMatches, 64 SemanticMatches, 609 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5097 ImplicationChecksByTransitivity, 15.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=13745occurred in iteration=42, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 10.0s AutomataMinimizationTime, 44 MinimizatonAttempts, 10474 StatesRemovedByMinimization, 38 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 2.0s SsaConstructionTime, 5.2s SatisfiabilityAnalysisTime, 15.3s InterpolantComputationTime, 9539 NumberOfCodeBlocks, 9539 NumberOfCodeBlocksAsserted, 53 NumberOfCheckSat, 13062 ConstructedInterpolants, 0 QuantifiedInterpolants, 7456952 SizeOfPredicates, 129 NumberOfNonLiveVariables, 33167 ConjunctsInSsa, 405 ConjunctsInUnsatCore, 67 InterpolantComputations, 37 PerfectInterpolantSequences, 4679/5503 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...