./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c -s /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 747981090a474d9d2269aea1ffd03eef2ddc8848 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-26 21:33:12,562 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 21:33:12,567 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 21:33:12,575 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 21:33:12,576 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 21:33:12,576 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 21:33:12,577 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 21:33:12,583 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 21:33:12,585 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 21:33:12,585 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 21:33:12,586 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 21:33:12,586 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 21:33:12,588 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 21:33:12,591 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 21:33:12,601 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 21:33:12,601 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 21:33:12,602 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 21:33:12,603 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 21:33:12,604 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 21:33:12,605 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 21:33:12,606 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 21:33:12,611 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 21:33:12,613 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 21:33:12,613 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 21:33:12,613 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 21:33:12,614 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 21:33:12,615 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 21:33:12,616 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 21:33:12,617 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 21:33:12,617 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 21:33:12,618 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 21:33:12,618 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 21:33:12,618 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 21:33:12,618 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 21:33:12,620 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 21:33:12,621 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 21:33:12,621 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-10-26 21:33:12,633 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 21:33:12,633 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 21:33:12,634 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 21:33:12,634 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-26 21:33:12,634 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-26 21:33:12,634 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-26 21:33:12,634 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-10-26 21:33:12,634 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-26 21:33:12,635 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-10-26 21:33:12,636 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-10-26 21:33:12,636 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-26 21:33:12,636 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 21:33:12,637 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-26 21:33:12,637 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-26 21:33:12,637 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-26 21:33:12,637 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 21:33:12,637 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 21:33:12,637 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 21:33:12,638 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 21:33:12,638 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-26 21:33:12,638 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 21:33:12,638 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 21:33:12,638 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 21:33:12,638 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-26 21:33:12,638 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 21:33:12,640 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-26 21:33:12,640 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 21:33:12,641 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 21:33:12,641 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 21:33:12,641 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 21:33:12,641 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-10-26 21:33:12,641 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 21:33:12,641 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-26 21:33:12,642 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-26 21:33:12,642 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 747981090a474d9d2269aea1ffd03eef2ddc8848 [2018-10-26 21:33:12,674 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 21:33:12,688 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 21:33:12,691 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 21:33:12,692 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 21:33:12,692 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 21:33:12,693 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-10-26 21:33:12,753 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/data/5ef94e58d/cacb1698a88a42b09ed0b307644889a5/FLAG1ad2077bc [2018-10-26 21:33:13,193 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 21:33:13,194 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-10-26 21:33:13,205 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/data/5ef94e58d/cacb1698a88a42b09ed0b307644889a5/FLAG1ad2077bc [2018-10-26 21:33:13,219 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/data/5ef94e58d/cacb1698a88a42b09ed0b307644889a5 [2018-10-26 21:33:13,223 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 21:33:13,224 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 21:33:13,225 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 21:33:13,226 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 21:33:13,230 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 21:33:13,231 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,233 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@267e2a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13, skipping insertion in model container [2018-10-26 21:33:13,234 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,244 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 21:33:13,294 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 21:33:13,630 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 21:33:13,634 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 21:33:13,729 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 21:33:13,766 INFO L193 MainTranslator]: Completed translation [2018-10-26 21:33:13,767 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13 WrapperNode [2018-10-26 21:33:13,767 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 21:33:13,768 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 21:33:13,768 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 21:33:13,768 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 21:33:13,780 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,805 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,820 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 21:33:13,820 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 21:33:13,820 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 21:33:13,820 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 21:33:13,830 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,830 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,833 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,833 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,849 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,953 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,956 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... [2018-10-26 21:33:13,960 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 21:33:13,960 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 21:33:13,961 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 21:33:13,961 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 21:33:13,962 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 21:33:14,031 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-26 21:33:14,033 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-26 21:33:14,033 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 21:33:14,033 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 21:33:14,033 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-26 21:33:14,034 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-26 21:33:15,663 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 21:33:15,663 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:33:15 BoogieIcfgContainer [2018-10-26 21:33:15,664 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 21:33:15,664 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-26 21:33:15,665 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-26 21:33:15,667 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-26 21:33:15,668 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.10 09:33:13" (1/3) ... [2018-10-26 21:33:15,668 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3473ff0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 09:33:15, skipping insertion in model container [2018-10-26 21:33:15,669 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:33:13" (2/3) ... [2018-10-26 21:33:15,669 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3473ff0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 09:33:15, skipping insertion in model container [2018-10-26 21:33:15,669 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:33:15" (3/3) ... [2018-10-26 21:33:15,671 INFO L112 eAbstractionObserver]: Analyzing ICFG psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-10-26 21:33:15,679 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-26 21:33:15,688 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-10-26 21:33:15,702 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-10-26 21:33:15,729 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-26 21:33:15,729 INFO L383 AbstractCegarLoop]: Hoare is true [2018-10-26 21:33:15,729 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-26 21:33:15,729 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-26 21:33:15,729 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-26 21:33:15,730 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-26 21:33:15,730 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-26 21:33:15,730 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-26 21:33:15,745 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states. [2018-10-26 21:33:15,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-26 21:33:15,750 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:15,751 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:15,753 INFO L424 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:15,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:15,758 INFO L82 PathProgramCache]: Analyzing trace with hash -662778961, now seen corresponding path program 1 times [2018-10-26 21:33:15,760 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:15,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:15,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:15,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:15,797 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:15,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:15,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:15,906 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:33:15,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:33:15,906 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:15,910 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:15,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:15,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:15,920 INFO L87 Difference]: Start difference. First operand 115 states. Second operand 3 states. [2018-10-26 21:33:16,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:16,871 INFO L93 Difference]: Finished difference Result 331 states and 635 transitions. [2018-10-26 21:33:16,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:16,873 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-10-26 21:33:16,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:16,887 INFO L225 Difference]: With dead ends: 331 [2018-10-26 21:33:16,887 INFO L226 Difference]: Without dead ends: 206 [2018-10-26 21:33:16,891 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:16,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-10-26 21:33:16,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 182. [2018-10-26 21:33:16,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-10-26 21:33:16,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 314 transitions. [2018-10-26 21:33:16,947 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 314 transitions. Word has length 14 [2018-10-26 21:33:16,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:16,947 INFO L481 AbstractCegarLoop]: Abstraction has 182 states and 314 transitions. [2018-10-26 21:33:16,948 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:16,948 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 314 transitions. [2018-10-26 21:33:16,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-10-26 21:33:16,949 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:16,949 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:16,949 INFO L424 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:16,949 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:16,950 INFO L82 PathProgramCache]: Analyzing trace with hash -1058783719, now seen corresponding path program 1 times [2018-10-26 21:33:16,950 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:16,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:16,952 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:16,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:16,953 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:16,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:17,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:17,020 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:33:17,020 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:33:17,020 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:17,021 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:17,021 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:17,021 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:17,021 INFO L87 Difference]: Start difference. First operand 182 states and 314 transitions. Second operand 3 states. [2018-10-26 21:33:17,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:17,063 INFO L93 Difference]: Finished difference Result 365 states and 632 transitions. [2018-10-26 21:33:17,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:17,064 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-10-26 21:33:17,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:17,066 INFO L225 Difference]: With dead ends: 365 [2018-10-26 21:33:17,066 INFO L226 Difference]: Without dead ends: 189 [2018-10-26 21:33:17,068 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:17,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-10-26 21:33:17,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2018-10-26 21:33:17,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-10-26 21:33:17,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 322 transitions. [2018-10-26 21:33:17,095 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 322 transitions. Word has length 15 [2018-10-26 21:33:17,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:17,095 INFO L481 AbstractCegarLoop]: Abstraction has 189 states and 322 transitions. [2018-10-26 21:33:17,095 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:17,096 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 322 transitions. [2018-10-26 21:33:17,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-10-26 21:33:17,096 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:17,096 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:17,097 INFO L424 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:17,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:17,097 INFO L82 PathProgramCache]: Analyzing trace with hash -426524154, now seen corresponding path program 1 times [2018-10-26 21:33:17,097 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:17,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:17,098 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:17,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:17,098 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:17,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:17,274 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:17,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:33:17,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:33:17,275 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:17,275 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:17,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:17,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:17,276 INFO L87 Difference]: Start difference. First operand 189 states and 322 transitions. Second operand 3 states. [2018-10-26 21:33:17,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:17,676 INFO L93 Difference]: Finished difference Result 290 states and 484 transitions. [2018-10-26 21:33:17,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:17,678 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 21 [2018-10-26 21:33:17,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:17,680 INFO L225 Difference]: With dead ends: 290 [2018-10-26 21:33:17,680 INFO L226 Difference]: Without dead ends: 274 [2018-10-26 21:33:17,681 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:17,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-10-26 21:33:17,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 259. [2018-10-26 21:33:17,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-10-26 21:33:17,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 436 transitions. [2018-10-26 21:33:17,698 INFO L78 Accepts]: Start accepts. Automaton has 259 states and 436 transitions. Word has length 21 [2018-10-26 21:33:17,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:17,698 INFO L481 AbstractCegarLoop]: Abstraction has 259 states and 436 transitions. [2018-10-26 21:33:17,698 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:17,699 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 436 transitions. [2018-10-26 21:33:17,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-10-26 21:33:17,699 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:17,700 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:17,700 INFO L424 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:17,700 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:17,700 INFO L82 PathProgramCache]: Analyzing trace with hash -1881066880, now seen corresponding path program 1 times [2018-10-26 21:33:17,700 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:17,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:17,701 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:17,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:17,701 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:17,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:17,743 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:17,743 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:33:17,743 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:33:17,744 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:17,744 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:17,744 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:17,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:17,744 INFO L87 Difference]: Start difference. First operand 259 states and 436 transitions. Second operand 3 states. [2018-10-26 21:33:17,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:17,826 INFO L93 Difference]: Finished difference Result 468 states and 791 transitions. [2018-10-26 21:33:17,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:17,827 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-10-26 21:33:17,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:17,828 INFO L225 Difference]: With dead ends: 468 [2018-10-26 21:33:17,828 INFO L226 Difference]: Without dead ends: 216 [2018-10-26 21:33:17,829 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:17,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-10-26 21:33:17,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 214. [2018-10-26 21:33:17,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-10-26 21:33:17,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 355 transitions. [2018-10-26 21:33:17,840 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 355 transitions. Word has length 22 [2018-10-26 21:33:17,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:17,840 INFO L481 AbstractCegarLoop]: Abstraction has 214 states and 355 transitions. [2018-10-26 21:33:17,840 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:17,840 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 355 transitions. [2018-10-26 21:33:17,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-10-26 21:33:17,841 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:17,842 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:17,842 INFO L424 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:17,842 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:17,842 INFO L82 PathProgramCache]: Analyzing trace with hash 30525515, now seen corresponding path program 1 times [2018-10-26 21:33:17,842 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:17,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:17,843 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:17,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:17,843 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:17,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:17,969 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 11 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:17,970 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:17,970 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:33:17,971 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 29 with the following transitions: [2018-10-26 21:33:17,972 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [18], [20], [24], [27], [30], [35], [42], [45], [48], [51], [54], [56], [526], [529], [530], [531] [2018-10-26 21:33:18,012 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:33:18,013 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:33:18,711 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:33:20,763 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:33:20,764 INFO L272 AbstractInterpreter]: Visited 21 different actions 45 times. Merged at 11 different actions 17 times. Never widened. Found 5 fixpoints after 4 different actions. Largest state had 38 variables. [2018-10-26 21:33:20,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:20,781 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:33:20,781 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:20,781 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:33:20,789 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:20,789 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:33:20,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:20,850 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:33:20,917 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:33:20,917 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:33:20,940 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:33:20,969 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-10-26 21:33:20,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [4] total 6 [2018-10-26 21:33:20,970 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:20,970 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:20,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:20,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-26 21:33:20,971 INFO L87 Difference]: Start difference. First operand 214 states and 355 transitions. Second operand 3 states. [2018-10-26 21:33:21,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:21,132 INFO L93 Difference]: Finished difference Result 389 states and 646 transitions. [2018-10-26 21:33:21,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:21,133 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2018-10-26 21:33:21,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:21,134 INFO L225 Difference]: With dead ends: 389 [2018-10-26 21:33:21,134 INFO L226 Difference]: Without dead ends: 182 [2018-10-26 21:33:21,135 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-26 21:33:21,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-10-26 21:33:21,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 180. [2018-10-26 21:33:21,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-10-26 21:33:21,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 291 transitions. [2018-10-26 21:33:21,143 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 291 transitions. Word has length 28 [2018-10-26 21:33:21,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:21,143 INFO L481 AbstractCegarLoop]: Abstraction has 180 states and 291 transitions. [2018-10-26 21:33:21,143 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:21,143 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 291 transitions. [2018-10-26 21:33:21,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-26 21:33:21,144 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:21,145 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:21,145 INFO L424 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:21,145 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:21,145 INFO L82 PathProgramCache]: Analyzing trace with hash 1381236108, now seen corresponding path program 1 times [2018-10-26 21:33:21,145 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:21,146 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:21,146 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:21,146 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:21,147 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:21,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:21,263 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:21,263 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:21,263 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:33:21,264 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 31 with the following transitions: [2018-10-26 21:33:21,264 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [18], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [239], [242], [245], [526], [529], [530], [531] [2018-10-26 21:33:21,266 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:33:21,266 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:33:21,683 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:33:23,310 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 21:33:23,310 INFO L272 AbstractInterpreter]: Visited 25 different actions 55 times. Merged at 16 different actions 22 times. Never widened. Found 4 fixpoints after 3 different actions. Largest state had 39 variables. [2018-10-26 21:33:23,319 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:23,319 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 21:33:24,052 INFO L227 lantSequenceWeakener]: Weakened 28 states. On average, predicates are now at 91.12% of their original sizes. [2018-10-26 21:33:24,052 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 21:33:24,917 INFO L415 sIntCurrentIteration]: We unified 29 AI predicates to 29 [2018-10-26 21:33:24,917 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 21:33:24,917 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-10-26 21:33:24,918 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [14] imperfect sequences [4] total 16 [2018-10-26 21:33:24,918 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:24,918 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-10-26 21:33:24,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-10-26 21:33:24,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-10-26 21:33:24,919 INFO L87 Difference]: Start difference. First operand 180 states and 291 transitions. Second operand 14 states. [2018-10-26 21:33:36,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:36,231 INFO L93 Difference]: Finished difference Result 375 states and 610 transitions. [2018-10-26 21:33:36,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 21:33:36,231 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 30 [2018-10-26 21:33:36,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:36,233 INFO L225 Difference]: With dead ends: 375 [2018-10-26 21:33:36,233 INFO L226 Difference]: Without dead ends: 220 [2018-10-26 21:33:36,233 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 36 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=97, Invalid=283, Unknown=0, NotChecked=0, Total=380 [2018-10-26 21:33:36,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-10-26 21:33:36,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 217. [2018-10-26 21:33:36,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-10-26 21:33:36,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 338 transitions. [2018-10-26 21:33:36,257 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 338 transitions. Word has length 30 [2018-10-26 21:33:36,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:36,258 INFO L481 AbstractCegarLoop]: Abstraction has 217 states and 338 transitions. [2018-10-26 21:33:36,258 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-10-26 21:33:36,258 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 338 transitions. [2018-10-26 21:33:36,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:33:36,265 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:36,266 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:36,266 INFO L424 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:36,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:36,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1339641340, now seen corresponding path program 1 times [2018-10-26 21:33:36,266 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:36,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:36,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:36,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:36,268 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:36,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:36,405 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:33:36,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:33:36,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:33:36,405 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:36,405 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:36,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:36,406 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:36,406 INFO L87 Difference]: Start difference. First operand 217 states and 338 transitions. Second operand 3 states. [2018-10-26 21:33:36,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:36,849 INFO L93 Difference]: Finished difference Result 391 states and 620 transitions. [2018-10-26 21:33:36,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:36,850 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2018-10-26 21:33:36,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:36,851 INFO L225 Difference]: With dead ends: 391 [2018-10-26 21:33:36,851 INFO L226 Difference]: Without dead ends: 223 [2018-10-26 21:33:36,852 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:36,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-10-26 21:33:36,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 221. [2018-10-26 21:33:36,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-10-26 21:33:36,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 341 transitions. [2018-10-26 21:33:36,866 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 341 transitions. Word has length 40 [2018-10-26 21:33:36,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:36,867 INFO L481 AbstractCegarLoop]: Abstraction has 221 states and 341 transitions. [2018-10-26 21:33:36,868 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:36,868 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 341 transitions. [2018-10-26 21:33:36,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:33:36,873 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:36,873 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:36,873 INFO L424 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:36,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:36,874 INFO L82 PathProgramCache]: Analyzing trace with hash 2019699710, now seen corresponding path program 1 times [2018-10-26 21:33:36,874 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:36,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:36,874 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:36,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:36,875 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:36,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:36,984 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:33:36,985 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:33:36,985 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:33:36,985 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:33:36,985 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:33:36,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:33:36,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:36,986 INFO L87 Difference]: Start difference. First operand 221 states and 341 transitions. Second operand 3 states. [2018-10-26 21:33:37,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:37,253 INFO L93 Difference]: Finished difference Result 395 states and 619 transitions. [2018-10-26 21:33:37,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:33:37,254 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2018-10-26 21:33:37,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:37,255 INFO L225 Difference]: With dead ends: 395 [2018-10-26 21:33:37,256 INFO L226 Difference]: Without dead ends: 223 [2018-10-26 21:33:37,256 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:33:37,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-10-26 21:33:37,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 221. [2018-10-26 21:33:37,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-10-26 21:33:37,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 339 transitions. [2018-10-26 21:33:37,269 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 339 transitions. Word has length 40 [2018-10-26 21:33:37,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:37,269 INFO L481 AbstractCegarLoop]: Abstraction has 221 states and 339 transitions. [2018-10-26 21:33:37,269 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:33:37,269 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 339 transitions. [2018-10-26 21:33:37,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-26 21:33:37,272 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:37,272 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:37,273 INFO L424 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:37,273 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:37,273 INFO L82 PathProgramCache]: Analyzing trace with hash 937434793, now seen corresponding path program 1 times [2018-10-26 21:33:37,273 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:37,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:37,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:37,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:37,276 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:37,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:37,900 WARN L179 SmtUtils]: Spent 255.00 ms on a formula simplification. DAG size of input: 12 DAG size of output: 11 [2018-10-26 21:33:38,560 WARN L179 SmtUtils]: Spent 571.00 ms on a formula simplification. DAG size of input: 27 DAG size of output: 16 [2018-10-26 21:33:38,565 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 14 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-10-26 21:33:38,565 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:38,565 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:33:38,565 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 42 with the following transitions: [2018-10-26 21:33:38,565 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [335], [338], [341], [526], [529], [530], [531] [2018-10-26 21:33:38,568 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:33:38,569 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:33:39,013 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:33:45,377 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:33:45,378 INFO L272 AbstractInterpreter]: Visited 31 different actions 145 times. Merged at 24 different actions 96 times. Widened at 2 different actions 4 times. Found 17 fixpoints after 6 different actions. Largest state had 41 variables. [2018-10-26 21:33:45,387 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:45,387 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:33:45,387 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:45,387 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:33:45,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:45,395 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:33:45,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:45,450 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:33:45,558 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:33:45,558 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:33:46,136 WARN L179 SmtUtils]: Spent 319.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 6 [2018-10-26 21:33:46,363 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:33:46,391 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:33:46,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10 [2018-10-26 21:33:46,391 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:33:46,392 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 21:33:46,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 21:33:46,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2018-10-26 21:33:46,392 INFO L87 Difference]: Start difference. First operand 221 states and 339 transitions. Second operand 7 states. [2018-10-26 21:33:47,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:47,683 INFO L93 Difference]: Finished difference Result 474 states and 733 transitions. [2018-10-26 21:33:47,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 21:33:47,687 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 41 [2018-10-26 21:33:47,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:47,689 INFO L225 Difference]: With dead ends: 474 [2018-10-26 21:33:47,689 INFO L226 Difference]: Without dead ends: 292 [2018-10-26 21:33:47,689 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 80 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2018-10-26 21:33:47,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2018-10-26 21:33:47,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 272. [2018-10-26 21:33:47,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2018-10-26 21:33:47,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 419 transitions. [2018-10-26 21:33:47,704 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 419 transitions. Word has length 41 [2018-10-26 21:33:47,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:47,705 INFO L481 AbstractCegarLoop]: Abstraction has 272 states and 419 transitions. [2018-10-26 21:33:47,705 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 21:33:47,705 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 419 transitions. [2018-10-26 21:33:47,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:33:47,705 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:47,705 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:47,705 INFO L424 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:47,706 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:47,706 INFO L82 PathProgramCache]: Analyzing trace with hash -992845957, now seen corresponding path program 1 times [2018-10-26 21:33:47,706 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:47,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:47,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:47,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:47,709 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:47,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:47,804 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:33:47,804 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:47,805 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:33:47,805 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 43 with the following transitions: [2018-10-26 21:33:47,805 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [350], [353], [356], [526], [529], [530], [531] [2018-10-26 21:33:47,806 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:33:47,807 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:33:48,043 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:33:52,452 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:33:52,452 INFO L272 AbstractInterpreter]: Visited 32 different actions 147 times. Merged at 25 different actions 95 times. Widened at 2 different actions 4 times. Found 17 fixpoints after 6 different actions. Largest state had 42 variables. [2018-10-26 21:33:52,459 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:52,459 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:33:52,459 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:52,459 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:33:52,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:52,476 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:33:52,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:52,532 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:33:52,673 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:33:52,673 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:33:52,732 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:33:52,753 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:33:52,753 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 4 [2018-10-26 21:33:52,753 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:33:52,753 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 21:33:52,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 21:33:52,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 21:33:52,754 INFO L87 Difference]: Start difference. First operand 272 states and 419 transitions. Second operand 4 states. [2018-10-26 21:33:53,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:33:53,098 INFO L93 Difference]: Finished difference Result 446 states and 695 transitions. [2018-10-26 21:33:53,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 21:33:53,098 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 42 [2018-10-26 21:33:53,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:33:53,099 INFO L225 Difference]: With dead ends: 446 [2018-10-26 21:33:53,099 INFO L226 Difference]: Without dead ends: 424 [2018-10-26 21:33:53,100 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 81 SyntacticMatches, 5 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 21:33:53,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states. [2018-10-26 21:33:53,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 422. [2018-10-26 21:33:53,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 422 states. [2018-10-26 21:33:53,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 636 transitions. [2018-10-26 21:33:53,117 INFO L78 Accepts]: Start accepts. Automaton has 422 states and 636 transitions. Word has length 42 [2018-10-26 21:33:53,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:33:53,117 INFO L481 AbstractCegarLoop]: Abstraction has 422 states and 636 transitions. [2018-10-26 21:33:53,117 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 21:33:53,117 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 636 transitions. [2018-10-26 21:33:53,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:33:53,118 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:33:53,118 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:33:53,118 INFO L424 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:33:53,118 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:53,118 INFO L82 PathProgramCache]: Analyzing trace with hash -275920596, now seen corresponding path program 1 times [2018-10-26 21:33:53,122 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:33:53,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:53,123 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:53,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:33:53,124 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:33:53,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:53,363 WARN L179 SmtUtils]: Spent 102.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:33:53,539 WARN L179 SmtUtils]: Spent 127.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-10-26 21:33:53,627 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:33:53,628 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:53,628 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:33:53,628 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 45 with the following transitions: [2018-10-26 21:33:53,628 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [386], [526], [529], [530], [531] [2018-10-26 21:33:53,630 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:33:53,630 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:33:53,916 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:33:59,851 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:33:59,851 INFO L272 AbstractInterpreter]: Visited 34 different actions 157 times. Merged at 27 different actions 105 times. Widened at 2 different actions 4 times. Found 17 fixpoints after 6 different actions. Largest state had 44 variables. [2018-10-26 21:33:59,863 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:33:59,863 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:33:59,863 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:33:59,863 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:33:59,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:33:59,870 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:33:59,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:33:59,913 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:34:00,026 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:34:00,026 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:34:00,231 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:34:00,251 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:34:00,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2018-10-26 21:34:00,252 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:34:00,252 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 21:34:00,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 21:34:00,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 21:34:00,252 INFO L87 Difference]: Start difference. First operand 422 states and 636 transitions. Second operand 5 states. [2018-10-26 21:34:00,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:34:00,936 INFO L93 Difference]: Finished difference Result 431 states and 643 transitions. [2018-10-26 21:34:00,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 21:34:00,939 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 44 [2018-10-26 21:34:00,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:34:00,941 INFO L225 Difference]: With dead ends: 431 [2018-10-26 21:34:00,941 INFO L226 Difference]: Without dead ends: 429 [2018-10-26 21:34:00,942 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 84 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-26 21:34:00,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states. [2018-10-26 21:34:00,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 423. [2018-10-26 21:34:00,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 423 states. [2018-10-26 21:34:00,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423 states to 423 states and 637 transitions. [2018-10-26 21:34:00,965 INFO L78 Accepts]: Start accepts. Automaton has 423 states and 637 transitions. Word has length 44 [2018-10-26 21:34:00,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:34:00,966 INFO L481 AbstractCegarLoop]: Abstraction has 423 states and 637 transitions. [2018-10-26 21:34:00,967 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 21:34:00,967 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 637 transitions. [2018-10-26 21:34:00,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:34:00,967 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:34:00,967 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:34:00,968 INFO L424 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:34:00,968 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:00,968 INFO L82 PathProgramCache]: Analyzing trace with hash 161633879, now seen corresponding path program 1 times [2018-10-26 21:34:00,968 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:34:00,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:00,969 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:00,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:00,969 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:34:00,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:01,072 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:34:01,072 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:34:01,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:34:01,073 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:34:01,073 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:34:01,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:34:01,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:34:01,073 INFO L87 Difference]: Start difference. First operand 423 states and 637 transitions. Second operand 3 states. [2018-10-26 21:34:01,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:34:01,110 INFO L93 Difference]: Finished difference Result 795 states and 1193 transitions. [2018-10-26 21:34:01,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:34:01,115 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-10-26 21:34:01,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:34:01,117 INFO L225 Difference]: With dead ends: 795 [2018-10-26 21:34:01,117 INFO L226 Difference]: Without dead ends: 421 [2018-10-26 21:34:01,119 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:34:01,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 421 states. [2018-10-26 21:34:01,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 421 to 399. [2018-10-26 21:34:01,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 399 states. [2018-10-26 21:34:01,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 584 transitions. [2018-10-26 21:34:01,138 INFO L78 Accepts]: Start accepts. Automaton has 399 states and 584 transitions. Word has length 45 [2018-10-26 21:34:01,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:34:01,138 INFO L481 AbstractCegarLoop]: Abstraction has 399 states and 584 transitions. [2018-10-26 21:34:01,138 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:34:01,138 INFO L276 IsEmpty]: Start isEmpty. Operand 399 states and 584 transitions. [2018-10-26 21:34:01,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:34:01,141 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:34:01,141 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:34:01,141 INFO L424 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:34:01,141 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:01,141 INFO L82 PathProgramCache]: Analyzing trace with hash 1614817955, now seen corresponding path program 1 times [2018-10-26 21:34:01,141 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:34:01,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:01,142 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:01,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:01,142 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:34:01,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:01,245 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-10-26 21:34:01,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 21:34:01,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-26 21:34:01,245 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:34:01,246 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-26 21:34:01,246 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-26 21:34:01,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:34:01,246 INFO L87 Difference]: Start difference. First operand 399 states and 584 transitions. Second operand 3 states. [2018-10-26 21:34:01,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:34:01,529 INFO L93 Difference]: Finished difference Result 555 states and 812 transitions. [2018-10-26 21:34:01,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-26 21:34:01,530 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2018-10-26 21:34:01,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:34:01,531 INFO L225 Difference]: With dead ends: 555 [2018-10-26 21:34:01,531 INFO L226 Difference]: Without dead ends: 225 [2018-10-26 21:34:01,532 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-26 21:34:01,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-10-26 21:34:01,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 223. [2018-10-26 21:34:01,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-10-26 21:34:01,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 316 transitions. [2018-10-26 21:34:01,548 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 316 transitions. Word has length 55 [2018-10-26 21:34:01,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:34:01,548 INFO L481 AbstractCegarLoop]: Abstraction has 223 states and 316 transitions. [2018-10-26 21:34:01,548 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-26 21:34:01,548 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 316 transitions. [2018-10-26 21:34:01,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:34:01,549 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:34:01,549 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:34:01,549 INFO L424 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:34:01,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:01,549 INFO L82 PathProgramCache]: Analyzing trace with hash 1860919614, now seen corresponding path program 1 times [2018-10-26 21:34:01,550 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:34:01,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:01,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:01,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:01,555 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:34:01,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:01,817 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:34:01,818 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:01,818 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:34:01,818 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 57 with the following transitions: [2018-10-26 21:34:01,818 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [18], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [446], [449], [452], [526], [529], [530], [531] [2018-10-26 21:34:01,822 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:34:01,822 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:34:02,168 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:34:11,582 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:34:11,585 INFO L272 AbstractInterpreter]: Visited 41 different actions 233 times. Merged at 33 different actions 152 times. Widened at 3 different actions 6 times. Found 27 fixpoints after 8 different actions. Largest state had 46 variables. [2018-10-26 21:34:11,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:11,623 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:34:11,623 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:11,623 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 21:34:11,639 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:11,639 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:34:11,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:11,698 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:34:11,710 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:34:11,710 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:34:12,223 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:34:12,252 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:34:12,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2018-10-26 21:34:12,253 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:34:12,253 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 21:34:12,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 21:34:12,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-10-26 21:34:12,253 INFO L87 Difference]: Start difference. First operand 223 states and 316 transitions. Second operand 5 states. [2018-10-26 21:34:13,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:34:13,679 INFO L93 Difference]: Finished difference Result 597 states and 858 transitions. [2018-10-26 21:34:13,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 21:34:13,680 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-10-26 21:34:13,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:34:13,682 INFO L225 Difference]: With dead ends: 597 [2018-10-26 21:34:13,682 INFO L226 Difference]: Without dead ends: 442 [2018-10-26 21:34:13,683 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-10-26 21:34:13,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2018-10-26 21:34:13,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 326. [2018-10-26 21:34:13,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-10-26 21:34:13,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 472 transitions. [2018-10-26 21:34:13,702 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 472 transitions. Word has length 56 [2018-10-26 21:34:13,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:34:13,702 INFO L481 AbstractCegarLoop]: Abstraction has 326 states and 472 transitions. [2018-10-26 21:34:13,702 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 21:34:13,702 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 472 transitions. [2018-10-26 21:34:13,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:34:13,705 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:34:13,705 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:34:13,705 INFO L424 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:34:13,705 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:13,705 INFO L82 PathProgramCache]: Analyzing trace with hash 2119085052, now seen corresponding path program 1 times [2018-10-26 21:34:13,705 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:34:13,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:13,708 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:13,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:13,708 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:34:13,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:14,155 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:34:14,155 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:14,155 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:34:14,155 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 57 with the following transitions: [2018-10-26 21:34:14,156 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [446], [449], [452], [526], [529], [530], [531] [2018-10-26 21:34:14,157 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:34:14,157 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:34:14,570 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:34:23,618 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:34:23,618 INFO L272 AbstractInterpreter]: Visited 40 different actions 222 times. Merged at 33 different actions 152 times. Widened at 3 different actions 6 times. Found 27 fixpoints after 8 different actions. Largest state had 46 variables. [2018-10-26 21:34:23,627 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:23,627 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:34:23,627 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:23,627 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:34:23,635 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:23,635 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:34:23,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:23,690 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:34:23,755 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:34:23,755 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:34:23,794 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 21 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:34:23,814 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:34:23,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 4] total 7 [2018-10-26 21:34:23,814 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:34:23,814 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 21:34:23,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 21:34:23,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-10-26 21:34:23,815 INFO L87 Difference]: Start difference. First operand 326 states and 472 transitions. Second operand 5 states. [2018-10-26 21:34:23,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:34:23,920 INFO L93 Difference]: Finished difference Result 373 states and 538 transitions. [2018-10-26 21:34:23,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 21:34:23,921 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-10-26 21:34:23,921 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:34:23,922 INFO L225 Difference]: With dead ends: 373 [2018-10-26 21:34:23,922 INFO L226 Difference]: Without dead ends: 367 [2018-10-26 21:34:23,923 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-10-26 21:34:23,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2018-10-26 21:34:23,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 364. [2018-10-26 21:34:23,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2018-10-26 21:34:23,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 526 transitions. [2018-10-26 21:34:23,938 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 526 transitions. Word has length 56 [2018-10-26 21:34:23,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:34:23,938 INFO L481 AbstractCegarLoop]: Abstraction has 364 states and 526 transitions. [2018-10-26 21:34:23,938 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 21:34:23,938 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 526 transitions. [2018-10-26 21:34:23,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-10-26 21:34:23,941 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:34:23,941 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:34:23,941 INFO L424 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:34:23,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:23,942 INFO L82 PathProgramCache]: Analyzing trace with hash 807144158, now seen corresponding path program 1 times [2018-10-26 21:34:23,942 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:34:23,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:23,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:23,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:23,943 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:34:23,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:24,155 WARN L179 SmtUtils]: Spent 123.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:34:24,307 WARN L179 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:34:24,495 WARN L179 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 7 [2018-10-26 21:34:24,624 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:34:24,624 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:24,624 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:34:24,624 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 61 with the following transitions: [2018-10-26 21:34:24,625 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [512], [526], [529], [530], [531] [2018-10-26 21:34:24,626 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:34:24,628 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:34:24,850 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:34:33,018 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:34:33,018 INFO L272 AbstractInterpreter]: Visited 44 different actions 243 times. Merged at 37 different actions 170 times. Widened at 3 different actions 6 times. Found 27 fixpoints after 8 different actions. Largest state had 50 variables. [2018-10-26 21:34:33,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:33,035 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:34:33,035 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:33,035 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:34:33,043 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:33,043 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:34:33,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:33,082 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:34:33,164 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:34:33,165 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:34:33,339 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:34:33,356 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:34:33,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 14 [2018-10-26 21:34:33,356 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:34:33,357 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 21:34:33,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 21:34:33,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=145, Unknown=0, NotChecked=0, Total=182 [2018-10-26 21:34:33,357 INFO L87 Difference]: Start difference. First operand 364 states and 526 transitions. Second operand 10 states. [2018-10-26 21:34:33,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:34:33,577 INFO L93 Difference]: Finished difference Result 367 states and 528 transitions. [2018-10-26 21:34:33,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 21:34:33,578 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 60 [2018-10-26 21:34:33,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:34:33,580 INFO L225 Difference]: With dead ends: 367 [2018-10-26 21:34:33,580 INFO L226 Difference]: Without dead ends: 365 [2018-10-26 21:34:33,580 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 113 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=43, Invalid=167, Unknown=0, NotChecked=0, Total=210 [2018-10-26 21:34:33,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 365 states. [2018-10-26 21:34:33,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 365 to 364. [2018-10-26 21:34:33,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2018-10-26 21:34:33,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 525 transitions. [2018-10-26 21:34:33,597 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 525 transitions. Word has length 60 [2018-10-26 21:34:33,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:34:33,597 INFO L481 AbstractCegarLoop]: Abstraction has 364 states and 525 transitions. [2018-10-26 21:34:33,598 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 21:34:33,598 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 525 transitions. [2018-10-26 21:34:33,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-10-26 21:34:33,598 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:34:33,598 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:34:33,598 INFO L424 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:34:33,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:34:33,602 INFO L82 PathProgramCache]: Analyzing trace with hash -743255307, now seen corresponding path program 1 times [2018-10-26 21:34:33,602 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:34:33,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:33,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:34:33,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:34:33,603 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:34:33,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:34:33,822 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:34:33,822 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:34:33,822 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:34:33,822 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 68 with the following transitions: [2018-10-26 21:34:33,823 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [54], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:34:33,825 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:34:33,827 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:34:34,079 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:35:08,941 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:35:08,941 INFO L272 AbstractInterpreter]: Visited 45 different actions 781 times. Merged at 38 different actions 630 times. Widened at 5 different actions 41 times. Found 105 fixpoints after 14 different actions. Largest state had 50 variables. [2018-10-26 21:35:08,951 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:35:08,951 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:35:08,951 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:35:08,951 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:35:08,961 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:35:08,961 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:35:09,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:35:09,007 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:35:09,149 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:35:09,149 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:35:09,640 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 44 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:35:09,664 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:35:09,664 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7] total 14 [2018-10-26 21:35:09,664 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:35:09,664 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 21:35:09,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 21:35:09,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=145, Unknown=0, NotChecked=0, Total=182 [2018-10-26 21:35:09,665 INFO L87 Difference]: Start difference. First operand 364 states and 525 transitions. Second operand 9 states. [2018-10-26 21:35:09,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:35:09,982 INFO L93 Difference]: Finished difference Result 368 states and 529 transitions. [2018-10-26 21:35:09,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 21:35:09,983 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 67 [2018-10-26 21:35:09,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:35:09,984 INFO L225 Difference]: With dead ends: 368 [2018-10-26 21:35:09,984 INFO L226 Difference]: Without dead ends: 366 [2018-10-26 21:35:09,985 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 124 SyntacticMatches, 6 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2018-10-26 21:35:09,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-10-26 21:35:10,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 365. [2018-10-26 21:35:10,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 365 states. [2018-10-26 21:35:10,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 365 states to 365 states and 526 transitions. [2018-10-26 21:35:10,001 INFO L78 Accepts]: Start accepts. Automaton has 365 states and 526 transitions. Word has length 67 [2018-10-26 21:35:10,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:35:10,002 INFO L481 AbstractCegarLoop]: Abstraction has 365 states and 526 transitions. [2018-10-26 21:35:10,002 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 21:35:10,002 INFO L276 IsEmpty]: Start isEmpty. Operand 365 states and 526 transitions. [2018-10-26 21:35:10,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-10-26 21:35:10,002 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:35:10,005 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:35:10,006 INFO L424 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:35:10,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:35:10,006 INFO L82 PathProgramCache]: Analyzing trace with hash -1746386041, now seen corresponding path program 1 times [2018-10-26 21:35:10,006 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:35:10,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:35:10,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:35:10,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:35:10,007 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:35:10,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:35:10,411 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:35:10,411 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:35:10,411 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:35:10,412 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 78 with the following transitions: [2018-10-26 21:35:10,412 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [18], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [260], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:35:10,413 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:35:10,413 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:35:10,686 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:35:53,013 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:35:53,013 INFO L272 AbstractInterpreter]: Visited 46 different actions 945 times. Merged at 39 different actions 734 times. Widened at 5 different actions 46 times. Found 128 fixpoints after 16 different actions. Largest state had 50 variables. [2018-10-26 21:35:53,019 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:35:53,019 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:35:53,019 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:35:53,019 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:35:53,026 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:35:53,026 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:35:53,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:35:53,089 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:35:53,094 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:35:53,094 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:35:53,166 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:35:53,182 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:35:53,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2018-10-26 21:35:53,182 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:35:53,183 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-26 21:35:53,183 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-26 21:35:53,183 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-10-26 21:35:53,183 INFO L87 Difference]: Start difference. First operand 365 states and 526 transitions. Second operand 6 states. [2018-10-26 21:35:53,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:35:53,441 INFO L93 Difference]: Finished difference Result 825 states and 1192 transitions. [2018-10-26 21:35:53,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 21:35:53,442 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 77 [2018-10-26 21:35:53,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:35:53,443 INFO L225 Difference]: With dead ends: 825 [2018-10-26 21:35:53,443 INFO L226 Difference]: Without dead ends: 568 [2018-10-26 21:35:53,444 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-10-26 21:35:53,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 568 states. [2018-10-26 21:35:53,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 568 to 446. [2018-10-26 21:35:53,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-10-26 21:35:53,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 649 transitions. [2018-10-26 21:35:53,461 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 649 transitions. Word has length 77 [2018-10-26 21:35:53,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:35:53,462 INFO L481 AbstractCegarLoop]: Abstraction has 446 states and 649 transitions. [2018-10-26 21:35:53,462 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-26 21:35:53,462 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 649 transitions. [2018-10-26 21:35:53,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-10-26 21:35:53,462 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:35:53,462 INFO L375 BasicCegarLoop]: trace histogram [7, 7, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:35:53,463 INFO L424 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:35:53,463 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:35:53,463 INFO L82 PathProgramCache]: Analyzing trace with hash -2139413051, now seen corresponding path program 1 times [2018-10-26 21:35:53,466 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:35:53,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:35:53,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:35:53,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:35:53,467 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:35:53,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:35:53,900 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:35:53,900 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:35:53,900 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:35:53,900 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 78 with the following transitions: [2018-10-26 21:35:53,901 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [260], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:35:53,902 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:35:53,902 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:35:54,174 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:36:26,233 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:36:26,233 INFO L272 AbstractInterpreter]: Visited 45 different actions 785 times. Merged at 38 different actions 632 times. Widened at 5 different actions 42 times. Found 104 fixpoints after 13 different actions. Largest state had 50 variables. [2018-10-26 21:36:26,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:36:26,243 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:36:26,243 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:36:26,243 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:36:26,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:36:26,251 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:36:26,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:36:26,300 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:36:26,362 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 70 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:36:26,362 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:36:26,482 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 35 proven. 43 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:36:26,503 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:36:26,503 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 16 [2018-10-26 21:36:26,503 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:36:26,503 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-26 21:36:26,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-26 21:36:26,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=190, Unknown=0, NotChecked=0, Total=240 [2018-10-26 21:36:26,504 INFO L87 Difference]: Start difference. First operand 446 states and 649 transitions. Second operand 12 states. [2018-10-26 21:36:26,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:36:26,641 INFO L93 Difference]: Finished difference Result 472 states and 685 transitions. [2018-10-26 21:36:26,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 21:36:26,642 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 77 [2018-10-26 21:36:26,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:36:26,643 INFO L225 Difference]: With dead ends: 472 [2018-10-26 21:36:26,643 INFO L226 Difference]: Without dead ends: 468 [2018-10-26 21:36:26,644 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 146 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=57, Invalid=215, Unknown=0, NotChecked=0, Total=272 [2018-10-26 21:36:26,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states. [2018-10-26 21:36:26,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 468. [2018-10-26 21:36:26,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 468 states. [2018-10-26 21:36:26,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 468 states and 679 transitions. [2018-10-26 21:36:26,662 INFO L78 Accepts]: Start accepts. Automaton has 468 states and 679 transitions. Word has length 77 [2018-10-26 21:36:26,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:36:26,662 INFO L481 AbstractCegarLoop]: Abstraction has 468 states and 679 transitions. [2018-10-26 21:36:26,662 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-26 21:36:26,662 INFO L276 IsEmpty]: Start isEmpty. Operand 468 states and 679 transitions. [2018-10-26 21:36:26,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-10-26 21:36:26,666 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:36:26,666 INFO L375 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:36:26,666 INFO L424 AbstractCegarLoop]: === Iteration 20 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:36:26,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:36:26,666 INFO L82 PathProgramCache]: Analyzing trace with hash -1314627048, now seen corresponding path program 1 times [2018-10-26 21:36:26,666 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:36:26,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:36:26,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:36:26,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:36:26,667 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:36:26,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:36:26,920 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 26 proven. 99 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:36:26,920 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:36:26,920 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:36:26,920 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-10-26 21:36:26,920 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [335], [338], [341], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:36:26,922 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:36:26,922 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:36:27,193 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:37:03,522 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:37:03,522 INFO L272 AbstractInterpreter]: Visited 47 different actions 822 times. Merged at 40 different actions 670 times. Widened at 5 different actions 44 times. Found 104 fixpoints after 13 different actions. Largest state had 50 variables. [2018-10-26 21:37:03,531 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:37:03,531 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:37:03,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:37:03,531 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:37:03,539 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:37:03,539 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:37:03,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:37:03,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:37:03,627 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 99 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:37:03,627 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:37:03,925 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 58 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2018-10-26 21:37:03,954 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:37:03,954 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 5] total 12 [2018-10-26 21:37:03,954 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:37:03,954 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 21:37:03,955 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 21:37:03,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-10-26 21:37:03,955 INFO L87 Difference]: Start difference. First operand 468 states and 679 transitions. Second operand 9 states. [2018-10-26 21:37:04,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:37:04,195 INFO L93 Difference]: Finished difference Result 498 states and 717 transitions. [2018-10-26 21:37:04,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 21:37:04,196 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 87 [2018-10-26 21:37:04,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:37:04,198 INFO L225 Difference]: With dead ends: 498 [2018-10-26 21:37:04,198 INFO L226 Difference]: Without dead ends: 494 [2018-10-26 21:37:04,199 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 171 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-10-26 21:37:04,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states. [2018-10-26 21:37:04,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 487. [2018-10-26 21:37:04,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 487 states. [2018-10-26 21:37:04,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 487 states to 487 states and 705 transitions. [2018-10-26 21:37:04,221 INFO L78 Accepts]: Start accepts. Automaton has 487 states and 705 transitions. Word has length 87 [2018-10-26 21:37:04,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:37:04,221 INFO L481 AbstractCegarLoop]: Abstraction has 487 states and 705 transitions. [2018-10-26 21:37:04,221 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 21:37:04,221 INFO L276 IsEmpty]: Start isEmpty. Operand 487 states and 705 transitions. [2018-10-26 21:37:04,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-10-26 21:37:04,222 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:37:04,222 INFO L375 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:37:04,222 INFO L424 AbstractCegarLoop]: === Iteration 21 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:37:04,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:37:04,227 INFO L82 PathProgramCache]: Analyzing trace with hash 233904989, now seen corresponding path program 1 times [2018-10-26 21:37:04,227 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:37:04,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:37:04,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:37:04,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:37:04,228 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:37:04,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:37:04,507 WARN L179 SmtUtils]: Spent 112.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:37:04,685 WARN L179 SmtUtils]: Spent 122.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-10-26 21:37:04,892 WARN L179 SmtUtils]: Spent 128.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:37:05,160 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:37:05,160 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:37:05,160 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:37:05,161 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 91 with the following transitions: [2018-10-26 21:37:05,161 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [386], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:37:05,162 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:37:05,162 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:37:05,564 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:37:43,297 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:37:43,298 INFO L272 AbstractInterpreter]: Visited 45 different actions 786 times. Merged at 38 different actions 636 times. Widened at 5 different actions 44 times. Found 104 fixpoints after 13 different actions. Largest state had 50 variables. [2018-10-26 21:37:43,307 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:37:43,307 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:37:43,307 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:37:43,307 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:37:43,316 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:37:43,316 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:37:43,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:37:43,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:37:43,526 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 110 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:37:43,526 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:37:45,049 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 67 proven. 64 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:37:45,088 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:37:45,088 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8] total 20 [2018-10-26 21:37:45,088 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:37:45,088 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-10-26 21:37:45,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-10-26 21:37:45,089 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=308, Unknown=1, NotChecked=0, Total=380 [2018-10-26 21:37:45,089 INFO L87 Difference]: Start difference. First operand 487 states and 705 transitions. Second operand 14 states. [2018-10-26 21:37:45,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:37:45,825 INFO L93 Difference]: Finished difference Result 492 states and 710 transitions. [2018-10-26 21:37:45,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 21:37:45,826 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 90 [2018-10-26 21:37:45,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:37:45,828 INFO L225 Difference]: With dead ends: 492 [2018-10-26 21:37:45,828 INFO L226 Difference]: Without dead ends: 490 [2018-10-26 21:37:45,829 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 170 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=92, Invalid=413, Unknown=1, NotChecked=0, Total=506 [2018-10-26 21:37:45,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2018-10-26 21:37:45,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 488. [2018-10-26 21:37:45,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 488 states. [2018-10-26 21:37:45,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 488 states to 488 states and 706 transitions. [2018-10-26 21:37:45,849 INFO L78 Accepts]: Start accepts. Automaton has 488 states and 706 transitions. Word has length 90 [2018-10-26 21:37:45,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:37:45,849 INFO L481 AbstractCegarLoop]: Abstraction has 488 states and 706 transitions. [2018-10-26 21:37:45,849 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-10-26 21:37:45,849 INFO L276 IsEmpty]: Start isEmpty. Operand 488 states and 706 transitions. [2018-10-26 21:37:45,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-10-26 21:37:45,853 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:37:45,853 INFO L375 BasicCegarLoop]: trace histogram [9, 8, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:37:45,853 INFO L424 AbstractCegarLoop]: === Iteration 22 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:37:45,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:37:45,853 INFO L82 PathProgramCache]: Analyzing trace with hash -1342705169, now seen corresponding path program 1 times [2018-10-26 21:37:45,853 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:37:45,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:37:45,854 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:37:45,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:37:45,854 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:37:45,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:37:46,170 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:37:46,171 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:37:46,171 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:37:46,171 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 103 with the following transitions: [2018-10-26 21:37:46,171 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [18], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [446], [449], [452], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:37:46,173 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:37:46,173 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:37:46,462 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:38:28,513 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:38:28,513 INFO L272 AbstractInterpreter]: Visited 48 different actions 980 times. Merged at 41 different actions 770 times. Widened at 5 different actions 46 times. Found 127 fixpoints after 16 different actions. Largest state had 50 variables. [2018-10-26 21:38:28,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:38:28,523 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:38:28,524 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:38:28,524 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:38:28,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:38:28,531 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:38:28,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:38:28,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:38:28,615 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:38:28,615 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:38:28,709 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:38:28,727 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:38:28,728 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2018-10-26 21:38:28,728 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:38:28,728 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 21:38:28,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 21:38:28,728 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 21:38:28,729 INFO L87 Difference]: Start difference. First operand 488 states and 706 transitions. Second operand 7 states. [2018-10-26 21:38:28,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:38:28,877 INFO L93 Difference]: Finished difference Result 1039 states and 1504 transitions. [2018-10-26 21:38:28,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 21:38:28,880 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-10-26 21:38:28,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:38:28,882 INFO L225 Difference]: With dead ends: 1039 [2018-10-26 21:38:28,882 INFO L226 Difference]: Without dead ends: 701 [2018-10-26 21:38:28,883 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 203 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 21:38:28,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states. [2018-10-26 21:38:28,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 569. [2018-10-26 21:38:28,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. [2018-10-26 21:38:28,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 829 transitions. [2018-10-26 21:38:28,906 INFO L78 Accepts]: Start accepts. Automaton has 569 states and 829 transitions. Word has length 102 [2018-10-26 21:38:28,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:38:28,908 INFO L481 AbstractCegarLoop]: Abstraction has 569 states and 829 transitions. [2018-10-26 21:38:28,908 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 21:38:28,908 INFO L276 IsEmpty]: Start isEmpty. Operand 569 states and 829 transitions. [2018-10-26 21:38:28,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-10-26 21:38:28,910 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:38:28,910 INFO L375 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:38:28,910 INFO L424 AbstractCegarLoop]: === Iteration 23 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:38:28,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:38:28,910 INFO L82 PathProgramCache]: Analyzing trace with hash -1084539731, now seen corresponding path program 1 times [2018-10-26 21:38:28,911 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:38:28,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:38:28,911 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:38:28,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:38:28,911 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:38:28,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:38:29,058 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:38:29,059 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:38:29,059 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:38:29,059 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 103 with the following transitions: [2018-10-26 21:38:29,059 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [446], [449], [452], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:38:29,061 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:38:29,061 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:38:29,308 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:38:57,197 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:38:57,197 INFO L272 AbstractInterpreter]: Visited 47 different actions 813 times. Merged at 40 different actions 660 times. Widened at 5 different actions 41 times. Found 104 fixpoints after 13 different actions. Largest state had 50 variables. [2018-10-26 21:38:57,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:38:57,207 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:38:57,207 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:38:57,207 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:38:57,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:38:57,217 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:38:57,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:38:57,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:38:57,300 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:38:57,300 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:38:57,383 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 84 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-10-26 21:38:57,404 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:38:57,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 4] total 9 [2018-10-26 21:38:57,405 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:38:57,405 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-26 21:38:57,405 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-26 21:38:57,405 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-10-26 21:38:57,406 INFO L87 Difference]: Start difference. First operand 569 states and 829 transitions. Second operand 7 states. [2018-10-26 21:38:57,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:38:57,512 INFO L93 Difference]: Finished difference Result 616 states and 895 transitions. [2018-10-26 21:38:57,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-26 21:38:57,513 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-10-26 21:38:57,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:38:57,515 INFO L225 Difference]: With dead ends: 616 [2018-10-26 21:38:57,515 INFO L226 Difference]: Without dead ends: 610 [2018-10-26 21:38:57,515 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 205 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-10-26 21:38:57,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610 states. [2018-10-26 21:38:57,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610 to 607. [2018-10-26 21:38:57,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 607 states. [2018-10-26 21:38:57,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 607 states to 607 states and 883 transitions. [2018-10-26 21:38:57,537 INFO L78 Accepts]: Start accepts. Automaton has 607 states and 883 transitions. Word has length 102 [2018-10-26 21:38:57,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:38:57,538 INFO L481 AbstractCegarLoop]: Abstraction has 607 states and 883 transitions. [2018-10-26 21:38:57,538 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-26 21:38:57,538 INFO L276 IsEmpty]: Start isEmpty. Operand 607 states and 883 transitions. [2018-10-26 21:38:57,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-10-26 21:38:57,542 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:38:57,542 INFO L375 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:38:57,543 INFO L424 AbstractCegarLoop]: === Iteration 24 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:38:57,543 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:38:57,543 INFO L82 PathProgramCache]: Analyzing trace with hash 35576591, now seen corresponding path program 1 times [2018-10-26 21:38:57,543 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:38:57,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:38:57,544 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:38:57,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:38:57,544 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:38:57,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:38:57,791 WARN L179 SmtUtils]: Spent 108.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:38:57,951 WARN L179 SmtUtils]: Spent 108.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-10-26 21:38:58,128 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 170 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:38:58,128 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:38:58,128 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:38:58,128 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 107 with the following transitions: [2018-10-26 21:38:58,129 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [512], [514], [526], [529], [530], [531] [2018-10-26 21:38:58,130 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:38:58,130 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:38:58,370 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:39:30,383 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:39:30,384 INFO L272 AbstractInterpreter]: Visited 45 different actions 782 times. Merged at 38 different actions 632 times. Widened at 5 different actions 42 times. Found 104 fixpoints after 13 different actions. Largest state had 50 variables. [2018-10-26 21:39:30,391 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:39:30,391 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:39:30,391 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:39:30,391 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:39:30,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:39:30,399 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:39:30,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:39:30,464 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:39:30,546 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 160 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:39:30,546 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:39:30,752 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 94 proven. 90 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:39:30,775 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:39:30,775 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9, 9] total 22 [2018-10-26 21:39:30,775 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:39:30,775 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-10-26 21:39:30,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-10-26 21:39:30,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=381, Unknown=0, NotChecked=0, Total=462 [2018-10-26 21:39:30,776 INFO L87 Difference]: Start difference. First operand 607 states and 883 transitions. Second operand 15 states. [2018-10-26 21:39:31,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:39:31,137 INFO L93 Difference]: Finished difference Result 610 states and 885 transitions. [2018-10-26 21:39:31,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-26 21:39:31,138 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 106 [2018-10-26 21:39:31,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:39:31,140 INFO L225 Difference]: With dead ends: 610 [2018-10-26 21:39:31,140 INFO L226 Difference]: Without dead ends: 608 [2018-10-26 21:39:31,141 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 225 GetRequests, 201 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=96, Invalid=456, Unknown=0, NotChecked=0, Total=552 [2018-10-26 21:39:31,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 608 states. [2018-10-26 21:39:31,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 608 to 607. [2018-10-26 21:39:31,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 607 states. [2018-10-26 21:39:31,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 607 states to 607 states and 882 transitions. [2018-10-26 21:39:31,165 INFO L78 Accepts]: Start accepts. Automaton has 607 states and 882 transitions. Word has length 106 [2018-10-26 21:39:31,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:39:31,165 INFO L481 AbstractCegarLoop]: Abstraction has 607 states and 882 transitions. [2018-10-26 21:39:31,165 INFO L482 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-10-26 21:39:31,165 INFO L276 IsEmpty]: Start isEmpty. Operand 607 states and 882 transitions. [2018-10-26 21:39:31,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-10-26 21:39:31,166 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:39:31,170 INFO L375 BasicCegarLoop]: trace histogram [10, 10, 9, 6, 6, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:39:31,171 INFO L424 AbstractCegarLoop]: === Iteration 25 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:39:31,171 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:39:31,171 INFO L82 PathProgramCache]: Analyzing trace with hash -234907228, now seen corresponding path program 2 times [2018-10-26 21:39:31,171 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:39:31,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:39:31,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:39:31,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:39:31,172 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:39:31,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:39:31,613 WARN L179 SmtUtils]: Spent 116.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-10-26 21:39:31,755 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 208 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:39:31,755 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:39:31,756 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:39:31,756 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:39:31,756 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:39:31,756 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:39:31,756 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:39:31,766 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 21:39:31,766 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 21:39:31,822 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-10-26 21:39:31,822 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:39:31,825 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:39:32,160 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 140 proven. 31 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2018-10-26 21:39:32,160 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:39:32,369 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 139 proven. 32 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2018-10-26 21:39:32,390 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:39:32,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 19 [2018-10-26 21:39:32,390 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:39:32,390 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-10-26 21:39:32,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-10-26 21:39:32,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=290, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:39:32,391 INFO L87 Difference]: Start difference. First operand 607 states and 882 transitions. Second operand 18 states. [2018-10-26 21:39:33,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:39:33,488 INFO L93 Difference]: Finished difference Result 1001 states and 1436 transitions. [2018-10-26 21:39:33,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-10-26 21:39:33,489 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 113 [2018-10-26 21:39:33,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:39:33,491 INFO L225 Difference]: With dead ends: 1001 [2018-10-26 21:39:33,491 INFO L226 Difference]: Without dead ends: 574 [2018-10-26 21:39:33,492 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 229 SyntacticMatches, 5 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=180, Invalid=1460, Unknown=0, NotChecked=0, Total=1640 [2018-10-26 21:39:33,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states. [2018-10-26 21:39:33,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 509. [2018-10-26 21:39:33,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 509 states. [2018-10-26 21:39:33,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 509 states to 509 states and 710 transitions. [2018-10-26 21:39:33,508 INFO L78 Accepts]: Start accepts. Automaton has 509 states and 710 transitions. Word has length 113 [2018-10-26 21:39:33,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:39:33,508 INFO L481 AbstractCegarLoop]: Abstraction has 509 states and 710 transitions. [2018-10-26 21:39:33,508 INFO L482 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-10-26 21:39:33,508 INFO L276 IsEmpty]: Start isEmpty. Operand 509 states and 710 transitions. [2018-10-26 21:39:33,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-10-26 21:39:33,509 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:39:33,510 INFO L375 BasicCegarLoop]: trace histogram [11, 10, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:39:33,510 INFO L424 AbstractCegarLoop]: === Iteration 26 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:39:33,510 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:39:33,510 INFO L82 PathProgramCache]: Analyzing trace with hash -238306442, now seen corresponding path program 2 times [2018-10-26 21:39:33,510 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:39:33,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:39:33,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:39:33,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:39:33,511 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:39:33,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:39:34,031 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:39:34,031 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:39:34,031 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:39:34,031 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:39:34,032 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:39:34,032 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:39:34,032 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:39:34,043 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 21:39:34,043 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 21:39:34,138 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-10-26 21:39:34,138 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:39:34,142 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:39:34,158 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:39:34,158 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:39:34,221 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:39:34,242 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:39:34,242 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 14 [2018-10-26 21:39:34,242 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:39:34,243 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 21:39:34,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 21:39:34,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-10-26 21:39:34,243 INFO L87 Difference]: Start difference. First operand 509 states and 710 transitions. Second operand 8 states. [2018-10-26 21:39:34,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:39:34,343 INFO L93 Difference]: Finished difference Result 698 states and 965 transitions. [2018-10-26 21:39:34,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-26 21:39:34,345 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 123 [2018-10-26 21:39:34,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:39:34,347 INFO L225 Difference]: With dead ends: 698 [2018-10-26 21:39:34,347 INFO L226 Difference]: Without dead ends: 610 [2018-10-26 21:39:34,347 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-10-26 21:39:34,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610 states. [2018-10-26 21:39:34,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610 to 548. [2018-10-26 21:39:34,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 548 states. [2018-10-26 21:39:34,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 548 states to 548 states and 766 transitions. [2018-10-26 21:39:34,364 INFO L78 Accepts]: Start accepts. Automaton has 548 states and 766 transitions. Word has length 123 [2018-10-26 21:39:34,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:39:34,364 INFO L481 AbstractCegarLoop]: Abstraction has 548 states and 766 transitions. [2018-10-26 21:39:34,364 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 21:39:34,364 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 766 transitions. [2018-10-26 21:39:34,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2018-10-26 21:39:34,366 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:39:34,366 INFO L375 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:39:34,366 INFO L424 AbstractCegarLoop]: === Iteration 27 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:39:34,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:39:34,366 INFO L82 PathProgramCache]: Analyzing trace with hash 564488152, now seen corresponding path program 1 times [2018-10-26 21:39:34,366 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:39:34,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:39:34,367 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:39:34,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:39:34,367 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:39:34,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:39:34,714 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 36 proven. 302 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-10-26 21:39:34,714 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:39:34,715 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:39:34,715 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 136 with the following transitions: [2018-10-26 21:39:34,715 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [365], [368], [371], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:39:34,716 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:39:34,717 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:39:35,007 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:40:12,985 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:40:12,985 INFO L272 AbstractInterpreter]: Visited 47 different actions 822 times. Merged at 40 different actions 670 times. Widened at 5 different actions 44 times. Found 104 fixpoints after 13 different actions. Largest state had 50 variables. [2018-10-26 21:40:12,999 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:12,999 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:40:12,999 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:12,999 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:13,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:40:13,009 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:40:13,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:13,088 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:13,152 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 335 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-10-26 21:40:13,152 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:40:13,415 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 277 proven. 64 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:40:13,437 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-10-26 21:40:13,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [9, 9] total 21 [2018-10-26 21:40:13,437 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 21:40:13,437 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 21:40:13,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 21:40:13,438 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=158, Invalid=262, Unknown=0, NotChecked=0, Total=420 [2018-10-26 21:40:13,438 INFO L87 Difference]: Start difference. First operand 548 states and 766 transitions. Second operand 8 states. [2018-10-26 21:40:13,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:40:13,526 INFO L93 Difference]: Finished difference Result 658 states and 916 transitions. [2018-10-26 21:40:13,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-26 21:40:13,527 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 135 [2018-10-26 21:40:13,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:40:13,529 INFO L225 Difference]: With dead ends: 658 [2018-10-26 21:40:13,529 INFO L226 Difference]: Without dead ends: 654 [2018-10-26 21:40:13,530 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 285 GetRequests, 262 SyntacticMatches, 4 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=158, Invalid=262, Unknown=0, NotChecked=0, Total=420 [2018-10-26 21:40:13,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-10-26 21:40:13,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 650. [2018-10-26 21:40:13,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 650 states. [2018-10-26 21:40:13,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 650 states to 650 states and 909 transitions. [2018-10-26 21:40:13,558 INFO L78 Accepts]: Start accepts. Automaton has 650 states and 909 transitions. Word has length 135 [2018-10-26 21:40:13,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:40:13,558 INFO L481 AbstractCegarLoop]: Abstraction has 650 states and 909 transitions. [2018-10-26 21:40:13,561 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 21:40:13,561 INFO L276 IsEmpty]: Start isEmpty. Operand 650 states and 909 transitions. [2018-10-26 21:40:13,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-10-26 21:40:13,562 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:40:13,563 INFO L375 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:40:13,563 INFO L424 AbstractCegarLoop]: === Iteration 28 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:40:13,563 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:13,563 INFO L82 PathProgramCache]: Analyzing trace with hash 330710990, now seen corresponding path program 2 times [2018-10-26 21:40:13,563 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:40:13,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:13,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:40:13,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:13,564 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:40:13,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:14,025 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:40:14,026 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:14,026 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:40:14,026 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:40:14,026 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:40:14,026 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:14,026 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:14,035 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 21:40:14,035 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 21:40:14,218 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-10-26 21:40:14,219 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:40:14,222 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:14,527 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 314 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:40:14,527 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:40:14,847 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 191 proven. 156 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:40:14,865 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:40:14,865 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 10, 10] total 28 [2018-10-26 21:40:14,865 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:40:14,865 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-10-26 21:40:14,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-10-26 21:40:14,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-10-26 21:40:14,866 INFO L87 Difference]: Start difference. First operand 650 states and 909 transitions. Second operand 20 states. [2018-10-26 21:40:15,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:40:15,766 INFO L93 Difference]: Finished difference Result 728 states and 1001 transitions. [2018-10-26 21:40:15,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-10-26 21:40:15,767 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 136 [2018-10-26 21:40:15,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:40:15,769 INFO L225 Difference]: With dead ends: 728 [2018-10-26 21:40:15,769 INFO L226 Difference]: Without dead ends: 726 [2018-10-26 21:40:15,770 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 258 SyntacticMatches, 3 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=216, Invalid=1266, Unknown=0, NotChecked=0, Total=1482 [2018-10-26 21:40:15,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 726 states. [2018-10-26 21:40:15,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 726 to 692. [2018-10-26 21:40:15,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 692 states. [2018-10-26 21:40:15,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 692 states to 692 states and 966 transitions. [2018-10-26 21:40:15,792 INFO L78 Accepts]: Start accepts. Automaton has 692 states and 966 transitions. Word has length 136 [2018-10-26 21:40:15,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:40:15,792 INFO L481 AbstractCegarLoop]: Abstraction has 692 states and 966 transitions. [2018-10-26 21:40:15,792 INFO L482 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-10-26 21:40:15,792 INFO L276 IsEmpty]: Start isEmpty. Operand 692 states and 966 transitions. [2018-10-26 21:40:15,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-10-26 21:40:15,794 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:40:15,794 INFO L375 BasicCegarLoop]: trace histogram [13, 12, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:40:15,794 INFO L424 AbstractCegarLoop]: === Iteration 29 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:40:15,794 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:15,794 INFO L82 PathProgramCache]: Analyzing trace with hash 2022069990, now seen corresponding path program 1 times [2018-10-26 21:40:15,794 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:40:15,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:15,795 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:40:15,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:15,795 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:40:15,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:16,498 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 91 proven. 330 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-10-26 21:40:16,498 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:16,499 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:40:16,499 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 152 with the following transitions: [2018-10-26 21:40:16,499 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [9], [15], [18], [20], [24], [27], [30], [35], [42], [45], [48], [51], [56], [138], [233], [236], [251], [254], [257], [262], [329], [332], [347], [362], [377], [380], [383], [388], [425], [428], [443], [458], [473], [488], [491], [494], [497], [503], [506], [509], [514], [526], [529], [530], [531] [2018-10-26 21:40:16,500 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 21:40:16,500 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 21:40:16,748 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 21:40:54,925 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 21:40:54,925 INFO L272 AbstractInterpreter]: Visited 48 different actions 982 times. Merged at 41 different actions 774 times. Widened at 5 different actions 48 times. Found 126 fixpoints after 15 different actions. Largest state had 50 variables. [2018-10-26 21:40:54,935 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:54,935 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 21:40:54,935 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:54,935 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:54,945 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:40:54,945 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:40:55,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:55,022 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:55,044 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 91 proven. 330 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-10-26 21:40:55,044 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:40:55,116 INFO L134 CoverageAnalysis]: Checked inductivity of 447 backedges. 91 proven. 330 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-10-26 21:40:55,134 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:40:55,134 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 16 [2018-10-26 21:40:55,134 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:40:55,134 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 21:40:55,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 21:40:55,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-10-26 21:40:55,135 INFO L87 Difference]: Start difference. First operand 692 states and 966 transitions. Second operand 9 states. [2018-10-26 21:40:55,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:40:55,240 INFO L93 Difference]: Finished difference Result 1213 states and 1690 transitions. [2018-10-26 21:40:55,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 21:40:55,241 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 151 [2018-10-26 21:40:55,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:40:55,243 INFO L225 Difference]: With dead ends: 1213 [2018-10-26 21:40:55,243 INFO L226 Difference]: Without dead ends: 837 [2018-10-26 21:40:55,244 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 315 GetRequests, 301 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-10-26 21:40:55,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 837 states. [2018-10-26 21:40:55,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 837 to 734. [2018-10-26 21:40:55,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 734 states. [2018-10-26 21:40:55,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 734 states to 734 states and 1025 transitions. [2018-10-26 21:40:55,272 INFO L78 Accepts]: Start accepts. Automaton has 734 states and 1025 transitions. Word has length 151 [2018-10-26 21:40:55,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:40:55,273 INFO L481 AbstractCegarLoop]: Abstraction has 734 states and 1025 transitions. [2018-10-26 21:40:55,273 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 21:40:55,273 INFO L276 IsEmpty]: Start isEmpty. Operand 734 states and 1025 transitions. [2018-10-26 21:40:55,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-10-26 21:40:55,274 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:40:55,274 INFO L375 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:40:55,274 INFO L424 AbstractCegarLoop]: === Iteration 30 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:40:55,274 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:55,274 INFO L82 PathProgramCache]: Analyzing trace with hash 1545010560, now seen corresponding path program 2 times [2018-10-26 21:40:55,274 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:40:55,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:55,280 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:40:55,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:55,280 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:40:55,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:55,615 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 417 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:40:55,615 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:55,615 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:40:55,615 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:40:55,615 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:40:55,615 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:55,615 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:55,625 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 21:40:55,625 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 21:40:55,728 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-10-26 21:40:55,728 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:40:55,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:56,094 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 414 proven. 19 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-26 21:40:56,094 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:40:56,468 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 380 proven. 57 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:40:56,485 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:40:56,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11, 12] total 34 [2018-10-26 21:40:56,486 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:40:56,486 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-10-26 21:40:56,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-10-26 21:40:56,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=804, Unknown=0, NotChecked=0, Total=1122 [2018-10-26 21:40:56,487 INFO L87 Difference]: Start difference. First operand 734 states and 1025 transitions. Second operand 24 states. [2018-10-26 21:40:57,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:40:57,339 INFO L93 Difference]: Finished difference Result 800 states and 1097 transitions. [2018-10-26 21:40:57,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-10-26 21:40:57,341 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 152 [2018-10-26 21:40:57,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:40:57,343 INFO L225 Difference]: With dead ends: 800 [2018-10-26 21:40:57,343 INFO L226 Difference]: Without dead ends: 798 [2018-10-26 21:40:57,344 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 346 GetRequests, 289 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 547 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=712, Invalid=2480, Unknown=0, NotChecked=0, Total=3192 [2018-10-26 21:40:57,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 798 states. [2018-10-26 21:40:57,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 798 to 734. [2018-10-26 21:40:57,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 734 states. [2018-10-26 21:40:57,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 734 states to 734 states and 1023 transitions. [2018-10-26 21:40:57,369 INFO L78 Accepts]: Start accepts. Automaton has 734 states and 1023 transitions. Word has length 152 [2018-10-26 21:40:57,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:40:57,369 INFO L481 AbstractCegarLoop]: Abstraction has 734 states and 1023 transitions. [2018-10-26 21:40:57,369 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-10-26 21:40:57,369 INFO L276 IsEmpty]: Start isEmpty. Operand 734 states and 1023 transitions. [2018-10-26 21:40:57,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2018-10-26 21:40:57,370 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:40:57,370 INFO L375 BasicCegarLoop]: trace histogram [15, 14, 14, 10, 10, 6, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:40:57,370 INFO L424 AbstractCegarLoop]: === Iteration 31 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:40:57,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:57,371 INFO L82 PathProgramCache]: Analyzing trace with hash -348083931, now seen corresponding path program 3 times [2018-10-26 21:40:57,371 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:40:57,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:57,371 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:40:57,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:57,372 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:40:57,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:57,583 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-10-26 21:40:57,584 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:57,584 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:40:57,584 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:40:57,584 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:40:57,584 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:57,584 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:57,592 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 21:40:57,592 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-10-26 21:40:57,691 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 21:40:57,691 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:40:57,695 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:57,713 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-10-26 21:40:57,713 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:40:57,828 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-10-26 21:40:57,845 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:40:57,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 18 [2018-10-26 21:40:57,845 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:40:57,846 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 21:40:57,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 21:40:57,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-10-26 21:40:57,846 INFO L87 Difference]: Start difference. First operand 734 states and 1023 transitions. Second operand 10 states. [2018-10-26 21:40:57,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:40:57,956 INFO L93 Difference]: Finished difference Result 1012 states and 1396 transitions. [2018-10-26 21:40:57,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-26 21:40:57,984 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 169 [2018-10-26 21:40:57,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:40:57,987 INFO L225 Difference]: With dead ends: 1012 [2018-10-26 21:40:57,987 INFO L226 Difference]: Without dead ends: 924 [2018-10-26 21:40:57,988 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 337 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-10-26 21:40:57,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states. [2018-10-26 21:40:58,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 812. [2018-10-26 21:40:58,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-10-26 21:40:58,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 1133 transitions. [2018-10-26 21:40:58,015 INFO L78 Accepts]: Start accepts. Automaton has 812 states and 1133 transitions. Word has length 169 [2018-10-26 21:40:58,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:40:58,016 INFO L481 AbstractCegarLoop]: Abstraction has 812 states and 1133 transitions. [2018-10-26 21:40:58,016 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 21:40:58,016 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 1133 transitions. [2018-10-26 21:40:58,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-10-26 21:40:58,017 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:40:58,017 INFO L375 BasicCegarLoop]: trace histogram [17, 16, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:40:58,017 INFO L424 AbstractCegarLoop]: === Iteration 32 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:40:58,017 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:58,017 INFO L82 PathProgramCache]: Analyzing trace with hash -1339885547, now seen corresponding path program 2 times [2018-10-26 21:40:58,017 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:40:58,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:58,018 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:40:58,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:58,018 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:40:58,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:58,270 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-10-26 21:40:58,270 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:58,270 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:40:58,270 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:40:58,270 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:40:58,270 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:58,270 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:58,279 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 21:40:58,279 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 21:40:58,324 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-10-26 21:40:58,325 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:40:58,328 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:58,531 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 295 proven. 4 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-10-26 21:40:58,531 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:40:58,603 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 295 proven. 4 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-10-26 21:40:58,620 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:40:58,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 6, 6] total 18 [2018-10-26 21:40:58,620 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:40:58,620 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-10-26 21:40:58,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-10-26 21:40:58,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=190, Unknown=0, NotChecked=0, Total=306 [2018-10-26 21:40:58,621 INFO L87 Difference]: Start difference. First operand 812 states and 1133 transitions. Second operand 15 states. [2018-10-26 21:40:59,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:40:59,164 INFO L93 Difference]: Finished difference Result 1007 states and 1391 transitions. [2018-10-26 21:40:59,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-10-26 21:40:59,165 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 197 [2018-10-26 21:40:59,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:40:59,167 INFO L225 Difference]: With dead ends: 1007 [2018-10-26 21:40:59,167 INFO L226 Difference]: Without dead ends: 550 [2018-10-26 21:40:59,168 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 436 GetRequests, 401 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 206 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=407, Invalid=853, Unknown=0, NotChecked=0, Total=1260 [2018-10-26 21:40:59,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 550 states. [2018-10-26 21:40:59,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 550 to 522. [2018-10-26 21:40:59,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 522 states. [2018-10-26 21:40:59,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 522 states to 522 states and 717 transitions. [2018-10-26 21:40:59,191 INFO L78 Accepts]: Start accepts. Automaton has 522 states and 717 transitions. Word has length 197 [2018-10-26 21:40:59,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:40:59,191 INFO L481 AbstractCegarLoop]: Abstraction has 522 states and 717 transitions. [2018-10-26 21:40:59,191 INFO L482 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-10-26 21:40:59,191 INFO L276 IsEmpty]: Start isEmpty. Operand 522 states and 717 transitions. [2018-10-26 21:40:59,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 262 [2018-10-26 21:40:59,193 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:40:59,193 INFO L375 BasicCegarLoop]: trace histogram [23, 22, 22, 16, 16, 10, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:40:59,193 INFO L424 AbstractCegarLoop]: === Iteration 33 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:40:59,193 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:40:59,193 INFO L82 PathProgramCache]: Analyzing trace with hash -438655549, now seen corresponding path program 4 times [2018-10-26 21:40:59,193 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:40:59,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:59,194 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:40:59,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:40:59,194 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:40:59,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:59,457 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-10-26 21:40:59,457 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:59,457 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:40:59,457 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:40:59,457 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:40:59,457 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:40:59,457 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:40:59,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:40:59,467 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 21:40:59,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:40:59,597 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:40:59,653 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-10-26 21:40:59,653 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:41:00,534 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-10-26 21:41:00,551 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:41:00,551 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 19 [2018-10-26 21:41:00,552 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:41:00,552 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-10-26 21:41:00,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-10-26 21:41:00,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:41:00,553 INFO L87 Difference]: Start difference. First operand 522 states and 717 transitions. Second operand 14 states. [2018-10-26 21:41:00,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:41:00,653 INFO L93 Difference]: Finished difference Result 737 states and 1014 transitions. [2018-10-26 21:41:00,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-10-26 21:41:00,654 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 261 [2018-10-26 21:41:00,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:41:00,656 INFO L225 Difference]: With dead ends: 737 [2018-10-26 21:41:00,656 INFO L226 Difference]: Without dead ends: 649 [2018-10-26 21:41:00,657 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 545 GetRequests, 515 SyntacticMatches, 13 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:41:00,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2018-10-26 21:41:00,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 603. [2018-10-26 21:41:00,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 603 states. [2018-10-26 21:41:00,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603 states to 603 states and 828 transitions. [2018-10-26 21:41:00,684 INFO L78 Accepts]: Start accepts. Automaton has 603 states and 828 transitions. Word has length 261 [2018-10-26 21:41:00,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:41:00,684 INFO L481 AbstractCegarLoop]: Abstraction has 603 states and 828 transitions. [2018-10-26 21:41:00,685 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-10-26 21:41:00,685 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 828 transitions. [2018-10-26 21:41:00,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 308 [2018-10-26 21:41:00,686 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:41:00,686 INFO L375 BasicCegarLoop]: trace histogram [27, 26, 26, 19, 19, 12, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:41:00,691 INFO L424 AbstractCegarLoop]: === Iteration 34 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:41:00,691 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:41:00,691 INFO L82 PathProgramCache]: Analyzing trace with hash -209480526, now seen corresponding path program 5 times [2018-10-26 21:41:00,691 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:41:00,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:41:00,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 21:41:00,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:41:00,692 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:41:00,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:41:01,214 INFO L134 CoverageAnalysis]: Checked inductivity of 2158 backedges. 188 proven. 1910 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-10-26 21:41:01,214 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:41:01,214 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:41:01,214 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:41:01,214 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:41:01,214 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:41:01,215 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:41:01,224 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 21:41:01,224 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 21:41:01,454 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-10-26 21:41:01,455 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:41:01,462 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:41:01,540 INFO L134 CoverageAnalysis]: Checked inductivity of 2158 backedges. 188 proven. 1910 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-10-26 21:41:01,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:41:01,800 INFO L134 CoverageAnalysis]: Checked inductivity of 2158 backedges. 188 proven. 1910 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-10-26 21:41:01,819 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:41:01,819 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 19 [2018-10-26 21:41:01,819 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:41:01,819 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-10-26 21:41:01,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-10-26 21:41:01,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:41:01,820 INFO L87 Difference]: Start difference. First operand 603 states and 828 transitions. Second operand 16 states. [2018-10-26 21:41:01,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:41:01,963 INFO L93 Difference]: Finished difference Result 818 states and 1125 transitions. [2018-10-26 21:41:01,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-10-26 21:41:01,964 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 307 [2018-10-26 21:41:01,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:41:01,966 INFO L225 Difference]: With dead ends: 818 [2018-10-26 21:41:01,966 INFO L226 Difference]: Without dead ends: 730 [2018-10-26 21:41:01,967 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 641 GetRequests, 603 SyntacticMatches, 21 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:41:01,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 730 states. [2018-10-26 21:41:01,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 730 to 684. [2018-10-26 21:41:01,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 684 states. [2018-10-26 21:41:01,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 939 transitions. [2018-10-26 21:41:01,989 INFO L78 Accepts]: Start accepts. Automaton has 684 states and 939 transitions. Word has length 307 [2018-10-26 21:41:01,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:41:01,989 INFO L481 AbstractCegarLoop]: Abstraction has 684 states and 939 transitions. [2018-10-26 21:41:01,989 INFO L482 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-10-26 21:41:01,989 INFO L276 IsEmpty]: Start isEmpty. Operand 684 states and 939 transitions. [2018-10-26 21:41:01,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-10-26 21:41:01,991 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:41:01,991 INFO L375 BasicCegarLoop]: trace histogram [31, 30, 30, 22, 22, 14, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:41:01,992 INFO L424 AbstractCegarLoop]: === Iteration 35 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:41:01,992 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:41:01,992 INFO L82 PathProgramCache]: Analyzing trace with hash -1748649631, now seen corresponding path program 6 times [2018-10-26 21:41:01,992 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:41:01,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:41:01,993 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:41:01,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:41:01,993 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:41:02,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:41:02,611 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-10-26 21:41:02,611 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:41:02,612 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 21:41:02,612 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 21:41:02,612 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 21:41:02,612 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 21:41:02,612 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 21:41:02,621 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 21:41:02,621 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-10-26 21:41:02,801 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 21:41:02,801 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 21:41:02,809 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 21:41:02,912 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-10-26 21:41:02,912 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 21:41:03,250 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-10-26 21:41:03,269 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-26 21:41:03,269 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 19 [2018-10-26 21:41:03,269 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 21:41:03,270 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-10-26 21:41:03,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-10-26 21:41:03,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:41:03,270 INFO L87 Difference]: Start difference. First operand 684 states and 939 transitions. Second operand 18 states. [2018-10-26 21:41:03,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 21:41:03,417 INFO L93 Difference]: Finished difference Result 899 states and 1236 transitions. [2018-10-26 21:41:03,418 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-10-26 21:41:03,418 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 353 [2018-10-26 21:41:03,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 21:41:03,420 INFO L225 Difference]: With dead ends: 899 [2018-10-26 21:41:03,420 INFO L226 Difference]: Without dead ends: 811 [2018-10-26 21:41:03,421 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 737 GetRequests, 691 SyntacticMatches, 29 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-10-26 21:41:03,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 811 states. [2018-10-26 21:41:03,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 811 to 765. [2018-10-26 21:41:03,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 765 states. [2018-10-26 21:41:03,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 765 states to 765 states and 1050 transitions. [2018-10-26 21:41:03,453 INFO L78 Accepts]: Start accepts. Automaton has 765 states and 1050 transitions. Word has length 353 [2018-10-26 21:41:03,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 21:41:03,454 INFO L481 AbstractCegarLoop]: Abstraction has 765 states and 1050 transitions. [2018-10-26 21:41:03,454 INFO L482 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-10-26 21:41:03,454 INFO L276 IsEmpty]: Start isEmpty. Operand 765 states and 1050 transitions. [2018-10-26 21:41:03,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 400 [2018-10-26 21:41:03,456 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 21:41:03,456 INFO L375 BasicCegarLoop]: trace histogram [35, 34, 34, 25, 25, 16, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 21:41:03,457 INFO L424 AbstractCegarLoop]: === Iteration 36 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 21:41:03,457 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:41:03,457 INFO L82 PathProgramCache]: Analyzing trace with hash -1805057072, now seen corresponding path program 7 times [2018-10-26 21:41:03,457 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 21:41:03,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:41:03,458 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 21:41:03,458 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 21:41:03,458 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 21:41:04,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 21:41:04,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 21:41:04,932 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-10-26 21:41:05,099 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.10 09:41:05 BoogieIcfgContainer [2018-10-26 21:41:05,099 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-10-26 21:41:05,099 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-26 21:41:05,099 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-26 21:41:05,099 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-26 21:41:05,102 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:33:15" (3/4) ... [2018-10-26 21:41:05,104 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-10-26 21:41:05,306 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_86fef0ce-deb4-4bc1-9492-51031c4e2d6d/bin-2019/utaipan/witness.graphml [2018-10-26 21:41:05,309 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-26 21:41:05,310 INFO L168 Benchmark]: Toolchain (without parser) took 472086.57 ms. Allocated memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: 4.1 GB). Free memory was 953.8 MB in the beginning and 1.6 GB in the end (delta: -681.4 MB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,311 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 21:41:05,311 INFO L168 Benchmark]: CACSL2BoogieTranslator took 541.90 ms. Allocated memory is still 1.0 GB. Free memory was 953.8 MB in the beginning and 932.3 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,311 INFO L168 Benchmark]: Boogie Procedure Inliner took 52.33 ms. Allocated memory is still 1.0 GB. Free memory was 932.3 MB in the beginning and 929.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,311 INFO L168 Benchmark]: Boogie Preprocessor took 139.98 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.0 MB). Free memory was 929.6 MB in the beginning and 1.1 GB in the end (delta: -195.5 MB). Peak memory consumption was 17.2 MB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,312 INFO L168 Benchmark]: RCFGBuilder took 1703.25 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 53.1 MB). Peak memory consumption was 53.1 MB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,312 INFO L168 Benchmark]: TraceAbstraction took 469434.49 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 4.0 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -563.1 MB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,312 INFO L168 Benchmark]: Witness Printer took 210.26 ms. Allocated memory is still 5.1 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 2.3 kB). Peak memory consumption was 2.3 kB. Max. memory is 11.5 GB. [2018-10-26 21:41:05,313 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 541.90 ms. Allocated memory is still 1.0 GB. Free memory was 953.8 MB in the beginning and 932.3 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 52.33 ms. Allocated memory is still 1.0 GB. Free memory was 932.3 MB in the beginning and 929.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 139.98 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.0 MB). Free memory was 929.6 MB in the beginning and 1.1 GB in the end (delta: -195.5 MB). Peak memory consumption was 17.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1703.25 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 53.1 MB). Peak memory consumption was 53.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 469434.49 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 4.0 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -563.1 MB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. * Witness Printer took 210.26 ms. Allocated memory is still 5.1 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 2.3 kB). Peak memory consumption was 2.3 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 569]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L5] int m_Protocol = 1; [L6] int m_msg_2 = 2; [L7] int m_recv_ack_2 = 3; [L8] int m_msg_1_1 = 4; [L9] int m_msg_1_2 = 5; [L10] int m_recv_ack_1_1 = 6; [L11] int m_recv_ack_1_2 = 7; VAL [\old(m_msg_1_1)=23, \old(m_msg_1_2)=20, \old(m_msg_2)=21, \old(m_Protocol)=25, \old(m_recv_ack_1_1)=22, \old(m_recv_ack_1_2)=24, \old(m_recv_ack_2)=26, m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3] [L16] int q = 0; [L17] int method_id; [L20] int this_expect = 0; [L21] int this_buffer_empty = 0; VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, q=0, this_buffer_empty=0, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=0, this_buffer_empty=0, this_expect=0] [L43] COND TRUE q == 0 [L44] COND TRUE __VERIFIER_nondet_int() [L46] COND TRUE 1 [L48] method_id = 1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=0, this_buffer_empty=0, this_expect=0] [L50] COND FALSE !(0) [L54] q = 1 [L56] this_expect=0 [L56] this_buffer_empty=1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=3, this_buffer_empty=0, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=1, this_buffer_empty=1, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=1, this_buffer_empty=1, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=1, this_buffer_empty=1, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=17] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND TRUE this_expect > 16 [L39] this_expect = -16 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L286] COND TRUE (((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2)))) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L569] __VERIFIER_error() VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 115 locations, 1 error locations. UNSAFE Result, 469.3s OverallTime, 36 OverallIterations, 35 TraceHistogramMax, 24.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 6721 SDtfs, 10345 SDslu, 30640 SDs, 0 SdLazy, 5803 SolverSat, 801 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 12.4s Time, PredicateUnifierStatistics: 2 DeclaredPredicates, 6736 GetRequests, 6174 SyntacticMatches, 107 SemanticMatches, 455 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 2131 ImplicationChecksByTransitivity, 20.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=812occurred in iteration=31, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 414.5s AbstIntTime, 18 AbstIntIterations, 1 AbstIntStrong, 0.949160035366932 AbsIntWeakeningRatio, 1.5517241379310345 AbsIntAvgWeakeningVarsNumRemoved, 593.7931034482758 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 35 MinimizatonAttempts, 1100 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 3.3s SatisfiabilityAnalysisTime, 21.3s InterpolantComputationTime, 6945 NumberOfCodeBlocks, 6761 NumberOfCodeBlocksAsserted, 121 NumberOfCheckSat, 9591 ConstructedInterpolants, 368 QuantifiedInterpolants, 6880378 SizeOfPredicates, 79 NumberOfNonLiveVariables, 17902 ConjunctsInSsa, 434 ConjunctsInUnsatCore, 87 InterpolantComputations, 11 PerfectInterpolantSequences, 8912/34533 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...