./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/reducercommutativity/rangesum60_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/reducercommutativity/rangesum60_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4405509d043dde59d941f33192dd2cdce1daabca ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-26 19:55:00,443 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 19:55:00,444 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 19:55:00,460 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 19:55:00,460 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 19:55:00,461 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 19:55:00,462 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 19:55:00,464 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 19:55:00,465 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 19:55:00,470 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 19:55:00,472 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 19:55:00,473 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 19:55:00,474 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 19:55:00,476 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 19:55:00,484 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 19:55:00,485 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 19:55:00,486 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 19:55:00,487 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 19:55:00,488 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 19:55:00,492 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 19:55:00,494 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 19:55:00,495 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 19:55:00,496 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 19:55:00,496 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 19:55:00,497 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 19:55:00,499 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 19:55:00,501 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 19:55:00,503 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 19:55:00,505 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 19:55:00,505 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 19:55:00,506 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 19:55:00,506 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 19:55:00,507 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 19:55:00,507 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 19:55:00,508 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 19:55:00,508 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 19:55:00,509 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-10-26 19:55:00,531 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 19:55:00,537 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 19:55:00,538 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 19:55:00,538 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-26 19:55:00,538 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-26 19:55:00,539 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-26 19:55:00,539 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-10-26 19:55:00,539 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-26 19:55:00,539 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-10-26 19:55:00,539 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-10-26 19:55:00,539 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-26 19:55:00,540 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 19:55:00,540 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-26 19:55:00,540 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-26 19:55:00,541 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-26 19:55:00,541 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 19:55:00,541 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 19:55:00,541 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 19:55:00,541 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 19:55:00,542 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-26 19:55:00,542 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 19:55:00,542 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 19:55:00,542 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 19:55:00,542 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-26 19:55:00,542 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 19:55:00,542 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-26 19:55:00,543 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 19:55:00,543 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 19:55:00,543 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 19:55:00,543 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 19:55:00,543 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-10-26 19:55:00,543 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 19:55:00,544 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-26 19:55:00,544 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-26 19:55:00,544 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4405509d043dde59d941f33192dd2cdce1daabca [2018-10-26 19:55:00,573 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 19:55:00,584 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 19:55:00,588 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 19:55:00,589 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 19:55:00,590 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 19:55:00,590 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/../../sv-benchmarks/c/reducercommutativity/rangesum60_false-unreach-call.i [2018-10-26 19:55:00,648 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/data/273cfbcc5/3a4b117b578a4e03be394973d0038f3f/FLAG75bd6455d [2018-10-26 19:55:01,064 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 19:55:01,065 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/sv-benchmarks/c/reducercommutativity/rangesum60_false-unreach-call.i [2018-10-26 19:55:01,071 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/data/273cfbcc5/3a4b117b578a4e03be394973d0038f3f/FLAG75bd6455d [2018-10-26 19:55:01,084 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/data/273cfbcc5/3a4b117b578a4e03be394973d0038f3f [2018-10-26 19:55:01,087 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 19:55:01,088 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 19:55:01,090 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 19:55:01,090 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 19:55:01,094 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 19:55:01,095 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,098 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7949ef93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01, skipping insertion in model container [2018-10-26 19:55:01,098 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,108 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 19:55:01,128 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 19:55:01,276 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 19:55:01,284 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 19:55:01,308 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 19:55:01,324 INFO L193 MainTranslator]: Completed translation [2018-10-26 19:55:01,324 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01 WrapperNode [2018-10-26 19:55:01,325 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 19:55:01,326 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 19:55:01,327 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 19:55:01,327 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 19:55:01,336 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,344 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,365 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 19:55:01,366 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 19:55:01,366 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 19:55:01,366 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 19:55:01,376 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,376 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,378 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,379 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,385 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,390 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,392 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... [2018-10-26 19:55:01,394 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 19:55:01,395 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 19:55:01,395 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 19:55:01,395 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 19:55:01,396 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-26 19:55:01,523 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-26 19:55:01,523 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-26 19:55:01,523 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 19:55:01,523 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 19:55:01,523 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-26 19:55:01,523 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-26 19:55:01,524 INFO L130 BoogieDeclarations]: Found specification of procedure rangesum [2018-10-26 19:55:01,524 INFO L138 BoogieDeclarations]: Found implementation of procedure rangesum [2018-10-26 19:55:01,524 INFO L130 BoogieDeclarations]: Found specification of procedure init_nondet [2018-10-26 19:55:01,524 INFO L138 BoogieDeclarations]: Found implementation of procedure init_nondet [2018-10-26 19:55:02,165 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 19:55:02,166 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 07:55:02 BoogieIcfgContainer [2018-10-26 19:55:02,166 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 19:55:02,167 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-26 19:55:02,167 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-26 19:55:02,171 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-26 19:55:02,171 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.10 07:55:01" (1/3) ... [2018-10-26 19:55:02,174 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6c18f498 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 07:55:02, skipping insertion in model container [2018-10-26 19:55:02,174 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 07:55:01" (2/3) ... [2018-10-26 19:55:02,174 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6c18f498 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.10 07:55:02, skipping insertion in model container [2018-10-26 19:55:02,174 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 07:55:02" (3/3) ... [2018-10-26 19:55:02,176 INFO L112 eAbstractionObserver]: Analyzing ICFG rangesum60_false-unreach-call.i [2018-10-26 19:55:02,188 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-26 19:55:02,197 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-10-26 19:55:02,215 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-10-26 19:55:02,250 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-26 19:55:02,250 INFO L383 AbstractCegarLoop]: Hoare is true [2018-10-26 19:55:02,251 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-26 19:55:02,251 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-26 19:55:02,251 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-26 19:55:02,252 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-26 19:55:02,252 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-26 19:55:02,252 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-26 19:55:02,272 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2018-10-26 19:55:02,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 19:55:02,280 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:02,281 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:02,284 INFO L424 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:02,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:02,291 INFO L82 PathProgramCache]: Analyzing trace with hash -1049289672, now seen corresponding path program 1 times [2018-10-26 19:55:02,294 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:02,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:02,347 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:02,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:02,347 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:02,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:02,429 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2018-10-26 19:55:02,430 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:02,430 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-26 19:55:02,431 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 38 with the following transitions: [2018-10-26 19:55:02,434 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [24], [26], [28], [31], [32], [39], [57], [61], [63], [64], [77], [79], [80], [81], [82], [84], [85], [86], [87], [88], [89], [90], [91] [2018-10-26 19:55:02,503 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 19:55:02,503 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 19:55:02,670 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 19:55:02,671 INFO L272 AbstractInterpreter]: Visited 9 different actions 9 times. Never merged. Never widened. Never found a fixpoint. Largest state had 37 variables. [2018-10-26 19:55:02,690 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:02,690 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 19:55:02,784 INFO L227 lantSequenceWeakener]: Weakened 8 states. On average, predicates are now at 93.06% of their original sizes. [2018-10-26 19:55:02,785 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 19:55:02,889 INFO L415 sIntCurrentIteration]: We unified 36 AI predicates to 36 [2018-10-26 19:55:02,889 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 19:55:02,891 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 19:55:02,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-26 19:55:02,891 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 19:55:02,897 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-26 19:55:02,901 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-26 19:55:02,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 19:55:02,904 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 4 states. [2018-10-26 19:55:03,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:03,355 INFO L93 Difference]: Finished difference Result 69 states and 90 transitions. [2018-10-26 19:55:03,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-26 19:55:03,356 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 37 [2018-10-26 19:55:03,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:03,367 INFO L225 Difference]: With dead ends: 69 [2018-10-26 19:55:03,367 INFO L226 Difference]: Without dead ends: 35 [2018-10-26 19:55:03,371 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 36 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-26 19:55:03,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-10-26 19:55:03,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 35. [2018-10-26 19:55:03,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-10-26 19:55:03,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 41 transitions. [2018-10-26 19:55:03,432 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 41 transitions. Word has length 37 [2018-10-26 19:55:03,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:03,432 INFO L481 AbstractCegarLoop]: Abstraction has 35 states and 41 transitions. [2018-10-26 19:55:03,432 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-26 19:55:03,433 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 41 transitions. [2018-10-26 19:55:03,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 19:55:03,436 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:03,436 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:03,437 INFO L424 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:03,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:03,437 INFO L82 PathProgramCache]: Analyzing trace with hash 1338067039, now seen corresponding path program 1 times [2018-10-26 19:55:03,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:03,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:03,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:03,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:03,439 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:03,464 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:03,464 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:03,465 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:03,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:03,483 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:03,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:03,567 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 43 with the following transitions: [2018-10-26 19:55:03,567 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [15], [18], [26], [28], [31], [32], [39], [43], [46], [61], [63], [64], [68], [71], [79], [80], [81], [82], [84], [85], [86], [87], [88], [89], [90], [91] [2018-10-26 19:55:03,570 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 19:55:03,570 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 19:55:03,599 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 19:55:03,599 INFO L272 AbstractInterpreter]: Visited 10 different actions 10 times. Never merged. Never widened. Never found a fixpoint. Largest state had 37 variables. [2018-10-26 19:55:03,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:03,626 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 19:55:03,681 INFO L227 lantSequenceWeakener]: Weakened 9 states. On average, predicates are now at 91.36% of their original sizes. [2018-10-26 19:55:03,683 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 19:55:03,844 INFO L415 sIntCurrentIteration]: We unified 41 AI predicates to 41 [2018-10-26 19:55:03,845 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 19:55:03,845 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 19:55:03,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-26 19:55:03,845 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 19:55:03,846 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-26 19:55:03,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-26 19:55:03,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-26 19:55:03,847 INFO L87 Difference]: Start difference. First operand 35 states and 41 transitions. Second operand 5 states. [2018-10-26 19:55:04,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:04,389 INFO L93 Difference]: Finished difference Result 62 states and 74 transitions. [2018-10-26 19:55:04,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-26 19:55:04,389 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-10-26 19:55:04,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:04,391 INFO L225 Difference]: With dead ends: 62 [2018-10-26 19:55:04,392 INFO L226 Difference]: Without dead ends: 38 [2018-10-26 19:55:04,393 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 42 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:04,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-10-26 19:55:04,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 37. [2018-10-26 19:55:04,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-10-26 19:55:04,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 43 transitions. [2018-10-26 19:55:04,402 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 43 transitions. Word has length 42 [2018-10-26 19:55:04,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:04,402 INFO L481 AbstractCegarLoop]: Abstraction has 37 states and 43 transitions. [2018-10-26 19:55:04,403 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-26 19:55:04,403 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 43 transitions. [2018-10-26 19:55:04,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 19:55:04,404 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:04,404 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:04,405 INFO L424 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:04,405 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:04,405 INFO L82 PathProgramCache]: Analyzing trace with hash -1866850875, now seen corresponding path program 1 times [2018-10-26 19:55:04,407 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:04,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:04,408 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:04,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:04,409 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:04,427 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:04,427 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:04,427 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:04,442 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:04,442 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:04,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:04,519 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 46 with the following transitions: [2018-10-26 19:55:04,519 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [15], [18], [26], [28], [31], [32], [39], [43], [46], [61], [63], [64], [68], [71], [73], [75], [79], [80], [81], [82], [84], [85], [86], [87], [88], [89], [90], [91] [2018-10-26 19:55:04,522 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 19:55:04,522 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 19:55:04,805 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 19:55:04,805 INFO L272 AbstractInterpreter]: Visited 19 different actions 54 times. Merged at 3 different actions 26 times. Widened at 1 different actions 5 times. Found 1 fixpoints after 1 different actions. Largest state had 37 variables. [2018-10-26 19:55:04,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:04,854 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 19:55:04,981 INFO L227 lantSequenceWeakener]: Weakened 19 states. On average, predicates are now at 85.03% of their original sizes. [2018-10-26 19:55:04,983 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 19:55:05,676 INFO L415 sIntCurrentIteration]: We unified 44 AI predicates to 44 [2018-10-26 19:55:05,677 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 19:55:05,677 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 19:55:05,677 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-26 19:55:05,677 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 19:55:05,678 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-26 19:55:05,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-26 19:55:05,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-10-26 19:55:05,679 INFO L87 Difference]: Start difference. First operand 37 states and 43 transitions. Second operand 9 states. [2018-10-26 19:55:06,710 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 19:55:07,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:07,480 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2018-10-26 19:55:07,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-26 19:55:07,480 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 45 [2018-10-26 19:55:07,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:07,481 INFO L225 Difference]: With dead ends: 61 [2018-10-26 19:55:07,481 INFO L226 Difference]: Without dead ends: 41 [2018-10-26 19:55:07,482 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 48 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:07,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-10-26 19:55:07,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2018-10-26 19:55:07,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-10-26 19:55:07,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 46 transitions. [2018-10-26 19:55:07,492 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 46 transitions. Word has length 45 [2018-10-26 19:55:07,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:07,492 INFO L481 AbstractCegarLoop]: Abstraction has 40 states and 46 transitions. [2018-10-26 19:55:07,492 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-26 19:55:07,492 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 46 transitions. [2018-10-26 19:55:07,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 19:55:07,495 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:07,495 INFO L375 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:07,495 INFO L424 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:07,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:07,496 INFO L82 PathProgramCache]: Analyzing trace with hash -1254084674, now seen corresponding path program 1 times [2018-10-26 19:55:07,496 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:07,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:07,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:07,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:07,497 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:07,517 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:07,517 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:07,518 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:07,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:07,552 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:07,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:07,600 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 58 with the following transitions: [2018-10-26 19:55:07,600 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [15], [18], [26], [28], [31], [32], [39], [43], [46], [48], [53], [55], [61], [63], [64], [68], [71], [73], [75], [79], [80], [81], [82], [84], [85], [86], [87], [88], [89], [90], [91] [2018-10-26 19:55:07,602 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 19:55:07,602 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 19:55:07,850 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 19:55:07,851 INFO L272 AbstractInterpreter]: Visited 22 different actions 105 times. Merged at 7 different actions 64 times. Widened at 2 different actions 11 times. Found 2 fixpoints after 2 different actions. Largest state had 37 variables. [2018-10-26 19:55:07,862 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:07,862 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 19:55:07,936 INFO L227 lantSequenceWeakener]: Weakened 23 states. On average, predicates are now at 82.89% of their original sizes. [2018-10-26 19:55:07,938 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 19:55:08,255 INFO L415 sIntCurrentIteration]: We unified 56 AI predicates to 56 [2018-10-26 19:55:08,255 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 19:55:08,255 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 19:55:08,256 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-10-26 19:55:08,256 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 19:55:08,257 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-26 19:55:08,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-26 19:55:08,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-10-26 19:55:08,259 INFO L87 Difference]: Start difference. First operand 40 states and 46 transitions. Second operand 10 states. [2018-10-26 19:55:08,893 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 19:55:09,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:09,302 INFO L93 Difference]: Finished difference Result 67 states and 82 transitions. [2018-10-26 19:55:09,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-26 19:55:09,303 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 57 [2018-10-26 19:55:09,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:09,304 INFO L225 Difference]: With dead ends: 67 [2018-10-26 19:55:09,304 INFO L226 Difference]: Without dead ends: 44 [2018-10-26 19:55:09,304 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 61 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2018-10-26 19:55:09,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-10-26 19:55:09,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-10-26 19:55:09,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-10-26 19:55:09,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2018-10-26 19:55:09,312 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 51 transitions. Word has length 57 [2018-10-26 19:55:09,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:09,313 INFO L481 AbstractCegarLoop]: Abstraction has 44 states and 51 transitions. [2018-10-26 19:55:09,313 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-26 19:55:09,313 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 51 transitions. [2018-10-26 19:55:09,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-10-26 19:55:09,316 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:09,316 INFO L375 BasicCegarLoop]: trace histogram [9, 6, 6, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:09,317 INFO L424 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:09,317 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:09,317 INFO L82 PathProgramCache]: Analyzing trace with hash -1360907787, now seen corresponding path program 1 times [2018-10-26 19:55:09,317 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:09,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:09,320 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:09,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:09,320 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:09,338 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:09,338 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:09,338 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:09,358 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:09,358 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:09,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:09,400 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 70 with the following transitions: [2018-10-26 19:55:09,401 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [15], [18], [26], [28], [31], [32], [39], [43], [46], [48], [51], [53], [55], [61], [63], [64], [68], [71], [73], [75], [79], [80], [81], [82], [84], [85], [86], [87], [88], [89], [90], [91] [2018-10-26 19:55:09,402 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 19:55:09,402 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 19:55:09,648 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 19:55:10,578 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-10-26 19:55:10,579 INFO L272 AbstractInterpreter]: Visited 32 different actions 352 times. Merged at 11 different actions 231 times. Widened at 2 different actions 34 times. Found 37 fixpoints after 6 different actions. Largest state had 37 variables. [2018-10-26 19:55:10,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:10,614 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-10-26 19:55:10,777 INFO L227 lantSequenceWeakener]: Weakened 49 states. On average, predicates are now at 77.76% of their original sizes. [2018-10-26 19:55:10,777 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-10-26 19:55:11,362 INFO L415 sIntCurrentIteration]: We unified 68 AI predicates to 68 [2018-10-26 19:55:11,362 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-10-26 19:55:11,363 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-26 19:55:11,363 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2018-10-26 19:55:11,363 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-26 19:55:11,363 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-10-26 19:55:11,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-10-26 19:55:11,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=295, Unknown=0, NotChecked=0, Total=342 [2018-10-26 19:55:11,364 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. Second operand 19 states. [2018-10-26 19:55:16,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:16,317 INFO L93 Difference]: Finished difference Result 75 states and 91 transitions. [2018-10-26 19:55:16,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-10-26 19:55:16,317 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 69 [2018-10-26 19:55:16,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:16,318 INFO L225 Difference]: With dead ends: 75 [2018-10-26 19:55:16,318 INFO L226 Difference]: Without dead ends: 48 [2018-10-26 19:55:16,319 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 78 GetRequests, 52 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=117, Invalid=639, Unknown=0, NotChecked=0, Total=756 [2018-10-26 19:55:16,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-10-26 19:55:16,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 46. [2018-10-26 19:55:16,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-10-26 19:55:16,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2018-10-26 19:55:16,333 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 69 [2018-10-26 19:55:16,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:16,335 INFO L481 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2018-10-26 19:55:16,336 INFO L482 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-10-26 19:55:16,336 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2018-10-26 19:55:16,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-10-26 19:55:16,337 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:16,338 INFO L375 BasicCegarLoop]: trace histogram [9, 6, 6, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:16,339 INFO L424 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:16,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:16,339 INFO L82 PathProgramCache]: Analyzing trace with hash 1443367440, now seen corresponding path program 1 times [2018-10-26 19:55:16,340 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:16,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:16,341 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:16,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:16,341 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:16,357 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:16,357 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:16,357 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:16,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:16,374 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:16,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:16,418 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 73 with the following transitions: [2018-10-26 19:55:16,418 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [15], [18], [20], [22], [26], [28], [31], [32], [39], [43], [46], [48], [51], [53], [55], [61], [63], [64], [68], [71], [73], [75], [79], [80], [81], [82], [84], [85], [86], [87], [88], [89], [90], [91] [2018-10-26 19:55:16,420 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-26 19:55:16,420 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-26 19:55:16,680 WARN L79 EvaluatorLogger]: Possible loss of precision. Operator ARITHMOD has no precise implementation. [2018-10-26 19:55:19,349 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-26 19:55:19,349 INFO L272 AbstractInterpreter]: Visited 40 different actions 723 times. Merged at 20 different actions 489 times. Widened at 3 different actions 75 times. Found 74 fixpoints after 8 different actions. Largest state had 39 variables. [2018-10-26 19:55:19,350 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:19,351 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-26 19:55:19,351 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:19,351 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:19,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:19,361 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 19:55:19,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:19,427 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:19,529 INFO L134 CoverageAnalysis]: Checked inductivity of 118 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 116 trivial. 0 not checked. [2018-10-26 19:55:19,529 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:19,652 INFO L134 CoverageAnalysis]: Checked inductivity of 118 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 116 trivial. 0 not checked. [2018-10-26 19:55:19,690 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:19,690 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-10-26 19:55:19,690 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:19,691 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-26 19:55:19,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-26 19:55:19,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:19,694 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand 6 states. [2018-10-26 19:55:19,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:19,748 INFO L93 Difference]: Finished difference Result 88 states and 102 transitions. [2018-10-26 19:55:19,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 19:55:19,749 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2018-10-26 19:55:19,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:19,750 INFO L225 Difference]: With dead ends: 88 [2018-10-26 19:55:19,750 INFO L226 Difference]: Without dead ends: 55 [2018-10-26 19:55:19,751 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:19,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-10-26 19:55:19,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-10-26 19:55:19,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-10-26 19:55:19,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 61 transitions. [2018-10-26 19:55:19,763 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 61 transitions. Word has length 72 [2018-10-26 19:55:19,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:19,763 INFO L481 AbstractCegarLoop]: Abstraction has 55 states and 61 transitions. [2018-10-26 19:55:19,763 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-26 19:55:19,763 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 61 transitions. [2018-10-26 19:55:19,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-10-26 19:55:19,765 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:19,765 INFO L375 BasicCegarLoop]: trace histogram [9, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:19,765 INFO L424 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:19,768 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:19,768 INFO L82 PathProgramCache]: Analyzing trace with hash -1140034890, now seen corresponding path program 2 times [2018-10-26 19:55:19,768 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:19,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:19,769 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:19,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:19,769 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:19,788 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:19,789 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:19,789 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:19,806 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:19,806 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:19,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:19,851 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:19,851 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:19,851 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:19,851 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:19,859 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 19:55:19,860 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 19:55:19,958 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-10-26 19:55:19,958 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:19,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:20,004 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 47 proven. 3 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-10-26 19:55:20,004 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:20,094 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 47 proven. 3 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-10-26 19:55:20,114 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:20,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2018-10-26 19:55:20,115 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:20,116 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-26 19:55:20,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-26 19:55:20,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-10-26 19:55:20,116 INFO L87 Difference]: Start difference. First operand 55 states and 61 transitions. Second operand 8 states. [2018-10-26 19:55:20,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:20,273 INFO L93 Difference]: Finished difference Result 103 states and 125 transitions. [2018-10-26 19:55:20,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-26 19:55:20,278 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 81 [2018-10-26 19:55:20,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:20,280 INFO L225 Difference]: With dead ends: 103 [2018-10-26 19:55:20,280 INFO L226 Difference]: Without dead ends: 74 [2018-10-26 19:55:20,280 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-10-26 19:55:20,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-10-26 19:55:20,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 70. [2018-10-26 19:55:20,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-10-26 19:55:20,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 79 transitions. [2018-10-26 19:55:20,299 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 79 transitions. Word has length 81 [2018-10-26 19:55:20,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:20,306 INFO L481 AbstractCegarLoop]: Abstraction has 70 states and 79 transitions. [2018-10-26 19:55:20,306 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-26 19:55:20,306 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 79 transitions. [2018-10-26 19:55:20,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-10-26 19:55:20,308 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:20,308 INFO L375 BasicCegarLoop]: trace histogram [21, 18, 18, 15, 5, 4, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:20,308 INFO L424 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:20,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:20,309 INFO L82 PathProgramCache]: Analyzing trace with hash 12732450, now seen corresponding path program 3 times [2018-10-26 19:55:20,309 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:20,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:20,314 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:20,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:20,314 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:20,355 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:20,356 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:20,356 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:20,370 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:20,370 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:20,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:20,425 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:20,426 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:20,426 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:20,426 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:20,444 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 19:55:20,444 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-10-26 19:55:20,533 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 19:55:20,534 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:20,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:20,653 INFO L134 CoverageAnalysis]: Checked inductivity of 766 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 740 trivial. 0 not checked. [2018-10-26 19:55:20,653 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:20,731 INFO L134 CoverageAnalysis]: Checked inductivity of 766 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 740 trivial. 0 not checked. [2018-10-26 19:55:20,754 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:20,754 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-10-26 19:55:20,754 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:20,755 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-26 19:55:20,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-26 19:55:20,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:20,755 INFO L87 Difference]: Start difference. First operand 70 states and 79 transitions. Second operand 12 states. [2018-10-26 19:55:20,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:20,858 INFO L93 Difference]: Finished difference Result 136 states and 159 transitions. [2018-10-26 19:55:20,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-10-26 19:55:20,862 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 129 [2018-10-26 19:55:20,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:20,863 INFO L225 Difference]: With dead ends: 136 [2018-10-26 19:55:20,863 INFO L226 Difference]: Without dead ends: 88 [2018-10-26 19:55:20,864 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 247 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:20,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-10-26 19:55:20,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 88. [2018-10-26 19:55:20,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-10-26 19:55:20,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 97 transitions. [2018-10-26 19:55:20,879 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 97 transitions. Word has length 129 [2018-10-26 19:55:20,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:20,879 INFO L481 AbstractCegarLoop]: Abstraction has 88 states and 97 transitions. [2018-10-26 19:55:20,879 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-26 19:55:20,879 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 97 transitions. [2018-10-26 19:55:20,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-10-26 19:55:20,881 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:20,883 INFO L375 BasicCegarLoop]: trace histogram [21, 18, 18, 15, 11, 10, 10, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:20,884 INFO L424 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:20,884 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:20,884 INFO L82 PathProgramCache]: Analyzing trace with hash 1495303522, now seen corresponding path program 4 times [2018-10-26 19:55:20,884 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:20,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:20,885 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:20,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:20,885 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:20,918 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:20,918 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:20,918 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:20,934 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:20,934 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:20,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:20,983 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:20,983 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:20,983 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:20,984 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:20,994 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:20,994 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 19:55:21,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:21,066 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:21,293 INFO L134 CoverageAnalysis]: Checked inductivity of 895 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 740 trivial. 0 not checked. [2018-10-26 19:55:21,294 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:21,520 INFO L134 CoverageAnalysis]: Checked inductivity of 895 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 740 trivial. 0 not checked. [2018-10-26 19:55:21,541 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:21,541 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-10-26 19:55:21,541 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:21,542 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-10-26 19:55:21,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-10-26 19:55:21,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-10-26 19:55:21,543 INFO L87 Difference]: Start difference. First operand 88 states and 97 transitions. Second operand 24 states. [2018-10-26 19:55:21,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:21,646 INFO L93 Difference]: Finished difference Result 172 states and 201 transitions. [2018-10-26 19:55:21,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-10-26 19:55:21,649 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 147 [2018-10-26 19:55:21,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:21,650 INFO L225 Difference]: With dead ends: 172 [2018-10-26 19:55:21,650 INFO L226 Difference]: Without dead ends: 124 [2018-10-26 19:55:21,651 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 271 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-10-26 19:55:21,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-10-26 19:55:21,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 124. [2018-10-26 19:55:21,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-10-26 19:55:21,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 133 transitions. [2018-10-26 19:55:21,670 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 133 transitions. Word has length 147 [2018-10-26 19:55:21,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:21,670 INFO L481 AbstractCegarLoop]: Abstraction has 124 states and 133 transitions. [2018-10-26 19:55:21,671 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-10-26 19:55:21,671 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 133 transitions. [2018-10-26 19:55:21,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2018-10-26 19:55:21,674 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:21,675 INFO L375 BasicCegarLoop]: trace histogram [23, 22, 22, 21, 18, 18, 15, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:21,675 INFO L424 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:21,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:21,675 INFO L82 PathProgramCache]: Analyzing trace with hash -2103799838, now seen corresponding path program 5 times [2018-10-26 19:55:21,675 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:21,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:21,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:21,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:21,676 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:21,721 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:21,721 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:21,721 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:21,733 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:21,733 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:21,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:21,838 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:21,839 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:21,839 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:21,839 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:21,853 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 19:55:21,853 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:21,948 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-10-26 19:55:21,949 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:21,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:22,064 INFO L134 CoverageAnalysis]: Checked inductivity of 1477 backedges. 348 proven. 2 refuted. 0 times theorem prover too weak. 1127 trivial. 0 not checked. [2018-10-26 19:55:22,065 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:22,144 INFO L134 CoverageAnalysis]: Checked inductivity of 1477 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1475 trivial. 0 not checked. [2018-10-26 19:55:22,164 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:22,164 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-10-26 19:55:22,164 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:22,164 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-26 19:55:22,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-26 19:55:22,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:22,165 INFO L87 Difference]: Start difference. First operand 124 states and 133 transitions. Second operand 6 states. [2018-10-26 19:55:22,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:22,364 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2018-10-26 19:55:22,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 19:55:22,365 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 183 [2018-10-26 19:55:22,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:22,366 INFO L225 Difference]: With dead ends: 169 [2018-10-26 19:55:22,366 INFO L226 Difference]: Without dead ends: 133 [2018-10-26 19:55:22,367 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 361 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:22,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-10-26 19:55:22,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2018-10-26 19:55:22,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-10-26 19:55:22,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 142 transitions. [2018-10-26 19:55:22,389 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 142 transitions. Word has length 183 [2018-10-26 19:55:22,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:22,389 INFO L481 AbstractCegarLoop]: Abstraction has 133 states and 142 transitions. [2018-10-26 19:55:22,390 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-26 19:55:22,390 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 142 transitions. [2018-10-26 19:55:22,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-10-26 19:55:22,392 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:22,392 INFO L375 BasicCegarLoop]: trace histogram [23, 22, 22, 21, 18, 18, 15, 5, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:22,392 INFO L424 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:22,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:22,393 INFO L82 PathProgramCache]: Analyzing trace with hash -295793557, now seen corresponding path program 6 times [2018-10-26 19:55:22,393 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:22,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:22,394 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:22,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:22,394 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:22,434 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:22,434 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:22,434 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:22,446 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:22,446 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:22,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:22,550 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:22,550 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:22,550 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:22,550 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:22,569 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 19:55:22,569 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:22,707 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 19:55:22,708 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:22,712 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:23,046 INFO L134 CoverageAnalysis]: Checked inductivity of 1501 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 764 trivial. 0 not checked. [2018-10-26 19:55:23,046 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:23,794 INFO L134 CoverageAnalysis]: Checked inductivity of 1501 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 764 trivial. 0 not checked. [2018-10-26 19:55:23,816 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:23,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 48 [2018-10-26 19:55:23,816 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:23,817 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-10-26 19:55:23,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-10-26 19:55:23,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-10-26 19:55:23,818 INFO L87 Difference]: Start difference. First operand 133 states and 142 transitions. Second operand 48 states. [2018-10-26 19:55:24,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:24,051 INFO L93 Difference]: Finished difference Result 262 states and 303 transitions. [2018-10-26 19:55:24,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-10-26 19:55:24,051 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 192 [2018-10-26 19:55:24,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:24,053 INFO L225 Difference]: With dead ends: 262 [2018-10-26 19:55:24,053 INFO L226 Difference]: Without dead ends: 205 [2018-10-26 19:55:24,054 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 337 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-10-26 19:55:24,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-10-26 19:55:24,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 205. [2018-10-26 19:55:24,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-10-26 19:55:24,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 214 transitions. [2018-10-26 19:55:24,075 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 214 transitions. Word has length 192 [2018-10-26 19:55:24,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:24,075 INFO L481 AbstractCegarLoop]: Abstraction has 205 states and 214 transitions. [2018-10-26 19:55:24,075 INFO L482 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-10-26 19:55:24,076 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 214 transitions. [2018-10-26 19:55:24,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 265 [2018-10-26 19:55:24,081 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:24,081 INFO L375 BasicCegarLoop]: trace histogram [47, 46, 46, 21, 18, 18, 15, 5, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:24,082 INFO L424 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:24,082 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:24,082 INFO L82 PathProgramCache]: Analyzing trace with hash 454285163, now seen corresponding path program 7 times [2018-10-26 19:55:24,082 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:24,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:24,083 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:24,083 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:24,083 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:24,140 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:24,140 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:24,140 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:24,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:24,162 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:24,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:24,299 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:24,299 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:24,299 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:24,299 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:24,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:24,323 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:24,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:24,465 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:26,508 INFO L134 CoverageAnalysis]: Checked inductivity of 3961 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 764 trivial. 0 not checked. [2018-10-26 19:55:26,509 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:28,667 INFO L134 CoverageAnalysis]: Checked inductivity of 3961 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 764 trivial. 0 not checked. [2018-10-26 19:55:28,689 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:28,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 62 [2018-10-26 19:55:28,689 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:28,690 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-10-26 19:55:28,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-10-26 19:55:28,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-10-26 19:55:28,691 INFO L87 Difference]: Start difference. First operand 205 states and 214 transitions. Second operand 62 states. [2018-10-26 19:55:28,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:28,867 INFO L93 Difference]: Finished difference Result 304 states and 335 transitions. [2018-10-26 19:55:28,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-10-26 19:55:28,870 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 264 [2018-10-26 19:55:28,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:28,871 INFO L225 Difference]: With dead ends: 304 [2018-10-26 19:55:28,871 INFO L226 Difference]: Without dead ends: 247 [2018-10-26 19:55:28,873 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 527 GetRequests, 433 SyntacticMatches, 34 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1003 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-10-26 19:55:28,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-10-26 19:55:28,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2018-10-26 19:55:28,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-10-26 19:55:28,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 256 transitions. [2018-10-26 19:55:28,894 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 256 transitions. Word has length 264 [2018-10-26 19:55:28,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:28,895 INFO L481 AbstractCegarLoop]: Abstraction has 247 states and 256 transitions. [2018-10-26 19:55:28,895 INFO L482 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-10-26 19:55:28,895 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 256 transitions. [2018-10-26 19:55:28,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 307 [2018-10-26 19:55:28,897 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:28,897 INFO L375 BasicCegarLoop]: trace histogram [61, 60, 60, 21, 18, 18, 15, 5, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:28,900 INFO L424 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:28,900 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:28,900 INFO L82 PathProgramCache]: Analyzing trace with hash 532876075, now seen corresponding path program 8 times [2018-10-26 19:55:28,900 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:28,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:28,901 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:28,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:28,901 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:28,953 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:28,953 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:28,953 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:28,969 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:28,970 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:29,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:29,084 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:29,085 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:29,085 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:29,085 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:29,094 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 19:55:29,094 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 19:55:29,388 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-10-26 19:55:29,388 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:29,393 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:29,500 INFO L134 CoverageAnalysis]: Checked inductivity of 6194 backedges. 348 proven. 26 refuted. 0 times theorem prover too weak. 5820 trivial. 0 not checked. [2018-10-26 19:55:29,500 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:29,593 INFO L134 CoverageAnalysis]: Checked inductivity of 6194 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 6168 trivial. 0 not checked. [2018-10-26 19:55:29,621 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:29,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-10-26 19:55:29,621 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:29,622 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-26 19:55:29,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-26 19:55:29,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:29,622 INFO L87 Difference]: Start difference. First operand 247 states and 256 transitions. Second operand 12 states. [2018-10-26 19:55:29,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:29,670 INFO L93 Difference]: Finished difference Result 301 states and 321 transitions. [2018-10-26 19:55:29,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-10-26 19:55:29,671 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 306 [2018-10-26 19:55:29,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:29,673 INFO L225 Difference]: With dead ends: 301 [2018-10-26 19:55:29,673 INFO L226 Difference]: Without dead ends: 265 [2018-10-26 19:55:29,674 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 611 GetRequests, 601 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:29,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-10-26 19:55:29,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2018-10-26 19:55:29,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2018-10-26 19:55:29,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 274 transitions. [2018-10-26 19:55:29,693 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 274 transitions. Word has length 306 [2018-10-26 19:55:29,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:29,695 INFO L481 AbstractCegarLoop]: Abstraction has 265 states and 274 transitions. [2018-10-26 19:55:29,695 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-26 19:55:29,695 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 274 transitions. [2018-10-26 19:55:29,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 325 [2018-10-26 19:55:29,697 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:29,697 INFO L375 BasicCegarLoop]: trace histogram [61, 60, 60, 21, 18, 18, 15, 11, 10, 10, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:29,697 INFO L424 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:29,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:29,698 INFO L82 PathProgramCache]: Analyzing trace with hash 978924811, now seen corresponding path program 9 times [2018-10-26 19:55:29,698 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:29,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:29,698 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:29,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:29,699 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:29,749 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:29,749 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:29,750 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:29,765 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:29,765 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:29,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:29,906 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:29,907 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:29,907 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:29,907 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:29,921 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 19:55:29,921 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:30,150 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 19:55:30,150 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:30,160 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:30,356 INFO L134 CoverageAnalysis]: Checked inductivity of 6323 backedges. 127 proven. 3 refuted. 0 times theorem prover too weak. 6193 trivial. 0 not checked. [2018-10-26 19:55:30,357 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:30,864 INFO L134 CoverageAnalysis]: Checked inductivity of 6323 backedges. 33 proven. 349 refuted. 0 times theorem prover too weak. 5941 trivial. 0 not checked. [2018-10-26 19:55:30,886 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:30,886 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-10-26 19:55:30,886 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:30,887 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-26 19:55:30,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-26 19:55:30,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:30,887 INFO L87 Difference]: Start difference. First operand 265 states and 274 transitions. Second operand 6 states. [2018-10-26 19:55:30,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:30,913 INFO L93 Difference]: Finished difference Result 348 states and 370 transitions. [2018-10-26 19:55:30,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-26 19:55:30,914 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 324 [2018-10-26 19:55:30,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:30,915 INFO L225 Difference]: With dead ends: 348 [2018-10-26 19:55:30,915 INFO L226 Difference]: Without dead ends: 277 [2018-10-26 19:55:30,916 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 647 GetRequests, 643 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-10-26 19:55:30,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-10-26 19:55:30,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2018-10-26 19:55:30,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-10-26 19:55:30,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 286 transitions. [2018-10-26 19:55:30,934 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 286 transitions. Word has length 324 [2018-10-26 19:55:30,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:30,935 INFO L481 AbstractCegarLoop]: Abstraction has 277 states and 286 transitions. [2018-10-26 19:55:30,935 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-26 19:55:30,935 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 286 transitions. [2018-10-26 19:55:30,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-10-26 19:55:30,938 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:30,938 INFO L375 BasicCegarLoop]: trace histogram [61, 60, 60, 30, 27, 27, 15, 12, 11, 10, 10, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:30,939 INFO L424 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:30,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:30,939 INFO L82 PathProgramCache]: Analyzing trace with hash -586419466, now seen corresponding path program 10 times [2018-10-26 19:55:30,939 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:30,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:30,940 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:30,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:30,940 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:30,986 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:30,986 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:30,986 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:31,001 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:31,001 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:31,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:31,124 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:31,125 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:31,125 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:31,125 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:31,135 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:31,135 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 19:55:31,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:31,340 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:31,490 INFO L134 CoverageAnalysis]: Checked inductivity of 7169 backedges. 454 proven. 36 refuted. 0 times theorem prover too weak. 6679 trivial. 0 not checked. [2018-10-26 19:55:31,490 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:31,592 INFO L134 CoverageAnalysis]: Checked inductivity of 7169 backedges. 90 proven. 766 refuted. 0 times theorem prover too weak. 6313 trivial. 0 not checked. [2018-10-26 19:55:31,615 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:31,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-10-26 19:55:31,615 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:31,616 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-26 19:55:31,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-26 19:55:31,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:31,616 INFO L87 Difference]: Start difference. First operand 277 states and 286 transitions. Second operand 12 states. [2018-10-26 19:55:31,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:31,682 INFO L93 Difference]: Finished difference Result 384 states and 409 transitions. [2018-10-26 19:55:31,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-10-26 19:55:31,684 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 360 [2018-10-26 19:55:31,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:31,685 INFO L225 Difference]: With dead ends: 384 [2018-10-26 19:55:31,686 INFO L226 Difference]: Without dead ends: 301 [2018-10-26 19:55:31,686 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 719 GetRequests, 709 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-10-26 19:55:31,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-10-26 19:55:31,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 301. [2018-10-26 19:55:31,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 301 states. [2018-10-26 19:55:31,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 310 transitions. [2018-10-26 19:55:31,711 INFO L78 Accepts]: Start accepts. Automaton has 301 states and 310 transitions. Word has length 360 [2018-10-26 19:55:31,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:31,712 INFO L481 AbstractCegarLoop]: Abstraction has 301 states and 310 transitions. [2018-10-26 19:55:31,712 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-26 19:55:31,712 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 310 transitions. [2018-10-26 19:55:31,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 433 [2018-10-26 19:55:31,718 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:31,718 INFO L375 BasicCegarLoop]: trace histogram [61, 60, 60, 48, 45, 45, 30, 15, 11, 10, 10, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:31,718 INFO L424 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:31,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:31,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1890280372, now seen corresponding path program 11 times [2018-10-26 19:55:31,719 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:31,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:31,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:31,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:31,720 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:31,765 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:31,765 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:31,765 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:31,782 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:31,782 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:31,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:31,936 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:31,937 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:31,937 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:31,937 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:31,948 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 19:55:31,949 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:32,501 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-10-26 19:55:32,502 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:32,511 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:32,947 INFO L134 CoverageAnalysis]: Checked inductivity of 9833 backedges. 944 proven. 55 refuted. 0 times theorem prover too weak. 8834 trivial. 0 not checked. [2018-10-26 19:55:32,947 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:33,155 INFO L134 CoverageAnalysis]: Checked inductivity of 9833 backedges. 944 proven. 55 refuted. 0 times theorem prover too weak. 8834 trivial. 0 not checked. [2018-10-26 19:55:33,177 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:33,177 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2018-10-26 19:55:33,177 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:33,178 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-10-26 19:55:33,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-10-26 19:55:33,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-10-26 19:55:33,179 INFO L87 Difference]: Start difference. First operand 301 states and 310 transitions. Second operand 16 states. [2018-10-26 19:55:33,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:33,272 INFO L93 Difference]: Finished difference Result 440 states and 475 transitions. [2018-10-26 19:55:33,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-10-26 19:55:33,280 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 432 [2018-10-26 19:55:33,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:33,282 INFO L225 Difference]: With dead ends: 440 [2018-10-26 19:55:33,282 INFO L226 Difference]: Without dead ends: 333 [2018-10-26 19:55:33,283 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 863 GetRequests, 849 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-10-26 19:55:33,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-10-26 19:55:33,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 333. [2018-10-26 19:55:33,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 333 states. [2018-10-26 19:55:33,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 333 states to 333 states and 350 transitions. [2018-10-26 19:55:33,308 INFO L78 Accepts]: Start accepts. Automaton has 333 states and 350 transitions. Word has length 432 [2018-10-26 19:55:33,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:33,309 INFO L481 AbstractCegarLoop]: Abstraction has 333 states and 350 transitions. [2018-10-26 19:55:33,309 INFO L482 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-10-26 19:55:33,309 INFO L276 IsEmpty]: Start isEmpty. Operand 333 states and 350 transitions. [2018-10-26 19:55:33,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 529 [2018-10-26 19:55:33,316 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:33,317 INFO L375 BasicCegarLoop]: trace histogram [72, 69, 69, 61, 60, 60, 39, 30, 11, 10, 10, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:33,317 INFO L424 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:33,319 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:33,319 INFO L82 PathProgramCache]: Analyzing trace with hash 1074105348, now seen corresponding path program 12 times [2018-10-26 19:55:33,319 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:33,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:33,322 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:33,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:33,322 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:33,371 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:33,371 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:33,371 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:33,388 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:33,389 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-10-26 19:55:33,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:33,557 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:33,557 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:33,557 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:33,557 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:33,568 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 19:55:33,569 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:33,901 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 19:55:33,901 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:33,915 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:34,228 INFO L134 CoverageAnalysis]: Checked inductivity of 15401 backedges. 4578 proven. 903 refuted. 0 times theorem prover too weak. 9920 trivial. 0 not checked. [2018-10-26 19:55:34,228 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:35,516 INFO L134 CoverageAnalysis]: Checked inductivity of 15401 backedges. 4578 proven. 903 refuted. 0 times theorem prover too weak. 9920 trivial. 0 not checked. [2018-10-26 19:55:35,552 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:35,552 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 33 [2018-10-26 19:55:35,552 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:35,553 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-10-26 19:55:35,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-10-26 19:55:35,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-10-26 19:55:35,554 INFO L87 Difference]: Start difference. First operand 333 states and 350 transitions. Second operand 33 states. [2018-10-26 19:55:36,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:36,527 INFO L93 Difference]: Finished difference Result 556 states and 612 transitions. [2018-10-26 19:55:36,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-10-26 19:55:36,528 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 528 [2018-10-26 19:55:36,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:36,532 INFO L225 Difference]: With dead ends: 556 [2018-10-26 19:55:36,532 INFO L226 Difference]: Without dead ends: 417 [2018-10-26 19:55:36,534 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1055 GetRequests, 1011 SyntacticMatches, 13 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 195 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-10-26 19:55:36,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417 states. [2018-10-26 19:55:36,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417 to 417. [2018-10-26 19:55:36,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 417 states. [2018-10-26 19:55:36,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 434 transitions. [2018-10-26 19:55:36,569 INFO L78 Accepts]: Start accepts. Automaton has 417 states and 434 transitions. Word has length 528 [2018-10-26 19:55:36,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:36,569 INFO L481 AbstractCegarLoop]: Abstraction has 417 states and 434 transitions. [2018-10-26 19:55:36,571 INFO L482 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-10-26 19:55:36,571 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 434 transitions. [2018-10-26 19:55:36,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2018-10-26 19:55:36,578 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:36,579 INFO L375 BasicCegarLoop]: trace histogram [135, 132, 132, 93, 61, 60, 60, 39, 11, 10, 10, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:36,579 INFO L424 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:36,579 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:36,579 INFO L82 PathProgramCache]: Analyzing trace with hash 93832817, now seen corresponding path program 13 times [2018-10-26 19:55:36,580 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:36,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:36,583 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:36,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:36,583 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:36,630 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:36,630 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:36,630 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:36,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:36,642 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:36,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:36,847 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:36,848 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:36,848 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:36,848 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:36,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:36,865 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:37,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:37,141 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:39,136 INFO L134 CoverageAnalysis]: Checked inductivity of 40979 backedges. 15846 proven. 3872 refuted. 0 times theorem prover too weak. 21261 trivial. 0 not checked. [2018-10-26 19:55:39,136 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:40,773 INFO L134 CoverageAnalysis]: Checked inductivity of 40979 backedges. 0 proven. 19722 refuted. 0 times theorem prover too weak. 21257 trivial. 0 not checked. [2018-10-26 19:55:40,794 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:40,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 62 [2018-10-26 19:55:40,795 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:40,796 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-10-26 19:55:40,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-10-26 19:55:40,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-10-26 19:55:40,797 INFO L87 Difference]: Start difference. First operand 417 states and 434 transitions. Second operand 62 states. [2018-10-26 19:55:41,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:41,521 INFO L93 Difference]: Finished difference Result 704 states and 771 transitions. [2018-10-26 19:55:41,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-10-26 19:55:41,526 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 780 [2018-10-26 19:55:41,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:41,528 INFO L225 Difference]: With dead ends: 704 [2018-10-26 19:55:41,529 INFO L226 Difference]: Without dead ends: 481 [2018-10-26 19:55:41,532 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1559 GetRequests, 1469 SyntacticMatches, 30 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 885 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-10-26 19:55:41,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-10-26 19:55:41,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 481. [2018-10-26 19:55:41,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 481 states. [2018-10-26 19:55:41,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 481 states to 481 states and 514 transitions. [2018-10-26 19:55:41,564 INFO L78 Accepts]: Start accepts. Automaton has 481 states and 514 transitions. Word has length 780 [2018-10-26 19:55:41,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:41,565 INFO L481 AbstractCegarLoop]: Abstraction has 481 states and 514 transitions. [2018-10-26 19:55:41,565 INFO L482 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-10-26 19:55:41,565 INFO L276 IsEmpty]: Start isEmpty. Operand 481 states and 514 transitions. [2018-10-26 19:55:41,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 973 [2018-10-26 19:55:41,576 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:41,576 INFO L375 BasicCegarLoop]: trace histogram [183, 180, 180, 93, 87, 61, 60, 60, 11, 10, 10, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:41,577 INFO L424 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:41,577 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:41,577 INFO L82 PathProgramCache]: Analyzing trace with hash -1206460959, now seen corresponding path program 14 times [2018-10-26 19:55:41,577 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:41,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:41,580 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:41,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:41,581 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:41,634 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:41,634 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:41,635 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:41,648 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:41,648 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:41,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:41,862 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:41,862 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:41,862 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:41,862 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:41,870 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-26 19:55:41,870 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-10-26 19:55:42,346 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-10-26 19:55:42,346 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:42,358 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:43,429 INFO L134 CoverageAnalysis]: Checked inductivity of 71123 backedges. 29292 proven. 155 refuted. 0 times theorem prover too weak. 41676 trivial. 0 not checked. [2018-10-26 19:55:43,430 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:44,182 INFO L134 CoverageAnalysis]: Checked inductivity of 71123 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 70968 trivial. 0 not checked. [2018-10-26 19:55:44,204 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:44,204 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-10-26 19:55:44,204 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:44,205 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-10-26 19:55:44,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-10-26 19:55:44,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-10-26 19:55:44,206 INFO L87 Difference]: Start difference. First operand 481 states and 514 transitions. Second operand 24 states. [2018-10-26 19:55:44,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:44,352 INFO L93 Difference]: Finished difference Result 769 states and 843 transitions. [2018-10-26 19:55:44,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-10-26 19:55:44,353 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 972 [2018-10-26 19:55:44,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:44,356 INFO L225 Difference]: With dead ends: 769 [2018-10-26 19:55:44,356 INFO L226 Difference]: Without dead ends: 517 [2018-10-26 19:55:44,359 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1943 GetRequests, 1921 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-10-26 19:55:44,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-10-26 19:55:44,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 517. [2018-10-26 19:55:44,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 517 states. [2018-10-26 19:55:44,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 517 states to 517 states and 550 transitions. [2018-10-26 19:55:44,399 INFO L78 Accepts]: Start accepts. Automaton has 517 states and 550 transitions. Word has length 972 [2018-10-26 19:55:44,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:44,400 INFO L481 AbstractCegarLoop]: Abstraction has 517 states and 550 transitions. [2018-10-26 19:55:44,400 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-10-26 19:55:44,400 INFO L276 IsEmpty]: Start isEmpty. Operand 517 states and 550 transitions. [2018-10-26 19:55:44,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1009 [2018-10-26 19:55:44,412 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:44,412 INFO L375 BasicCegarLoop]: trace histogram [183, 180, 180, 93, 87, 61, 60, 60, 23, 22, 22, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:44,412 INFO L424 AbstractCegarLoop]: === Iteration 20 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:44,412 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:44,413 INFO L82 PathProgramCache]: Analyzing trace with hash -913464415, now seen corresponding path program 15 times [2018-10-26 19:55:44,413 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:44,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:44,416 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:44,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:44,416 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:44,469 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:44,470 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:44,470 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:44,485 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:44,485 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:44,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:44,763 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:44,763 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:44,763 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:44,764 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-26 19:55:44,775 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-26 19:55:44,775 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:45,274 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-26 19:55:45,274 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-26 19:55:45,296 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:46,102 INFO L134 CoverageAnalysis]: Checked inductivity of 71705 backedges. 29292 proven. 737 refuted. 0 times theorem prover too weak. 41676 trivial. 0 not checked. [2018-10-26 19:55:46,102 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:47,141 INFO L134 CoverageAnalysis]: Checked inductivity of 71705 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 70968 trivial. 0 not checked. [2018-10-26 19:55:47,164 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:47,164 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 48 [2018-10-26 19:55:47,164 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:47,165 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-10-26 19:55:47,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-10-26 19:55:47,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-10-26 19:55:47,166 INFO L87 Difference]: Start difference. First operand 517 states and 550 transitions. Second operand 48 states. [2018-10-26 19:55:47,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:47,337 INFO L93 Difference]: Finished difference Result 841 states and 927 transitions. [2018-10-26 19:55:47,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-10-26 19:55:47,338 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 1008 [2018-10-26 19:55:47,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:47,341 INFO L225 Difference]: With dead ends: 841 [2018-10-26 19:55:47,342 INFO L226 Difference]: Without dead ends: 589 [2018-10-26 19:55:47,343 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2015 GetRequests, 1969 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-10-26 19:55:47,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 589 states. [2018-10-26 19:55:47,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 589 to 589. [2018-10-26 19:55:47,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 589 states. [2018-10-26 19:55:47,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 589 states to 589 states and 622 transitions. [2018-10-26 19:55:47,387 INFO L78 Accepts]: Start accepts. Automaton has 589 states and 622 transitions. Word has length 1008 [2018-10-26 19:55:47,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:47,388 INFO L481 AbstractCegarLoop]: Abstraction has 589 states and 622 transitions. [2018-10-26 19:55:47,388 INFO L482 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-10-26 19:55:47,388 INFO L276 IsEmpty]: Start isEmpty. Operand 589 states and 622 transitions. [2018-10-26 19:55:47,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1081 [2018-10-26 19:55:47,401 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:47,403 INFO L375 BasicCegarLoop]: trace histogram [183, 180, 180, 93, 87, 61, 60, 60, 47, 46, 46, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:47,403 INFO L424 AbstractCegarLoop]: === Iteration 21 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:47,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:47,403 INFO L82 PathProgramCache]: Analyzing trace with hash -1194619103, now seen corresponding path program 16 times [2018-10-26 19:55:47,403 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:47,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:47,404 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:47,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:47,404 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:47,455 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:47,455 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:47,455 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:47,472 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:47,473 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:47,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:47,718 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-10-26 19:55:47,718 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-10-26 19:55:47,718 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-26 19:55:47,718 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-26 19:55:47,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:47,732 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-26 19:55:48,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 19:55:48,235 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-26 19:55:49,540 INFO L134 CoverageAnalysis]: Checked inductivity of 74165 backedges. 29292 proven. 3197 refuted. 0 times theorem prover too weak. 41676 trivial. 0 not checked. [2018-10-26 19:55:49,541 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-26 19:55:51,107 INFO L134 CoverageAnalysis]: Checked inductivity of 74165 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 70968 trivial. 0 not checked. [2018-10-26 19:55:51,129 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-26 19:55:51,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 61 [2018-10-26 19:55:51,130 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-26 19:55:51,131 INFO L460 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-10-26 19:55:51,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-10-26 19:55:51,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-10-26 19:55:51,132 INFO L87 Difference]: Start difference. First operand 589 states and 622 transitions. Second operand 61 states. [2018-10-26 19:55:51,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-26 19:55:51,331 INFO L93 Difference]: Finished difference Result 880 states and 955 transitions. [2018-10-26 19:55:51,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-10-26 19:55:51,332 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 1080 [2018-10-26 19:55:51,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-26 19:55:51,335 INFO L225 Difference]: With dead ends: 880 [2018-10-26 19:55:51,335 INFO L226 Difference]: Without dead ends: 628 [2018-10-26 19:55:51,337 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2159 GetRequests, 2065 SyntacticMatches, 35 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1015 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-10-26 19:55:51,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 628 states. [2018-10-26 19:55:51,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 628 to 628. [2018-10-26 19:55:51,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 628 states. [2018-10-26 19:55:51,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 628 states and 661 transitions. [2018-10-26 19:55:51,383 INFO L78 Accepts]: Start accepts. Automaton has 628 states and 661 transitions. Word has length 1080 [2018-10-26 19:55:51,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-26 19:55:51,384 INFO L481 AbstractCegarLoop]: Abstraction has 628 states and 661 transitions. [2018-10-26 19:55:51,384 INFO L482 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-10-26 19:55:51,384 INFO L276 IsEmpty]: Start isEmpty. Operand 628 states and 661 transitions. [2018-10-26 19:55:51,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1120 [2018-10-26 19:55:51,397 INFO L367 BasicCegarLoop]: Found error trace [2018-10-26 19:55:51,398 INFO L375 BasicCegarLoop]: trace histogram [183, 180, 180, 93, 87, 61, 60, 60, 60, 59, 59, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-26 19:55:51,398 INFO L424 AbstractCegarLoop]: === Iteration 22 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-10-26 19:55:51,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 19:55:51,399 INFO L82 PathProgramCache]: Analyzing trace with hash -2117153536, now seen corresponding path program 17 times [2018-10-26 19:55:51,399 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-26 19:55:51,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:51,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-26 19:55:51,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-26 19:55:51,400 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-26 19:55:51,455 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-10-26 19:55:51,455 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-10-26 19:55:51,455 INFO L171 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c3e632e4-caee-4e48-a461-bf3266300e26/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2018-10-26 19:55:51,469 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-26 19:55:51,469 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-10-26 19:55:53,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2018-10-26 19:55:53,809 INFO L285 seRefinementStrategy]: Strategy TaipanRefinementStrategy was unsuccessful and could not determine trace feasibility. [2018-10-26 19:55:53,809 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-10-26 19:55:53,927 WARN L208 ceAbstractionStarter]: Unable to decide correctness. Please check the following counterexample manually. [2018-10-26 19:55:53,928 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.10 07:55:53 BoogieIcfgContainer [2018-10-26 19:55:53,928 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-10-26 19:55:53,928 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-26 19:55:53,928 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-26 19:55:53,929 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-26 19:55:53,932 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 07:55:02" (3/4) ... [2018-10-26 19:55:53,935 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-10-26 19:55:53,935 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-26 19:55:53,936 INFO L168 Benchmark]: Toolchain (without parser) took 52848.55 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.6 GB). Free memory was 958.5 MB in the beginning and 1.1 GB in the end (delta: -92.0 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-10-26 19:55:53,937 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 19:55:53,938 INFO L168 Benchmark]: CACSL2BoogieTranslator took 235.44 ms. Allocated memory is still 1.0 GB. Free memory was 958.5 MB in the beginning and 947.7 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-10-26 19:55:53,938 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.03 ms. Allocated memory is still 1.0 GB. Free memory was 947.7 MB in the beginning and 945.0 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-10-26 19:55:53,939 INFO L168 Benchmark]: Boogie Preprocessor took 28.76 ms. Allocated memory is still 1.0 GB. Free memory is still 945.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 19:55:53,939 INFO L168 Benchmark]: RCFGBuilder took 771.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.8 MB). Free memory was 945.0 MB in the beginning and 1.1 GB in the end (delta: -186.0 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2018-10-26 19:55:53,940 INFO L168 Benchmark]: TraceAbstraction took 51761.09 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 77.9 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-10-26 19:55:53,940 INFO L168 Benchmark]: Witness Printer took 7.04 ms. Allocated memory is still 2.6 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 19:55:53,946 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 235.44 ms. Allocated memory is still 1.0 GB. Free memory was 958.5 MB in the beginning and 947.7 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.03 ms. Allocated memory is still 1.0 GB. Free memory was 947.7 MB in the beginning and 945.0 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 28.76 ms. Allocated memory is still 1.0 GB. Free memory is still 945.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 771.21 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.8 MB). Free memory was 945.0 MB in the beginning and 1.1 GB in the end (delta: -186.0 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 51761.09 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 77.9 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. * Witness Printer took 7.04 ms. Allocated memory is still 2.6 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 50]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: unable to decide satisfiability of path constraint. Possible FailurePath: [L31] CALL int x[60]; [L31] RET int x[60]; [L32] CALL init_nondet(x) [L5] int i; [L6] i = 0 [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND TRUE i < 60 [L7] CALL x[i] = __VERIFIER_nondet_int() [L7] RET x[i] = __VERIFIER_nondet_int() [L6] i++ [L6] COND FALSE, RET !(i < 60) [L32] init_nondet(x) [L33] int temp; [L34] int ret; [L35] int ret2; [L36] int ret5; [L38] CALL, EXPR rangesum(x) [L13] int i; [L14] long long ret; [L15] ret = 0 [L16] int cnt = 0; [L17] i = 0 [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND FALSE !(i < 60) [L23] COND TRUE cnt !=0 [L24] RET return ret / cnt; [L38] EXPR rangesum(x) [L38] ret = rangesum(x) [L40] CALL, EXPR x[0] [L40] RET, EXPR x[0] [L40] temp=x[0] [L40] CALL, EXPR x[1] [L40] RET, EXPR x[1] [L40] CALL x[0] = x[1] [L40] RET x[0] = x[1] [L40] CALL x[1] = temp [L40] RET x[1] = temp [L41] CALL, EXPR rangesum(x) [L13] int i; [L14] long long ret; [L15] ret = 0 [L16] int cnt = 0; [L17] i = 0 [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND FALSE !(i < 60) [L23] COND TRUE cnt !=0 [L24] RET return ret / cnt; [L41] EXPR rangesum(x) [L41] ret2 = rangesum(x) [L42] CALL, EXPR x[0] [L42] RET, EXPR x[0] [L42] temp=x[0] [L43] int i =0 ; [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND TRUE i<60 -1 [L44] CALL, EXPR x[i+1] [L44] RET, EXPR x[i+1] [L44] CALL x[i] = x[i+1] [L44] RET x[i] = x[i+1] [L43] i++ [L43] COND FALSE !(i<60 -1) [L46] CALL x[60 -1] = temp [L46] RET x[60 -1] = temp [L47] CALL, EXPR rangesum(x) [L13] int i; [L14] long long ret; [L15] ret = 0 [L16] int cnt = 0; [L17] i = 0 [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND FALSE !(i > 60/2) [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND TRUE i < 60 [L18] COND TRUE i > 60/2 [L19] CALL, EXPR x[i] [L19] RET, EXPR x[i] [L19] ret = ret + x[i] [L20] cnt = cnt + 1 [L17] i++ [L17] COND FALSE !(i < 60) [L23] COND TRUE cnt !=0 [L24] RET return ret / cnt; [L47] EXPR rangesum(x) [L47] ret5 = rangesum(x) [L49] COND TRUE ret != ret2 || ret !=ret5 [L50] __VERIFIER_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 40 locations, 1 error locations. UNKNOWN Result, 51.6s OverallTime, 22 OverallIterations, 183 TraceHistogramMax, 12.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 740 SDtfs, 941 SDslu, 2554 SDs, 0 SdLazy, 1068 SolverSat, 282 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.9s Time, PredicateUnifierStatistics: 10 DeclaredPredicates, 13965 GetRequests, 13391 SyntacticMatches, 112 SemanticMatches, 462 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3217 ImplicationChecksByTransitivity, 17.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=628occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 5.0s AbstIntTime, 6 AbstIntIterations, 5 AbstIntStrong, 0.9726047715521402 AbsIntWeakeningRatio, 1.6408163265306122 AbsIntAvgWeakeningVarsNumRemoved, 42.74285714285714 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 21 MinimizatonAttempts, 8 StatesRemovedByMinimization, 4 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.7s SsaConstructionTime, 6.3s SatisfiabilityAnalysisTime, 20.2s InterpolantComputationTime, 15085 NumberOfCodeBlocks, 13638 NumberOfCodeBlocksAsserted, 71 NumberOfCheckSat, 13684 ConstructedInterpolants, 0 QuantifiedInterpolants, 11477148 SizeOfPredicates, 18 NumberOfNonLiveVariables, 21715 ConjunctsInSsa, 276 ConjunctsInUnsatCore, 32 InterpolantComputations, 0 PerfectInterpolantSequences, 580366/623504 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...