./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i -s /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2552da43a16cb54d5090a24426eb170717bf5525 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i -s /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2552da43a16cb54d5090a24426eb170717bf5525 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: AssertionError: var is still there: v_arrayElimCell_99 term size 26 --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-27 04:46:31,829 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-27 04:46:31,830 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-27 04:46:31,840 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-27 04:46:31,840 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-27 04:46:31,841 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-27 04:46:31,842 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-27 04:46:31,843 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-27 04:46:31,844 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-27 04:46:31,845 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-27 04:46:31,846 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-27 04:46:31,846 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-27 04:46:31,846 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-27 04:46:31,847 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-27 04:46:31,848 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-27 04:46:31,849 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-27 04:46:31,849 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-27 04:46:31,850 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-27 04:46:31,852 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-27 04:46:31,853 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-27 04:46:31,854 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-27 04:46:31,855 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-27 04:46:31,857 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-27 04:46:31,857 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-27 04:46:31,857 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-27 04:46:31,858 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-27 04:46:31,859 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-27 04:46:31,859 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-27 04:46:31,860 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-27 04:46:31,861 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-27 04:46:31,861 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-27 04:46:31,862 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-27 04:46:31,862 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-27 04:46:31,862 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-27 04:46:31,863 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-27 04:46:31,863 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-27 04:46:31,864 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf [2018-10-27 04:46:31,877 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-27 04:46:31,878 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-27 04:46:31,881 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-27 04:46:31,881 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-27 04:46:31,882 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-27 04:46:31,882 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-27 04:46:31,882 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-10-27 04:46:31,882 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-27 04:46:31,882 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-10-27 04:46:31,882 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-10-27 04:46:31,882 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-27 04:46:31,883 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-27 04:46:31,883 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-27 04:46:31,883 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-10-27 04:46:31,884 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-10-27 04:46:31,885 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-27 04:46:31,885 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-27 04:46:31,885 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-27 04:46:31,885 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-27 04:46:31,885 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-27 04:46:31,888 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-27 04:46:31,888 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-27 04:46:31,889 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-27 04:46:31,889 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-27 04:46:31,889 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-10-27 04:46:31,889 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-27 04:46:31,889 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-27 04:46:31,889 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2552da43a16cb54d5090a24426eb170717bf5525 [2018-10-27 04:46:31,926 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-27 04:46:31,939 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-27 04:46:31,941 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-27 04:46:31,943 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-27 04:46:31,943 INFO L276 PluginConnector]: CDTParser initialized [2018-10-27 04:46:31,944 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/../../sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i [2018-10-27 04:46:31,990 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/b002ea342/b0f4dcdaeb2f488699e39482808bb2ed/FLAGb2c5af034 [2018-10-27 04:46:32,403 INFO L298 CDTParser]: Found 1 translation units. [2018-10-27 04:46:32,404 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i [2018-10-27 04:46:32,415 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/b002ea342/b0f4dcdaeb2f488699e39482808bb2ed/FLAGb2c5af034 [2018-10-27 04:46:32,425 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/b002ea342/b0f4dcdaeb2f488699e39482808bb2ed [2018-10-27 04:46:32,427 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-27 04:46:32,428 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-27 04:46:32,429 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-27 04:46:32,429 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-27 04:46:32,432 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-27 04:46:32,433 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,435 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@19d317e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32, skipping insertion in model container [2018-10-27 04:46:32,435 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,443 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-27 04:46:32,474 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-27 04:46:32,732 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 04:46:32,746 INFO L189 MainTranslator]: Completed pre-run [2018-10-27 04:46:32,797 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 04:46:32,843 INFO L193 MainTranslator]: Completed translation [2018-10-27 04:46:32,843 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32 WrapperNode [2018-10-27 04:46:32,843 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-27 04:46:32,844 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-27 04:46:32,844 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-27 04:46:32,844 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-27 04:46:32,852 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,871 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,964 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-27 04:46:32,968 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-27 04:46:32,968 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-27 04:46:32,969 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-27 04:46:32,977 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,977 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,984 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:32,986 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:33,016 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:33,020 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:33,022 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... [2018-10-27 04:46:33,025 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-27 04:46:33,026 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-27 04:46:33,026 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-27 04:46:33,026 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-27 04:46:33,027 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-27 04:46:33,081 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-27 04:46:33,082 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-27 04:46:33,082 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-27 04:46:33,082 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-27 04:46:33,082 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-27 04:46:33,082 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-27 04:46:33,083 INFO L130 BoogieDeclarations]: Found specification of procedure append [2018-10-27 04:46:33,083 INFO L138 BoogieDeclarations]: Found implementation of procedure append [2018-10-27 04:46:34,106 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-27 04:46:34,106 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:46:34 BoogieIcfgContainer [2018-10-27 04:46:34,107 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-27 04:46:34,107 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-27 04:46:34,107 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-27 04:46:34,111 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-27 04:46:34,111 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.10 04:46:32" (1/3) ... [2018-10-27 04:46:34,112 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@66b27e10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.10 04:46:34, skipping insertion in model container [2018-10-27 04:46:34,112 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:46:32" (2/3) ... [2018-10-27 04:46:34,112 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@66b27e10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.10 04:46:34, skipping insertion in model container [2018-10-27 04:46:34,113 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:46:34" (3/3) ... [2018-10-27 04:46:34,115 INFO L112 eAbstractionObserver]: Analyzing ICFG length_test03_false-valid-memtrack.i [2018-10-27 04:46:34,124 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-27 04:46:34,132 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 55 error locations. [2018-10-27 04:46:34,148 INFO L257 AbstractCegarLoop]: Starting to check reachability of 55 error locations. [2018-10-27 04:46:34,175 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-27 04:46:34,175 INFO L383 AbstractCegarLoop]: Hoare is false [2018-10-27 04:46:34,175 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-27 04:46:34,175 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-27 04:46:34,176 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-27 04:46:34,178 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-27 04:46:34,178 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-27 04:46:34,178 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-27 04:46:34,199 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states. [2018-10-27 04:46:34,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-10-27 04:46:34,213 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:34,214 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:34,216 INFO L424 AbstractCegarLoop]: === Iteration 1 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:34,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:34,227 INFO L82 PathProgramCache]: Analyzing trace with hash 1984049023, now seen corresponding path program 1 times [2018-10-27 04:46:34,229 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:34,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:34,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:34,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:34,276 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:34,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:34,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:34,400 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:34,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:46:34,400 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:34,403 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:46:34,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:46:34,412 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:34,413 INFO L87 Difference]: Start difference. First operand 141 states. Second operand 3 states. [2018-10-27 04:46:34,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:34,736 INFO L93 Difference]: Finished difference Result 141 states and 148 transitions. [2018-10-27 04:46:34,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:46:34,738 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-10-27 04:46:34,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:34,748 INFO L225 Difference]: With dead ends: 141 [2018-10-27 04:46:34,748 INFO L226 Difference]: Without dead ends: 138 [2018-10-27 04:46:34,750 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:34,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-10-27 04:46:34,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 136. [2018-10-27 04:46:34,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-10-27 04:46:34,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 142 transitions. [2018-10-27 04:46:34,794 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 142 transitions. Word has length 7 [2018-10-27 04:46:34,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:34,794 INFO L481 AbstractCegarLoop]: Abstraction has 136 states and 142 transitions. [2018-10-27 04:46:34,795 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:46:34,795 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 142 transitions. [2018-10-27 04:46:34,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-10-27 04:46:34,795 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:34,795 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:34,796 INFO L424 AbstractCegarLoop]: === Iteration 2 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:34,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:34,797 INFO L82 PathProgramCache]: Analyzing trace with hash 1375977608, now seen corresponding path program 1 times [2018-10-27 04:46:34,797 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:34,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:34,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:34,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:34,800 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:34,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:34,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:34,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:34,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:46:34,872 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:34,874 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:46:34,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:46:34,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:34,874 INFO L87 Difference]: Start difference. First operand 136 states and 142 transitions. Second operand 3 states. [2018-10-27 04:46:35,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:35,076 INFO L93 Difference]: Finished difference Result 134 states and 140 transitions. [2018-10-27 04:46:35,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:46:35,078 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-10-27 04:46:35,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:35,079 INFO L225 Difference]: With dead ends: 134 [2018-10-27 04:46:35,079 INFO L226 Difference]: Without dead ends: 134 [2018-10-27 04:46:35,080 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:35,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-10-27 04:46:35,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-10-27 04:46:35,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-10-27 04:46:35,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 140 transitions. [2018-10-27 04:46:35,089 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 140 transitions. Word has length 8 [2018-10-27 04:46:35,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:35,089 INFO L481 AbstractCegarLoop]: Abstraction has 134 states and 140 transitions. [2018-10-27 04:46:35,089 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:46:35,090 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 140 transitions. [2018-10-27 04:46:35,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-10-27 04:46:35,091 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:35,091 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:35,092 INFO L424 AbstractCegarLoop]: === Iteration 3 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:35,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:35,092 INFO L82 PathProgramCache]: Analyzing trace with hash -294367071, now seen corresponding path program 1 times [2018-10-27 04:46:35,092 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:35,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:35,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:35,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:35,093 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:35,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:35,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:35,171 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:35,171 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:46:35,171 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:35,172 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:46:35,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:46:35,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:46:35,172 INFO L87 Difference]: Start difference. First operand 134 states and 140 transitions. Second operand 5 states. [2018-10-27 04:46:35,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:35,713 INFO L93 Difference]: Finished difference Result 135 states and 142 transitions. [2018-10-27 04:46:35,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:46:35,715 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 9 [2018-10-27 04:46:35,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:35,716 INFO L225 Difference]: With dead ends: 135 [2018-10-27 04:46:35,716 INFO L226 Difference]: Without dead ends: 135 [2018-10-27 04:46:35,717 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-10-27 04:46:35,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-10-27 04:46:35,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 133. [2018-10-27 04:46:35,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-10-27 04:46:35,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 139 transitions. [2018-10-27 04:46:35,723 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 139 transitions. Word has length 9 [2018-10-27 04:46:35,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:35,723 INFO L481 AbstractCegarLoop]: Abstraction has 133 states and 139 transitions. [2018-10-27 04:46:35,723 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:46:35,723 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 139 transitions. [2018-10-27 04:46:35,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-10-27 04:46:35,724 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:35,724 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:35,725 INFO L424 AbstractCegarLoop]: === Iteration 4 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:35,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:35,728 INFO L82 PathProgramCache]: Analyzing trace with hash -535444566, now seen corresponding path program 1 times [2018-10-27 04:46:35,728 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:35,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:35,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:35,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:35,729 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:35,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:35,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:35,823 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:35,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:46:35,823 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:35,823 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:46:35,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:46:35,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:46:35,824 INFO L87 Difference]: Start difference. First operand 133 states and 139 transitions. Second operand 4 states. [2018-10-27 04:46:36,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:36,002 INFO L93 Difference]: Finished difference Result 132 states and 138 transitions. [2018-10-27 04:46:36,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:46:36,005 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 10 [2018-10-27 04:46:36,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:36,006 INFO L225 Difference]: With dead ends: 132 [2018-10-27 04:46:36,006 INFO L226 Difference]: Without dead ends: 132 [2018-10-27 04:46:36,006 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:46:36,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-10-27 04:46:36,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2018-10-27 04:46:36,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-10-27 04:46:36,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 138 transitions. [2018-10-27 04:46:36,017 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 138 transitions. Word has length 10 [2018-10-27 04:46:36,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:36,017 INFO L481 AbstractCegarLoop]: Abstraction has 132 states and 138 transitions. [2018-10-27 04:46:36,017 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:46:36,017 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 138 transitions. [2018-10-27 04:46:36,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-10-27 04:46:36,018 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:36,018 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:36,019 INFO L424 AbstractCegarLoop]: === Iteration 5 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:36,019 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:36,025 INFO L82 PathProgramCache]: Analyzing trace with hash 79516389, now seen corresponding path program 1 times [2018-10-27 04:46:36,026 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:36,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,027 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:36,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,027 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:36,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:36,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:36,109 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:36,109 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:46:36,109 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:36,110 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:46:36,110 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:46:36,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:46:36,111 INFO L87 Difference]: Start difference. First operand 132 states and 138 transitions. Second operand 5 states. [2018-10-27 04:46:36,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:36,260 INFO L93 Difference]: Finished difference Result 133 states and 140 transitions. [2018-10-27 04:46:36,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:46:36,260 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 13 [2018-10-27 04:46:36,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:36,261 INFO L225 Difference]: With dead ends: 133 [2018-10-27 04:46:36,261 INFO L226 Difference]: Without dead ends: 133 [2018-10-27 04:46:36,262 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:46:36,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-10-27 04:46:36,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 131. [2018-10-27 04:46:36,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-10-27 04:46:36,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 137 transitions. [2018-10-27 04:46:36,270 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 137 transitions. Word has length 13 [2018-10-27 04:46:36,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:36,275 INFO L481 AbstractCegarLoop]: Abstraction has 131 states and 137 transitions. [2018-10-27 04:46:36,275 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:46:36,275 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 137 transitions. [2018-10-27 04:46:36,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-27 04:46:36,276 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:36,276 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:36,276 INFO L424 AbstractCegarLoop]: === Iteration 6 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:36,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:36,277 INFO L82 PathProgramCache]: Analyzing trace with hash -1829959186, now seen corresponding path program 1 times [2018-10-27 04:46:36,277 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:36,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,278 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:36,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,278 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:36,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:36,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:36,360 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:36,361 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:46:36,361 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:36,361 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:46:36,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:46:36,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:46:36,361 INFO L87 Difference]: Start difference. First operand 131 states and 137 transitions. Second operand 4 states. [2018-10-27 04:46:36,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:36,560 INFO L93 Difference]: Finished difference Result 132 states and 139 transitions. [2018-10-27 04:46:36,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:46:36,560 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-10-27 04:46:36,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:36,561 INFO L225 Difference]: With dead ends: 132 [2018-10-27 04:46:36,561 INFO L226 Difference]: Without dead ends: 132 [2018-10-27 04:46:36,561 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:46:36,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-10-27 04:46:36,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 130. [2018-10-27 04:46:36,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-10-27 04:46:36,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 136 transitions. [2018-10-27 04:46:36,568 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 136 transitions. Word has length 14 [2018-10-27 04:46:36,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:36,569 INFO L481 AbstractCegarLoop]: Abstraction has 130 states and 136 transitions. [2018-10-27 04:46:36,569 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:46:36,569 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 136 transitions. [2018-10-27 04:46:36,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-10-27 04:46:36,571 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:36,571 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:36,572 INFO L424 AbstractCegarLoop]: === Iteration 7 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:36,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:36,573 INFO L82 PathProgramCache]: Analyzing trace with hash -529089576, now seen corresponding path program 1 times [2018-10-27 04:46:36,573 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:36,574 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,574 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:36,574 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,574 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:36,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:36,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:36,631 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:36,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:46:36,632 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:36,632 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:46:36,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:46:36,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:36,633 INFO L87 Difference]: Start difference. First operand 130 states and 136 transitions. Second operand 3 states. [2018-10-27 04:46:36,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:36,735 INFO L93 Difference]: Finished difference Result 129 states and 135 transitions. [2018-10-27 04:46:36,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:46:36,736 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2018-10-27 04:46:36,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:36,737 INFO L225 Difference]: With dead ends: 129 [2018-10-27 04:46:36,737 INFO L226 Difference]: Without dead ends: 129 [2018-10-27 04:46:36,737 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:36,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-10-27 04:46:36,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 129. [2018-10-27 04:46:36,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-10-27 04:46:36,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 135 transitions. [2018-10-27 04:46:36,742 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 135 transitions. Word has length 18 [2018-10-27 04:46:36,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:36,743 INFO L481 AbstractCegarLoop]: Abstraction has 129 states and 135 transitions. [2018-10-27 04:46:36,743 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:46:36,743 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 135 transitions. [2018-10-27 04:46:36,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-10-27 04:46:36,743 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:36,744 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:36,747 INFO L424 AbstractCegarLoop]: === Iteration 8 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:36,747 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:36,747 INFO L82 PathProgramCache]: Analyzing trace with hash 778092487, now seen corresponding path program 1 times [2018-10-27 04:46:36,747 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:36,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:36,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,748 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:36,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:36,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:36,809 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:36,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:46:36,809 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:36,809 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:46:36,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:46:36,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:36,810 INFO L87 Difference]: Start difference. First operand 129 states and 135 transitions. Second operand 3 states. [2018-10-27 04:46:36,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:36,912 INFO L93 Difference]: Finished difference Result 128 states and 134 transitions. [2018-10-27 04:46:36,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:46:36,912 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-10-27 04:46:36,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:36,913 INFO L225 Difference]: With dead ends: 128 [2018-10-27 04:46:36,913 INFO L226 Difference]: Without dead ends: 128 [2018-10-27 04:46:36,914 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:36,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-10-27 04:46:36,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2018-10-27 04:46:36,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-10-27 04:46:36,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 134 transitions. [2018-10-27 04:46:36,917 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 134 transitions. Word has length 19 [2018-10-27 04:46:36,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:36,917 INFO L481 AbstractCegarLoop]: Abstraction has 128 states and 134 transitions. [2018-10-27 04:46:36,917 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:46:36,917 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 134 transitions. [2018-10-27 04:46:36,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-10-27 04:46:36,921 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:36,921 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:36,922 INFO L424 AbstractCegarLoop]: === Iteration 9 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:36,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:36,922 INFO L82 PathProgramCache]: Analyzing trace with hash -1648936518, now seen corresponding path program 1 times [2018-10-27 04:46:36,922 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:36,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,923 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:36,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,923 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:36,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:37,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:37,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:37,136 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-27 04:46:37,136 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:37,136 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-27 04:46:37,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-27 04:46:37,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-10-27 04:46:37,137 INFO L87 Difference]: Start difference. First operand 128 states and 134 transitions. Second operand 9 states. [2018-10-27 04:46:37,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:37,472 INFO L93 Difference]: Finished difference Result 225 states and 236 transitions. [2018-10-27 04:46:37,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:46:37,473 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 20 [2018-10-27 04:46:37,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:37,474 INFO L225 Difference]: With dead ends: 225 [2018-10-27 04:46:37,474 INFO L226 Difference]: Without dead ends: 225 [2018-10-27 04:46:37,474 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-10-27 04:46:37,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-10-27 04:46:37,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 159. [2018-10-27 04:46:37,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-10-27 04:46:37,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 186 transitions. [2018-10-27 04:46:37,481 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 186 transitions. Word has length 20 [2018-10-27 04:46:37,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:37,481 INFO L481 AbstractCegarLoop]: Abstraction has 159 states and 186 transitions. [2018-10-27 04:46:37,481 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-27 04:46:37,481 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 186 transitions. [2018-10-27 04:46:37,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-10-27 04:46:37,481 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:37,482 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:37,482 INFO L424 AbstractCegarLoop]: === Iteration 10 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:37,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:37,483 INFO L82 PathProgramCache]: Analyzing trace with hash 422575657, now seen corresponding path program 1 times [2018-10-27 04:46:37,483 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:37,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:37,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:37,483 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:37,484 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:37,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:37,687 WARN L179 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-27 04:46:37,859 WARN L179 SmtUtils]: Spent 121.00 ms on a formula simplification that was a NOOP. DAG size: 15 [2018-10-27 04:46:37,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:37,963 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:37,963 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-10-27 04:46:37,963 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:37,964 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-10-27 04:46:37,964 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-10-27 04:46:37,964 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-10-27 04:46:37,964 INFO L87 Difference]: Start difference. First operand 159 states and 186 transitions. Second operand 9 states. [2018-10-27 04:46:39,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:39,047 INFO L93 Difference]: Finished difference Result 249 states and 260 transitions. [2018-10-27 04:46:39,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:46:39,048 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 21 [2018-10-27 04:46:39,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:39,048 INFO L225 Difference]: With dead ends: 249 [2018-10-27 04:46:39,049 INFO L226 Difference]: Without dead ends: 249 [2018-10-27 04:46:39,049 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-10-27 04:46:39,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-10-27 04:46:39,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 188. [2018-10-27 04:46:39,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-10-27 04:46:39,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 235 transitions. [2018-10-27 04:46:39,054 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 235 transitions. Word has length 21 [2018-10-27 04:46:39,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:39,055 INFO L481 AbstractCegarLoop]: Abstraction has 188 states and 235 transitions. [2018-10-27 04:46:39,055 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-10-27 04:46:39,055 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 235 transitions. [2018-10-27 04:46:39,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-27 04:46:39,055 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:39,056 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:39,056 INFO L424 AbstractCegarLoop]: === Iteration 11 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:39,057 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:39,057 INFO L82 PathProgramCache]: Analyzing trace with hash 402418015, now seen corresponding path program 1 times [2018-10-27 04:46:39,057 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:39,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:39,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:39,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:39,062 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:39,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:39,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:39,306 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:39,307 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-10-27 04:46:39,307 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:39,307 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-27 04:46:39,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-27 04:46:39,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-10-27 04:46:39,307 INFO L87 Difference]: Start difference. First operand 188 states and 235 transitions. Second operand 10 states. [2018-10-27 04:46:39,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:39,980 INFO L93 Difference]: Finished difference Result 246 states and 257 transitions. [2018-10-27 04:46:39,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-27 04:46:39,982 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 24 [2018-10-27 04:46:39,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:39,982 INFO L225 Difference]: With dead ends: 246 [2018-10-27 04:46:39,983 INFO L226 Difference]: Without dead ends: 246 [2018-10-27 04:46:39,983 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2018-10-27 04:46:39,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-10-27 04:46:39,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 188. [2018-10-27 04:46:39,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-10-27 04:46:39,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 232 transitions. [2018-10-27 04:46:39,987 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 232 transitions. Word has length 24 [2018-10-27 04:46:39,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:39,988 INFO L481 AbstractCegarLoop]: Abstraction has 188 states and 232 transitions. [2018-10-27 04:46:39,988 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-27 04:46:39,988 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 232 transitions. [2018-10-27 04:46:39,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-27 04:46:39,988 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:39,989 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:39,993 INFO L424 AbstractCegarLoop]: === Iteration 12 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:39,993 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:39,993 INFO L82 PathProgramCache]: Analyzing trace with hash 402424037, now seen corresponding path program 1 times [2018-10-27 04:46:39,993 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:39,994 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:39,994 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:39,994 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:39,994 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:40,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:40,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:40,063 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:40,063 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:46:40,063 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:40,064 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:46:40,064 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:46:40,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:40,064 INFO L87 Difference]: Start difference. First operand 188 states and 232 transitions. Second operand 3 states. [2018-10-27 04:46:40,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:40,117 INFO L93 Difference]: Finished difference Result 190 states and 234 transitions. [2018-10-27 04:46:40,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:46:40,118 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2018-10-27 04:46:40,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:40,119 INFO L225 Difference]: With dead ends: 190 [2018-10-27 04:46:40,119 INFO L226 Difference]: Without dead ends: 190 [2018-10-27 04:46:40,119 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:40,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2018-10-27 04:46:40,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 190. [2018-10-27 04:46:40,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-10-27 04:46:40,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 234 transitions. [2018-10-27 04:46:40,123 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 234 transitions. Word has length 24 [2018-10-27 04:46:40,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:40,124 INFO L481 AbstractCegarLoop]: Abstraction has 190 states and 234 transitions. [2018-10-27 04:46:40,124 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:46:40,124 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 234 transitions. [2018-10-27 04:46:40,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-27 04:46:40,125 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:40,125 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:40,126 INFO L424 AbstractCegarLoop]: === Iteration 13 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:40,126 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:40,126 INFO L82 PathProgramCache]: Analyzing trace with hash 176661409, now seen corresponding path program 1 times [2018-10-27 04:46:40,126 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:40,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:40,126 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:40,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:40,126 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:40,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:40,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:40,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:40,398 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:46:40,399 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:40,399 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:46:40,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:46:40,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:46:40,399 INFO L87 Difference]: Start difference. First operand 190 states and 234 transitions. Second operand 5 states. [2018-10-27 04:46:40,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:40,756 INFO L93 Difference]: Finished difference Result 184 states and 225 transitions. [2018-10-27 04:46:40,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:46:40,756 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-10-27 04:46:40,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:40,757 INFO L225 Difference]: With dead ends: 184 [2018-10-27 04:46:40,757 INFO L226 Difference]: Without dead ends: 184 [2018-10-27 04:46:40,757 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-10-27 04:46:40,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-10-27 04:46:40,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 184. [2018-10-27 04:46:40,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-10-27 04:46:40,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 225 transitions. [2018-10-27 04:46:40,760 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 225 transitions. Word has length 26 [2018-10-27 04:46:40,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:40,760 INFO L481 AbstractCegarLoop]: Abstraction has 184 states and 225 transitions. [2018-10-27 04:46:40,760 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:46:40,761 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 225 transitions. [2018-10-27 04:46:40,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-27 04:46:40,761 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:40,761 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:40,764 INFO L424 AbstractCegarLoop]: === Iteration 14 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:40,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:40,764 INFO L82 PathProgramCache]: Analyzing trace with hash 182972007, now seen corresponding path program 1 times [2018-10-27 04:46:40,764 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:40,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:40,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:40,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:40,765 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:40,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:41,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:41,021 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:41,022 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 04:46:41,022 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:41,022 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-27 04:46:41,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-27 04:46:41,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:46:41,022 INFO L87 Difference]: Start difference. First operand 184 states and 225 transitions. Second operand 6 states. [2018-10-27 04:46:41,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:41,175 INFO L93 Difference]: Finished difference Result 180 states and 217 transitions. [2018-10-27 04:46:41,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:46:41,177 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-10-27 04:46:41,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:41,178 INFO L225 Difference]: With dead ends: 180 [2018-10-27 04:46:41,178 INFO L226 Difference]: Without dead ends: 180 [2018-10-27 04:46:41,178 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-10-27 04:46:41,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-10-27 04:46:41,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-10-27 04:46:41,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-10-27 04:46:41,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 217 transitions. [2018-10-27 04:46:41,181 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 217 transitions. Word has length 26 [2018-10-27 04:46:41,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:41,182 INFO L481 AbstractCegarLoop]: Abstraction has 180 states and 217 transitions. [2018-10-27 04:46:41,182 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-27 04:46:41,183 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 217 transitions. [2018-10-27 04:46:41,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-10-27 04:46:41,184 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:41,184 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:41,185 INFO L424 AbstractCegarLoop]: === Iteration 15 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:41,185 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:41,185 INFO L82 PathProgramCache]: Analyzing trace with hash 1181536563, now seen corresponding path program 1 times [2018-10-27 04:46:41,185 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:41,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:41,186 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:41,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:41,186 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:41,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:41,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:41,314 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:41,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:46:41,314 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:41,314 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:46:41,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:46:41,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:46:41,315 INFO L87 Difference]: Start difference. First operand 180 states and 217 transitions. Second operand 8 states. [2018-10-27 04:46:41,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:41,516 INFO L93 Difference]: Finished difference Result 189 states and 217 transitions. [2018-10-27 04:46:41,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:46:41,517 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-10-27 04:46:41,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:41,518 INFO L225 Difference]: With dead ends: 189 [2018-10-27 04:46:41,518 INFO L226 Difference]: Without dead ends: 189 [2018-10-27 04:46:41,518 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:46:41,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-10-27 04:46:41,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 150. [2018-10-27 04:46:41,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-10-27 04:46:41,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 165 transitions. [2018-10-27 04:46:41,522 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 165 transitions. Word has length 27 [2018-10-27 04:46:41,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:41,522 INFO L481 AbstractCegarLoop]: Abstraction has 150 states and 165 transitions. [2018-10-27 04:46:41,522 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:46:41,522 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 165 transitions. [2018-10-27 04:46:41,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-10-27 04:46:41,523 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:41,523 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:41,523 INFO L424 AbstractCegarLoop]: === Iteration 16 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:41,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:41,524 INFO L82 PathProgramCache]: Analyzing trace with hash 1377165122, now seen corresponding path program 1 times [2018-10-27 04:46:41,524 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:41,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:41,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:41,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:41,525 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:41,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:41,694 WARN L179 SmtUtils]: Spent 103.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-27 04:46:41,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:41,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:41,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:46:41,979 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:41,979 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:46:41,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:46:41,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:46:41,980 INFO L87 Difference]: Start difference. First operand 150 states and 165 transitions. Second operand 5 states. [2018-10-27 04:46:42,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:42,088 INFO L93 Difference]: Finished difference Result 148 states and 161 transitions. [2018-10-27 04:46:42,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:46:42,089 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-10-27 04:46:42,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:42,089 INFO L225 Difference]: With dead ends: 148 [2018-10-27 04:46:42,089 INFO L226 Difference]: Without dead ends: 148 [2018-10-27 04:46:42,090 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:46:42,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-10-27 04:46:42,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2018-10-27 04:46:42,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-10-27 04:46:42,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 161 transitions. [2018-10-27 04:46:42,093 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 161 transitions. Word has length 27 [2018-10-27 04:46:42,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:42,093 INFO L481 AbstractCegarLoop]: Abstraction has 148 states and 161 transitions. [2018-10-27 04:46:42,093 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:46:42,093 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 161 transitions. [2018-10-27 04:46:42,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-10-27 04:46:42,094 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:42,094 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:42,094 INFO L424 AbstractCegarLoop]: === Iteration 17 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:42,094 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:42,095 INFO L82 PathProgramCache]: Analyzing trace with hash 1585276725, now seen corresponding path program 1 times [2018-10-27 04:46:42,095 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:42,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:42,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,096 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:42,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:42,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:42,253 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:42,253 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:46:42,253 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:42,254 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:46:42,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:46:42,254 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:46:42,254 INFO L87 Difference]: Start difference. First operand 148 states and 161 transitions. Second operand 8 states. [2018-10-27 04:46:42,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:42,419 INFO L93 Difference]: Finished difference Result 156 states and 163 transitions. [2018-10-27 04:46:42,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:46:42,422 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-10-27 04:46:42,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:42,423 INFO L225 Difference]: With dead ends: 156 [2018-10-27 04:46:42,423 INFO L226 Difference]: Without dead ends: 156 [2018-10-27 04:46:42,424 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:46:42,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-10-27 04:46:42,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 148. [2018-10-27 04:46:42,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-10-27 04:46:42,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 159 transitions. [2018-10-27 04:46:42,426 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 159 transitions. Word has length 29 [2018-10-27 04:46:42,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:42,427 INFO L481 AbstractCegarLoop]: Abstraction has 148 states and 159 transitions. [2018-10-27 04:46:42,427 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:46:42,427 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 159 transitions. [2018-10-27 04:46:42,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-10-27 04:46:42,427 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:42,427 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:42,428 INFO L424 AbstractCegarLoop]: === Iteration 18 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:42,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:42,428 INFO L82 PathProgramCache]: Analyzing trace with hash 605761572, now seen corresponding path program 1 times [2018-10-27 04:46:42,428 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:42,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:42,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,429 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:42,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:42,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:42,518 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:42,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 04:46:42,518 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:42,519 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-27 04:46:42,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-27 04:46:42,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:46:42,519 INFO L87 Difference]: Start difference. First operand 148 states and 159 transitions. Second operand 6 states. [2018-10-27 04:46:42,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:42,651 INFO L93 Difference]: Finished difference Result 150 states and 159 transitions. [2018-10-27 04:46:42,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:46:42,652 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 29 [2018-10-27 04:46:42,652 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:42,653 INFO L225 Difference]: With dead ends: 150 [2018-10-27 04:46:42,653 INFO L226 Difference]: Without dead ends: 150 [2018-10-27 04:46:42,653 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:46:42,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-10-27 04:46:42,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 146. [2018-10-27 04:46:42,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-10-27 04:46:42,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 155 transitions. [2018-10-27 04:46:42,657 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 155 transitions. Word has length 29 [2018-10-27 04:46:42,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:42,657 INFO L481 AbstractCegarLoop]: Abstraction has 146 states and 155 transitions. [2018-10-27 04:46:42,660 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-27 04:46:42,660 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 155 transitions. [2018-10-27 04:46:42,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-27 04:46:42,661 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:42,661 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:42,662 INFO L424 AbstractCegarLoop]: === Iteration 19 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:42,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:42,662 INFO L82 PathProgramCache]: Analyzing trace with hash -1209380723, now seen corresponding path program 1 times [2018-10-27 04:46:42,662 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:42,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:42,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,663 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:42,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:42,862 WARN L179 SmtUtils]: Spent 124.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-10-27 04:46:43,089 WARN L179 SmtUtils]: Spent 163.00 ms on a formula simplification that was a NOOP. DAG size: 16 [2018-10-27 04:46:43,322 WARN L179 SmtUtils]: Spent 163.00 ms on a formula simplification that was a NOOP. DAG size: 21 [2018-10-27 04:46:43,527 WARN L179 SmtUtils]: Spent 109.00 ms on a formula simplification that was a NOOP. DAG size: 18 [2018-10-27 04:46:43,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:43,582 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:43,582 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-10-27 04:46:43,582 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:43,582 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-27 04:46:43,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-27 04:46:43,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:46:43,583 INFO L87 Difference]: Start difference. First operand 146 states and 155 transitions. Second operand 12 states. [2018-10-27 04:46:43,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:43,908 INFO L93 Difference]: Finished difference Result 163 states and 174 transitions. [2018-10-27 04:46:43,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-10-27 04:46:43,909 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 32 [2018-10-27 04:46:43,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:43,909 INFO L225 Difference]: With dead ends: 163 [2018-10-27 04:46:43,909 INFO L226 Difference]: Without dead ends: 163 [2018-10-27 04:46:43,910 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2018-10-27 04:46:43,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-10-27 04:46:43,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 154. [2018-10-27 04:46:43,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-10-27 04:46:43,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 164 transitions. [2018-10-27 04:46:43,913 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 164 transitions. Word has length 32 [2018-10-27 04:46:43,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:43,914 INFO L481 AbstractCegarLoop]: Abstraction has 154 states and 164 transitions. [2018-10-27 04:46:43,914 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-27 04:46:43,914 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 164 transitions. [2018-10-27 04:46:43,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-27 04:46:43,914 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:43,914 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:43,915 INFO L424 AbstractCegarLoop]: === Iteration 20 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:43,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:43,915 INFO L82 PathProgramCache]: Analyzing trace with hash -394987703, now seen corresponding path program 1 times [2018-10-27 04:46:43,915 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:43,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:43,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:43,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:43,916 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:43,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:44,214 WARN L179 SmtUtils]: Spent 215.00 ms on a formula simplification. DAG size of input: 10 DAG size of output: 9 [2018-10-27 04:46:44,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:44,448 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:44,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-10-27 04:46:44,448 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:44,448 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-10-27 04:46:44,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-10-27 04:46:44,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2018-10-27 04:46:44,449 INFO L87 Difference]: Start difference. First operand 154 states and 164 transitions. Second operand 13 states. [2018-10-27 04:46:44,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:44,736 INFO L93 Difference]: Finished difference Result 159 states and 169 transitions. [2018-10-27 04:46:44,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-10-27 04:46:44,737 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 34 [2018-10-27 04:46:44,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:44,738 INFO L225 Difference]: With dead ends: 159 [2018-10-27 04:46:44,738 INFO L226 Difference]: Without dead ends: 159 [2018-10-27 04:46:44,738 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=59, Invalid=247, Unknown=0, NotChecked=0, Total=306 [2018-10-27 04:46:44,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-10-27 04:46:44,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 157. [2018-10-27 04:46:44,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-10-27 04:46:44,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 167 transitions. [2018-10-27 04:46:44,741 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 167 transitions. Word has length 34 [2018-10-27 04:46:44,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:44,742 INFO L481 AbstractCegarLoop]: Abstraction has 157 states and 167 transitions. [2018-10-27 04:46:44,742 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-10-27 04:46:44,742 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 167 transitions. [2018-10-27 04:46:44,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-27 04:46:44,742 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:44,742 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:44,743 INFO L424 AbstractCegarLoop]: === Iteration 21 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:44,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:44,743 INFO L82 PathProgramCache]: Analyzing trace with hash 226936518, now seen corresponding path program 1 times [2018-10-27 04:46:44,743 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:44,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:44,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:44,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:44,744 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:44,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:44,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:44,823 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:46:44,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:46:44,823 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:46:44,823 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:46:44,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:46:44,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:44,824 INFO L87 Difference]: Start difference. First operand 157 states and 167 transitions. Second operand 3 states. [2018-10-27 04:46:44,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:44,836 INFO L93 Difference]: Finished difference Result 172 states and 183 transitions. [2018-10-27 04:46:44,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:46:44,837 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2018-10-27 04:46:44,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:44,838 INFO L225 Difference]: With dead ends: 172 [2018-10-27 04:46:44,838 INFO L226 Difference]: Without dead ends: 172 [2018-10-27 04:46:44,838 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:46:44,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-10-27 04:46:44,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 161. [2018-10-27 04:46:44,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-10-27 04:46:44,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 171 transitions. [2018-10-27 04:46:44,840 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 171 transitions. Word has length 42 [2018-10-27 04:46:44,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:44,841 INFO L481 AbstractCegarLoop]: Abstraction has 161 states and 171 transitions. [2018-10-27 04:46:44,841 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:46:44,841 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 171 transitions. [2018-10-27 04:46:44,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-27 04:46:44,841 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:44,843 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:44,843 INFO L424 AbstractCegarLoop]: === Iteration 22 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:44,843 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:44,843 INFO L82 PathProgramCache]: Analyzing trace with hash 577923455, now seen corresponding path program 1 times [2018-10-27 04:46:44,843 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:44,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:44,844 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:44,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:44,844 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:44,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:45,256 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:45,257 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:45,257 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-27 04:46:45,257 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 46 with the following transitions: [2018-10-27 04:46:45,259 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [13], [15], [17], [19], [21], [25], [28], [31], [37], [41], [46], [125], [127], [129], [130], [131], [133], [136], [138], [140], [146], [148], [150], [152], [154], [156], [158], [160], [162], [188], [189], [190], [191], [193], [194], [195] [2018-10-27 04:46:45,300 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-27 04:46:45,300 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-27 04:46:46,378 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-27 04:46:46,380 INFO L272 AbstractInterpreter]: Visited 42 different actions 61 times. Never merged. Never widened. Never found a fixpoint. Largest state had 54 variables. [2018-10-27 04:46:46,391 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:46,392 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-27 04:46:46,392 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:46,392 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:46,402 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:46,403 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-27 04:46:46,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:46,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:46,525 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:46,527 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:46,531 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:46,532 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:46:46,554 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_#res.base| Int)) (and (= 0 (select |c_old(#valid)| |append_#Ultimate.alloc_#res.base|)) (= (store |c_old(#valid)| |append_#Ultimate.alloc_#res.base| 1) |c_#valid|))) is different from true [2018-10-27 04:46:46,609 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:46,614 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:46,615 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:46:46,616 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:46,632 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:46:46,632 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-10-27 04:46:46,755 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2018-10-27 04:46:46,755 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:46,760 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:46:46,761 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:21, output treesize:20 [2018-10-27 04:46:47,175 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 3 not checked. [2018-10-27 04:46:47,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:46:48,050 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:48,077 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-27 04:46:48,078 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 8, 8] total 19 [2018-10-27 04:46:48,078 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-27 04:46:48,078 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-10-27 04:46:48,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-10-27 04:46:48,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=289, Unknown=1, NotChecked=34, Total=380 [2018-10-27 04:46:48,081 INFO L87 Difference]: Start difference. First operand 161 states and 171 transitions. Second operand 17 states. [2018-10-27 04:46:49,623 WARN L179 SmtUtils]: Spent 272.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 24 [2018-10-27 04:46:50,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:50,332 INFO L93 Difference]: Finished difference Result 195 states and 204 transitions. [2018-10-27 04:46:50,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-27 04:46:50,334 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 45 [2018-10-27 04:46:50,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:50,335 INFO L225 Difference]: With dead ends: 195 [2018-10-27 04:46:50,335 INFO L226 Difference]: Without dead ends: 195 [2018-10-27 04:46:50,335 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 80 SyntacticMatches, 4 SemanticMatches, 27 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 185 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=134, Invalid=622, Unknown=4, NotChecked=52, Total=812 [2018-10-27 04:46:50,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-10-27 04:46:50,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 162. [2018-10-27 04:46:50,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-10-27 04:46:50,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 172 transitions. [2018-10-27 04:46:50,339 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 172 transitions. Word has length 45 [2018-10-27 04:46:50,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:50,339 INFO L481 AbstractCegarLoop]: Abstraction has 162 states and 172 transitions. [2018-10-27 04:46:50,339 INFO L482 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-10-27 04:46:50,339 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 172 transitions. [2018-10-27 04:46:50,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-27 04:46:50,340 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:50,340 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:50,340 INFO L424 AbstractCegarLoop]: === Iteration 23 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:50,340 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:50,341 INFO L82 PathProgramCache]: Analyzing trace with hash 735758084, now seen corresponding path program 1 times [2018-10-27 04:46:50,341 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:50,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:50,348 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:50,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:50,348 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:50,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:50,542 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:50,542 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:50,542 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-27 04:46:50,543 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 47 with the following transitions: [2018-10-27 04:46:50,543 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [13], [15], [17], [19], [21], [25], [28], [31], [37], [41], [46], [125], [127], [129], [131], [132], [133], [136], [138], [140], [146], [148], [150], [152], [154], [156], [158], [160], [162], [188], [189], [190], [191], [193], [194], [195] [2018-10-27 04:46:50,545 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-27 04:46:50,547 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-27 04:46:51,285 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-27 04:46:51,285 INFO L272 AbstractInterpreter]: Visited 42 different actions 61 times. Never merged. Never widened. Never found a fixpoint. Largest state had 54 variables. [2018-10-27 04:46:51,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:51,294 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-27 04:46:51,294 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:51,294 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:51,301 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:51,301 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-27 04:46:51,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:51,362 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:51,372 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:51,372 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,377 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:51,377 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,383 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,383 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:19, output treesize:14 [2018-10-27 04:46:51,406 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_~size| Int) (|append_#Ultimate.alloc_#res.base| Int)) (and (= 0 (select |c_old(#valid)| |append_#Ultimate.alloc_#res.base|)) (= (store |c_old(#valid)| |append_#Ultimate.alloc_#res.base| 1) |c_#valid|) (= (store |c_old(#length)| |append_#Ultimate.alloc_#res.base| |append_#Ultimate.alloc_~size|) |c_#length|))) is different from true [2018-10-27 04:46:51,456 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:51,458 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:46:51,459 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,482 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:51,483 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:51,484 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:46:51,484 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,491 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:46:51,492 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:31, output treesize:23 [2018-10-27 04:46:51,555 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:51,556 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:51,557 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:51,557 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-10-27 04:46:51,558 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,606 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:46:51,606 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,615 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:51,616 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:34, output treesize:9 [2018-10-27 04:46:51,650 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 4 not checked. [2018-10-27 04:46:51,651 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:46:52,004 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-10-27 04:46:52,145 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 48 [2018-10-27 04:46:55,396 WARN L179 SmtUtils]: Spent 846.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 36 [2018-10-27 04:46:55,629 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:55,653 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-27 04:46:55,653 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8] total 22 [2018-10-27 04:46:55,653 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-27 04:46:55,654 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-10-27 04:46:55,654 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-10-27 04:46:55,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=396, Unknown=2, NotChecked=40, Total=506 [2018-10-27 04:46:55,654 INFO L87 Difference]: Start difference. First operand 162 states and 172 transitions. Second operand 16 states. [2018-10-27 04:46:57,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:57,867 INFO L93 Difference]: Finished difference Result 346 states and 369 transitions. [2018-10-27 04:46:57,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-10-27 04:46:57,867 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 46 [2018-10-27 04:46:57,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:57,869 INFO L225 Difference]: With dead ends: 346 [2018-10-27 04:46:57,869 INFO L226 Difference]: Without dead ends: 346 [2018-10-27 04:46:57,869 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 79 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 210 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=193, Invalid=926, Unknown=7, NotChecked=64, Total=1190 [2018-10-27 04:46:57,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2018-10-27 04:46:57,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 270. [2018-10-27 04:46:57,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-10-27 04:46:57,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 323 transitions. [2018-10-27 04:46:57,878 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 323 transitions. Word has length 46 [2018-10-27 04:46:57,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:57,879 INFO L481 AbstractCegarLoop]: Abstraction has 270 states and 323 transitions. [2018-10-27 04:46:57,879 INFO L482 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-10-27 04:46:57,879 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 323 transitions. [2018-10-27 04:46:57,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-27 04:46:57,879 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:57,879 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:57,880 INFO L424 AbstractCegarLoop]: === Iteration 24 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:46:57,880 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:57,880 INFO L82 PathProgramCache]: Analyzing trace with hash 1751133860, now seen corresponding path program 1 times [2018-10-27 04:46:57,880 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:46:57,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:57,887 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:57,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:57,887 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:46:57,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:58,086 WARN L179 SmtUtils]: Spent 103.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-27 04:46:58,250 WARN L179 SmtUtils]: Spent 115.00 ms on a formula simplification that was a NOOP. DAG size: 15 [2018-10-27 04:46:58,604 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:46:58,604 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:58,605 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-27 04:46:58,605 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 50 with the following transitions: [2018-10-27 04:46:58,605 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [13], [15], [17], [19], [21], [25], [28], [31], [37], [41], [46], [125], [127], [129], [131], [133], [136], [138], [139], [140], [146], [148], [150], [152], [154], [156], [158], [160], [162], [188], [189], [190], [191], [193], [194], [195] [2018-10-27 04:46:58,608 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-27 04:46:58,608 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-27 04:46:59,158 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-27 04:46:59,158 INFO L272 AbstractInterpreter]: Visited 42 different actions 61 times. Never merged. Never widened. Never found a fixpoint. Largest state had 54 variables. [2018-10-27 04:46:59,165 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:59,165 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-27 04:46:59,165 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:59,165 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:59,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:59,172 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-27 04:46:59,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:59,217 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:59,221 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:59,221 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:59,244 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,249 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,249 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:19, output treesize:14 [2018-10-27 04:46:59,287 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_~size| Int) (|append_#Ultimate.alloc_#res.base| Int)) (and (= 0 (select |c_old(#valid)| |append_#Ultimate.alloc_#res.base|)) (= (store |c_old(#valid)| |append_#Ultimate.alloc_#res.base| 1) |c_#valid|) (= (store |c_old(#length)| |append_#Ultimate.alloc_#res.base| |append_#Ultimate.alloc_~size|) |c_#length|))) is different from true [2018-10-27 04:46:59,318 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:59,319 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:46:59,319 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,328 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:59,329 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:59,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:46:59,330 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,351 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:46:59,352 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:31, output treesize:23 [2018-10-27 04:46:59,386 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:59,387 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:59,388 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:46:59,389 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-10-27 04:46:59,389 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,397 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:46:59,397 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,404 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:59,404 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:34, output treesize:9 [2018-10-27 04:46:59,431 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 7 not checked. [2018-10-27 04:46:59,431 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:47:01,538 WARN L179 SmtUtils]: Spent 2.03 s on a formula simplification that was a NOOP. DAG size: 27 [2018-10-27 04:47:03,722 WARN L179 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 41 [2018-10-27 04:47:03,729 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-10-27 04:47:03,749 WARN L138 XnfTransformerHelper]: expecting exponential blowup for input size 21 [2018-10-27 04:47:04,246 WARN L179 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 40 [2018-10-27 04:47:04,762 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:04,779 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-27 04:47:04,779 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 8, 8] total 23 [2018-10-27 04:47:04,779 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-10-27 04:47:04,779 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-10-27 04:47:04,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-10-27 04:47:04,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=437, Unknown=1, NotChecked=42, Total=552 [2018-10-27 04:47:04,780 INFO L87 Difference]: Start difference. First operand 270 states and 323 transitions. Second operand 17 states. [2018-10-27 04:47:06,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:06,901 INFO L93 Difference]: Finished difference Result 340 states and 363 transitions. [2018-10-27 04:47:06,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-10-27 04:47:06,902 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 49 [2018-10-27 04:47:06,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:06,903 INFO L225 Difference]: With dead ends: 340 [2018-10-27 04:47:06,903 INFO L226 Difference]: Without dead ends: 340 [2018-10-27 04:47:06,904 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 85 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 260 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=231, Invalid=1098, Unknown=7, NotChecked=70, Total=1406 [2018-10-27 04:47:06,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-10-27 04:47:06,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 270. [2018-10-27 04:47:06,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-10-27 04:47:06,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 317 transitions. [2018-10-27 04:47:06,912 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 317 transitions. Word has length 49 [2018-10-27 04:47:06,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:06,912 INFO L481 AbstractCegarLoop]: Abstraction has 270 states and 317 transitions. [2018-10-27 04:47:06,912 INFO L482 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-10-27 04:47:06,912 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 317 transitions. [2018-10-27 04:47:06,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-27 04:47:06,913 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:06,913 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:06,913 INFO L424 AbstractCegarLoop]: === Iteration 25 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:06,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:06,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1356220878, now seen corresponding path program 1 times [2018-10-27 04:47:06,913 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:47:06,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:06,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:06,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:06,914 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:47:06,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:07,163 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:07,163 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:07,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:47:07,163 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:47:07,164 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:47:07,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:47:07,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:07,164 INFO L87 Difference]: Start difference. First operand 270 states and 317 transitions. Second operand 8 states. [2018-10-27 04:47:07,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:07,318 INFO L93 Difference]: Finished difference Result 277 states and 320 transitions. [2018-10-27 04:47:07,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:47:07,319 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 52 [2018-10-27 04:47:07,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:07,321 INFO L225 Difference]: With dead ends: 277 [2018-10-27 04:47:07,321 INFO L226 Difference]: Without dead ends: 277 [2018-10-27 04:47:07,321 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:47:07,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-10-27 04:47:07,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 241. [2018-10-27 04:47:07,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 241 states. [2018-10-27 04:47:07,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 268 transitions. [2018-10-27 04:47:07,330 INFO L78 Accepts]: Start accepts. Automaton has 241 states and 268 transitions. Word has length 52 [2018-10-27 04:47:07,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:07,331 INFO L481 AbstractCegarLoop]: Abstraction has 241 states and 268 transitions. [2018-10-27 04:47:07,331 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:47:07,331 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 268 transitions. [2018-10-27 04:47:07,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-27 04:47:07,331 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:07,331 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:07,332 INFO L424 AbstractCegarLoop]: === Iteration 26 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:07,332 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:07,332 INFO L82 PathProgramCache]: Analyzing trace with hash 1953178896, now seen corresponding path program 1 times [2018-10-27 04:47:07,332 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:47:07,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:07,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:07,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:07,333 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:47:07,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:07,818 WARN L179 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 13 [2018-10-27 04:47:08,051 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:08,051 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:08,051 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:47:08,051 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-10-27 04:47:08,052 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:47:08,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:47:08,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:08,052 INFO L87 Difference]: Start difference. First operand 241 states and 268 transitions. Second operand 8 states. [2018-10-27 04:47:08,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:08,224 INFO L93 Difference]: Finished difference Result 254 states and 275 transitions. [2018-10-27 04:47:08,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:47:08,225 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 54 [2018-10-27 04:47:08,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:08,226 INFO L225 Difference]: With dead ends: 254 [2018-10-27 04:47:08,226 INFO L226 Difference]: Without dead ends: 254 [2018-10-27 04:47:08,227 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:47:08,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states. [2018-10-27 04:47:08,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 239. [2018-10-27 04:47:08,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-10-27 04:47:08,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 262 transitions. [2018-10-27 04:47:08,232 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 262 transitions. Word has length 54 [2018-10-27 04:47:08,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:08,233 INFO L481 AbstractCegarLoop]: Abstraction has 239 states and 262 transitions. [2018-10-27 04:47:08,233 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:47:08,233 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 262 transitions. [2018-10-27 04:47:08,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-27 04:47:08,233 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:08,233 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:08,234 INFO L424 AbstractCegarLoop]: === Iteration 27 === [mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:08,234 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:08,234 INFO L82 PathProgramCache]: Analyzing trace with hash 1093930211, now seen corresponding path program 1 times [2018-10-27 04:47:08,234 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-10-27 04:47:08,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:08,235 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:08,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:08,235 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-10-27 04:47:08,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:08,797 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:08,797 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:08,797 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-10-27 04:47:08,797 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 56 with the following transitions: [2018-10-27 04:47:08,799 INFO L202 CegarAbsIntRunner]: [0], [1], [5], [7], [9], [11], [13], [15], [17], [19], [21], [25], [28], [33], [125], [127], [129], [131], [133], [136], [138], [140], [142], [146], [148], [150], [152], [154], [156], [158], [160], [162], [163], [165], [167], [169], [171], [173], [175], [177], [179], [180], [188], [189], [190], [191], [193], [194] [2018-10-27 04:47:08,802 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, OctagonDomain] [2018-10-27 04:47:08,802 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-10-27 04:47:09,234 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-10-27 04:47:09,234 INFO L272 AbstractInterpreter]: Visited 48 different actions 50 times. Merged at 1 different actions 1 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 58 variables. [2018-10-27 04:47:09,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:09,246 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-10-27 04:47:09,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:09,246 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:09,253 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:09,253 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-10-27 04:47:09,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:09,335 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:09,353 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:09,353 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,357 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,358 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:09,413 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:09,414 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:09,415 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:47:09,415 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,421 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:09,421 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:20, output treesize:18 [2018-10-27 04:47:09,679 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:47:09,681 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:47:09,681 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,683 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,689 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,690 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-10-27 04:47:09,729 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 21 treesize of output 33 [2018-10-27 04:47:09,732 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-10-27 04:47:09,732 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:09,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 19 treesize of output 26 [2018-10-27 04:47:09,770 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:09,782 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:47:09,796 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:47:09,796 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:37, output treesize:47 [2018-10-27 04:47:10,960 WARN L179 SmtUtils]: Spent 625.00 ms on a formula simplification. DAG size of input: 23 DAG size of output: 23 [2018-10-27 04:47:10,976 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 52 treesize of output 57 [2018-10-27 04:47:10,979 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 52 [2018-10-27 04:47:10,979 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:11,415 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 35 treesize of output 34 [2018-10-27 04:47:11,416 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:11,431 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:47:11,450 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 20 [2018-10-27 04:47:11,452 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:11,452 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:11,456 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:11,472 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:47:11,473 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:76, output treesize:42 [2018-10-27 04:47:11,523 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-10-27 04:47:11,524 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:11,533 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,534 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,535 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,535 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 52 [2018-10-27 04:47:11,535 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:11,544 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:11,544 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:76, output treesize:49 [2018-10-27 04:47:11,808 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,810 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,810 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,814 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:11,814 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 75 [2018-10-27 04:47:11,815 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:11,830 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:11,830 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:63, output treesize:75 [2018-10-27 04:47:12,158 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 54 [2018-10-27 04:47:12,167 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:12,168 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,196 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,217 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:12,217 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:89, output treesize:78 [2018-10-27 04:47:12,278 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 54 [2018-10-27 04:47:12,290 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:12,290 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,303 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,320 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:12,320 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:91, output treesize:80 [2018-10-27 04:47:12,558 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 39 [2018-10-27 04:47:12,569 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:12,569 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 23 [2018-10-27 04:47:12,570 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,575 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,589 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:12,589 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:87, output treesize:45 [2018-10-27 04:47:12,638 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:12,638 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:47:15,918 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 62 [2018-10-27 04:47:16,050 WARN L179 SmtUtils]: Spent 130.00 ms on a formula simplification that was a NOOP. DAG size: 50 [2018-10-27 04:47:16,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 10 [2018-10-27 04:47:16,053 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:16,065 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:16,066 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:16,081 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 50 treesize of output 74 [2018-10-27 04:47:16,234 WARN L179 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 65 [2018-10-27 04:47:16,238 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 52 [2018-10-27 04:47:16,246 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 16 treesize of output 22 [2018-10-27 04:47:16,246 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:16,262 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:47:16,306 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 42 treesize of output 52 [2018-10-27 04:47:16,315 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 43 treesize of output 53 [2018-10-27 04:47:16,316 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:16,363 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 5 case distinctions, treesize of input 45 treesize of output 70 [2018-10-27 04:47:16,364 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 8 xjuncts. [2018-10-27 04:47:16,417 INFO L267 ElimStorePlain]: Start of recursive call 7: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-10-27 04:47:16,510 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 38 [2018-10-27 04:47:16,542 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:16,602 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:16,627 INFO L303 Elim1Store]: Index analysis took 116 ms [2018-10-27 04:47:16,634 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 30 treesize of output 42 [2018-10-27 04:47:16,636 INFO L267 ElimStorePlain]: Start of recursive call 11: 2 dim-0 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-10-27 04:47:16,663 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 3 xjuncts. [2018-10-27 04:47:16,665 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 40 [2018-10-27 04:47:16,684 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 3 case distinctions, treesize of input 30 treesize of output 44 [2018-10-27 04:47:16,685 INFO L267 ElimStorePlain]: Start of recursive call 13: 2 dim-0 vars, End of recursive call: 2 dim-0 vars, and 8 xjuncts. [2018-10-27 04:47:16,757 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-10-27 04:47:16,759 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 38 [2018-10-27 04:47:16,775 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 3 case distinctions, treesize of input 28 treesize of output 44 [2018-10-27 04:47:16,776 INFO L267 ElimStorePlain]: Start of recursive call 15: 2 dim-0 vars, End of recursive call: 2 dim-0 vars, and 8 xjuncts. [2018-10-27 04:47:16,821 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-10-27 04:47:16,823 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 40 [2018-10-27 04:47:16,826 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:16,832 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:16,853 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 2 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 5 case distinctions, treesize of input 36 treesize of output 70 [2018-10-27 04:47:16,855 INFO L267 ElimStorePlain]: Start of recursive call 17: 8 dim-0 vars, End of recursive call: 8 dim-0 vars, and 20 xjuncts. [2018-10-27 04:47:17,081 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: 8 dim-0 vars, and 13 xjuncts. [2018-10-27 04:47:17,084 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 38 [2018-10-27 04:47:17,092 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 24 [2018-10-27 04:47:17,093 INFO L267 ElimStorePlain]: Start of recursive call 19: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:47:17,110 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:47:17,500 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 39 [2018-10-27 04:47:17,508 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 8 [2018-10-27 04:47:17,508 INFO L267 ElimStorePlain]: Start of recursive call 21: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:17,518 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:17,519 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:17,519 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2018-10-27 04:47:17,520 INFO L267 ElimStorePlain]: Start of recursive call 22: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:17,529 INFO L267 ElimStorePlain]: Start of recursive call 20: 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-10-27 04:47:17,532 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 37 [2018-10-27 04:47:17,534 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 1 [2018-10-27 04:47:17,534 INFO L267 ElimStorePlain]: Start of recursive call 24: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:17,558 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:17,558 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:17,559 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 22 [2018-10-27 04:47:17,560 INFO L267 ElimStorePlain]: Start of recursive call 25: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:17,679 INFO L267 ElimStorePlain]: Start of recursive call 23: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:18,003 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 42 [2018-10-27 04:47:18,005 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:18,008 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:47:18,221 WARN L522 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:18,222 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.AssertionError: var is still there: v_prenex_66 term size 41 at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.Elim1Store.elim1(Elim1Store.java:452) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:221) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:225) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:225) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:225) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.elimAllRec(ElimStorePlain.java:199) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.PartialQuantifierElimination.elim(PartialQuantifierElimination.java:293) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.PartialQuantifierElimination.tryToEliminate(PartialQuantifierElimination.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer$QuantifierEliminationPostprocessor.postprocess(IterativePredicateTransformer.java:245) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeBackwardSequence(IterativePredicateTransformer.java:383) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeWeakestPreconditionSequence(IterativePredicateTransformer.java:290) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:330) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseTaipanRefinementStrategy.getTraceCheck(BaseTaipanRefinementStrategy.java:216) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:429) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:435) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:312) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:154) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:123) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-10-27 04:47:18,225 INFO L168 Benchmark]: Toolchain (without parser) took 45797.39 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 770.7 MB). Free memory was 951.8 MB in the beginning and 1.7 GB in the end (delta: -771.7 MB). Peak memory consumption was 868.5 MB. Max. memory is 11.5 GB. [2018-10-27 04:47:18,226 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 977.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-27 04:47:18,226 INFO L168 Benchmark]: CACSL2BoogieTranslator took 414.59 ms. Allocated memory is still 1.0 GB. Free memory was 951.8 MB in the beginning and 928.8 MB in the end (delta: 23.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2018-10-27 04:47:18,226 INFO L168 Benchmark]: Boogie Procedure Inliner took 124.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.2 MB). Free memory was 928.8 MB in the beginning and 1.2 GB in the end (delta: -222.5 MB). Peak memory consumption was 16.5 MB. Max. memory is 11.5 GB. [2018-10-27 04:47:18,226 INFO L168 Benchmark]: Boogie Preprocessor took 57.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-10-27 04:47:18,226 INFO L168 Benchmark]: RCFGBuilder took 1080.73 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.9 MB). Peak memory consumption was 47.9 MB. Max. memory is 11.5 GB. [2018-10-27 04:47:18,227 INFO L168 Benchmark]: TraceAbstraction took 44117.15 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 614.5 MB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -628.2 MB). Peak memory consumption was 855.8 MB. Max. memory is 11.5 GB. [2018-10-27 04:47:18,228 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 977.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 414.59 ms. Allocated memory is still 1.0 GB. Free memory was 951.8 MB in the beginning and 928.8 MB in the end (delta: 23.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 124.22 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.2 MB). Free memory was 928.8 MB in the beginning and 1.2 GB in the end (delta: -222.5 MB). Peak memory consumption was 16.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 57.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1080.73 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.9 MB). Peak memory consumption was 47.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 44117.15 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 614.5 MB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -628.2 MB). Peak memory consumption was 855.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: AssertionError: var is still there: v_prenex_66 term size 41 de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: AssertionError: var is still there: v_prenex_66 term size 41: de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.Elim1Store.elim1(Elim1Store.java:452) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-1dbac8b [2018-10-27 04:47:20,038 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-27 04:47:20,039 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-27 04:47:20,048 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-27 04:47:20,048 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-27 04:47:20,049 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-27 04:47:20,050 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-27 04:47:20,052 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-27 04:47:20,053 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-27 04:47:20,054 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-27 04:47:20,054 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-27 04:47:20,055 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-27 04:47:20,055 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-27 04:47:20,056 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-27 04:47:20,057 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-27 04:47:20,058 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-27 04:47:20,059 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-27 04:47:20,060 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-27 04:47:20,062 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-27 04:47:20,063 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-27 04:47:20,064 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-27 04:47:20,065 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-27 04:47:20,069 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-27 04:47:20,069 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-27 04:47:20,069 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-27 04:47:20,070 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-27 04:47:20,070 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-27 04:47:20,071 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-27 04:47:20,072 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-27 04:47:20,072 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-27 04:47:20,072 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-27 04:47:20,073 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-27 04:47:20,073 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-27 04:47:20,073 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-27 04:47:20,076 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-27 04:47:20,077 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-27 04:47:20,077 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Bitvector.epf [2018-10-27 04:47:20,097 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-27 04:47:20,098 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-27 04:47:20,099 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-27 04:47:20,099 INFO L133 SettingsManager]: * User list type=DISABLED [2018-10-27 04:47:20,100 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-10-27 04:47:20,100 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-10-27 04:47:20,100 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-10-27 04:47:20,101 INFO L133 SettingsManager]: * Interval Domain=false [2018-10-27 04:47:20,101 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-27 04:47:20,102 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-27 04:47:20,103 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-27 04:47:20,103 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-27 04:47:20,103 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-10-27 04:47:20,103 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-10-27 04:47:20,104 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-10-27 04:47:20,105 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-27 04:47:20,105 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-27 04:47:20,105 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-27 04:47:20,105 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-27 04:47:20,105 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-27 04:47:20,105 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-27 04:47:20,106 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-27 04:47:20,106 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-27 04:47:20,106 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-10-27 04:47:20,106 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-27 04:47:20,106 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-10-27 04:47:20,106 INFO L133 SettingsManager]: * Logic for external solver=AUFBV Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2552da43a16cb54d5090a24426eb170717bf5525 [2018-10-27 04:47:20,145 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-27 04:47:20,156 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-27 04:47:20,160 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-27 04:47:20,162 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-27 04:47:20,162 INFO L276 PluginConnector]: CDTParser initialized [2018-10-27 04:47:20,162 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/../../sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i [2018-10-27 04:47:20,207 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/693142620/c69057bed8b6412b91cb87186994d05d/FLAGef52d721c [2018-10-27 04:47:20,646 INFO L298 CDTParser]: Found 1 translation units. [2018-10-27 04:47:20,650 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/sv-benchmarks/c/memsafety-ext2/length_test03_false-valid-memtrack.i [2018-10-27 04:47:20,659 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/693142620/c69057bed8b6412b91cb87186994d05d/FLAGef52d721c [2018-10-27 04:47:20,670 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/data/693142620/c69057bed8b6412b91cb87186994d05d [2018-10-27 04:47:20,672 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-27 04:47:20,673 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-27 04:47:20,674 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-27 04:47:20,674 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-27 04:47:20,677 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-27 04:47:20,678 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 04:47:20" (1/1) ... [2018-10-27 04:47:20,680 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@d37e630 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:20, skipping insertion in model container [2018-10-27 04:47:20,681 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 04:47:20" (1/1) ... [2018-10-27 04:47:20,690 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-27 04:47:20,737 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-27 04:47:21,022 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 04:47:21,036 INFO L189 MainTranslator]: Completed pre-run [2018-10-27 04:47:21,078 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 04:47:21,133 INFO L193 MainTranslator]: Completed translation [2018-10-27 04:47:21,133 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21 WrapperNode [2018-10-27 04:47:21,133 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-27 04:47:21,134 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-27 04:47:21,134 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-27 04:47:21,134 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-27 04:47:21,142 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,159 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,196 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-27 04:47:21,204 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-27 04:47:21,204 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-27 04:47:21,204 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-27 04:47:21,212 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,212 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,295 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,295 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,307 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,312 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,322 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... [2018-10-27 04:47:21,326 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-27 04:47:21,330 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-27 04:47:21,331 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-27 04:47:21,331 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-27 04:47:21,331 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-27 04:47:21,378 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-27 04:47:21,379 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-27 04:47:21,379 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-27 04:47:21,379 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-27 04:47:21,379 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-27 04:47:21,379 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-27 04:47:21,379 INFO L130 BoogieDeclarations]: Found specification of procedure append [2018-10-27 04:47:21,379 INFO L138 BoogieDeclarations]: Found implementation of procedure append [2018-10-27 04:47:22,628 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-27 04:47:22,629 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:47:22 BoogieIcfgContainer [2018-10-27 04:47:22,629 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-27 04:47:22,629 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-27 04:47:22,630 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-27 04:47:22,633 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-27 04:47:22,633 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.10 04:47:20" (1/3) ... [2018-10-27 04:47:22,634 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1bf7d64b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.10 04:47:22, skipping insertion in model container [2018-10-27 04:47:22,634 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:47:21" (2/3) ... [2018-10-27 04:47:22,634 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1bf7d64b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.10 04:47:22, skipping insertion in model container [2018-10-27 04:47:22,634 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:47:22" (3/3) ... [2018-10-27 04:47:22,635 INFO L112 eAbstractionObserver]: Analyzing ICFG length_test03_false-valid-memtrack.i [2018-10-27 04:47:22,645 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-27 04:47:22,653 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 55 error locations. [2018-10-27 04:47:22,668 INFO L257 AbstractCegarLoop]: Starting to check reachability of 55 error locations. [2018-10-27 04:47:22,691 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-27 04:47:22,692 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-27 04:47:22,692 INFO L383 AbstractCegarLoop]: Hoare is false [2018-10-27 04:47:22,692 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-27 04:47:22,692 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-27 04:47:22,692 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-27 04:47:22,692 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-27 04:47:22,692 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-27 04:47:22,693 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-27 04:47:22,706 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states. [2018-10-27 04:47:22,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-10-27 04:47:22,714 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:22,715 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:22,718 INFO L424 AbstractCegarLoop]: === Iteration 1 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:22,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:22,724 INFO L82 PathProgramCache]: Analyzing trace with hash 1096514590, now seen corresponding path program 1 times [2018-10-27 04:47:22,727 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:22,727 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:22,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:22,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:22,779 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:22,834 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:22,836 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:22,862 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:22,862 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:47:22,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:22,881 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:22,884 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:22,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:47:22,887 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:47:22,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:47:22,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:22,902 INFO L87 Difference]: Start difference. First operand 140 states. Second operand 3 states. [2018-10-27 04:47:23,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:23,621 INFO L93 Difference]: Finished difference Result 140 states and 147 transitions. [2018-10-27 04:47:23,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:47:23,623 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-10-27 04:47:23,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:23,635 INFO L225 Difference]: With dead ends: 140 [2018-10-27 04:47:23,635 INFO L226 Difference]: Without dead ends: 137 [2018-10-27 04:47:23,637 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:23,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-10-27 04:47:23,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 135. [2018-10-27 04:47:23,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-10-27 04:47:23,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 141 transitions. [2018-10-27 04:47:23,690 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 141 transitions. Word has length 7 [2018-10-27 04:47:23,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:23,691 INFO L481 AbstractCegarLoop]: Abstraction has 135 states and 141 transitions. [2018-10-27 04:47:23,691 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:47:23,691 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 141 transitions. [2018-10-27 04:47:23,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-10-27 04:47:23,692 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:23,692 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:23,693 INFO L424 AbstractCegarLoop]: === Iteration 2 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:23,694 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:23,695 INFO L82 PathProgramCache]: Analyzing trace with hash -367786039, now seen corresponding path program 1 times [2018-10-27 04:47:23,695 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:23,695 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:23,723 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:23,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:23,762 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:23,786 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:23,786 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:23,890 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:23,891 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-10-27 04:47:24,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:24,013 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:24,018 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:24,019 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:47:24,020 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:47:24,021 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:47:24,021 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:24,021 INFO L87 Difference]: Start difference. First operand 135 states and 141 transitions. Second operand 3 states. [2018-10-27 04:47:24,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:24,464 INFO L93 Difference]: Finished difference Result 133 states and 139 transitions. [2018-10-27 04:47:24,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:47:24,465 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-10-27 04:47:24,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:24,467 INFO L225 Difference]: With dead ends: 133 [2018-10-27 04:47:24,467 INFO L226 Difference]: Without dead ends: 133 [2018-10-27 04:47:24,467 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:24,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-10-27 04:47:24,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2018-10-27 04:47:24,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-10-27 04:47:24,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 139 transitions. [2018-10-27 04:47:24,479 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 139 transitions. Word has length 8 [2018-10-27 04:47:24,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:24,479 INFO L481 AbstractCegarLoop]: Abstraction has 133 states and 139 transitions. [2018-10-27 04:47:24,479 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:47:24,479 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 139 transitions. [2018-10-27 04:47:24,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-10-27 04:47:24,480 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:24,480 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:24,481 INFO L424 AbstractCegarLoop]: === Iteration 3 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:24,483 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:24,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1483534720, now seen corresponding path program 1 times [2018-10-27 04:47:24,483 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:24,483 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:24,510 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:24,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:24,542 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:24,550 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:24,550 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:24,555 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:24,555 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:24,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:24,579 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:24,582 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:24,582 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:47:24,582 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:47:24,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:47:24,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:24,583 INFO L87 Difference]: Start difference. First operand 133 states and 139 transitions. Second operand 5 states. [2018-10-27 04:47:24,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:24,976 INFO L93 Difference]: Finished difference Result 134 states and 141 transitions. [2018-10-27 04:47:24,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:47:24,990 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 9 [2018-10-27 04:47:24,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:24,991 INFO L225 Difference]: With dead ends: 134 [2018-10-27 04:47:24,991 INFO L226 Difference]: Without dead ends: 134 [2018-10-27 04:47:24,991 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:47:24,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-10-27 04:47:25,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 132. [2018-10-27 04:47:25,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-10-27 04:47:25,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 138 transitions. [2018-10-27 04:47:25,004 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 138 transitions. Word has length 9 [2018-10-27 04:47:25,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:25,005 INFO L481 AbstractCegarLoop]: Abstraction has 132 states and 138 transitions. [2018-10-27 04:47:25,005 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:47:25,005 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 138 transitions. [2018-10-27 04:47:25,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-10-27 04:47:25,005 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:25,005 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:25,006 INFO L424 AbstractCegarLoop]: === Iteration 4 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:25,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:25,006 INFO L82 PathProgramCache]: Analyzing trace with hash -1255063893, now seen corresponding path program 1 times [2018-10-27 04:47:25,006 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:25,007 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:25,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:25,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:25,055 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:25,070 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:25,070 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:25,086 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:25,087 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:25,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:25,179 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:25,180 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:25,180 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:25,181 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:47:25,181 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:47:25,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:47:25,181 INFO L87 Difference]: Start difference. First operand 132 states and 138 transitions. Second operand 4 states. [2018-10-27 04:47:25,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:25,559 INFO L93 Difference]: Finished difference Result 133 states and 140 transitions. [2018-10-27 04:47:25,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:47:25,560 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 10 [2018-10-27 04:47:25,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:25,561 INFO L225 Difference]: With dead ends: 133 [2018-10-27 04:47:25,561 INFO L226 Difference]: Without dead ends: 133 [2018-10-27 04:47:25,562 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:25,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-10-27 04:47:25,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 131. [2018-10-27 04:47:25,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-10-27 04:47:25,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 137 transitions. [2018-10-27 04:47:25,570 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 137 transitions. Word has length 10 [2018-10-27 04:47:25,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:25,570 INFO L481 AbstractCegarLoop]: Abstraction has 131 states and 137 transitions. [2018-10-27 04:47:25,570 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:47:25,571 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 137 transitions. [2018-10-27 04:47:25,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-10-27 04:47:25,571 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:25,571 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:25,572 INFO L424 AbstractCegarLoop]: === Iteration 5 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:25,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:25,572 INFO L82 PathProgramCache]: Analyzing trace with hash -1918079932, now seen corresponding path program 1 times [2018-10-27 04:47:25,573 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:25,573 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:25,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:25,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:25,638 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:25,666 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:25,666 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:25,690 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:25,690 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:47:25,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:25,726 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:25,729 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:25,730 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:25,730 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:47:25,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:47:25,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:47:25,730 INFO L87 Difference]: Start difference. First operand 131 states and 137 transitions. Second operand 4 states. [2018-10-27 04:47:26,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:26,090 INFO L93 Difference]: Finished difference Result 132 states and 139 transitions. [2018-10-27 04:47:26,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:47:26,091 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-10-27 04:47:26,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:26,092 INFO L225 Difference]: With dead ends: 132 [2018-10-27 04:47:26,092 INFO L226 Difference]: Without dead ends: 132 [2018-10-27 04:47:26,092 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:26,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-10-27 04:47:26,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 130. [2018-10-27 04:47:26,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-10-27 04:47:26,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 136 transitions. [2018-10-27 04:47:26,103 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 136 transitions. Word has length 13 [2018-10-27 04:47:26,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:26,104 INFO L481 AbstractCegarLoop]: Abstraction has 130 states and 136 transitions. [2018-10-27 04:47:26,104 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:47:26,104 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 136 transitions. [2018-10-27 04:47:26,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-27 04:47:26,104 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:26,104 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:26,105 INFO L424 AbstractCegarLoop]: === Iteration 6 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:26,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:26,113 INFO L82 PathProgramCache]: Analyzing trace with hash 669064303, now seen corresponding path program 1 times [2018-10-27 04:47:26,113 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:26,113 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:26,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:26,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:26,199 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:26,215 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:26,215 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:26,250 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:26,250 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:26,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:26,268 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:26,270 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:26,270 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:26,271 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:47:26,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:47:26,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:47:26,271 INFO L87 Difference]: Start difference. First operand 130 states and 136 transitions. Second operand 4 states. [2018-10-27 04:47:26,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:26,670 INFO L93 Difference]: Finished difference Result 131 states and 138 transitions. [2018-10-27 04:47:26,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:47:26,670 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-10-27 04:47:26,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:26,671 INFO L225 Difference]: With dead ends: 131 [2018-10-27 04:47:26,671 INFO L226 Difference]: Without dead ends: 131 [2018-10-27 04:47:26,672 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:26,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-10-27 04:47:26,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 129. [2018-10-27 04:47:26,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-10-27 04:47:26,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 135 transitions. [2018-10-27 04:47:26,676 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 135 transitions. Word has length 14 [2018-10-27 04:47:26,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:26,677 INFO L481 AbstractCegarLoop]: Abstraction has 129 states and 135 transitions. [2018-10-27 04:47:26,677 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:47:26,677 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 135 transitions. [2018-10-27 04:47:26,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-10-27 04:47:26,677 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:26,680 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:26,681 INFO L424 AbstractCegarLoop]: === Iteration 7 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:26,681 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:26,681 INFO L82 PathProgramCache]: Analyzing trace with hash -534011400, now seen corresponding path program 1 times [2018-10-27 04:47:26,682 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:26,682 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:26,697 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:26,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:26,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:26,789 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:26,790 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:26,794 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:26,794 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:47:26,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:26,799 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:26,800 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:26,801 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:47:26,801 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:47:26,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:47:26,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:26,801 INFO L87 Difference]: Start difference. First operand 129 states and 135 transitions. Second operand 3 states. [2018-10-27 04:47:27,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:27,043 INFO L93 Difference]: Finished difference Result 128 states and 134 transitions. [2018-10-27 04:47:27,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:47:27,043 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2018-10-27 04:47:27,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:27,044 INFO L225 Difference]: With dead ends: 128 [2018-10-27 04:47:27,044 INFO L226 Difference]: Without dead ends: 128 [2018-10-27 04:47:27,044 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:27,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-10-27 04:47:27,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2018-10-27 04:47:27,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-10-27 04:47:27,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 134 transitions. [2018-10-27 04:47:27,050 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 134 transitions. Word has length 18 [2018-10-27 04:47:27,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:27,050 INFO L481 AbstractCegarLoop]: Abstraction has 128 states and 134 transitions. [2018-10-27 04:47:27,050 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:47:27,050 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 134 transitions. [2018-10-27 04:47:27,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-10-27 04:47:27,051 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:27,051 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:27,052 INFO L424 AbstractCegarLoop]: === Iteration 8 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:27,052 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:27,052 INFO L82 PathProgramCache]: Analyzing trace with hash 625515942, now seen corresponding path program 1 times [2018-10-27 04:47:27,052 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:27,053 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:27,071 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:27,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:27,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:27,178 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:27,178 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:27,187 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:27,187 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-10-27 04:47:27,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:27,195 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:27,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:27,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:47:27,198 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:47:27,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:47:27,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:27,198 INFO L87 Difference]: Start difference. First operand 128 states and 134 transitions. Second operand 3 states. [2018-10-27 04:47:27,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:27,518 INFO L93 Difference]: Finished difference Result 127 states and 133 transitions. [2018-10-27 04:47:27,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:47:27,519 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2018-10-27 04:47:27,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:27,520 INFO L225 Difference]: With dead ends: 127 [2018-10-27 04:47:27,520 INFO L226 Difference]: Without dead ends: 127 [2018-10-27 04:47:27,520 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:27,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-10-27 04:47:27,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2018-10-27 04:47:27,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-10-27 04:47:27,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 133 transitions. [2018-10-27 04:47:27,524 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 133 transitions. Word has length 19 [2018-10-27 04:47:27,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:27,524 INFO L481 AbstractCegarLoop]: Abstraction has 127 states and 133 transitions. [2018-10-27 04:47:27,524 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:47:27,524 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 133 transitions. [2018-10-27 04:47:27,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-10-27 04:47:27,525 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:27,525 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:27,527 INFO L424 AbstractCegarLoop]: === Iteration 9 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:27,527 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:27,527 INFO L82 PathProgramCache]: Analyzing trace with hash -2083842118, now seen corresponding path program 1 times [2018-10-27 04:47:27,528 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:27,528 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:27,541 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:27,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:27,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:27,647 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:27,647 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:27,652 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:27,652 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:27,674 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:27,675 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:27,675 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:47:27,676 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:27,692 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:27,692 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-10-27 04:47:27,853 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-10-27 04:47:27,853 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:27,887 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:27,887 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:20 [2018-10-27 04:47:27,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:27,936 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:27,943 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:27,943 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:47:27,943 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:47:27,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:47:27,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:27,944 INFO L87 Difference]: Start difference. First operand 127 states and 133 transitions. Second operand 8 states. [2018-10-27 04:47:29,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:29,202 INFO L93 Difference]: Finished difference Result 224 states and 235 transitions. [2018-10-27 04:47:29,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-27 04:47:29,202 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 20 [2018-10-27 04:47:29,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:29,203 INFO L225 Difference]: With dead ends: 224 [2018-10-27 04:47:29,204 INFO L226 Difference]: Without dead ends: 224 [2018-10-27 04:47:29,204 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-10-27 04:47:29,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-10-27 04:47:29,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 158. [2018-10-27 04:47:29,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-10-27 04:47:29,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 185 transitions. [2018-10-27 04:47:29,211 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 185 transitions. Word has length 20 [2018-10-27 04:47:29,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:29,211 INFO L481 AbstractCegarLoop]: Abstraction has 158 states and 185 transitions. [2018-10-27 04:47:29,211 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:47:29,211 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 185 transitions. [2018-10-27 04:47:29,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-10-27 04:47:29,211 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:29,211 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:29,212 INFO L424 AbstractCegarLoop]: === Iteration 10 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:29,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:29,213 INFO L82 PathProgramCache]: Analyzing trace with hash -174596056, now seen corresponding path program 1 times [2018-10-27 04:47:29,213 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:29,213 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:29,236 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:29,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:29,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:29,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:29,361 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:29,368 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:29,369 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:29,397 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:29,397 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-10-27 04:47:29,430 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:29,431 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:29,432 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-10-27 04:47:29,432 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:29,456 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:47:29,456 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:29,468 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:29,469 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:25, output treesize:9 [2018-10-27 04:47:29,488 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:29,494 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 15 [2018-10-27 04:47:29,495 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:29,508 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:47:29,509 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:24 [2018-10-27 04:47:29,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:29,562 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:29,567 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:29,567 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-10-27 04:47:29,568 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-10-27 04:47:29,568 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-10-27 04:47:29,568 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-10-27 04:47:29,568 INFO L87 Difference]: Start difference. First operand 158 states and 185 transitions. Second operand 7 states. [2018-10-27 04:47:29,928 WARN L179 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 35 [2018-10-27 04:47:30,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:30,864 INFO L93 Difference]: Finished difference Result 229 states and 259 transitions. [2018-10-27 04:47:30,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-27 04:47:30,865 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-10-27 04:47:30,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:30,865 INFO L225 Difference]: With dead ends: 229 [2018-10-27 04:47:30,865 INFO L226 Difference]: Without dead ends: 229 [2018-10-27 04:47:30,866 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:30,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-10-27 04:47:30,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 191. [2018-10-27 04:47:30,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2018-10-27 04:47:30,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 239 transitions. [2018-10-27 04:47:30,869 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 239 transitions. Word has length 21 [2018-10-27 04:47:30,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:30,869 INFO L481 AbstractCegarLoop]: Abstraction has 191 states and 239 transitions. [2018-10-27 04:47:30,869 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-10-27 04:47:30,869 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 239 transitions. [2018-10-27 04:47:30,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-27 04:47:30,879 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:30,879 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:30,880 INFO L424 AbstractCegarLoop]: === Iteration 11 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:30,880 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:30,880 INFO L82 PathProgramCache]: Analyzing trace with hash -185544929, now seen corresponding path program 1 times [2018-10-27 04:47:30,881 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:30,881 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:30,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:30,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:31,021 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:31,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:31,028 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:31,035 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:31,036 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:31,040 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:31,041 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-10-27 04:47:31,062 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:31,066 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:31,066 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-10-27 04:47:31,066 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:31,078 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:47:31,078 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:31,087 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:31,088 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:25, output treesize:9 [2018-10-27 04:47:31,116 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:31,125 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 15 [2018-10-27 04:47:31,126 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-10-27 04:47:31,137 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:47:31,137 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:24 [2018-10-27 04:47:31,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:31,323 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:31,331 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:31,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:47:31,332 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:47:31,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:47:31,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:31,332 INFO L87 Difference]: Start difference. First operand 191 states and 239 transitions. Second operand 8 states. [2018-10-27 04:47:33,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:33,204 INFO L93 Difference]: Finished difference Result 226 states and 256 transitions. [2018-10-27 04:47:33,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-27 04:47:33,204 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-10-27 04:47:33,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:33,205 INFO L225 Difference]: With dead ends: 226 [2018-10-27 04:47:33,206 INFO L226 Difference]: Without dead ends: 226 [2018-10-27 04:47:33,206 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 16 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-10-27 04:47:33,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-10-27 04:47:33,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 191. [2018-10-27 04:47:33,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2018-10-27 04:47:33,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 236 transitions. [2018-10-27 04:47:33,212 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 236 transitions. Word has length 24 [2018-10-27 04:47:33,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:33,212 INFO L481 AbstractCegarLoop]: Abstraction has 191 states and 236 transitions. [2018-10-27 04:47:33,212 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:47:33,213 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 236 transitions. [2018-10-27 04:47:33,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-27 04:47:33,214 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:33,214 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:33,215 INFO L424 AbstractCegarLoop]: === Iteration 12 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:33,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:33,215 INFO L82 PathProgramCache]: Analyzing trace with hash -185538907, now seen corresponding path program 1 times [2018-10-27 04:47:33,216 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:33,216 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:33,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:33,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:33,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:33,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:33,283 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:33,285 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:33,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:33,285 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:47:33,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:47:33,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:33,286 INFO L87 Difference]: Start difference. First operand 191 states and 236 transitions. Second operand 3 states. [2018-10-27 04:47:33,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:33,300 INFO L93 Difference]: Finished difference Result 194 states and 239 transitions. [2018-10-27 04:47:33,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:47:33,300 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2018-10-27 04:47:33,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:33,301 INFO L225 Difference]: With dead ends: 194 [2018-10-27 04:47:33,301 INFO L226 Difference]: Without dead ends: 194 [2018-10-27 04:47:33,302 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:33,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-10-27 04:47:33,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 194. [2018-10-27 04:47:33,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-10-27 04:47:33,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 239 transitions. [2018-10-27 04:47:33,306 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 239 transitions. Word has length 24 [2018-10-27 04:47:33,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:33,307 INFO L481 AbstractCegarLoop]: Abstraction has 194 states and 239 transitions. [2018-10-27 04:47:33,307 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:47:33,307 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 239 transitions. [2018-10-27 04:47:33,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-27 04:47:33,307 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:33,308 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:33,309 INFO L424 AbstractCegarLoop]: === Iteration 13 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:33,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:33,309 INFO L82 PathProgramCache]: Analyzing trace with hash 2079955265, now seen corresponding path program 1 times [2018-10-27 04:47:33,309 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:33,309 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:33,341 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:33,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:33,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:33,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:33,485 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:33,487 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:33,487 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:47:33,487 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:47:33,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:47:33,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:33,487 INFO L87 Difference]: Start difference. First operand 194 states and 239 transitions. Second operand 5 states. [2018-10-27 04:47:33,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:33,790 INFO L93 Difference]: Finished difference Result 188 states and 227 transitions. [2018-10-27 04:47:33,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:47:33,791 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-10-27 04:47:33,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:33,792 INFO L225 Difference]: With dead ends: 188 [2018-10-27 04:47:33,792 INFO L226 Difference]: Without dead ends: 188 [2018-10-27 04:47:33,792 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-10-27 04:47:33,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-10-27 04:47:33,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 188. [2018-10-27 04:47:33,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-10-27 04:47:33,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 227 transitions. [2018-10-27 04:47:33,796 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 227 transitions. Word has length 26 [2018-10-27 04:47:33,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:33,796 INFO L481 AbstractCegarLoop]: Abstraction has 188 states and 227 transitions. [2018-10-27 04:47:33,796 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:47:33,796 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 227 transitions. [2018-10-27 04:47:33,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-27 04:47:33,797 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:33,797 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:33,800 INFO L424 AbstractCegarLoop]: === Iteration 14 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:33,800 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:33,800 INFO L82 PathProgramCache]: Analyzing trace with hash 2086265863, now seen corresponding path program 1 times [2018-10-27 04:47:33,800 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:33,800 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:33,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:33,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:33,904 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:33,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:33,914 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:33,915 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:33,916 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:47:33,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:33,935 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:33,936 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:33,936 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:33,937 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:47:33,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:47:33,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:47:33,937 INFO L87 Difference]: Start difference. First operand 188 states and 227 transitions. Second operand 4 states. [2018-10-27 04:47:34,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:34,387 INFO L93 Difference]: Finished difference Result 184 states and 215 transitions. [2018-10-27 04:47:34,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:47:34,388 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 26 [2018-10-27 04:47:34,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:34,388 INFO L225 Difference]: With dead ends: 184 [2018-10-27 04:47:34,388 INFO L226 Difference]: Without dead ends: 184 [2018-10-27 04:47:34,389 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:34,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-10-27 04:47:34,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 184. [2018-10-27 04:47:34,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-10-27 04:47:34,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 215 transitions. [2018-10-27 04:47:34,393 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 215 transitions. Word has length 26 [2018-10-27 04:47:34,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:34,393 INFO L481 AbstractCegarLoop]: Abstraction has 184 states and 215 transitions. [2018-10-27 04:47:34,393 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:47:34,393 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 215 transitions. [2018-10-27 04:47:34,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-10-27 04:47:34,395 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:34,395 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:34,395 INFO L424 AbstractCegarLoop]: === Iteration 15 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:34,395 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:34,396 INFO L82 PathProgramCache]: Analyzing trace with hash 54103954, now seen corresponding path program 1 times [2018-10-27 04:47:34,396 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:34,396 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:34,411 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:34,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:34,550 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:34,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:34,697 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:34,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:34,699 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:47:34,699 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:47:34,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:47:34,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:34,699 INFO L87 Difference]: Start difference. First operand 184 states and 215 transitions. Second operand 8 states. [2018-10-27 04:47:35,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:35,204 INFO L93 Difference]: Finished difference Result 198 states and 215 transitions. [2018-10-27 04:47:35,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:47:35,205 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-10-27 04:47:35,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:35,206 INFO L225 Difference]: With dead ends: 198 [2018-10-27 04:47:35,206 INFO L226 Difference]: Without dead ends: 198 [2018-10-27 04:47:35,206 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:47:35,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-10-27 04:47:35,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 185. [2018-10-27 04:47:35,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-10-27 04:47:35,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 213 transitions. [2018-10-27 04:47:35,211 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 213 transitions. Word has length 27 [2018-10-27 04:47:35,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:35,211 INFO L481 AbstractCegarLoop]: Abstraction has 185 states and 213 transitions. [2018-10-27 04:47:35,212 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:47:35,212 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 213 transitions. [2018-10-27 04:47:35,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-10-27 04:47:35,212 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:35,212 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:35,212 INFO L424 AbstractCegarLoop]: === Iteration 16 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:35,212 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:35,213 INFO L82 PathProgramCache]: Analyzing trace with hash 249732513, now seen corresponding path program 1 times [2018-10-27 04:47:35,213 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:35,213 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:35,226 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:35,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:35,322 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:35,332 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:35,332 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:35,335 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:35,336 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:35,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:35,353 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:35,366 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:35,366 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:35,366 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:47:35,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:47:35,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:47:35,367 INFO L87 Difference]: Start difference. First operand 185 states and 213 transitions. Second operand 4 states. [2018-10-27 04:47:35,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:35,676 INFO L93 Difference]: Finished difference Result 183 states and 207 transitions. [2018-10-27 04:47:35,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:47:35,677 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2018-10-27 04:47:35,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:35,678 INFO L225 Difference]: With dead ends: 183 [2018-10-27 04:47:35,678 INFO L226 Difference]: Without dead ends: 183 [2018-10-27 04:47:35,678 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:35,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-10-27 04:47:35,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 183. [2018-10-27 04:47:35,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-10-27 04:47:35,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 207 transitions. [2018-10-27 04:47:35,681 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 207 transitions. Word has length 27 [2018-10-27 04:47:35,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:35,681 INFO L481 AbstractCegarLoop]: Abstraction has 183 states and 207 transitions. [2018-10-27 04:47:35,681 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:47:35,681 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 207 transitions. [2018-10-27 04:47:35,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-10-27 04:47:35,681 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:35,681 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:35,682 INFO L424 AbstractCegarLoop]: === Iteration 17 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:35,682 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:35,682 INFO L82 PathProgramCache]: Analyzing trace with hash 454298036, now seen corresponding path program 1 times [2018-10-27 04:47:35,682 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:35,682 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:35,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:35,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:35,812 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:35,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:35,893 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:35,895 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:35,895 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:47:35,895 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:47:35,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:47:35,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:47:35,896 INFO L87 Difference]: Start difference. First operand 183 states and 207 transitions. Second operand 8 states. [2018-10-27 04:47:36,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:36,438 INFO L93 Difference]: Finished difference Result 196 states and 209 transitions. [2018-10-27 04:47:36,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:47:36,439 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-10-27 04:47:36,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:36,440 INFO L225 Difference]: With dead ends: 196 [2018-10-27 04:47:36,440 INFO L226 Difference]: Without dead ends: 196 [2018-10-27 04:47:36,441 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:47:36,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-10-27 04:47:36,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 183. [2018-10-27 04:47:36,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-10-27 04:47:36,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 203 transitions. [2018-10-27 04:47:36,444 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 203 transitions. Word has length 29 [2018-10-27 04:47:36,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:36,445 INFO L481 AbstractCegarLoop]: Abstraction has 183 states and 203 transitions. [2018-10-27 04:47:36,445 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:47:36,445 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 203 transitions. [2018-10-27 04:47:36,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-10-27 04:47:36,445 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:36,445 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:36,447 INFO L424 AbstractCegarLoop]: === Iteration 18 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:36,447 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:36,447 INFO L82 PathProgramCache]: Analyzing trace with hash -525217117, now seen corresponding path program 1 times [2018-10-27 04:47:36,448 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:36,448 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:36,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:36,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:36,568 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:36,594 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:36,594 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:36,666 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:36,667 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:36,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:36,773 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:36,775 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:36,775 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:36,775 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-10-27 04:47:36,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-10-27 04:47:36,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-10-27 04:47:36,775 INFO L87 Difference]: Start difference. First operand 183 states and 203 transitions. Second operand 4 states. [2018-10-27 04:47:37,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:37,117 INFO L93 Difference]: Finished difference Result 187 states and 203 transitions. [2018-10-27 04:47:37,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:47:37,118 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 29 [2018-10-27 04:47:37,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:37,118 INFO L225 Difference]: With dead ends: 187 [2018-10-27 04:47:37,119 INFO L226 Difference]: Without dead ends: 187 [2018-10-27 04:47:37,119 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:47:37,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-10-27 04:47:37,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 181. [2018-10-27 04:47:37,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181 states. [2018-10-27 04:47:37,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 197 transitions. [2018-10-27 04:47:37,122 INFO L78 Accepts]: Start accepts. Automaton has 181 states and 197 transitions. Word has length 29 [2018-10-27 04:47:37,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:37,123 INFO L481 AbstractCegarLoop]: Abstraction has 181 states and 197 transitions. [2018-10-27 04:47:37,123 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-10-27 04:47:37,123 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 197 transitions. [2018-10-27 04:47:37,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-27 04:47:37,123 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:37,124 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:37,124 INFO L424 AbstractCegarLoop]: === Iteration 19 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:37,124 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:37,124 INFO L82 PathProgramCache]: Analyzing trace with hash -177068595, now seen corresponding path program 1 times [2018-10-27 04:47:37,124 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:37,124 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:37,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:37,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:37,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:37,363 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:37,363 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,381 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,382 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:22, output treesize:21 [2018-10-27 04:47:37,413 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-10-27 04:47:37,415 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:37,415 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,417 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-10-27 04:47:37,466 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:37,466 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,490 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,608 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,609 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:41, output treesize:33 [2018-10-27 04:47:37,643 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:37,645 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:37,646 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-10-27 04:47:37,646 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,689 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-10-27 04:47:37,694 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:37,697 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-10-27 04:47:37,697 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,707 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,733 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-10-27 04:47:37,737 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:37,739 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-10-27 04:47:37,740 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,747 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,763 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,763 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 5 variables, input treesize:57, output treesize:25 [2018-10-27 04:47:37,802 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-10-27 04:47:37,805 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:37,805 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,812 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,834 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-10-27 04:47:37,837 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:37,838 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,846 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,859 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,859 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:44, output treesize:22 [2018-10-27 04:47:37,885 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-10-27 04:47:37,889 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:37,889 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,897 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,931 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-10-27 04:47:37,933 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:37,934 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,940 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,954 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:37,954 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:44, output treesize:18 [2018-10-27 04:47:38,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2018-10-27 04:47:38,027 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:38,031 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2018-10-27 04:47:38,032 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:38,033 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:38,033 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:1 [2018-10-27 04:47:38,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:38,046 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:38,047 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:38,048 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-10-27 04:47:38,048 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-10-27 04:47:38,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-10-27 04:47:38,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-10-27 04:47:38,048 INFO L87 Difference]: Start difference. First operand 181 states and 197 transitions. Second operand 11 states. [2018-10-27 04:47:39,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:39,189 INFO L93 Difference]: Finished difference Result 180 states and 195 transitions. [2018-10-27 04:47:39,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-10-27 04:47:39,190 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 32 [2018-10-27 04:47:39,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:39,190 INFO L225 Difference]: With dead ends: 180 [2018-10-27 04:47:39,190 INFO L226 Difference]: Without dead ends: 180 [2018-10-27 04:47:39,191 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=54, Invalid=218, Unknown=0, NotChecked=0, Total=272 [2018-10-27 04:47:39,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-10-27 04:47:39,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-10-27 04:47:39,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-10-27 04:47:39,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 195 transitions. [2018-10-27 04:47:39,195 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 195 transitions. Word has length 32 [2018-10-27 04:47:39,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:39,195 INFO L481 AbstractCegarLoop]: Abstraction has 180 states and 195 transitions. [2018-10-27 04:47:39,195 INFO L482 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-10-27 04:47:39,195 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 195 transitions. [2018-10-27 04:47:39,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-27 04:47:39,196 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:39,196 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:39,196 INFO L424 AbstractCegarLoop]: === Iteration 20 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:39,196 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:39,197 INFO L82 PathProgramCache]: Analyzing trace with hash -480478103, now seen corresponding path program 1 times [2018-10-27 04:47:39,197 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:39,197 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:39,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:39,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:39,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:39,447 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:39,448 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,455 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,455 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:39,482 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:39,484 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:39,484 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-10-27 04:47:39,485 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,513 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:47:39,515 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:47:39,515 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,517 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,530 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:47:39,532 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:47:39,532 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,534 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,543 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,543 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:43, output treesize:29 [2018-10-27 04:47:39,582 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 22 [2018-10-27 04:47:39,589 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:39,589 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,597 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,619 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 22 [2018-10-27 04:47:39,621 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:39,622 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,629 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,643 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,643 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:48, output treesize:26 [2018-10-27 04:47:39,668 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 22 [2018-10-27 04:47:39,681 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:39,681 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,689 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,711 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 22 [2018-10-27 04:47:39,714 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:47:39,714 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,721 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,735 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,735 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:48, output treesize:22 [2018-10-27 04:47:39,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:39,850 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:39,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:39,853 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-10-27 04:47:39,853 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-10-27 04:47:39,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-10-27 04:47:39,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-10-27 04:47:39,853 INFO L87 Difference]: Start difference. First operand 180 states and 195 transitions. Second operand 11 states. [2018-10-27 04:47:40,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:40,695 INFO L93 Difference]: Finished difference Result 168 states and 180 transitions. [2018-10-27 04:47:40,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-27 04:47:40,697 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 34 [2018-10-27 04:47:40,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:40,698 INFO L225 Difference]: With dead ends: 168 [2018-10-27 04:47:40,698 INFO L226 Difference]: Without dead ends: 168 [2018-10-27 04:47:40,698 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2018-10-27 04:47:40,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states. [2018-10-27 04:47:40,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 168. [2018-10-27 04:47:40,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-10-27 04:47:40,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 180 transitions. [2018-10-27 04:47:40,702 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 180 transitions. Word has length 34 [2018-10-27 04:47:40,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:40,703 INFO L481 AbstractCegarLoop]: Abstraction has 168 states and 180 transitions. [2018-10-27 04:47:40,703 INFO L482 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-10-27 04:47:40,703 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 180 transitions. [2018-10-27 04:47:40,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-27 04:47:40,703 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:40,704 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:40,704 INFO L424 AbstractCegarLoop]: === Iteration 21 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:40,704 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:40,704 INFO L82 PathProgramCache]: Analyzing trace with hash 1152905065, now seen corresponding path program 1 times [2018-10-27 04:47:40,704 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:40,704 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:40,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:40,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:40,852 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:40,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:40,858 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:47:40,859 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:47:40,859 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:47:40,860 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:47:40,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:47:40,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:40,860 INFO L87 Difference]: Start difference. First operand 168 states and 180 transitions. Second operand 3 states. [2018-10-27 04:47:41,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:41,028 INFO L93 Difference]: Finished difference Result 183 states and 196 transitions. [2018-10-27 04:47:41,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:47:41,029 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 41 [2018-10-27 04:47:41,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:41,030 INFO L225 Difference]: With dead ends: 183 [2018-10-27 04:47:41,030 INFO L226 Difference]: Without dead ends: 183 [2018-10-27 04:47:41,030 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:47:41,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-10-27 04:47:41,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 172. [2018-10-27 04:47:41,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-10-27 04:47:41,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 184 transitions. [2018-10-27 04:47:41,033 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 184 transitions. Word has length 41 [2018-10-27 04:47:41,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:41,035 INFO L481 AbstractCegarLoop]: Abstraction has 172 states and 184 transitions. [2018-10-27 04:47:41,035 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:47:41,035 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 184 transitions. [2018-10-27 04:47:41,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-27 04:47:41,036 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:41,036 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:41,036 INFO L424 AbstractCegarLoop]: === Iteration 22 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:47:41,037 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:41,037 INFO L82 PathProgramCache]: Analyzing trace with hash -2007997801, now seen corresponding path program 1 times [2018-10-27 04:47:41,037 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:47:41,037 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:47:41,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:41,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:41,488 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:41,502 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:41,502 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:41,578 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:41,578 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:41,682 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:41,686 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:41,686 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:47:41,687 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:41,694 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:41,694 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:20, output treesize:18 [2018-10-27 04:47:41,903 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-10-27 04:47:41,903 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:42,056 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:42,057 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:33, output treesize:30 [2018-10-27 04:47:42,149 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:42,152 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 17 [2018-10-27 04:47:42,152 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:42,172 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:42,173 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:42,174 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:42,175 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 13 [2018-10-27 04:47:42,175 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:42,192 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:42,192 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:38, output treesize:11 [2018-10-27 04:47:42,256 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:42,256 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:47:45,139 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2018-10-27 04:47:45,140 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:45,230 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2018-10-27 04:47:45,231 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:45,234 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 25 [2018-10-27 04:47:45,235 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:45,306 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2018-10-27 04:47:45,307 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:47:45,372 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 3 dim-1 vars, End of recursive call: 12 dim-0 vars, and 4 xjuncts. [2018-10-27 04:47:45,372 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 10 variables, input treesize:73, output treesize:86 [2018-10-27 04:47:51,727 WARN L179 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 51 [2018-10-27 04:47:51,730 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:51,731 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:51,737 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:51,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:51,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:52,573 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:52,603 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 17 [2018-10-27 04:47:52,603 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:52,622 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:52,630 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:47:52,631 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 4 [2018-10-27 04:47:52,631 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:52,641 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:52,641 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:11 [2018-10-27 04:47:52,645 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:47:52,645 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:00,959 WARN L179 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 33 [2018-10-27 04:48:01,190 WARN L179 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 1 [2018-10-27 04:48:01,191 INFO L267 ElimStorePlain]: Start of recursive call 1: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:01,191 INFO L202 ElimStorePlain]: Needed 1 recursive calls to eliminate 9 variables, input treesize:98, output treesize:1 [2018-10-27 04:48:08,037 WARN L179 SmtUtils]: Spent 141.00 ms on a formula simplification that was a NOOP. DAG size: 45 [2018-10-27 04:48:08,400 WARN L179 SmtUtils]: Spent 111.00 ms on a formula simplification that was a NOOP. DAG size: 46 [2018-10-27 04:48:08,610 WARN L179 SmtUtils]: Spent 199.00 ms on a formula simplification that was a NOOP. DAG size: 69 [2018-10-27 04:48:08,690 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 50 treesize of output 54 [2018-10-27 04:48:08,692 INFO L267 ElimStorePlain]: Start of recursive call 2: 3 dim-0 vars, End of recursive call: 3 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:08,764 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 53 treesize of output 71 [2018-10-27 04:48:08,770 INFO L267 ElimStorePlain]: Start of recursive call 3: 13 dim-0 vars, End of recursive call: 13 dim-0 vars, and 8 xjuncts. [2018-10-27 04:48:08,861 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 69 [2018-10-27 04:48:08,867 INFO L267 ElimStorePlain]: Start of recursive call 4: 13 dim-0 vars, End of recursive call: 13 dim-0 vars, and 8 xjuncts. [2018-10-27 04:48:11,494 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 46 treesize of output 50 [2018-10-27 04:48:11,496 INFO L267 ElimStorePlain]: Start of recursive call 5: 3 dim-0 vars, End of recursive call: 3 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:14,259 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 48 [2018-10-27 04:48:14,261 INFO L267 ElimStorePlain]: Start of recursive call 6: 3 dim-0 vars, End of recursive call: 3 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:17,104 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 3 dim-1 vars, End of recursive call: 65 dim-0 vars, and 22 xjuncts. [2018-10-27 04:48:17,104 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 7 variables, input treesize:142, output treesize:1066 [2018-10-27 04:48:22,067 WARN L179 SmtUtils]: Spent 2.33 s on a formula simplification. DAG size of input: 390 DAG size of output: 93 [2018-10-27 04:48:22,080 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,080 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,081 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 27 [2018-10-27 04:48:22,082 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:22,357 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,357 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,359 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 39 [2018-10-27 04:48:22,359 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:22,623 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,624 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,625 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 28 [2018-10-27 04:48:22,625 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:22,876 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,876 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:22,877 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 42 [2018-10-27 04:48:22,879 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:23,157 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:23,158 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:23,159 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 25 [2018-10-27 04:48:23,159 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:23,427 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:23,428 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:23,429 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 22 [2018-10-27 04:48:23,429 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:23,596 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:23,596 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:23,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 36 [2018-10-27 04:48:23,598 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:23,742 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 7 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-10-27 04:48:23,743 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 16 variables, input treesize:286, output treesize:138 [2018-10-27 04:48:24,143 WARN L179 SmtUtils]: Spent 165.00 ms on a formula simplification that was a NOOP. DAG size: 44 [2018-10-27 04:48:24,646 WARN L179 SmtUtils]: Spent 210.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 32 [2018-10-27 04:48:24,661 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:48:24,678 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-10-27 04:48:24,678 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 10] total 32 [2018-10-27 04:48:24,679 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-10-27 04:48:24,679 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-10-27 04:48:24,679 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=1000, Unknown=6, NotChecked=0, Total=1122 [2018-10-27 04:48:24,680 INFO L87 Difference]: Start difference. First operand 172 states and 184 transitions. Second operand 33 states. [2018-10-27 04:48:26,338 WARN L179 SmtUtils]: Spent 350.00 ms on a formula simplification that was a NOOP. DAG size: 25 [2018-10-27 04:48:26,981 WARN L179 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 41 [2018-10-27 04:48:27,388 WARN L179 SmtUtils]: Spent 205.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 48 [2018-10-27 04:48:28,552 WARN L179 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 32 [2018-10-27 04:48:29,037 WARN L179 SmtUtils]: Spent 202.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 32 [2018-10-27 04:48:29,864 WARN L179 SmtUtils]: Spent 336.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 37 [2018-10-27 04:48:31,067 WARN L179 SmtUtils]: Spent 587.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 44 [2018-10-27 04:48:34,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:34,661 INFO L93 Difference]: Finished difference Result 207 states and 217 transitions. [2018-10-27 04:48:34,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-10-27 04:48:34,664 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 43 [2018-10-27 04:48:34,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:34,664 INFO L225 Difference]: With dead ends: 207 [2018-10-27 04:48:34,664 INFO L226 Difference]: Without dead ends: 207 [2018-10-27 04:48:34,665 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 101 SyntacticMatches, 3 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440 ImplicationChecksByTransitivity, 34.5s TimeCoverageRelationStatistics Valid=327, Invalid=1828, Unknown=7, NotChecked=0, Total=2162 [2018-10-27 04:48:34,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-10-27 04:48:34,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 169. [2018-10-27 04:48:34,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-10-27 04:48:34,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 178 transitions. [2018-10-27 04:48:34,669 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 178 transitions. Word has length 43 [2018-10-27 04:48:34,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:34,669 INFO L481 AbstractCegarLoop]: Abstraction has 169 states and 178 transitions. [2018-10-27 04:48:34,671 INFO L482 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-10-27 04:48:34,671 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 178 transitions. [2018-10-27 04:48:34,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-27 04:48:34,671 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:34,671 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:34,672 INFO L424 AbstractCegarLoop]: === Iteration 23 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:48:34,672 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:34,672 INFO L82 PathProgramCache]: Analyzing trace with hash -468036069, now seen corresponding path program 1 times [2018-10-27 04:48:34,672 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:48:34,673 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:48:34,697 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:34,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:34,918 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:34,938 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:34,939 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:34,942 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:34,942 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:48:34,958 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_write~$Pointer$_#value.base| (_ BitVec 32))) (and (= |c_#valid| (store |c_old(#valid)| |append_write~$Pointer$_#value.base| (_ bv1 1))) (= (select |c_old(#valid)| |append_write~$Pointer$_#value.base|) (_ bv0 1)))) is different from true [2018-10-27 04:48:34,972 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:34,974 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:34,974 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 23 [2018-10-27 04:48:34,975 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:34,983 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:34,983 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:19, output treesize:16 [2018-10-27 04:48:35,035 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:35,036 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 20 [2018-10-27 04:48:35,037 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:35,044 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:35,044 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:22, output treesize:20 [2018-10-27 04:48:35,083 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:48:35,083 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:35,210 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:35,210 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:35,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:35,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:35,332 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:35,350 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:35,350 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:35,364 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:35,364 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-10-27 04:48:35,368 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#t~malloc2.base| (_ BitVec 32))) (and (= |c_#valid| (store |c_old(#valid)| |append_#t~malloc2.base| (_ bv1 1))) (= (select |c_old(#valid)| |append_#t~malloc2.base|) (_ bv0 1)))) is different from true [2018-10-27 04:48:35,385 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:35,390 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:35,390 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:48:35,391 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:35,396 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:35,396 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:16 [2018-10-27 04:48:35,409 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:35,410 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:35,410 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:48:35,411 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 42 [2018-10-27 04:48:35,411 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:35,422 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:35,423 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:27, output treesize:31 [2018-10-27 04:48:35,746 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 3 not checked. [2018-10-27 04:48:35,747 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:35,925 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:35,926 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8] total 12 [2018-10-27 04:48:35,926 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-10-27 04:48:35,926 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-10-27 04:48:35,926 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=226, Unknown=4, NotChecked=62, Total=342 [2018-10-27 04:48:35,926 INFO L87 Difference]: Start difference. First operand 169 states and 178 transitions. Second operand 13 states. [2018-10-27 04:48:36,843 WARN L179 SmtUtils]: Spent 235.00 ms on a formula simplification that was a NOOP. DAG size: 17 [2018-10-27 04:48:39,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:39,370 INFO L93 Difference]: Finished difference Result 199 states and 207 transitions. [2018-10-27 04:48:39,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:48:39,371 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 44 [2018-10-27 04:48:39,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:39,371 INFO L225 Difference]: With dead ends: 199 [2018-10-27 04:48:39,371 INFO L226 Difference]: Without dead ends: 199 [2018-10-27 04:48:39,372 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 86 SyntacticMatches, 7 SemanticMatches, 20 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 66 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=78, Invalid=306, Unknown=4, NotChecked=74, Total=462 [2018-10-27 04:48:39,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-10-27 04:48:39,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 168. [2018-10-27 04:48:39,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-10-27 04:48:39,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 177 transitions. [2018-10-27 04:48:39,375 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 177 transitions. Word has length 44 [2018-10-27 04:48:39,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:39,375 INFO L481 AbstractCegarLoop]: Abstraction has 168 states and 177 transitions. [2018-10-27 04:48:39,375 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-10-27 04:48:39,375 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 177 transitions. [2018-10-27 04:48:39,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-27 04:48:39,376 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:39,376 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:39,376 INFO L424 AbstractCegarLoop]: === Iteration 24 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:48:39,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:39,376 INFO L82 PathProgramCache]: Analyzing trace with hash -1624216089, now seen corresponding path program 1 times [2018-10-27 04:48:39,377 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:48:39,377 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:48:39,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:39,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:39,782 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:39,798 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:39,798 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:39,910 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:39,910 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:39,982 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:39,982 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-10-27 04:48:40,029 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_~size| (_ BitVec 32)) (|append_write~$Pointer$_#value.base| (_ BitVec 32))) (and (= |c_#length| (store |c_old(#length)| |append_write~$Pointer$_#value.base| |append_#Ultimate.alloc_~size|)) (= (select |c_old(#valid)| |append_write~$Pointer$_#value.base|) (_ bv0 1)))) is different from true [2018-10-27 04:48:40,036 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,037 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,037 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 4 [2018-10-27 04:48:40,038 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,049 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:48:40,049 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,057 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,057 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:27, output treesize:9 [2018-10-27 04:48:40,161 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,167 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 15 [2018-10-27 04:48:40,167 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:40,179 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:40,179 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:24 [2018-10-27 04:48:40,260 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:48:40,260 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:40,718 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:40,719 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:40,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:40,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:40,789 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:40,791 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:40,791 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,799 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:40,800 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,806 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,806 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:17 [2018-10-27 04:48:40,839 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_~size| (_ BitVec 32)) (|append_#t~malloc2.base| (_ BitVec 32))) (and (= |c_#length| (store |c_old(#length)| |append_#t~malloc2.base| |append_#Ultimate.alloc_~size|)) (= (select |c_old(#valid)| |append_#t~malloc2.base|) (_ bv0 1)))) is different from true [2018-10-27 04:48:40,880 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,882 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:48:40,882 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,895 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,896 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,896 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 4 [2018-10-27 04:48:40,896 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,904 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:40,904 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:27, output treesize:9 [2018-10-27 04:48:40,908 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:40,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 15 [2018-10-27 04:48:40,915 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:40,928 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:40,928 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:24 [2018-10-27 04:48:40,944 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 4 not checked. [2018-10-27 04:48:40,944 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:41,232 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:41,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 11 [2018-10-27 04:48:41,232 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-27 04:48:41,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-27 04:48:41,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=174, Unknown=2, NotChecked=54, Total=272 [2018-10-27 04:48:41,233 INFO L87 Difference]: Start difference. First operand 168 states and 177 transitions. Second operand 12 states. [2018-10-27 04:48:46,152 WARN L179 SmtUtils]: Spent 4.17 s on a formula simplification. DAG size of input: 51 DAG size of output: 45 [2018-10-27 04:48:47,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:47,558 INFO L93 Difference]: Finished difference Result 214 states and 227 transitions. [2018-10-27 04:48:47,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-10-27 04:48:47,560 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 45 [2018-10-27 04:48:47,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:47,561 INFO L225 Difference]: With dead ends: 214 [2018-10-27 04:48:47,561 INFO L226 Difference]: Without dead ends: 214 [2018-10-27 04:48:47,561 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 92 SyntacticMatches, 8 SemanticMatches, 18 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=60, Invalid=252, Unknown=2, NotChecked=66, Total=380 [2018-10-27 04:48:47,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2018-10-27 04:48:47,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 207. [2018-10-27 04:48:47,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-10-27 04:48:47,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 224 transitions. [2018-10-27 04:48:47,565 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 224 transitions. Word has length 45 [2018-10-27 04:48:47,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:47,567 INFO L481 AbstractCegarLoop]: Abstraction has 207 states and 224 transitions. [2018-10-27 04:48:47,567 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-27 04:48:47,567 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 224 transitions. [2018-10-27 04:48:47,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-27 04:48:47,568 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:47,568 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:47,568 INFO L424 AbstractCegarLoop]: === Iteration 25 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:48:47,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:47,568 INFO L82 PathProgramCache]: Analyzing trace with hash 80213248, now seen corresponding path program 1 times [2018-10-27 04:48:47,569 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:48:47,569 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:48:47,599 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:47,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:47,895 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:47,902 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:47,902 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:47,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:47,914 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:47,921 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:47,922 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-10-27 04:48:47,947 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_~size| (_ BitVec 32)) (|append_write~$Pointer$_#value.base| (_ BitVec 32))) (and (= |c_#length| (store |c_old(#length)| |append_write~$Pointer$_#value.base| |append_#Ultimate.alloc_~size|)) (= (select |c_old(#valid)| |append_write~$Pointer$_#value.base|) (_ bv0 1)))) is different from true [2018-10-27 04:48:47,955 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:47,957 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:48:47,957 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:47,970 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:47,971 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:47,972 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 4 [2018-10-27 04:48:47,972 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:47,981 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:47,981 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:27, output treesize:9 [2018-10-27 04:48:48,025 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:48,031 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 15 [2018-10-27 04:48:48,031 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:48,045 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:48,045 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:24 [2018-10-27 04:48:48,195 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:48:48,195 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:49,132 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:49,132 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:49,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:49,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:49,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:49,275 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:49,275 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,283 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:49,284 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,291 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,291 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:17 [2018-10-27 04:48:49,336 WARN L854 $PredicateComparison]: unable to prove that (exists ((|append_#Ultimate.alloc_~size| (_ BitVec 32)) (|append_#t~malloc2.base| (_ BitVec 32))) (and (= |c_#length| (store |c_old(#length)| |append_#t~malloc2.base| |append_#Ultimate.alloc_~size|)) (= (select |c_old(#valid)| |append_#t~malloc2.base|) (_ bv0 1)))) is different from true [2018-10-27 04:48:49,394 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:49,398 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-10-27 04:48:49,398 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,411 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:49,413 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:49,413 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 4 [2018-10-27 04:48:49,413 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,422 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,422 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:27, output treesize:9 [2018-10-27 04:48:49,426 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:49,432 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 15 [2018-10-27 04:48:49,432 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:49,444 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:49,445 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:24 [2018-10-27 04:48:49,485 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 7 not checked. [2018-10-27 04:48:49,485 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:48:50,127 WARN L179 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 31 [2018-10-27 04:48:51,087 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:51,087 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 12 [2018-10-27 04:48:51,088 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-10-27 04:48:51,088 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-10-27 04:48:51,088 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=427, Unknown=3, NotChecked=86, Total=600 [2018-10-27 04:48:51,088 INFO L87 Difference]: Start difference. First operand 207 states and 224 transitions. Second operand 13 states. [2018-10-27 04:48:52,127 WARN L179 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 36 [2018-10-27 04:48:52,446 WARN L179 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 46 [2018-10-27 04:48:55,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:55,262 INFO L93 Difference]: Finished difference Result 212 states and 225 transitions. [2018-10-27 04:48:55,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-10-27 04:48:55,263 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 48 [2018-10-27 04:48:55,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:55,264 INFO L225 Difference]: With dead ends: 212 [2018-10-27 04:48:55,264 INFO L226 Difference]: Without dead ends: 212 [2018-10-27 04:48:55,265 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 96 SyntacticMatches, 8 SemanticMatches, 27 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 143 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=123, Invalid=584, Unknown=3, NotChecked=102, Total=812 [2018-10-27 04:48:55,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-10-27 04:48:55,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 205. [2018-10-27 04:48:55,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-10-27 04:48:55,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 220 transitions. [2018-10-27 04:48:55,268 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 220 transitions. Word has length 48 [2018-10-27 04:48:55,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:55,268 INFO L481 AbstractCegarLoop]: Abstraction has 205 states and 220 transitions. [2018-10-27 04:48:55,268 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-10-27 04:48:55,268 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 220 transitions. [2018-10-27 04:48:55,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-27 04:48:55,269 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:55,269 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:55,269 INFO L424 AbstractCegarLoop]: === Iteration 26 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:48:55,278 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:55,278 INFO L82 PathProgramCache]: Analyzing trace with hash 1631228433, now seen corresponding path program 1 times [2018-10-27 04:48:55,279 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:48:55,279 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:48:55,302 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:55,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:55,562 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:55,633 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:48:55,634 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-10-27 04:48:55,636 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:48:55,636 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:48:55,636 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:48:55,636 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:48:55,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:48:55,637 INFO L87 Difference]: Start difference. First operand 205 states and 220 transitions. Second operand 8 states. [2018-10-27 04:48:56,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:56,508 INFO L93 Difference]: Finished difference Result 207 states and 219 transitions. [2018-10-27 04:48:56,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:48:56,510 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-10-27 04:48:56,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:56,510 INFO L225 Difference]: With dead ends: 207 [2018-10-27 04:48:56,511 INFO L226 Difference]: Without dead ends: 207 [2018-10-27 04:48:56,511 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:48:56,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-10-27 04:48:56,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 203. [2018-10-27 04:48:56,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-10-27 04:48:56,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 217 transitions. [2018-10-27 04:48:56,514 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 217 transitions. Word has length 51 [2018-10-27 04:48:56,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:56,514 INFO L481 AbstractCegarLoop]: Abstraction has 203 states and 217 transitions. [2018-10-27 04:48:56,514 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:48:56,514 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 217 transitions. [2018-10-27 04:48:56,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-27 04:48:56,515 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:56,515 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:56,515 INFO L424 AbstractCegarLoop]: === Iteration 27 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:48:56,515 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:56,515 INFO L82 PathProgramCache]: Analyzing trace with hash -1950672898, now seen corresponding path program 1 times [2018-10-27 04:48:56,516 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:48:56,516 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:48:56,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:56,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:57,002 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:57,004 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:57,004 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,023 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,023 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-10-27 04:48:57,046 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,047 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,048 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:48:57,048 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,059 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,060 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:20, output treesize:18 [2018-10-27 04:48:57,130 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:48:57,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:48:57,133 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,136 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,146 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,146 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-10-27 04:48:57,217 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 21 treesize of output 33 [2018-10-27 04:48:57,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-10-27 04:48:57,220 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,304 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 19 treesize of output 26 [2018-10-27 04:48:57,305 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:57,339 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:48:57,372 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:48:57,372 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:32, output treesize:37 [2018-10-27 04:48:57,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 20 [2018-10-27 04:48:57,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:48:57,419 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,426 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,505 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 47 treesize of output 52 [2018-10-27 04:48:57,508 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-10-27 04:48:57,509 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,610 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 35 treesize of output 34 [2018-10-27 04:48:57,610 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:57,651 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:48:57,703 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:48:57,703 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:71, output treesize:37 [2018-10-27 04:48:57,751 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,753 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,754 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,754 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 57 [2018-10-27 04:48:57,755 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,798 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:57,798 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:75, output treesize:51 [2018-10-27 04:48:57,920 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,922 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,923 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,924 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:48:57,925 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 73 [2018-10-27 04:48:57,925 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:57,952 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:57,952 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:60, output treesize:70 [2018-10-27 04:48:58,189 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 54 [2018-10-27 04:48:58,211 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-10-27 04:48:58,212 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:58,225 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:58,258 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:58,258 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:83, output treesize:79 [2018-10-27 04:48:58,368 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 55 [2018-10-27 04:48:58,384 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 18 treesize of output 23 [2018-10-27 04:48:58,385 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-10-27 04:48:58,411 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:48:58,485 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 5 dim-0 vars, and 2 xjuncts. [2018-10-27 04:48:58,485 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:90, output treesize:148 [2018-10-27 04:48:58,591 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 33 [2018-10-27 04:48:58,594 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 20 [2018-10-27 04:48:58,595 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:58,604 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:58,624 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-10-27 04:48:58,624 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:72, output treesize:49 [2018-10-27 04:48:58,689 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:48:58,689 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:49:10,380 WARN L179 SmtUtils]: Spent 135.00 ms on a formula simplification that was a NOOP. DAG size: 24 [2018-10-27 04:49:21,148 WARN L179 SmtUtils]: Spent 284.00 ms on a formula simplification that was a NOOP. DAG size: 68 [2018-10-27 04:49:21,326 WARN L179 SmtUtils]: Spent 176.00 ms on a formula simplification that was a NOOP. DAG size: 48 [2018-10-27 04:49:21,553 WARN L179 SmtUtils]: Spent 225.00 ms on a formula simplification that was a NOOP. DAG size: 56 [2018-10-27 04:49:21,755 WARN L179 SmtUtils]: Spent 202.00 ms on a formula simplification that was a NOOP. DAG size: 54 [2018-10-27 04:49:21,791 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 129 treesize of output 81 [2018-10-27 04:49:22,006 WARN L179 SmtUtils]: Spent 213.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 50 [2018-10-27 04:49:22,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 10 [2018-10-27 04:49:22,020 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:22,179 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:22,262 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 4 case distinctions, treesize of input 56 treesize of output 75 [2018-10-27 04:49:22,530 WARN L179 SmtUtils]: Spent 266.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 76 [2018-10-27 04:49:22,598 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 47 treesize of output 57 [2018-10-27 04:49:22,614 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:22,620 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:22,641 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 3 case distinctions, treesize of input 50 treesize of output 65 [2018-10-27 04:49:22,642 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 3 xjuncts. [2018-10-27 04:49:22,947 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 45 treesize of output 55 [2018-10-27 04:49:22,947 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,085 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:49:23,354 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 59 [2018-10-27 04:49:23,377 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 16 treesize of output 22 [2018-10-27 04:49:23,378 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,424 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,709 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 42 [2018-10-27 04:49:23,731 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 24 [2018-10-27 04:49:23,731 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,766 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,772 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 40 [2018-10-27 04:49:23,795 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 30 treesize of output 28 [2018-10-27 04:49:23,795 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,830 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:23,834 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 40 [2018-10-27 04:49:23,849 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2018-10-27 04:49:23,849 INFO L267 ElimStorePlain]: Start of recursive call 15: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:23,865 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,084 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:24,092 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 53 [2018-10-27 04:49:24,100 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 33 [2018-10-27 04:49:24,149 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2018-10-27 04:49:24,149 INFO L267 ElimStorePlain]: Start of recursive call 18: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,161 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,196 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 8 [2018-10-27 04:49:24,196 INFO L267 ElimStorePlain]: Start of recursive call 19: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:24,214 INFO L267 ElimStorePlain]: Start of recursive call 16: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:24,217 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:24,224 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 51 [2018-10-27 04:49:24,232 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 33 [2018-10-27 04:49:24,279 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2018-10-27 04:49:24,279 INFO L267 ElimStorePlain]: Start of recursive call 22: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,289 INFO L267 ElimStorePlain]: Start of recursive call 21: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,313 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 1 [2018-10-27 04:49:24,313 INFO L267 ElimStorePlain]: Start of recursive call 23: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,326 INFO L267 ElimStorePlain]: Start of recursive call 20: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:24,466 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, 3 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:49:24,521 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:49:24,587 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 3 xjuncts. [2018-10-27 04:49:24,588 INFO L202 ElimStorePlain]: Needed 23 recursive calls to eliminate 10 variables, input treesize:145, output treesize:86 [2018-10-27 04:49:26,713 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:26,714 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:26,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:49:26,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:26,845 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:26,850 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:49:26,850 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:26,862 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:26,862 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:49:26,870 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:26,871 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:26,871 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:49:26,872 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:26,886 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:49:26,887 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:20, output treesize:18 [2018-10-27 04:49:27,460 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:49:27,465 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:49:27,465 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:27,468 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:27,486 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:27,486 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:40, output treesize:36 [2018-10-27 04:49:27,632 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 21 treesize of output 33 [2018-10-27 04:49:27,683 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 19 treesize of output 26 [2018-10-27 04:49:27,683 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:27,756 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-10-27 04:49:27,757 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:27,798 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:27,840 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:27,840 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:44, output treesize:61 [2018-10-27 04:49:30,058 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 59 treesize of output 64 [2018-10-27 04:49:30,078 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 59 [2018-10-27 04:49:30,079 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:30,260 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 40 treesize of output 39 [2018-10-27 04:49:30,260 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:30,328 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:30,443 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 25 [2018-10-27 04:49:30,446 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:49:30,446 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:30,461 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:30,541 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:30,541 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:88, output treesize:54 [2018-10-27 04:49:30,686 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-10-27 04:49:30,686 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:30,706 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,707 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,709 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,710 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 54 [2018-10-27 04:49:30,710 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:30,729 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:49:30,730 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:92, output treesize:51 [2018-10-27 04:49:30,845 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,847 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,848 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,850 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:30,851 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 73 [2018-10-27 04:49:30,851 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:30,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:49:30,888 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:60, output treesize:70 [2018-10-27 04:49:31,387 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 48 [2018-10-27 04:49:31,391 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:49:31,392 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:31,406 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:31,438 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:49:31,438 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:77, output treesize:66 [2018-10-27 04:49:31,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2018-10-27 04:49:31,602 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:49:31,603 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:31,621 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:31,657 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-10-27 04:49:31,657 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:79, output treesize:68 [2018-10-27 04:49:31,735 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 33 [2018-10-27 04:49:31,739 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 20 [2018-10-27 04:49:31,739 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:31,751 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:31,776 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-10-27 04:49:31,776 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:72, output treesize:49 [2018-10-27 04:49:31,791 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:49:31,791 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:49:33,845 WARN L832 $PredicateComparison]: unable to prove that (forall ((|append_write~$Pointer$_#ptr.offset| (_ BitVec 32)) (v_subst_3 (_ BitVec 32)) (v_subst_4 (_ BitVec 32)) (|append_write~$Pointer$_#value.base| (_ BitVec 32))) (= (bvadd (select |c_#valid| (select (select (let ((.cse0 (store |c_append_write~$Pointer$_old_#memory_$Pointer$.base| |c_append_write~$Pointer$_#ptr.base| (store (select |c_append_write~$Pointer$_old_#memory_$Pointer$.base| |c_append_write~$Pointer$_#ptr.base|) |append_write~$Pointer$_#ptr.offset| |append_write~$Pointer$_#value.base|)))) (store .cse0 c_append_~node~0.base (store (select .cse0 c_append_~node~0.base) v_subst_3 v_subst_4))) c_append_~head.base) (bvadd c_append_~head.offset (_ bv4 32)))) (_ bv1 1)) (_ bv0 1))) is different from false [2018-10-27 04:49:39,855 WARN L179 SmtUtils]: Spent 1.87 s on a formula simplification that was a NOOP. DAG size: 28 [2018-10-27 04:49:44,164 WARN L179 SmtUtils]: Spent 344.00 ms on a formula simplification that was a NOOP. DAG size: 70 [2018-10-27 04:49:44,383 WARN L179 SmtUtils]: Spent 218.00 ms on a formula simplification that was a NOOP. DAG size: 52 [2018-10-27 04:49:44,668 WARN L179 SmtUtils]: Spent 283.00 ms on a formula simplification that was a NOOP. DAG size: 60 [2018-10-27 04:49:45,031 WARN L179 SmtUtils]: Spent 362.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-10-27 04:49:45,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 64 [2018-10-27 04:49:45,227 WARN L179 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 50 [2018-10-27 04:49:45,238 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 10 [2018-10-27 04:49:45,238 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:45,302 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:45,303 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:45,312 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:45,326 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 67 [2018-10-27 04:49:45,484 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 21 treesize of output 31 [2018-10-27 04:49:45,509 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:49:45,515 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:49:45,754 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 45 [2018-10-27 04:49:45,754 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 3 xjuncts. [2018-10-27 04:49:45,943 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 22 treesize of output 32 [2018-10-27 04:49:45,943 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,344 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:49:46,427 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 38 [2018-10-27 04:49:46,454 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 24 [2018-10-27 04:49:46,454 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,497 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,517 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 38 [2018-10-27 04:49:46,606 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 24 [2018-10-27 04:49:46,606 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,646 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,663 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 36 [2018-10-27 04:49:46,670 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2018-10-27 04:49:46,671 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:46,691 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:46,750 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,789 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:49:46,859 INFO L267 ElimStorePlain]: Start of recursive call 1: 10 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-10-27 04:49:46,859 INFO L202 ElimStorePlain]: Needed 13 recursive calls to eliminate 11 variables, input treesize:123, output treesize:67 [2018-10-27 04:49:49,110 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:49:49,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 21] total 30 [2018-10-27 04:49:49,111 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-10-27 04:49:49,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-10-27 04:49:49,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=1802, Unknown=12, NotChecked=86, Total=2070 [2018-10-27 04:49:49,112 INFO L87 Difference]: Start difference. First operand 203 states and 217 transitions. Second operand 31 states. [2018-10-27 04:49:50,987 WARN L179 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 35 [2018-10-27 04:49:51,425 WARN L179 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 47 [2018-10-27 04:49:51,972 WARN L179 SmtUtils]: Spent 241.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 52 [2018-10-27 04:49:52,790 WARN L179 SmtUtils]: Spent 402.00 ms on a formula simplification that was a NOOP. DAG size: 32 [2018-10-27 04:49:53,367 WARN L179 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 46 [2018-10-27 04:49:53,659 WARN L179 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 50 [2018-10-27 04:49:54,054 WARN L179 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 101 DAG size of output: 65 [2018-10-27 04:49:54,418 WARN L179 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 66 [2018-10-27 04:49:54,987 WARN L179 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 57 [2018-10-27 04:49:55,346 WARN L179 SmtUtils]: Spent 189.00 ms on a formula simplification. DAG size of input: 108 DAG size of output: 69 [2018-10-27 04:49:56,142 WARN L179 SmtUtils]: Spent 324.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 68 [2018-10-27 04:49:57,538 WARN L179 SmtUtils]: Spent 653.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 75 [2018-10-27 04:49:59,533 WARN L179 SmtUtils]: Spent 411.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 70 [2018-10-27 04:50:00,260 WARN L179 SmtUtils]: Spent 221.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 47 [2018-10-27 04:50:01,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:50:01,741 INFO L93 Difference]: Finished difference Result 242 states and 257 transitions. [2018-10-27 04:50:01,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-10-27 04:50:01,742 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 54 [2018-10-27 04:50:01,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:50:01,743 INFO L225 Difference]: With dead ends: 242 [2018-10-27 04:50:01,743 INFO L226 Difference]: Without dead ends: 242 [2018-10-27 04:50:01,744 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 96 SyntacticMatches, 6 SemanticMatches, 63 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 1034 ImplicationChecksByTransitivity, 49.1s TimeCoverageRelationStatistics Valid=487, Invalid=3537, Unknown=12, NotChecked=124, Total=4160 [2018-10-27 04:50:01,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-10-27 04:50:01,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 203. [2018-10-27 04:50:01,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-10-27 04:50:01,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 216 transitions. [2018-10-27 04:50:01,749 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 216 transitions. Word has length 54 [2018-10-27 04:50:01,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:50:01,749 INFO L481 AbstractCegarLoop]: Abstraction has 203 states and 216 transitions. [2018-10-27 04:50:01,749 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-10-27 04:50:01,749 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 216 transitions. [2018-10-27 04:50:01,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-27 04:50:01,750 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:50:01,750 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:50:01,750 INFO L424 AbstractCegarLoop]: === Iteration 28 === [mainErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr25ASSERT_VIOLATIONMEMORY_FREE, mainErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr23ASSERT_VIOLATIONMEMORY_FREE, mainErr22ASSERT_VIOLATIONMEMORY_FREE, mainErr28ENSURES_VIOLATIONMEMORY_LEAK, mainErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr24ASSERT_VIOLATIONMEMORY_FREE, mainErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr26ASSERT_VIOLATIONMEMORY_FREE, mainErr14ASSERT_VIOLATIONMEMORY_FREE, mainErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, mainErr15ASSERT_VIOLATIONMEMORY_FREE, mainErr27ASSERT_VIOLATIONMEMORY_FREE, appendErr24ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr10ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr7ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr22ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr19ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr8ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr15ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr23ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr6ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr4ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr5ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr12ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr25ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr3ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr18ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr2ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr16ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr13ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr14ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr9ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr17ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr20ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr21ASSERT_VIOLATIONMEMORY_DEREFERENCE, appendErr11ASSERT_VIOLATIONMEMORY_DEREFERENCE]=== [2018-10-27 04:50:01,750 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:50:01,750 INFO L82 PathProgramCache]: Analyzing trace with hash -341317482, now seen corresponding path program 1 times [2018-10-27 04:50:01,751 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-10-27 04:50:01,751 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9680befc-cd50-46b8-b9ee-9d85158452ac/bin-2019/utaipan/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:50:01,776 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:50:02,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:50:02,357 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:50:02,382 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:50:02,382 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:02,458 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:02,459 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:50:02,604 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:02,637 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:02,639 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-10-27 04:50:02,639 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:02,786 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:02,786 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:20, output treesize:18 [2018-10-27 04:50:02,970 WARN L179 SmtUtils]: Spent 132.00 ms on a formula simplification that was a NOOP. DAG size: 16 [2018-10-27 04:50:03,071 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:50:03,071 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,084 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,084 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:27, output treesize:26 [2018-10-27 04:50:03,145 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:50:03,148 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:50:03,149 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,152 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,175 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-10-27 04:50:03,178 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-10-27 04:50:03,178 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,181 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,199 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,199 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:46, output treesize:38 [2018-10-27 04:50:03,281 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 21 treesize of output 33 [2018-10-27 04:50:03,347 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 19 treesize of output 26 [2018-10-27 04:50:03,348 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:03,425 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 17 [2018-10-27 04:50:03,426 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,466 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:03,552 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 21 treesize of output 33 [2018-10-27 04:50:03,557 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-10-27 04:50:03,557 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,665 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 19 treesize of output 26 [2018-10-27 04:50:03,665 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:03,699 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:03,769 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: and 4 xjuncts. [2018-10-27 04:50:03,769 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 5 variables, input treesize:59, output treesize:122 [2018-10-27 04:50:03,870 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 36 [2018-10-27 04:50:03,892 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:50:03,893 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:03,905 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:04,162 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 92 treesize of output 110 [2018-10-27 04:50:04,166 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 92 [2018-10-27 04:50:04,167 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:04,330 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 90 treesize of output 103 [2018-10-27 04:50:04,331 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:04,418 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:04,610 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 32 [2018-10-27 04:50:04,613 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:50:04,613 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:04,625 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:04,776 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 62 [2018-10-27 04:50:04,782 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 38 [2018-10-27 04:50:04,782 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:04,800 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:04,846 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 82 treesize of output 83 [2018-10-27 04:50:04,851 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 82 [2018-10-27 04:50:04,851 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,056 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 66 treesize of output 57 [2018-10-27 04:50:05,057 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:05,154 INFO L267 ElimStorePlain]: Start of recursive call 11: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:05,274 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 4 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:50:05,274 INFO L202 ElimStorePlain]: Needed 13 recursive calls to eliminate 10 variables, input treesize:132, output treesize:83 [2018-10-27 04:50:05,350 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-10-27 04:50:05,350 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,374 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,375 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,376 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,377 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 54 [2018-10-27 04:50:05,377 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,397 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:50:05,397 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:102, output treesize:73 [2018-10-27 04:50:05,524 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,527 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-10-27 04:50:05,527 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,566 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,567 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,569 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,570 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:05,571 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 37 [2018-10-27 04:50:05,571 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,599 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,600 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:74, output treesize:40 [2018-10-27 04:50:05,785 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 26 [2018-10-27 04:50:05,789 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-10-27 04:50:05,789 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,798 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,834 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 40 [2018-10-27 04:50:05,838 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:50:05,838 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,850 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:05,873 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-10-27 04:50:05,873 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:70, output treesize:55 [2018-10-27 04:50:05,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 29 [2018-10-27 04:50:05,983 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 18 treesize of output 23 [2018-10-27 04:50:05,983 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:06,014 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:06,085 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 40 [2018-10-27 04:50:06,090 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-10-27 04:50:06,090 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,109 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,165 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-10-27 04:50:06,165 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 7 variables, input treesize:77, output treesize:88 [2018-10-27 04:50:06,259 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-10-27 04:50:06,262 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 5 [2018-10-27 04:50:06,262 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,266 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,279 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 19 [2018-10-27 04:50:06,282 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 10 [2018-10-27 04:50:06,282 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,288 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,297 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:06,297 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:44, output treesize:14 [2018-10-27 04:50:06,363 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:50:06,363 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-10-27 04:50:07,339 WARN L179 SmtUtils]: Spent 153.00 ms on a formula simplification that was a NOOP. DAG size: 48 [2018-10-27 04:50:16,830 WARN L179 SmtUtils]: Spent 901.00 ms on a formula simplification that was a NOOP. DAG size: 66 [2018-10-27 04:50:18,095 WARN L179 SmtUtils]: Spent 510.00 ms on a formula simplification that was a NOOP. DAG size: 60 [2018-10-27 04:50:23,233 WARN L179 SmtUtils]: Spent 220.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-10-27 04:50:27,538 WARN L179 SmtUtils]: Spent 665.00 ms on a formula simplification that was a NOOP. DAG size: 78 [2018-10-27 04:50:30,720 WARN L179 SmtUtils]: Spent 369.00 ms on a formula simplification that was a NOOP. DAG size: 78 [2018-10-27 04:50:32,433 WARN L179 SmtUtils]: Spent 1.71 s on a formula simplification that was a NOOP. DAG size: 104 [2018-10-27 04:50:33,551 WARN L179 SmtUtils]: Spent 1.12 s on a formula simplification that was a NOOP. DAG size: 78 [2018-10-27 04:50:35,181 WARN L179 SmtUtils]: Spent 1.63 s on a formula simplification that was a NOOP. DAG size: 86 [2018-10-27 04:50:36,945 WARN L179 SmtUtils]: Spent 1.76 s on a formula simplification that was a NOOP. DAG size: 84 [2018-10-27 04:50:36,972 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 224 treesize of output 227 [2018-10-27 04:50:37,197 WARN L179 SmtUtils]: Spent 224.00 ms on a formula simplification that was a NOOP. DAG size: 73 [2018-10-27 04:50:37,323 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 209 treesize of output 209 [2018-10-27 04:50:37,324 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-10-27 04:50:37,340 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 83 [2018-10-27 04:50:37,340 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:37,573 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 5 xjuncts. [2018-10-27 04:50:40,093 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 219 treesize of output 170 [2018-10-27 04:50:40,638 WARN L179 SmtUtils]: Spent 543.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 64 [2018-10-27 04:50:40,656 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 10 [2018-10-27 04:50:40,657 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:40,841 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:50:40,901 INFO L303 Elim1Store]: Index analysis took 114 ms [2018-10-27 04:50:40,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 4 case distinctions, treesize of input 50 treesize of output 69 [2018-10-27 04:50:41,331 WARN L179 SmtUtils]: Spent 364.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 71 [2018-10-27 04:50:41,337 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 56 [2018-10-27 04:50:41,358 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 16 treesize of output 22 [2018-10-27 04:50:41,358 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:41,455 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:41,802 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 46 [2018-10-27 04:50:41,875 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 37 treesize of output 47 [2018-10-27 04:50:41,875 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:42,128 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:42,144 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:50:42,230 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 60 [2018-10-27 04:50:42,231 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 3 xjuncts. [2018-10-27 04:50:42,537 INFO L267 ElimStorePlain]: Start of recursive call 10: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:50:43,073 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 34 [2018-10-27 04:50:43,109 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 24 treesize of output 16 [2018-10-27 04:50:43,109 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:43,188 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:43,208 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 34 [2018-10-27 04:50:43,252 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 24 treesize of output 16 [2018-10-27 04:50:43,252 INFO L267 ElimStorePlain]: Start of recursive call 16: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:43,316 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:43,334 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 32 [2018-10-27 04:50:43,355 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 12 [2018-10-27 04:50:43,355 INFO L267 ElimStorePlain]: Start of recursive call 18: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:43,397 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:43,781 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:50:43,789 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 47 [2018-10-27 04:50:43,804 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 8 [2018-10-27 04:50:43,804 INFO L267 ElimStorePlain]: Start of recursive call 20: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:43,859 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2018-10-27 04:50:43,913 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2018-10-27 04:50:43,913 INFO L267 ElimStorePlain]: Start of recursive call 22: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:43,938 INFO L267 ElimStorePlain]: Start of recursive call 21: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:43,978 INFO L267 ElimStorePlain]: Start of recursive call 19: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:43,983 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:50:43,991 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 45 [2018-10-27 04:50:44,001 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2018-10-27 04:50:44,050 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2018-10-27 04:50:44,050 INFO L267 ElimStorePlain]: Start of recursive call 25: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:44,073 INFO L267 ElimStorePlain]: Start of recursive call 24: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:44,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 1 [2018-10-27 04:50:44,115 INFO L267 ElimStorePlain]: Start of recursive call 26: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:44,153 INFO L267 ElimStorePlain]: Start of recursive call 23: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:44,489 INFO L267 ElimStorePlain]: Start of recursive call 7: 2 dim-1 vars, 3 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:50:44,683 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:50:44,717 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 301 treesize of output 252 [2018-10-27 04:50:45,175 WARN L179 SmtUtils]: Spent 456.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 66 [2018-10-27 04:50:45,193 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 10 [2018-10-27 04:50:45,193 INFO L267 ElimStorePlain]: Start of recursive call 28: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:45,358 INFO L682 Elim1Store]: detected equality via solver [2018-10-27 04:50:45,420 INFO L303 Elim1Store]: Index analysis took 117 ms [2018-10-27 04:50:45,477 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 4 case distinctions, treesize of input 50 treesize of output 69 [2018-10-27 04:50:45,986 WARN L179 SmtUtils]: Spent 506.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 80 [2018-10-27 04:50:45,991 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-10-27 04:50:45,991 INFO L267 ElimStorePlain]: Start of recursive call 30: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:45,998 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 59 [2018-10-27 04:50:46,029 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 16 treesize of output 22 [2018-10-27 04:50:46,029 INFO L267 ElimStorePlain]: Start of recursive call 32: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:46,123 INFO L267 ElimStorePlain]: Start of recursive call 31: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:46,141 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 66 [2018-10-27 04:50:46,195 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 16 treesize of output 22 [2018-10-27 04:50:46,195 INFO L267 ElimStorePlain]: Start of recursive call 34: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:46,302 INFO L267 ElimStorePlain]: Start of recursive call 33: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-10-27 04:50:46,949 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 36 treesize of output 46 [2018-10-27 04:50:47,048 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 37 treesize of output 47 [2018-10-27 04:50:47,049 INFO L267 ElimStorePlain]: Start of recursive call 36: End of recursive call: and 2 xjuncts. [2018-10-27 04:50:47,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 5 case distinctions, treesize of input 39 treesize of output 64 [2018-10-27 04:50:47,443 INFO L267 ElimStorePlain]: Start of recursive call 37: End of recursive call: and 8 xjuncts. [2018-10-27 04:50:47,710 INFO L267 ElimStorePlain]: Start of recursive call 35: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-10-27 04:50:48,243 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:50:48,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 35 [2018-10-27 04:50:48,534 WARN L522 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-10-27 04:50:48,534 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.AssertionError: var is still there: v_arrayElimCell_99 term size 26 at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.Elim1Store.elim1(Elim1Store.java:452) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:221) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:225) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:225) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimOneRec(ElimStorePlain.java:225) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.doElimAllRec(ElimStorePlain.java:247) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.ElimStorePlain.elimAllRec(ElimStorePlain.java:199) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.PartialQuantifierElimination.elim(PartialQuantifierElimination.java:293) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.PartialQuantifierElimination.tryToEliminate(PartialQuantifierElimination.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer$QuantifierEliminationPostprocessor.postprocess(IterativePredicateTransformer.java:245) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeBackwardSequence(IterativePredicateTransformer.java:383) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeWeakestPreconditionSequence(IterativePredicateTransformer.java:290) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:330) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackRefinementStrategy.getTraceCheck(MultiTrackRefinementStrategy.java:234) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:429) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:435) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:312) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:154) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:123) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-10-27 04:50:48,537 INFO L168 Benchmark]: Toolchain (without parser) took 207865.13 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 271.6 MB). Free memory was 949.2 MB in the beginning and 1.1 GB in the end (delta: -118.5 MB). Peak memory consumption was 400.4 MB. Max. memory is 11.5 GB. [2018-10-27 04:50:48,538 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-27 04:50:48,538 INFO L168 Benchmark]: CACSL2BoogieTranslator took 459.82 ms. Allocated memory is still 1.0 GB. Free memory was 949.2 MB in the beginning and 927.7 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-10-27 04:50:48,538 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.65 ms. Allocated memory is still 1.0 GB. Free memory was 927.7 MB in the beginning and 922.4 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-10-27 04:50:48,538 INFO L168 Benchmark]: Boogie Preprocessor took 125.94 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 168.3 MB). Free memory was 922.4 MB in the beginning and 1.1 GB in the end (delta: -225.9 MB). Peak memory consumption was 18.0 MB. Max. memory is 11.5 GB. [2018-10-27 04:50:48,539 INFO L168 Benchmark]: RCFGBuilder took 1298.42 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 52.0 MB). Peak memory consumption was 52.0 MB. Max. memory is 11.5 GB. [2018-10-27 04:50:48,539 INFO L168 Benchmark]: TraceAbstraction took 205907.36 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 103.3 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 28.7 MB). Peak memory consumption was 379.2 MB. Max. memory is 11.5 GB. [2018-10-27 04:50:48,540 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 459.82 ms. Allocated memory is still 1.0 GB. Free memory was 949.2 MB in the beginning and 927.7 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.65 ms. Allocated memory is still 1.0 GB. Free memory was 927.7 MB in the beginning and 922.4 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 125.94 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 168.3 MB). Free memory was 922.4 MB in the beginning and 1.1 GB in the end (delta: -225.9 MB). Peak memory consumption was 18.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1298.42 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 52.0 MB). Peak memory consumption was 52.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 205907.36 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 103.3 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 28.7 MB). Peak memory consumption was 379.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: AssertionError: var is still there: v_arrayElimCell_99 term size 26 de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: AssertionError: var is still there: v_arrayElimCell_99 term size 26: de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.Elim1Store.elim1(Elim1Store.java:452) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...