./Ultimate.py --spec ../../sv-benchmarks/c/Systems_DeviceDriversLinux64_ReachSafety.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default-EXP.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 11:27:43,115 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 11:27:43,117 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 11:27:43,125 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 11:27:43,125 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 11:27:43,126 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 11:27:43,127 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 11:27:43,128 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 11:27:43,130 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 11:27:43,130 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 11:27:43,131 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 11:27:43,131 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 11:27:43,132 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 11:27:43,133 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 11:27:43,133 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 11:27:43,134 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 11:27:43,134 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 11:27:43,136 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 11:27:43,138 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 11:27:43,139 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 11:27:43,140 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 11:27:43,141 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 11:27:43,143 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 11:27:43,143 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 11:27:43,143 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 11:27:43,144 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 11:27:43,145 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 11:27:43,146 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 11:27:43,146 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 11:27:43,147 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 11:27:43,148 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 11:27:43,148 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 11:27:43,148 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 11:27:43,149 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 11:27:43,149 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 11:27:43,150 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 11:27:43,150 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default-EXP.epf [2018-11-10 11:27:43,159 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 11:27:43,159 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 11:27:43,160 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-10 11:27:43,160 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-10 11:27:43,160 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-10 11:27:43,160 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-10 11:27:43,160 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Log string format=TERM [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-10 11:27:43,161 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-10 11:27:43,162 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 11:27:43,162 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 11:27:43,162 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 11:27:43,163 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-10 11:27:43,163 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 11:27:43,163 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-10 11:27:43,163 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 11:27:43,163 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-10 11:27:43,163 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 11:27:43,164 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 11:27:43,164 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 11:27:43,164 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-10 11:27:43,164 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 11:27:43,164 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 11:27:43,164 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 11:27:43,164 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-10 11:27:43,165 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-10 11:27:43,165 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 11:27:43,165 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-10 11:27:43,165 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-10 11:27:43,165 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-11-10 11:27:43,165 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-11-10 11:27:43,192 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 11:27:43,202 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 11:27:43,205 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 11:27:43,206 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 11:27:43,206 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 11:27:43,207 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-10 11:27:43,253 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/7c82b2e3a/fa08e1162c82462f90ae72a8b59f7764/FLAG08cd031ec [2018-11-10 11:27:43,733 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 11:27:43,733 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-10 11:27:43,749 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/7c82b2e3a/fa08e1162c82462f90ae72a8b59f7764/FLAG08cd031ec [2018-11-10 11:27:43,762 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/7c82b2e3a/fa08e1162c82462f90ae72a8b59f7764 [2018-11-10 11:27:43,765 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 11:27:43,767 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 11:27:43,767 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 11:27:43,768 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 11:27:43,771 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 11:27:43,772 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 11:27:43" (1/1) ... [2018-11-10 11:27:43,775 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e8b0b89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:43, skipping insertion in model container [2018-11-10 11:27:43,775 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 11:27:43" (1/1) ... [2018-11-10 11:27:43,784 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 11:27:43,841 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 11:27:44,559 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 11:27:44,590 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 11:27:44,761 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 11:27:44,816 INFO L193 MainTranslator]: Completed translation [2018-11-10 11:27:44,817 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44 WrapperNode [2018-11-10 11:27:44,817 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 11:27:44,817 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 11:27:44,818 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 11:27:44,818 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 11:27:44,826 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,853 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,904 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 11:27:44,904 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 11:27:44,905 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 11:27:44,905 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 11:27:44,914 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,914 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,925 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,926 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,958 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,967 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,975 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... [2018-11-10 11:27:44,985 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 11:27:44,986 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 11:27:44,986 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 11:27:44,986 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 11:27:44,987 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 11:27:45,040 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-11-10 11:27:45,041 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-11-10 11:27:45,041 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-11-10 11:27:45,041 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-11-10 11:27:45,041 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-11-10 11:27:45,041 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-11-10 11:27:45,041 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-10 11:27:45,041 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-10 11:27:45,042 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-11-10 11:27:45,042 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-11-10 11:27:45,042 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-11-10 11:27:45,042 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-11-10 11:27:45,042 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-11-10 11:27:45,042 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-11-10 11:27:45,042 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-11-10 11:27:45,042 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-11-10 11:27:45,043 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-11-10 11:27:45,043 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-11-10 11:27:45,043 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-11-10 11:27:45,043 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-11-10 11:27:45,043 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-11-10 11:27:45,043 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-11-10 11:27:45,043 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-11-10 11:27:45,043 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-11-10 11:27:45,043 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-11-10 11:27:45,044 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-11-10 11:27:45,044 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-11-10 11:27:45,044 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-11-10 11:27:45,044 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-11-10 11:27:45,044 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-11-10 11:27:45,044 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-10 11:27:45,044 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-10 11:27:45,044 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-11-10 11:27:45,045 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-11-10 11:27:45,045 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-10 11:27:45,045 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-10 11:27:45,045 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-11-10 11:27:45,045 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-11-10 11:27:45,045 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-11-10 11:27:45,045 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-11-10 11:27:45,045 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-11-10 11:27:45,046 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-11-10 11:27:45,046 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-10 11:27:45,046 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-10 11:27:45,046 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-11-10 11:27:45,046 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-11-10 11:27:45,046 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-11-10 11:27:45,046 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-11-10 11:27:45,046 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-11-10 11:27:45,047 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-11-10 11:27:45,047 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-11-10 11:27:45,047 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-11-10 11:27:45,047 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-11-10 11:27:45,047 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-11-10 11:27:45,047 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-11-10 11:27:45,047 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-11-10 11:27:45,047 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-11-10 11:27:45,048 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-11-10 11:27:45,048 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-11-10 11:27:45,048 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-11-10 11:27:45,048 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-11-10 11:27:45,048 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-11-10 11:27:45,048 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-11-10 11:27:45,048 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-11-10 11:27:45,049 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-11-10 11:27:45,049 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-11-10 11:27:45,049 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-11-10 11:27:45,049 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-11-10 11:27:45,049 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-11-10 11:27:45,049 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-11-10 11:27:45,049 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-11-10 11:27:45,049 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-11-10 11:27:45,050 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-11-10 11:27:45,050 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-11-10 11:27:45,050 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-11-10 11:27:45,050 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-11-10 11:27:45,050 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-11-10 11:27:45,050 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-11-10 11:27:45,050 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-10 11:27:45,050 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-10 11:27:45,051 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-11-10 11:27:45,051 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-11-10 11:27:45,051 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 11:27:45,051 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 11:27:46,691 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 11:27:46,691 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 11:27:46 BoogieIcfgContainer [2018-11-10 11:27:46,692 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 11:27:46,692 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-10 11:27:46,692 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-10 11:27:46,695 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-10 11:27:46,695 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.11 11:27:43" (1/3) ... [2018-11-10 11:27:46,696 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@48518642 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 11:27:46, skipping insertion in model container [2018-11-10 11:27:46,696 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:27:44" (2/3) ... [2018-11-10 11:27:46,696 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@48518642 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 11:27:46, skipping insertion in model container [2018-11-10 11:27:46,697 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 11:27:46" (3/3) ... [2018-11-10 11:27:46,698 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-10 11:27:46,707 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-10 11:27:46,714 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-10 11:27:46,725 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-10 11:27:46,748 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-10 11:27:46,748 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-10 11:27:46,748 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-10 11:27:46,748 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 11:27:46,748 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 11:27:46,748 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-10 11:27:46,749 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 11:27:46,749 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-10 11:27:46,770 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states. [2018-11-10 11:27:46,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-10 11:27:46,778 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:46,778 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:46,780 INFO L424 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:46,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:46,786 INFO L82 PathProgramCache]: Analyzing trace with hash 273110255, now seen corresponding path program 1 times [2018-11-10 11:27:46,788 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:46,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:46,839 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:46,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:46,840 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:46,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:47,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:27:47,046 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:27:47,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:27:47,046 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:47,050 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:27:47,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:27:47,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:27:47,061 INFO L87 Difference]: Start difference. First operand 362 states. Second operand 3 states. [2018-11-10 11:27:47,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:47,122 INFO L93 Difference]: Finished difference Result 612 states and 814 transitions. [2018-11-10 11:27:47,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:27:47,123 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-10 11:27:47,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:47,132 INFO L225 Difference]: With dead ends: 612 [2018-11-10 11:27:47,132 INFO L226 Difference]: Without dead ends: 248 [2018-11-10 11:27:47,136 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:27:47,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-11-10 11:27:47,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 248. [2018-11-10 11:27:47,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-11-10 11:27:47,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 314 transitions. [2018-11-10 11:27:47,179 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 314 transitions. Word has length 34 [2018-11-10 11:27:47,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:47,180 INFO L481 AbstractCegarLoop]: Abstraction has 248 states and 314 transitions. [2018-11-10 11:27:47,180 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:27:47,180 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 314 transitions. [2018-11-10 11:27:47,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-10 11:27:47,182 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:47,183 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:47,183 INFO L424 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:47,183 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:47,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1454992326, now seen corresponding path program 1 times [2018-11-10 11:27:47,183 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:47,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:47,186 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:47,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:47,187 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:47,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:47,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:27:47,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:27:47,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:27:47,301 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:47,302 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:27:47,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:27:47,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:27:47,303 INFO L87 Difference]: Start difference. First operand 248 states and 314 transitions. Second operand 5 states. [2018-11-10 11:27:47,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:47,554 INFO L93 Difference]: Finished difference Result 727 states and 939 transitions. [2018-11-10 11:27:47,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 11:27:47,555 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-11-10 11:27:47,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:47,559 INFO L225 Difference]: With dead ends: 727 [2018-11-10 11:27:47,560 INFO L226 Difference]: Without dead ends: 493 [2018-11-10 11:27:47,561 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:27:47,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493 states. [2018-11-10 11:27:47,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493 to 480. [2018-11-10 11:27:47,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2018-11-10 11:27:47,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 615 transitions. [2018-11-10 11:27:47,601 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 615 transitions. Word has length 47 [2018-11-10 11:27:47,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:47,602 INFO L481 AbstractCegarLoop]: Abstraction has 480 states and 615 transitions. [2018-11-10 11:27:47,602 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:27:47,602 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 615 transitions. [2018-11-10 11:27:47,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 11:27:47,604 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:47,604 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:47,604 INFO L424 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:47,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:47,604 INFO L82 PathProgramCache]: Analyzing trace with hash -1690200814, now seen corresponding path program 1 times [2018-11-10 11:27:47,604 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:47,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:47,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:47,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:47,607 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:47,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:47,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:27:47,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:27:47,703 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:27:47,703 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:47,703 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:27:47,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:27:47,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:27:47,704 INFO L87 Difference]: Start difference. First operand 480 states and 615 transitions. Second operand 5 states. [2018-11-10 11:27:47,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:47,793 INFO L93 Difference]: Finished difference Result 962 states and 1247 transitions. [2018-11-10 11:27:47,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:27:47,794 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-11-10 11:27:47,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:47,798 INFO L225 Difference]: With dead ends: 962 [2018-11-10 11:27:47,798 INFO L226 Difference]: Without dead ends: 496 [2018-11-10 11:27:47,800 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:27:47,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-11-10 11:27:47,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 484. [2018-11-10 11:27:47,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-11-10 11:27:47,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 615 transitions. [2018-11-10 11:27:47,831 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 615 transitions. Word has length 48 [2018-11-10 11:27:47,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:47,831 INFO L481 AbstractCegarLoop]: Abstraction has 484 states and 615 transitions. [2018-11-10 11:27:47,831 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:27:47,831 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 615 transitions. [2018-11-10 11:27:47,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-10 11:27:47,833 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:47,833 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:47,833 INFO L424 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:47,833 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:47,833 INFO L82 PathProgramCache]: Analyzing trace with hash 284618944, now seen corresponding path program 1 times [2018-11-10 11:27:47,833 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:47,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:47,836 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:47,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:47,836 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:47,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:47,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:27:47,894 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:27:47,894 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:27:47,894 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:47,894 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:27:47,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:27:47,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:27:47,895 INFO L87 Difference]: Start difference. First operand 484 states and 615 transitions. Second operand 3 states. [2018-11-10 11:27:47,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:47,965 INFO L93 Difference]: Finished difference Result 1146 states and 1460 transitions. [2018-11-10 11:27:47,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:27:47,965 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-10 11:27:47,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:47,969 INFO L225 Difference]: With dead ends: 1146 [2018-11-10 11:27:47,969 INFO L226 Difference]: Without dead ends: 676 [2018-11-10 11:27:47,970 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:27:47,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states. [2018-11-10 11:27:48,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 673. [2018-11-10 11:27:48,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2018-11-10 11:27:48,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 857 transitions. [2018-11-10 11:27:48,032 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 857 transitions. Word has length 45 [2018-11-10 11:27:48,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:48,033 INFO L481 AbstractCegarLoop]: Abstraction has 673 states and 857 transitions. [2018-11-10 11:27:48,033 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:27:48,033 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 857 transitions. [2018-11-10 11:27:48,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-10 11:27:48,034 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:48,034 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:48,034 INFO L424 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:48,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:48,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1747554851, now seen corresponding path program 1 times [2018-11-10 11:27:48,035 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:48,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:48,037 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:48,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:48,037 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:48,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:48,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:27:48,151 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:27:48,151 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:27:48,151 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:48,151 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:27:48,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:27:48,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:27:48,152 INFO L87 Difference]: Start difference. First operand 673 states and 857 transitions. Second operand 5 states. [2018-11-10 11:27:48,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:48,259 INFO L93 Difference]: Finished difference Result 1354 states and 1739 transitions. [2018-11-10 11:27:48,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:27:48,261 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-11-10 11:27:48,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:48,264 INFO L225 Difference]: With dead ends: 1354 [2018-11-10 11:27:48,265 INFO L226 Difference]: Without dead ends: 705 [2018-11-10 11:27:48,267 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:27:48,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states. [2018-11-10 11:27:48,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 681. [2018-11-10 11:27:48,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2018-11-10 11:27:48,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 859 transitions. [2018-11-10 11:27:48,306 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 859 transitions. Word has length 49 [2018-11-10 11:27:48,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:48,307 INFO L481 AbstractCegarLoop]: Abstraction has 681 states and 859 transitions. [2018-11-10 11:27:48,307 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:27:48,307 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 859 transitions. [2018-11-10 11:27:48,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-10 11:27:48,308 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:48,309 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:48,309 INFO L424 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:48,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:48,309 INFO L82 PathProgramCache]: Analyzing trace with hash -1196674033, now seen corresponding path program 1 times [2018-11-10 11:27:48,309 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:48,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:48,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:48,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:48,311 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:48,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:48,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:27:48,397 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:27:48,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:27:48,397 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:48,397 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:27:48,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:27:48,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:27:48,398 INFO L87 Difference]: Start difference. First operand 681 states and 859 transitions. Second operand 5 states. [2018-11-10 11:27:48,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:48,496 INFO L93 Difference]: Finished difference Result 1297 states and 1651 transitions. [2018-11-10 11:27:48,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:27:48,496 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-10 11:27:48,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:48,500 INFO L225 Difference]: With dead ends: 1297 [2018-11-10 11:27:48,500 INFO L226 Difference]: Without dead ends: 640 [2018-11-10 11:27:48,502 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:27:48,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-11-10 11:27:48,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 622. [2018-11-10 11:27:48,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-11-10 11:27:48,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 777 transitions. [2018-11-10 11:27:48,535 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 777 transitions. Word has length 50 [2018-11-10 11:27:48,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:48,536 INFO L481 AbstractCegarLoop]: Abstraction has 622 states and 777 transitions. [2018-11-10 11:27:48,536 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:27:48,536 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 777 transitions. [2018-11-10 11:27:48,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-10 11:27:48,537 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:48,537 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:48,538 INFO L424 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:48,538 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:48,538 INFO L82 PathProgramCache]: Analyzing trace with hash -922844006, now seen corresponding path program 1 times [2018-11-10 11:27:48,538 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:48,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:48,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:48,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:48,540 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:48,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:48,662 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-10 11:27:48,663 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:27:48,663 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:27:48,664 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 63 with the following transitions: [2018-11-10 11:27:48,666 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [540], [555], [573], [583], [588], [590], [617], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [830], [834], [835], [878], [879], [880] [2018-11-10 11:27:48,702 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:27:48,703 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:27:49,018 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:27:49,019 INFO L272 AbstractInterpreter]: Visited 15 different actions 15 times. Never merged. Never widened. Never found a fixpoint. Largest state had 182 variables. [2018-11-10 11:27:49,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:49,036 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:27:49,169 INFO L227 lantSequenceWeakener]: Weakened 13 states. On average, predicates are now at 94.58% of their original sizes. [2018-11-10 11:27:49,169 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:27:49,220 INFO L415 sIntCurrentIteration]: We unified 61 AI predicates to 61 [2018-11-10 11:27:49,220 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:27:49,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:27:49,221 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [9] total 15 [2018-11-10 11:27:49,221 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:49,221 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-10 11:27:49,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-10 11:27:49,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:27:49,222 INFO L87 Difference]: Start difference. First operand 622 states and 777 transitions. Second operand 8 states. [2018-11-10 11:27:52,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:27:52,852 INFO L93 Difference]: Finished difference Result 1492 states and 1864 transitions. [2018-11-10 11:27:52,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-10 11:27:52,852 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 62 [2018-11-10 11:27:52,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:27:52,855 INFO L225 Difference]: With dead ends: 1492 [2018-11-10 11:27:52,855 INFO L226 Difference]: Without dead ends: 891 [2018-11-10 11:27:52,856 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 62 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-11-10 11:27:52,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 891 states. [2018-11-10 11:27:52,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 891 to 827. [2018-11-10 11:27:52,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 827 states. [2018-11-10 11:27:52,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1042 transitions. [2018-11-10 11:27:52,881 INFO L78 Accepts]: Start accepts. Automaton has 827 states and 1042 transitions. Word has length 62 [2018-11-10 11:27:52,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:27:52,881 INFO L481 AbstractCegarLoop]: Abstraction has 827 states and 1042 transitions. [2018-11-10 11:27:52,881 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-10 11:27:52,881 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1042 transitions. [2018-11-10 11:27:52,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-10 11:27:52,882 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:27:52,883 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:27:52,883 INFO L424 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:27:52,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:52,883 INFO L82 PathProgramCache]: Analyzing trace with hash -1234114431, now seen corresponding path program 1 times [2018-11-10 11:27:52,883 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:27:52,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:52,885 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:27:52,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:27:52,886 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:27:52,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:27:52,995 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-10 11:27:52,995 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:27:52,995 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:27:52,995 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 64 with the following transitions: [2018-11-10 11:27:52,995 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [830], [834], [835], [878], [879], [880] [2018-11-10 11:27:52,999 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:27:52,999 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:27:53,121 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:27:53,121 INFO L272 AbstractInterpreter]: Visited 35 different actions 39 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:27:53,129 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:27:53,129 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:27:53,299 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:27:53,299 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:27:54,335 INFO L415 sIntCurrentIteration]: We unified 62 AI predicates to 62 [2018-11-10 11:27:54,336 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:27:54,336 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:27:54,336 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [25] imperfect sequences [9] total 32 [2018-11-10 11:27:54,336 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:27:54,337 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-10 11:27:54,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-10 11:27:54,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=492, Unknown=0, NotChecked=0, Total=600 [2018-11-10 11:27:54,337 INFO L87 Difference]: Start difference. First operand 827 states and 1042 transitions. Second operand 25 states. [2018-11-10 11:28:06,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:28:06,720 INFO L93 Difference]: Finished difference Result 2011 states and 2547 transitions. [2018-11-10 11:28:06,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-10 11:28:06,720 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 63 [2018-11-10 11:28:06,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:28:06,725 INFO L225 Difference]: With dead ends: 2011 [2018-11-10 11:28:06,726 INFO L226 Difference]: Without dead ends: 1209 [2018-11-10 11:28:06,728 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 64 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 264 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=123, Invalid=579, Unknown=0, NotChecked=0, Total=702 [2018-11-10 11:28:06,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states. [2018-11-10 11:28:06,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 866. [2018-11-10 11:28:06,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 866 states. [2018-11-10 11:28:06,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 866 states to 866 states and 1093 transitions. [2018-11-10 11:28:06,803 INFO L78 Accepts]: Start accepts. Automaton has 866 states and 1093 transitions. Word has length 63 [2018-11-10 11:28:06,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:28:06,803 INFO L481 AbstractCegarLoop]: Abstraction has 866 states and 1093 transitions. [2018-11-10 11:28:06,804 INFO L482 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-10 11:28:06,804 INFO L276 IsEmpty]: Start isEmpty. Operand 866 states and 1093 transitions. [2018-11-10 11:28:06,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-10 11:28:06,805 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:28:06,805 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:28:06,806 INFO L424 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:28:06,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:28:06,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1389860382, now seen corresponding path program 1 times [2018-11-10 11:28:06,806 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:28:06,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:28:06,808 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:28:06,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:28:06,808 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:28:06,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:28:06,983 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 11:28:06,983 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:28:06,983 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:28:06,984 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 65 with the following transitions: [2018-11-10 11:28:06,984 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [830], [834], [835], [878], [879], [880] [2018-11-10 11:28:06,986 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:28:06,987 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:28:07,233 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:28:07,233 INFO L272 AbstractInterpreter]: Visited 38 different actions 47 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:28:07,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:28:07,241 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:28:07,432 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:28:07,432 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:28:08,459 INFO L415 sIntCurrentIteration]: We unified 63 AI predicates to 63 [2018-11-10 11:28:08,459 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:28:08,460 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:28:08,460 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [10] total 34 [2018-11-10 11:28:08,460 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:28:08,460 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-10 11:28:08,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-10 11:28:08,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=538, Unknown=0, NotChecked=0, Total=650 [2018-11-10 11:28:08,461 INFO L87 Difference]: Start difference. First operand 866 states and 1093 transitions. Second operand 26 states. [2018-11-10 11:28:34,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:28:34,446 INFO L93 Difference]: Finished difference Result 2046 states and 2591 transitions. [2018-11-10 11:28:34,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-10 11:28:34,446 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 64 [2018-11-10 11:28:34,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:28:34,452 INFO L225 Difference]: With dead ends: 2046 [2018-11-10 11:28:34,452 INFO L226 Difference]: Without dead ends: 1448 [2018-11-10 11:28:34,454 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 65 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 283 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-11-10 11:28:34,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states. [2018-11-10 11:28:34,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 927. [2018-11-10 11:28:34,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 927 states. [2018-11-10 11:28:34,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 927 states to 927 states and 1178 transitions. [2018-11-10 11:28:34,539 INFO L78 Accepts]: Start accepts. Automaton has 927 states and 1178 transitions. Word has length 64 [2018-11-10 11:28:34,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:28:34,540 INFO L481 AbstractCegarLoop]: Abstraction has 927 states and 1178 transitions. [2018-11-10 11:28:34,540 INFO L482 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-10 11:28:34,540 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 1178 transitions. [2018-11-10 11:28:34,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-10 11:28:34,541 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:28:34,541 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:28:34,542 INFO L424 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:28:34,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:28:34,542 INFO L82 PathProgramCache]: Analyzing trace with hash 115780858, now seen corresponding path program 1 times [2018-11-10 11:28:34,542 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:28:34,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:28:34,544 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:28:34,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:28:34,544 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:28:34,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:28:34,686 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 11:28:34,686 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:28:34,686 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:28:34,686 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 66 with the following transitions: [2018-11-10 11:28:34,687 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [519], [521], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [824], [825], [830], [834], [835], [878], [879], [880] [2018-11-10 11:28:34,689 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:28:34,689 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:28:34,858 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:28:34,858 INFO L272 AbstractInterpreter]: Visited 39 different actions 48 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:28:34,860 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:28:34,860 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:28:35,091 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:28:35,092 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:28:36,323 INFO L415 sIntCurrentIteration]: We unified 64 AI predicates to 64 [2018-11-10 11:28:36,324 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:28:36,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:28:36,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-11-10 11:28:36,324 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:28:36,324 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-10 11:28:36,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-10 11:28:36,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-11-10 11:28:36,325 INFO L87 Difference]: Start difference. First operand 927 states and 1178 transitions. Second operand 27 states. [2018-11-10 11:28:58,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:28:58,162 INFO L93 Difference]: Finished difference Result 2088 states and 2645 transitions. [2018-11-10 11:28:58,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-10 11:28:58,162 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 65 [2018-11-10 11:28:58,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:28:58,167 INFO L225 Difference]: With dead ends: 2088 [2018-11-10 11:28:58,167 INFO L226 Difference]: Without dead ends: 1490 [2018-11-10 11:28:58,169 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 66 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 302 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=131, Invalid=681, Unknown=0, NotChecked=0, Total=812 [2018-11-10 11:28:58,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states. [2018-11-10 11:28:58,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 962. [2018-11-10 11:28:58,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 962 states. [2018-11-10 11:28:58,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 962 states to 962 states and 1225 transitions. [2018-11-10 11:28:58,268 INFO L78 Accepts]: Start accepts. Automaton has 962 states and 1225 transitions. Word has length 65 [2018-11-10 11:28:58,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:28:58,269 INFO L481 AbstractCegarLoop]: Abstraction has 962 states and 1225 transitions. [2018-11-10 11:28:58,269 INFO L482 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-10 11:28:58,269 INFO L276 IsEmpty]: Start isEmpty. Operand 962 states and 1225 transitions. [2018-11-10 11:28:58,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-10 11:28:58,270 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:28:58,271 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:28:58,271 INFO L424 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:28:58,271 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:28:58,271 INFO L82 PathProgramCache]: Analyzing trace with hash 1584817467, now seen corresponding path program 1 times [2018-11-10 11:28:58,271 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:28:58,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:28:58,273 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:28:58,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:28:58,273 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:28:58,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:28:58,409 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 11:28:58,410 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:28:58,410 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:28:58,410 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 67 with the following transitions: [2018-11-10 11:28:58,410 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [826], [827], [830], [834], [835], [878], [879], [880] [2018-11-10 11:28:58,412 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:28:58,412 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:28:58,622 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:28:58,622 INFO L272 AbstractInterpreter]: Visited 40 different actions 49 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:28:58,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:28:58,632 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:28:58,772 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:28:58,772 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:29:00,067 INFO L415 sIntCurrentIteration]: We unified 65 AI predicates to 65 [2018-11-10 11:29:00,067 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:29:00,067 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:29:00,067 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-11-10 11:29:00,067 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:29:00,068 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-10 11:29:00,068 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-10 11:29:00,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=636, Unknown=0, NotChecked=0, Total=756 [2018-11-10 11:29:00,068 INFO L87 Difference]: Start difference. First operand 962 states and 1225 transitions. Second operand 28 states. [2018-11-10 11:29:21,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:29:21,079 INFO L93 Difference]: Finished difference Result 2130 states and 2698 transitions. [2018-11-10 11:29:21,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-10 11:29:21,080 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 66 [2018-11-10 11:29:21,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:29:21,083 INFO L225 Difference]: With dead ends: 2130 [2018-11-10 11:29:21,083 INFO L226 Difference]: Without dead ends: 1532 [2018-11-10 11:29:21,084 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 67 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-11-10 11:29:21,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1532 states. [2018-11-10 11:29:21,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1532 to 997. [2018-11-10 11:29:21,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 997 states. [2018-11-10 11:29:21,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 997 states to 997 states and 1271 transitions. [2018-11-10 11:29:21,146 INFO L78 Accepts]: Start accepts. Automaton has 997 states and 1271 transitions. Word has length 66 [2018-11-10 11:29:21,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:29:21,146 INFO L481 AbstractCegarLoop]: Abstraction has 997 states and 1271 transitions. [2018-11-10 11:29:21,147 INFO L482 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-10 11:29:21,147 INFO L276 IsEmpty]: Start isEmpty. Operand 997 states and 1271 transitions. [2018-11-10 11:29:21,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 11:29:21,148 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:29:21,148 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:29:21,148 INFO L424 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:29:21,148 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:21,149 INFO L82 PathProgramCache]: Analyzing trace with hash -821331501, now seen corresponding path program 1 times [2018-11-10 11:29:21,149 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:29:21,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:21,150 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:29:21,151 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:21,151 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:29:21,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:29:21,245 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-10 11:29:21,245 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:29:21,245 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:29:21,245 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 70 with the following transitions: [2018-11-10 11:29:21,246 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [830], [834], [835], [872], [873], [878], [879], [880] [2018-11-10 11:29:21,248 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:29:21,248 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:29:21,346 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:29:21,346 INFO L272 AbstractInterpreter]: Visited 41 different actions 45 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:29:21,352 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:21,352 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:29:21,508 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:29:21,508 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:29:22,525 INFO L415 sIntCurrentIteration]: We unified 68 AI predicates to 68 [2018-11-10 11:29:22,525 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:29:22,526 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:29:22,526 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-11-10 11:29:22,526 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:29:22,526 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-10 11:29:22,526 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-10 11:29:22,527 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=535, Unknown=0, NotChecked=0, Total=650 [2018-11-10 11:29:22,527 INFO L87 Difference]: Start difference. First operand 997 states and 1271 transitions. Second operand 26 states. [2018-11-10 11:29:33,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:29:33,139 INFO L93 Difference]: Finished difference Result 2409 states and 3064 transitions. [2018-11-10 11:29:33,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-10 11:29:33,140 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 69 [2018-11-10 11:29:33,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:29:33,143 INFO L225 Difference]: With dead ends: 2409 [2018-11-10 11:29:33,143 INFO L226 Difference]: Without dead ends: 1607 [2018-11-10 11:29:33,144 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 70 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 284 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=130, Invalid=626, Unknown=0, NotChecked=0, Total=756 [2018-11-10 11:29:33,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states. [2018-11-10 11:29:33,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1032. [2018-11-10 11:29:33,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1032 states. [2018-11-10 11:29:33,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1032 states to 1032 states and 1317 transitions. [2018-11-10 11:29:33,259 INFO L78 Accepts]: Start accepts. Automaton has 1032 states and 1317 transitions. Word has length 69 [2018-11-10 11:29:33,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:29:33,259 INFO L481 AbstractCegarLoop]: Abstraction has 1032 states and 1317 transitions. [2018-11-10 11:29:33,259 INFO L482 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-10 11:29:33,259 INFO L276 IsEmpty]: Start isEmpty. Operand 1032 states and 1317 transitions. [2018-11-10 11:29:33,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 11:29:33,261 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:29:33,261 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:29:33,261 INFO L424 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:29:33,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:33,262 INFO L82 PathProgramCache]: Analyzing trace with hash -1478491440, now seen corresponding path program 1 times [2018-11-10 11:29:33,262 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:29:33,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:33,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:29:33,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:33,264 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:29:33,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:29:33,358 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 11:29:33,359 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:29:33,359 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:29:33,359 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 71 with the following transitions: [2018-11-10 11:29:33,359 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [830], [834], [835], [872], [873], [878], [879], [880] [2018-11-10 11:29:33,361 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:29:33,361 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:29:33,468 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:29:33,468 INFO L272 AbstractInterpreter]: Visited 44 different actions 53 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:29:33,470 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:33,470 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:29:33,621 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:29:33,622 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:29:34,771 INFO L415 sIntCurrentIteration]: We unified 69 AI predicates to 69 [2018-11-10 11:29:34,771 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:29:34,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:29:34,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-11-10 11:29:34,772 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:29:34,772 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-10 11:29:34,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-10 11:29:34,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=119, Invalid=583, Unknown=0, NotChecked=0, Total=702 [2018-11-10 11:29:34,773 INFO L87 Difference]: Start difference. First operand 1032 states and 1317 transitions. Second operand 27 states. [2018-11-10 11:29:46,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:29:46,792 INFO L93 Difference]: Finished difference Result 2244 states and 2848 transitions. [2018-11-10 11:29:46,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-10 11:29:46,792 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 70 [2018-11-10 11:29:46,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:29:46,796 INFO L225 Difference]: With dead ends: 2244 [2018-11-10 11:29:46,796 INFO L226 Difference]: Without dead ends: 1646 [2018-11-10 11:29:46,797 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 71 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 304 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=134, Invalid=678, Unknown=0, NotChecked=0, Total=812 [2018-11-10 11:29:46,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1646 states. [2018-11-10 11:29:46,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1646 to 1093. [2018-11-10 11:29:46,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1093 states. [2018-11-10 11:29:46,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1093 states to 1093 states and 1402 transitions. [2018-11-10 11:29:46,882 INFO L78 Accepts]: Start accepts. Automaton has 1093 states and 1402 transitions. Word has length 70 [2018-11-10 11:29:46,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:29:46,882 INFO L481 AbstractCegarLoop]: Abstraction has 1093 states and 1402 transitions. [2018-11-10 11:29:46,882 INFO L482 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-10 11:29:46,882 INFO L276 IsEmpty]: Start isEmpty. Operand 1093 states and 1402 transitions. [2018-11-10 11:29:46,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 11:29:46,884 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:29:46,884 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:29:46,884 INFO L424 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:29:46,884 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:46,884 INFO L82 PathProgramCache]: Analyzing trace with hash 789073739, now seen corresponding path program 1 times [2018-11-10 11:29:46,884 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:29:46,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:46,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:29:46,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:46,886 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:29:46,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:29:46,955 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-10 11:29:46,956 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:29:46,956 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:29:46,956 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:29:46,956 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:29:46,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:29:46,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:29:46,957 INFO L87 Difference]: Start difference. First operand 1093 states and 1402 transitions. Second operand 3 states. [2018-11-10 11:29:47,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:29:47,421 INFO L93 Difference]: Finished difference Result 2119 states and 2735 transitions. [2018-11-10 11:29:47,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:29:47,421 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2018-11-10 11:29:47,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:29:47,424 INFO L225 Difference]: With dead ends: 2119 [2018-11-10 11:29:47,425 INFO L226 Difference]: Without dead ends: 1317 [2018-11-10 11:29:47,426 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:29:47,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1317 states. [2018-11-10 11:29:47,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1317 to 1314. [2018-11-10 11:29:47,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1314 states. [2018-11-10 11:29:47,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1314 states to 1314 states and 1692 transitions. [2018-11-10 11:29:47,515 INFO L78 Accepts]: Start accepts. Automaton has 1314 states and 1692 transitions. Word has length 70 [2018-11-10 11:29:47,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:29:47,516 INFO L481 AbstractCegarLoop]: Abstraction has 1314 states and 1692 transitions. [2018-11-10 11:29:47,516 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:29:47,516 INFO L276 IsEmpty]: Start isEmpty. Operand 1314 states and 1692 transitions. [2018-11-10 11:29:47,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-10 11:29:47,517 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:29:47,517 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:29:47,517 INFO L424 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:29:47,518 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:47,518 INFO L82 PathProgramCache]: Analyzing trace with hash 1663185356, now seen corresponding path program 1 times [2018-11-10 11:29:47,518 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:29:47,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:47,520 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:29:47,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:29:47,520 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:29:47,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:29:47,606 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 11:29:47,606 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:29:47,606 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:29:47,606 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 72 with the following transitions: [2018-11-10 11:29:47,607 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [519], [521], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [824], [825], [830], [834], [835], [872], [873], [878], [879], [880] [2018-11-10 11:29:47,609 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:29:47,609 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:29:47,715 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:29:47,715 INFO L272 AbstractInterpreter]: Visited 45 different actions 54 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:29:47,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:29:47,724 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:29:47,867 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:29:47,868 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:29:49,184 INFO L415 sIntCurrentIteration]: We unified 70 AI predicates to 70 [2018-11-10 11:29:49,184 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:29:49,184 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:29:49,184 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-11-10 11:29:49,184 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:29:49,184 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-10 11:29:49,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-10 11:29:49,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=633, Unknown=0, NotChecked=0, Total=756 [2018-11-10 11:29:49,185 INFO L87 Difference]: Start difference. First operand 1314 states and 1692 transitions. Second operand 28 states. [2018-11-10 11:30:08,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:30:08,826 INFO L93 Difference]: Finished difference Result 2811 states and 3588 transitions. [2018-11-10 11:30:08,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-10 11:30:08,826 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 71 [2018-11-10 11:30:08,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:30:08,830 INFO L225 Difference]: With dead ends: 2811 [2018-11-10 11:30:08,831 INFO L226 Difference]: Without dead ends: 2041 [2018-11-10 11:30:08,832 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 72 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 324 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=138, Invalid=732, Unknown=0, NotChecked=0, Total=870 [2018-11-10 11:30:08,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2041 states. [2018-11-10 11:30:08,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2041 to 1349. [2018-11-10 11:30:08,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1349 states. [2018-11-10 11:30:08,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1349 states to 1349 states and 1739 transitions. [2018-11-10 11:30:08,943 INFO L78 Accepts]: Start accepts. Automaton has 1349 states and 1739 transitions. Word has length 71 [2018-11-10 11:30:08,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:30:08,943 INFO L481 AbstractCegarLoop]: Abstraction has 1349 states and 1739 transitions. [2018-11-10 11:30:08,943 INFO L482 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-10 11:30:08,943 INFO L276 IsEmpty]: Start isEmpty. Operand 1349 states and 1739 transitions. [2018-11-10 11:30:08,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 11:30:08,945 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:30:08,945 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:30:08,945 INFO L424 AbstractCegarLoop]: === Iteration 16 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:30:08,945 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:08,945 INFO L82 PathProgramCache]: Analyzing trace with hash -1985250647, now seen corresponding path program 1 times [2018-11-10 11:30:08,945 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:30:08,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:08,947 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:30:08,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:08,947 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:30:08,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:30:09,049 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 11:30:09,050 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:30:09,050 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:30:09,050 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 73 with the following transitions: [2018-11-10 11:30:09,050 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [523], [526], [528], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [826], [827], [830], [834], [835], [872], [873], [878], [879], [880] [2018-11-10 11:30:09,053 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:30:09,053 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:30:09,166 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:30:09,166 INFO L272 AbstractInterpreter]: Visited 46 different actions 55 times. Merged at 1 different actions 2 times. Never widened. Found 2 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:30:09,169 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:09,169 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:30:09,356 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:30:09,357 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:30:10,822 INFO L415 sIntCurrentIteration]: We unified 71 AI predicates to 71 [2018-11-10 11:30:10,822 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:30:10,822 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:30:10,822 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-11-10 11:30:10,822 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:30:10,823 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-10 11:30:10,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-10 11:30:10,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=685, Unknown=0, NotChecked=0, Total=812 [2018-11-10 11:30:10,823 INFO L87 Difference]: Start difference. First operand 1349 states and 1739 transitions. Second operand 29 states. [2018-11-10 11:30:25,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:30:25,876 INFO L93 Difference]: Finished difference Result 2853 states and 3641 transitions. [2018-11-10 11:30:25,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-10 11:30:25,876 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 72 [2018-11-10 11:30:25,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:30:25,880 INFO L225 Difference]: With dead ends: 2853 [2018-11-10 11:30:25,881 INFO L226 Difference]: Without dead ends: 2083 [2018-11-10 11:30:25,882 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 73 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 344 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=142, Invalid=788, Unknown=0, NotChecked=0, Total=930 [2018-11-10 11:30:25,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states. [2018-11-10 11:30:26,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 1384. [2018-11-10 11:30:26,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1384 states. [2018-11-10 11:30:26,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1384 states to 1384 states and 1785 transitions. [2018-11-10 11:30:26,010 INFO L78 Accepts]: Start accepts. Automaton has 1384 states and 1785 transitions. Word has length 72 [2018-11-10 11:30:26,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:30:26,011 INFO L481 AbstractCegarLoop]: Abstraction has 1384 states and 1785 transitions. [2018-11-10 11:30:26,011 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-10 11:30:26,011 INFO L276 IsEmpty]: Start isEmpty. Operand 1384 states and 1785 transitions. [2018-11-10 11:30:26,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-10 11:30:26,014 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:30:26,014 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:30:26,015 INFO L424 AbstractCegarLoop]: === Iteration 17 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:30:26,015 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:26,015 INFO L82 PathProgramCache]: Analyzing trace with hash -198691610, now seen corresponding path program 1 times [2018-11-10 11:30:26,015 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:30:26,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:26,017 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:30:26,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:26,017 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:30:26,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:30:26,169 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 15 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 11:30:26,170 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:30:26,170 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:30:26,170 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 81 with the following transitions: [2018-11-10 11:30:26,170 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [516], [519], [521], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [824], [825], [830], [834], [835], [878], [879], [880] [2018-11-10 11:30:26,172 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:30:26,172 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:30:26,338 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:30:26,338 INFO L272 AbstractInterpreter]: Visited 41 different actions 52 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:30:26,352 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:26,353 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:30:26,579 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:30:26,579 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:30:28,085 INFO L415 sIntCurrentIteration]: We unified 79 AI predicates to 79 [2018-11-10 11:30:28,085 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:30:28,085 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:30:28,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [12] total 40 [2018-11-10 11:30:28,086 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:30:28,086 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-10 11:30:28,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-10 11:30:28,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-11-10 11:30:28,087 INFO L87 Difference]: Start difference. First operand 1384 states and 1785 transitions. Second operand 30 states. [2018-11-10 11:30:48,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:30:48,880 INFO L93 Difference]: Finished difference Result 2888 states and 3688 transitions. [2018-11-10 11:30:48,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-10 11:30:48,880 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 80 [2018-11-10 11:30:48,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:30:48,886 INFO L225 Difference]: With dead ends: 2888 [2018-11-10 11:30:48,886 INFO L226 Difference]: Without dead ends: 2118 [2018-11-10 11:30:48,888 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 81 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-11-10 11:30:48,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2118 states. [2018-11-10 11:30:49,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2118 to 1428. [2018-11-10 11:30:49,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1428 states. [2018-11-10 11:30:49,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1428 states to 1428 states and 1842 transitions. [2018-11-10 11:30:49,029 INFO L78 Accepts]: Start accepts. Automaton has 1428 states and 1842 transitions. Word has length 80 [2018-11-10 11:30:49,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:30:49,029 INFO L481 AbstractCegarLoop]: Abstraction has 1428 states and 1842 transitions. [2018-11-10 11:30:49,029 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-10 11:30:49,029 INFO L276 IsEmpty]: Start isEmpty. Operand 1428 states and 1842 transitions. [2018-11-10 11:30:49,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-10 11:30:49,031 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:30:49,031 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:30:49,031 INFO L424 AbstractCegarLoop]: === Iteration 18 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:30:49,031 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:49,032 INFO L82 PathProgramCache]: Analyzing trace with hash 2019719707, now seen corresponding path program 1 times [2018-11-10 11:30:49,032 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:30:49,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:49,036 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:30:49,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:49,036 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:30:49,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:30:49,082 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-10 11:30:49,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:30:49,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:30:49,082 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:30:49,083 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:30:49,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:30:49,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:30:49,083 INFO L87 Difference]: Start difference. First operand 1428 states and 1842 transitions. Second operand 3 states. [2018-11-10 11:30:49,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:30:49,382 INFO L93 Difference]: Finished difference Result 2454 states and 3149 transitions. [2018-11-10 11:30:49,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:30:49,383 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 77 [2018-11-10 11:30:49,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:30:49,385 INFO L225 Difference]: With dead ends: 2454 [2018-11-10 11:30:49,386 INFO L226 Difference]: Without dead ends: 1422 [2018-11-10 11:30:49,387 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:30:49,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1422 states. [2018-11-10 11:30:49,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1422 to 1386. [2018-11-10 11:30:49,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1386 states. [2018-11-10 11:30:49,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1386 states to 1386 states and 1791 transitions. [2018-11-10 11:30:49,509 INFO L78 Accepts]: Start accepts. Automaton has 1386 states and 1791 transitions. Word has length 77 [2018-11-10 11:30:49,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:30:49,509 INFO L481 AbstractCegarLoop]: Abstraction has 1386 states and 1791 transitions. [2018-11-10 11:30:49,509 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:30:49,509 INFO L276 IsEmpty]: Start isEmpty. Operand 1386 states and 1791 transitions. [2018-11-10 11:30:49,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-10 11:30:49,512 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:30:49,512 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:30:49,512 INFO L424 AbstractCegarLoop]: === Iteration 19 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:30:49,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:49,512 INFO L82 PathProgramCache]: Analyzing trace with hash 643475997, now seen corresponding path program 1 times [2018-11-10 11:30:49,512 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:30:49,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:49,514 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:30:49,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:30:49,514 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:30:49,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:30:49,613 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-10 11:30:49,614 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:30:49,614 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:30:49,614 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 82 with the following transitions: [2018-11-10 11:30:49,614 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [516], [519], [521], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [824], [825], [830], [834], [835], [878], [879], [880] [2018-11-10 11:30:49,616 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:30:49,616 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:30:49,727 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:30:49,727 INFO L272 AbstractInterpreter]: Visited 43 different actions 59 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:30:49,732 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:30:49,732 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:30:49,957 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:30:49,957 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:30:51,405 INFO L415 sIntCurrentIteration]: We unified 80 AI predicates to 80 [2018-11-10 11:30:51,406 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:30:51,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:30:51,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-11-10 11:30:51,406 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:30:51,406 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-10 11:30:51,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-10 11:30:51,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-11-10 11:30:51,407 INFO L87 Difference]: Start difference. First operand 1386 states and 1791 transitions. Second operand 30 states. [2018-11-10 11:31:04,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:31:04,427 INFO L93 Difference]: Finished difference Result 2841 states and 3633 transitions. [2018-11-10 11:31:04,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-10 11:31:04,427 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 81 [2018-11-10 11:31:04,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:31:04,431 INFO L225 Difference]: With dead ends: 2841 [2018-11-10 11:31:04,431 INFO L226 Difference]: Without dead ends: 2099 [2018-11-10 11:31:04,432 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 82 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-11-10 11:31:04,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2099 states. [2018-11-10 11:31:04,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2099 to 1430. [2018-11-10 11:31:04,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1430 states. [2018-11-10 11:31:04,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1430 states to 1430 states and 1848 transitions. [2018-11-10 11:31:04,595 INFO L78 Accepts]: Start accepts. Automaton has 1430 states and 1848 transitions. Word has length 81 [2018-11-10 11:31:04,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:31:04,595 INFO L481 AbstractCegarLoop]: Abstraction has 1430 states and 1848 transitions. [2018-11-10 11:31:04,595 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-10 11:31:04,595 INFO L276 IsEmpty]: Start isEmpty. Operand 1430 states and 1848 transitions. [2018-11-10 11:31:04,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-11-10 11:31:04,596 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:31:04,596 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:31:04,597 INFO L424 AbstractCegarLoop]: === Iteration 20 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:31:04,597 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:31:04,597 INFO L82 PathProgramCache]: Analyzing trace with hash 832763812, now seen corresponding path program 1 times [2018-11-10 11:31:04,597 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:31:04,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:31:04,598 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:31:04,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:31:04,598 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:31:04,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:31:04,699 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-10 11:31:04,700 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:31:04,700 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:31:04,700 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 80 with the following transitions: [2018-11-10 11:31:04,701 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [512], [514], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [822], [823], [830], [834], [835], [878], [879], [880] [2018-11-10 11:31:04,703 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:31:04,703 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:31:04,809 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:31:04,809 INFO L272 AbstractInterpreter]: Visited 40 different actions 51 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:31:04,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:31:04,813 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:31:04,982 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:31:04,982 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:31:06,354 INFO L415 sIntCurrentIteration]: We unified 78 AI predicates to 78 [2018-11-10 11:31:06,354 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:31:06,355 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:31:06,355 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-11-10 11:31:06,355 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:31:06,355 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-10 11:31:06,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-10 11:31:06,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=681, Unknown=0, NotChecked=0, Total=812 [2018-11-10 11:31:06,355 INFO L87 Difference]: Start difference. First operand 1430 states and 1848 transitions. Second operand 29 states. [2018-11-10 11:31:28,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:31:28,011 INFO L93 Difference]: Finished difference Result 2892 states and 3697 transitions. [2018-11-10 11:31:28,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-10 11:31:28,011 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 79 [2018-11-10 11:31:28,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:31:28,015 INFO L225 Difference]: With dead ends: 2892 [2018-11-10 11:31:28,015 INFO L226 Difference]: Without dead ends: 2150 [2018-11-10 11:31:28,016 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 80 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 362 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=146, Invalid=784, Unknown=0, NotChecked=0, Total=930 [2018-11-10 11:31:28,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2150 states. [2018-11-10 11:31:28,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2150 to 1474. [2018-11-10 11:31:28,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1474 states. [2018-11-10 11:31:28,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1474 states to 1474 states and 1905 transitions. [2018-11-10 11:31:28,169 INFO L78 Accepts]: Start accepts. Automaton has 1474 states and 1905 transitions. Word has length 79 [2018-11-10 11:31:28,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:31:28,170 INFO L481 AbstractCegarLoop]: Abstraction has 1474 states and 1905 transitions. [2018-11-10 11:31:28,170 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-10 11:31:28,170 INFO L276 IsEmpty]: Start isEmpty. Operand 1474 states and 1905 transitions. [2018-11-10 11:31:28,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-10 11:31:28,171 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:31:28,172 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:31:28,172 INFO L424 AbstractCegarLoop]: === Iteration 21 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:31:28,172 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:31:28,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1410958006, now seen corresponding path program 1 times [2018-11-10 11:31:28,172 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:31:28,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:31:28,174 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:31:28,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:31:28,174 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:31:28,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:31:28,270 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 11:31:28,270 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:31:28,270 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:31:28,270 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 84 with the following transitions: [2018-11-10 11:31:28,270 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [516], [519], [521], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [824], [825], [826], [827], [830], [834], [835], [878], [879], [880] [2018-11-10 11:31:28,272 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:31:28,272 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:31:28,378 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:31:28,378 INFO L272 AbstractInterpreter]: Visited 44 different actions 60 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:31:28,384 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:31:28,384 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:31:28,557 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:31:28,558 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:31:30,211 INFO L415 sIntCurrentIteration]: We unified 82 AI predicates to 82 [2018-11-10 11:31:30,211 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:31:30,212 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:31:30,212 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-11-10 11:31:30,212 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:31:30,212 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-10 11:31:30,212 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-10 11:31:30,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=791, Unknown=0, NotChecked=0, Total=930 [2018-11-10 11:31:30,213 INFO L87 Difference]: Start difference. First operand 1474 states and 1905 transitions. Second operand 31 states. [2018-11-10 11:31:45,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:31:45,203 INFO L93 Difference]: Finished difference Result 2936 states and 3753 transitions. [2018-11-10 11:31:45,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-10 11:31:45,203 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 83 [2018-11-10 11:31:45,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:31:45,209 INFO L225 Difference]: With dead ends: 2936 [2018-11-10 11:31:45,209 INFO L226 Difference]: Without dead ends: 2194 [2018-11-10 11:31:45,211 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 84 GetRequests, 52 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-11-10 11:31:45,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2194 states. [2018-11-10 11:31:45,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2194 to 1518. [2018-11-10 11:31:45,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1518 states. [2018-11-10 11:31:45,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1518 states to 1518 states and 1961 transitions. [2018-11-10 11:31:45,381 INFO L78 Accepts]: Start accepts. Automaton has 1518 states and 1961 transitions. Word has length 83 [2018-11-10 11:31:45,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:31:45,381 INFO L481 AbstractCegarLoop]: Abstraction has 1518 states and 1961 transitions. [2018-11-10 11:31:45,381 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-10 11:31:45,381 INFO L276 IsEmpty]: Start isEmpty. Operand 1518 states and 1961 transitions. [2018-11-10 11:31:45,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-10 11:31:45,383 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:31:45,383 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:31:45,383 INFO L424 AbstractCegarLoop]: === Iteration 22 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:31:45,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:31:45,383 INFO L82 PathProgramCache]: Analyzing trace with hash -1367045507, now seen corresponding path program 1 times [2018-11-10 11:31:45,383 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:31:45,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:31:45,384 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:31:45,384 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:31:45,384 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:31:45,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:31:45,513 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-10 11:31:45,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:31:45,513 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:31:45,513 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 82 with the following transitions: [2018-11-10 11:31:45,513 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [516], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [826], [827], [830], [834], [835], [878], [879], [880] [2018-11-10 11:31:45,515 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:31:45,515 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:31:45,695 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:31:45,696 INFO L272 AbstractInterpreter]: Visited 42 different actions 53 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:31:45,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:31:45,698 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:31:45,943 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:31:45,943 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:31:47,505 INFO L415 sIntCurrentIteration]: We unified 80 AI predicates to 80 [2018-11-10 11:31:47,505 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:31:47,506 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:31:47,506 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-11-10 11:31:47,506 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:31:47,506 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-10 11:31:47,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-10 11:31:47,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=791, Unknown=0, NotChecked=0, Total=930 [2018-11-10 11:31:47,507 INFO L87 Difference]: Start difference. First operand 1518 states and 1961 transitions. Second operand 31 states. [2018-11-10 11:32:00,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:32:00,437 INFO L93 Difference]: Finished difference Result 2987 states and 3816 transitions. [2018-11-10 11:32:00,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-10 11:32:00,437 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 81 [2018-11-10 11:32:00,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:32:00,443 INFO L225 Difference]: With dead ends: 2987 [2018-11-10 11:32:00,443 INFO L226 Difference]: Without dead ends: 2245 [2018-11-10 11:32:00,446 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 82 GetRequests, 50 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 410 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-11-10 11:32:00,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2245 states. [2018-11-10 11:32:00,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2245 to 1562. [2018-11-10 11:32:00,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1562 states. [2018-11-10 11:32:00,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1562 states to 1562 states and 2017 transitions. [2018-11-10 11:32:00,622 INFO L78 Accepts]: Start accepts. Automaton has 1562 states and 2017 transitions. Word has length 81 [2018-11-10 11:32:00,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:32:00,622 INFO L481 AbstractCegarLoop]: Abstraction has 1562 states and 2017 transitions. [2018-11-10 11:32:00,622 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-10 11:32:00,622 INFO L276 IsEmpty]: Start isEmpty. Operand 1562 states and 2017 transitions. [2018-11-10 11:32:00,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-10 11:32:00,623 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:32:00,623 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:32:00,624 INFO L424 AbstractCegarLoop]: === Iteration 23 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:32:00,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:00,624 INFO L82 PathProgramCache]: Analyzing trace with hash -833825378, now seen corresponding path program 1 times [2018-11-10 11:32:00,624 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:32:00,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:00,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:32:00,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:00,625 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:32:00,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:32:00,719 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-10 11:32:00,720 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:32:00,720 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:32:00,720 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 83 with the following transitions: [2018-11-10 11:32:00,720 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [516], [523], [526], [528], [540], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [826], [827], [830], [834], [835], [878], [879], [880] [2018-11-10 11:32:00,721 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:32:00,722 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:32:00,831 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:32:00,831 INFO L272 AbstractInterpreter]: Visited 44 different actions 60 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:32:00,832 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:00,832 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:32:01,002 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:32:01,002 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:32:02,635 INFO L415 sIntCurrentIteration]: We unified 81 AI predicates to 81 [2018-11-10 11:32:02,635 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:32:02,635 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:32:02,635 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-11-10 11:32:02,635 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:32:02,635 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-10 11:32:02,636 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-10 11:32:02,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=791, Unknown=0, NotChecked=0, Total=930 [2018-11-10 11:32:02,636 INFO L87 Difference]: Start difference. First operand 1562 states and 2017 transitions. Second operand 31 states. [2018-11-10 11:32:26,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:32:26,749 INFO L93 Difference]: Finished difference Result 3032 states and 3872 transitions. [2018-11-10 11:32:26,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-10 11:32:26,749 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 82 [2018-11-10 11:32:26,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:32:26,754 INFO L225 Difference]: With dead ends: 3032 [2018-11-10 11:32:26,754 INFO L226 Difference]: Without dead ends: 2290 [2018-11-10 11:32:26,755 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 83 GetRequests, 51 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 405 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-11-10 11:32:26,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2290 states. [2018-11-10 11:32:26,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2290 to 1606. [2018-11-10 11:32:26,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2018-11-10 11:32:26,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2072 transitions. [2018-11-10 11:32:26,957 INFO L78 Accepts]: Start accepts. Automaton has 1606 states and 2072 transitions. Word has length 82 [2018-11-10 11:32:26,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:32:26,957 INFO L481 AbstractCegarLoop]: Abstraction has 1606 states and 2072 transitions. [2018-11-10 11:32:26,957 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-10 11:32:26,958 INFO L276 IsEmpty]: Start isEmpty. Operand 1606 states and 2072 transitions. [2018-11-10 11:32:26,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-10 11:32:26,959 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:32:26,959 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:32:26,959 INFO L424 AbstractCegarLoop]: === Iteration 24 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:32:26,959 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:26,959 INFO L82 PathProgramCache]: Analyzing trace with hash -1968261165, now seen corresponding path program 1 times [2018-11-10 11:32:26,959 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:32:26,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:26,960 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:32:26,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:26,960 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:32:26,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:32:27,021 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-10 11:32:27,021 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:32:27,021 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:32:27,021 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:32:27,022 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:32:27,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:32:27,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:32:27,022 INFO L87 Difference]: Start difference. First operand 1606 states and 2072 transitions. Second operand 3 states. [2018-11-10 11:32:27,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:32:27,409 INFO L93 Difference]: Finished difference Result 3026 states and 3870 transitions. [2018-11-10 11:32:27,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:32:27,409 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2018-11-10 11:32:27,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:32:27,413 INFO L225 Difference]: With dead ends: 3026 [2018-11-10 11:32:27,413 INFO L226 Difference]: Without dead ends: 2045 [2018-11-10 11:32:27,415 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:32:27,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2045 states. [2018-11-10 11:32:27,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2045 to 2021. [2018-11-10 11:32:27,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2021 states. [2018-11-10 11:32:27,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2567 transitions. [2018-11-10 11:32:27,633 INFO L78 Accepts]: Start accepts. Automaton has 2021 states and 2567 transitions. Word has length 82 [2018-11-10 11:32:27,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:32:27,633 INFO L481 AbstractCegarLoop]: Abstraction has 2021 states and 2567 transitions. [2018-11-10 11:32:27,633 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:32:27,633 INFO L276 IsEmpty]: Start isEmpty. Operand 2021 states and 2567 transitions. [2018-11-10 11:32:27,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-11-10 11:32:27,635 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:32:27,635 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:32:27,635 INFO L424 AbstractCegarLoop]: === Iteration 25 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:32:27,635 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:27,635 INFO L82 PathProgramCache]: Analyzing trace with hash 1852197615, now seen corresponding path program 1 times [2018-11-10 11:32:27,635 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:32:27,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:27,637 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:32:27,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:27,637 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:32:27,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:32:27,733 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-10 11:32:27,733 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:32:27,733 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:32:27,733 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-11-10 11:32:27,733 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [509], [512], [514], [516], [519], [521], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [822], [823], [824], [825], [830], [834], [835], [872], [873], [878], [879], [880] [2018-11-10 11:32:27,735 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:32:27,735 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:32:27,901 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:32:27,901 INFO L272 AbstractInterpreter]: Visited 49 different actions 65 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:32:27,919 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:27,920 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:32:28,123 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:32:28,123 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:32:29,804 INFO L415 sIntCurrentIteration]: We unified 86 AI predicates to 86 [2018-11-10 11:32:29,804 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:32:29,804 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:32:29,805 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-11-10 11:32:29,805 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:32:29,805 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-10 11:32:29,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-10 11:32:29,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=788, Unknown=0, NotChecked=0, Total=930 [2018-11-10 11:32:29,806 INFO L87 Difference]: Start difference. First operand 2021 states and 2567 transitions. Second operand 31 states. [2018-11-10 11:32:45,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:32:45,134 INFO L93 Difference]: Finished difference Result 4041 states and 5085 transitions. [2018-11-10 11:32:45,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-10 11:32:45,134 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 87 [2018-11-10 11:32:45,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:32:45,140 INFO L225 Difference]: With dead ends: 4041 [2018-11-10 11:32:45,141 INFO L226 Difference]: Without dead ends: 2984 [2018-11-10 11:32:45,143 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 88 GetRequests, 56 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 401 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=157, Invalid=899, Unknown=0, NotChecked=0, Total=1056 [2018-11-10 11:32:45,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2984 states. [2018-11-10 11:32:45,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2984 to 2065. [2018-11-10 11:32:45,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2065 states. [2018-11-10 11:32:45,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2065 states to 2065 states and 2624 transitions. [2018-11-10 11:32:45,372 INFO L78 Accepts]: Start accepts. Automaton has 2065 states and 2624 transitions. Word has length 87 [2018-11-10 11:32:45,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:32:45,372 INFO L481 AbstractCegarLoop]: Abstraction has 2065 states and 2624 transitions. [2018-11-10 11:32:45,372 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-10 11:32:45,372 INFO L276 IsEmpty]: Start isEmpty. Operand 2065 states and 2624 transitions. [2018-11-10 11:32:45,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-10 11:32:45,374 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:32:45,374 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:32:45,374 INFO L424 AbstractCegarLoop]: === Iteration 26 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:32:45,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:45,375 INFO L82 PathProgramCache]: Analyzing trace with hash -479943434, now seen corresponding path program 1 times [2018-11-10 11:32:45,375 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:32:45,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:45,376 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:32:45,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:32:45,377 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:32:45,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:32:45,479 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-10 11:32:45,479 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:32:45,479 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:32:45,479 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 86 with the following transitions: [2018-11-10 11:32:45,479 INFO L202 CegarAbsIntRunner]: [21], [23], [25], [27], [30], [33], [413], [416], [418], [444], [447], [450], [453], [456], [472], [474], [475], [502], [505], [507], [509], [512], [514], [540], [541], [547], [548], [555], [573], [583], [588], [590], [617], [621], [623], [624], [697], [698], [700], [701], [702], [706], [708], [709], [742], [743], [744], [745], [746], [747], [804], [805], [806], [814], [820], [821], [822], [823], [830], [834], [835], [872], [873], [878], [879], [880] [2018-11-10 11:32:45,483 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:32:45,483 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:32:45,649 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-10 11:32:45,649 INFO L272 AbstractInterpreter]: Visited 46 different actions 57 times. Merged at 3 different actions 4 times. Never widened. Found 3 fixpoints after 2 different actions. Largest state had 182 variables. [2018-11-10 11:32:45,651 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:32:45,651 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-10 11:32:45,830 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.83% of their original sizes. [2018-11-10 11:32:45,831 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-10 11:32:47,189 INFO L415 sIntCurrentIteration]: We unified 84 AI predicates to 84 [2018-11-10 11:32:47,189 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-10 11:32:47,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:32:47,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-11-10 11:32:47,190 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-10 11:32:47,190 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-10 11:32:47,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-10 11:32:47,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=732, Unknown=0, NotChecked=0, Total=870 [2018-11-10 11:32:47,190 INFO L87 Difference]: Start difference. First operand 2065 states and 2624 transitions. Second operand 30 states. [2018-11-10 11:33:09,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:09,159 INFO L93 Difference]: Finished difference Result 4094 states and 5151 transitions. [2018-11-10 11:33:09,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-10 11:33:09,160 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 85 [2018-11-10 11:33:09,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:09,165 INFO L225 Difference]: With dead ends: 4094 [2018-11-10 11:33:09,165 INFO L226 Difference]: Without dead ends: 3037 [2018-11-10 11:33:09,167 INFO L605 BasicCegarLoop]: 2 DeclaredPredicates, 86 GetRequests, 55 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 386 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=153, Invalid=839, Unknown=0, NotChecked=0, Total=992 [2018-11-10 11:33:09,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3037 states. [2018-11-10 11:33:09,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3037 to 2111. [2018-11-10 11:33:09,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2111 states. [2018-11-10 11:33:09,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2111 states to 2111 states and 2683 transitions. [2018-11-10 11:33:09,412 INFO L78 Accepts]: Start accepts. Automaton has 2111 states and 2683 transitions. Word has length 85 [2018-11-10 11:33:09,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:09,412 INFO L481 AbstractCegarLoop]: Abstraction has 2111 states and 2683 transitions. [2018-11-10 11:33:09,412 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-10 11:33:09,412 INFO L276 IsEmpty]: Start isEmpty. Operand 2111 states and 2683 transitions. [2018-11-10 11:33:09,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-10 11:33:09,414 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:09,414 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:09,414 INFO L424 AbstractCegarLoop]: === Iteration 27 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:09,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:09,415 INFO L82 PathProgramCache]: Analyzing trace with hash 913353771, now seen corresponding path program 1 times [2018-11-10 11:33:09,415 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:33:09,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:09,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:09,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:09,416 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:33:09,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:09,472 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:33:09,472 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:09,472 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:33:09,472 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 84 with the following transitions: [2018-11-10 11:33:09,473 INFO L202 CegarAbsIntRunner]: [19], [20], [21], [23], [25], [27], [39], [42], [45], [57], [60], [63], [65], [68], [77], [96], [256], [259], [262], [265], [272], [276], [283], [302], [331], [350], [353], [356], [444], [498], [500], [501], [555], [573], [583], [588], [590], [601], [603], [617], [621], [623], [624], [672], [697], [698], [700], [701], [702], [705], [709], [742], [743], [744], [745], [750], [751], [752], [753], [782], [818], [819], [830], [834], [835], [838], [839], [840], [860], [878], [879], [880] [2018-11-10 11:33:09,474 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-10 11:33:09,474 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-10 11:33:10,225 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-10 11:33:10,225 INFO L272 AbstractInterpreter]: Visited 72 different actions 255 times. Merged at 26 different actions 87 times. Never widened. Found 6 fixpoints after 4 different actions. Largest state had 191 variables. [2018-11-10 11:33:10,232 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:10,233 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-10 11:33:10,233 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:10,233 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:33:10,242 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:10,242 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-10 11:33:10,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:10,420 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:10,493 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 11:33:10,493 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:10,606 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:33:10,625 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-10 11:33:10,625 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2018-11-10 11:33:10,626 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-10 11:33:10,626 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-10 11:33:10,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-10 11:33:10,626 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-11-10 11:33:10,626 INFO L87 Difference]: Start difference. First operand 2111 states and 2683 transitions. Second operand 8 states. [2018-11-10 11:33:11,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:11,018 INFO L93 Difference]: Finished difference Result 4197 states and 5339 transitions. [2018-11-10 11:33:11,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 11:33:11,018 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 83 [2018-11-10 11:33:11,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:11,024 INFO L225 Difference]: With dead ends: 4197 [2018-11-10 11:33:11,024 INFO L226 Difference]: Without dead ends: 2112 [2018-11-10 11:33:11,028 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 160 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=81, Unknown=0, NotChecked=0, Total=132 [2018-11-10 11:33:11,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2112 states. [2018-11-10 11:33:11,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2112 to 2112. [2018-11-10 11:33:11,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2112 states. [2018-11-10 11:33:11,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2112 states to 2112 states and 2684 transitions. [2018-11-10 11:33:11,325 INFO L78 Accepts]: Start accepts. Automaton has 2112 states and 2684 transitions. Word has length 83 [2018-11-10 11:33:11,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:11,325 INFO L481 AbstractCegarLoop]: Abstraction has 2112 states and 2684 transitions. [2018-11-10 11:33:11,325 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-10 11:33:11,325 INFO L276 IsEmpty]: Start isEmpty. Operand 2112 states and 2684 transitions. [2018-11-10 11:33:11,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-11-10 11:33:11,327 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:11,328 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:11,328 INFO L424 AbstractCegarLoop]: === Iteration 28 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:11,328 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:11,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1642754396, now seen corresponding path program 2 times [2018-11-10 11:33:11,328 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:33:11,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:11,330 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:11,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:11,330 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:33:11,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:11,416 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:33:11,416 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:11,417 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:33:11,417 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-10 11:33:11,417 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-10 11:33:11,417 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:11,417 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:33:11,440 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 11:33:11,440 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-10 11:33:12,253 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-10 11:33:12,253 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 11:33:12,259 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:12,316 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 11:33:12,316 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:12,379 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:33:12,400 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-10 11:33:12,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 14 [2018-11-10 11:33:12,400 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-10 11:33:12,400 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-10 11:33:12,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-10 11:33:12,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2018-11-10 11:33:12,401 INFO L87 Difference]: Start difference. First operand 2112 states and 2684 transitions. Second operand 10 states. [2018-11-10 11:33:12,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:12,800 INFO L93 Difference]: Finished difference Result 4198 states and 5340 transitions. [2018-11-10 11:33:12,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:33:12,801 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 84 [2018-11-10 11:33:12,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:12,809 INFO L225 Difference]: With dead ends: 4198 [2018-11-10 11:33:12,809 INFO L226 Difference]: Without dead ends: 2113 [2018-11-10 11:33:12,813 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 160 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=82, Invalid=128, Unknown=0, NotChecked=0, Total=210 [2018-11-10 11:33:12,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2113 states. [2018-11-10 11:33:13,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2113 to 2113. [2018-11-10 11:33:13,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2113 states. [2018-11-10 11:33:13,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2113 states to 2113 states and 2685 transitions. [2018-11-10 11:33:13,197 INFO L78 Accepts]: Start accepts. Automaton has 2113 states and 2685 transitions. Word has length 84 [2018-11-10 11:33:13,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:13,197 INFO L481 AbstractCegarLoop]: Abstraction has 2113 states and 2685 transitions. [2018-11-10 11:33:13,197 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-10 11:33:13,197 INFO L276 IsEmpty]: Start isEmpty. Operand 2113 states and 2685 transitions. [2018-11-10 11:33:13,199 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-10 11:33:13,199 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:13,199 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:13,200 INFO L424 AbstractCegarLoop]: === Iteration 29 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:13,200 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:13,200 INFO L82 PathProgramCache]: Analyzing trace with hash 722271051, now seen corresponding path program 3 times [2018-11-10 11:33:13,200 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:33:13,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:13,202 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 11:33:13,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:13,202 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:33:13,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:13,282 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:33:13,282 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:13,282 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-10 11:33:13,282 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-10 11:33:13,283 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-10 11:33:13,283 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:13,283 INFO L194 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:33:13,301 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 11:33:13,302 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-10 11:33:13,432 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 11:33:13,433 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 11:33:13,439 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:13,517 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 11:33:13,518 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:13,608 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:33:13,628 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-10 11:33:13,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 16 [2018-11-10 11:33:13,628 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-10 11:33:13,629 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-10 11:33:13,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-10 11:33:13,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-11-10 11:33:13,629 INFO L87 Difference]: Start difference. First operand 2113 states and 2685 transitions. Second operand 12 states. [2018-11-10 11:33:13,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:13,941 INFO L93 Difference]: Finished difference Result 4199 states and 5341 transitions. [2018-11-10 11:33:13,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 11:33:13,941 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-11-10 11:33:13,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:13,945 INFO L225 Difference]: With dead ends: 4199 [2018-11-10 11:33:13,946 INFO L226 Difference]: Without dead ends: 2114 [2018-11-10 11:33:13,949 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 177 GetRequests, 160 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=106, Invalid=166, Unknown=0, NotChecked=0, Total=272 [2018-11-10 11:33:13,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states. [2018-11-10 11:33:14,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2018-11-10 11:33:14,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2114 states. [2018-11-10 11:33:14,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 2686 transitions. [2018-11-10 11:33:14,295 INFO L78 Accepts]: Start accepts. Automaton has 2114 states and 2686 transitions. Word has length 85 [2018-11-10 11:33:14,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:14,295 INFO L481 AbstractCegarLoop]: Abstraction has 2114 states and 2686 transitions. [2018-11-10 11:33:14,295 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-10 11:33:14,296 INFO L276 IsEmpty]: Start isEmpty. Operand 2114 states and 2686 transitions. [2018-11-10 11:33:14,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-10 11:33:14,298 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:14,298 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:14,298 INFO L424 AbstractCegarLoop]: === Iteration 30 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:14,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:14,298 INFO L82 PathProgramCache]: Analyzing trace with hash 1023615876, now seen corresponding path program 4 times [2018-11-10 11:33:14,298 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-10 11:33:14,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:14,300 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 11:33:14,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 11:33:14,300 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-10 11:33:14,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 11:33:14,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 11:33:14,430 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-10 11:33:14,449 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,451 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,453 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,454 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,455 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,456 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,460 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,460 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,460 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,461 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,463 WARN L387 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-10 11:33:14,464 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,468 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,468 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,468 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,469 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,469 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,469 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,469 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,469 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,470 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,470 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,470 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,470 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,471 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,471 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,471 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,471 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,471 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,472 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,472 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,473 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,473 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,473 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,473 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,475 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,475 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,475 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,476 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,476 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,476 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,476 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,477 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,477 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,477 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,477 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,478 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,478 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,478 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,478 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,479 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,479 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,479 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,479 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,479 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,480 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,480 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,480 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,480 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,481 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,481 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,481 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,481 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,482 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,482 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,482 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,482 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,483 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,483 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,483 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,483 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,484 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,484 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,484 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,484 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,485 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,485 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,485 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,485 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,486 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,486 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:33:14,537 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-11-10 11:33:14,556 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:33:14,558 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:33:14,562 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:33:14,563 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:33:14,564 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:33:14,586 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.11 11:33:14 BoogieIcfgContainer [2018-11-10 11:33:14,587 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-10 11:33:14,587 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 11:33:14,587 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 11:33:14,587 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 11:33:14,588 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 11:27:46" (3/4) ... [2018-11-10 11:33:14,591 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-10 11:33:14,591 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 11:33:14,592 INFO L168 Benchmark]: Toolchain (without parser) took 330826.26 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 953.9 MB in the beginning and 1.7 GB in the end (delta: -696.5 MB). Peak memory consumption was 441.2 MB. Max. memory is 11.5 GB. [2018-11-10 11:33:14,593 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 11:33:14,594 INFO L168 Benchmark]: CACSL2BoogieTranslator took 1049.73 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.4 MB). Free memory was 953.9 MB in the beginning and 1.0 GB in the end (delta: -88.7 MB). Peak memory consumption was 99.1 MB. Max. memory is 11.5 GB. [2018-11-10 11:33:14,594 INFO L168 Benchmark]: Boogie Procedure Inliner took 86.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-11-10 11:33:14,595 INFO L168 Benchmark]: Boogie Preprocessor took 80.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-11-10 11:33:14,595 INFO L168 Benchmark]: RCFGBuilder took 1706.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 6.4 MB). Peak memory consumption was 168.4 MB. Max. memory is 11.5 GB. [2018-11-10 11:33:14,595 INFO L168 Benchmark]: TraceAbstraction took 327894.36 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 999.3 MB). Free memory was 1.0 GB in the beginning and 1.7 GB in the end (delta: -630.3 MB). Peak memory consumption was 369.0 MB. Max. memory is 11.5 GB. [2018-11-10 11:33:14,596 INFO L168 Benchmark]: Witness Printer took 4.37 ms. Allocated memory is still 2.2 GB. Free memory is still 1.7 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 11:33:14,600 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 1049.73 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.4 MB). Free memory was 953.9 MB in the beginning and 1.0 GB in the end (delta: -88.7 MB). Peak memory consumption was 99.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 86.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 80.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1706.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 6.4 MB). Peak memory consumption was 168.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 327894.36 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 999.3 MB). Free memory was 1.0 GB in the beginning and 1.7 GB in the end (delta: -630.3 MB). Peak memory consumption was 369.0 MB. Max. memory is 11.5 GB. * Witness Printer took 4.37 ms. Allocated memory is still 2.2 GB. Free memory is still 1.7 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1684]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseAnd at line 1870. Possible FailurePath: [L1905] CALL "write failed:retry count exceeded.\n" [L1905] RET "write failed:retry count exceeded.\n" [L2072] CALL "name\t\t: %s\n" [L2072] RET "name\t\t: %s\n" [L2150] CALL "Unable to allocate resources for device.\n" [L2150] RET "Unable to allocate resources for device.\n" [L2159] CALL "Unable to request mem region for device.\n" [L2159] RET "Unable to request mem region for device.\n" [L2175] CALL "Unable to grab IOs for device.\n" [L2175] RET "Unable to grab IOs for device.\n" [L2189] CALL "info->tegra_rtc_lock" [L2189] RET "info->tegra_rtc_lock" [L2211] CALL "Unable to register device (err=%d).\n" [L2211] RET "Unable to register device (err=%d).\n" [L2218] CALL "rtc alarm" [L2218] RET "rtc alarm" [L2220] CALL "Unable to request interrupt for device (err=%d).\n" [L2220] RET "Unable to request interrupt for device (err=%d).\n" [L2226] CALL "Tegra internal Real Time Clock\n" [L2226] RET "Tegra internal Real Time Clock\n" [L2323] CALL, EXPR "tegra_rtc" [L2323] RET, EXPR "tegra_rtc" [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] CALL static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] CALL static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] CALL pm_message_t ldvarg2 ; [L2522] RET pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2533] FCALL ldv_initialize() [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] CALL, EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] EXPR, FCALL platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] RET return (tmp); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2569] CALL ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] RET tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2766] FCALL ldv_probe_2() [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={156:219}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={167:-16}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] CALL, EXPR info->rtc_base [L1867] RET, EXPR info->rtc_base [L1867] CALL, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] RET, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] RET return (__v & 1U); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={167:-16}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] RET return (0); VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={167:-16}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, dev_get_drvdata_#res={156:219}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2017] CALL ldv_spin_lock_check() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL ["info->tegra_rtc_lock"={234:0}, "name\t\t: %s\n"={160:0}, "rtc alarm"={218:0}, "Tegra internal Real Time Clock\n"={226:0}, "tegra_rtc"={203:0}, "Unable to allocate resources for device.\n"={240:0}, "Unable to grab IOs for device.\n"={190:0}, "Unable to register device (err=%d).\n"={222:0}, "Unable to request interrupt for device (err=%d).\n"={177:0}, "Unable to request mem region for device.\n"={155:0}, "write failed:retry count exceeded.\n"={170:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={201:166}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={158:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={229:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 42 procedures, 364 locations, 1 error locations. UNSAFE Result, 327.8s OverallTime, 30 OverallIterations, 4 TraceHistogramMax, 290.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9574 SDtfs, 7071 SDslu, 26904 SDs, 0 SdLazy, 9426 SolverSat, 1083 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 115.6s Time, PredicateUnifierStatistics: 34 DeclaredPredicates, 1850 GetRequests, 1297 SyntacticMatches, 20 SemanticMatches, 533 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5683 ImplicationChecksByTransitivity, 22.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=2114occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 3.5s AbstIntTime, 18 AbstIntIterations, 17 AbstIntStrong, 0.9898682516096965 AbsIntWeakeningRatio, 3.4601769911504423 AbsIntAvgWeakeningVarsNumRemoved, 65.16170555108609 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 3.9s AutomataMinimizationTime, 29 MinimizatonAttempts, 10566 StatesRemovedByMinimization, 25 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 1.4s SatisfiabilityAnalysisTime, 2.8s InterpolantComputationTime, 2352 NumberOfCodeBlocks, 2352 NumberOfCodeBlocksAsserted, 36 NumberOfCheckSat, 2483 ConstructedInterpolants, 0 QuantifiedInterpolants, 286015 SizeOfPredicates, 3 NumberOfNonLiveVariables, 2679 ConjunctsInSsa, 15 ConjunctsInUnsatCore, 35 InterpolantComputations, 9 PerfectInterpolantSequences, 405/555 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-1dbac8b [2018-11-10 11:33:16,291 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 11:33:16,293 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 11:33:16,303 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 11:33:16,303 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 11:33:16,304 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 11:33:16,305 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 11:33:16,306 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 11:33:16,307 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 11:33:16,308 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 11:33:16,309 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 11:33:16,309 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 11:33:16,310 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 11:33:16,311 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 11:33:16,312 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 11:33:16,313 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 11:33:16,314 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 11:33:16,315 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 11:33:16,317 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 11:33:16,318 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 11:33:16,319 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 11:33:16,321 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 11:33:16,323 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 11:33:16,323 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 11:33:16,323 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 11:33:16,324 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 11:33:16,325 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 11:33:16,326 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 11:33:16,327 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 11:33:16,327 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 11:33:16,328 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 11:33:16,329 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 11:33:16,329 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 11:33:16,329 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 11:33:16,330 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 11:33:16,331 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 11:33:16,331 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2018-11-10 11:33:16,342 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 11:33:16,343 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 11:33:16,343 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-10 11:33:16,343 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-10 11:33:16,344 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-10 11:33:16,344 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-10 11:33:16,344 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-10 11:33:16,345 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-10 11:33:16,345 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 11:33:16,346 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 11:33:16,346 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-10 11:33:16,346 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 11:33:16,346 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-10 11:33:16,346 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-10 11:33:16,346 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-10 11:33:16,347 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 11:33:16,347 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-10 11:33:16,347 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 11:33:16,347 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 11:33:16,347 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 11:33:16,347 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-10 11:33:16,347 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 11:33:16,348 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 11:33:16,348 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 11:33:16,348 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-10 11:33:16,350 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-11-10 11:33:16,350 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 11:33:16,350 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-10 11:33:16,350 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-10 11:33:16,350 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-11-10 11:33:16,383 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 11:33:16,393 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 11:33:16,396 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 11:33:16,397 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 11:33:16,398 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 11:33:16,398 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-10 11:33:16,451 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/bb6d8f953/7224b8c75b6a4ee69c80496992085af1/FLAG6f468addc [2018-11-10 11:33:16,915 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 11:33:16,915 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-10 11:33:16,933 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/bb6d8f953/7224b8c75b6a4ee69c80496992085af1/FLAG6f468addc [2018-11-10 11:33:16,945 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/data/bb6d8f953/7224b8c75b6a4ee69c80496992085af1 [2018-11-10 11:33:16,948 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 11:33:16,949 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 11:33:16,949 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 11:33:16,949 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 11:33:16,951 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 11:33:16,952 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 11:33:16" (1/1) ... [2018-11-10 11:33:16,954 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3580801f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:16, skipping insertion in model container [2018-11-10 11:33:16,954 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 11:33:16" (1/1) ... [2018-11-10 11:33:16,961 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 11:33:17,016 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 11:33:18,271 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 11:33:18,297 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 11:33:19,114 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 11:33:19,171 INFO L193 MainTranslator]: Completed translation [2018-11-10 11:33:19,171 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19 WrapperNode [2018-11-10 11:33:19,171 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 11:33:19,172 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 11:33:19,172 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 11:33:19,173 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 11:33:19,180 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,208 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,253 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 11:33:19,253 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 11:33:19,253 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 11:33:19,253 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 11:33:19,260 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,260 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,269 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,269 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,297 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,305 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,313 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... [2018-11-10 11:33:19,327 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 11:33:19,327 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 11:33:19,327 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 11:33:19,327 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 11:33:19,328 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 11:33:19,379 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-11-10 11:33:19,379 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-11-10 11:33:19,379 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-11-10 11:33:19,379 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-11-10 11:33:19,379 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-11-10 11:33:19,380 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-11-10 11:33:19,380 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-10 11:33:19,380 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-10 11:33:19,380 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-11-10 11:33:19,380 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-11-10 11:33:19,380 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-11-10 11:33:19,380 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-11-10 11:33:19,381 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-11-10 11:33:19,381 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-11-10 11:33:19,381 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-11-10 11:33:19,382 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-11-10 11:33:19,382 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-11-10 11:33:19,382 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-11-10 11:33:19,382 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-11-10 11:33:19,382 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-11-10 11:33:19,382 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-11-10 11:33:19,382 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-11-10 11:33:19,382 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-11-10 11:33:19,383 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-11-10 11:33:19,383 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-11-10 11:33:19,383 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-11-10 11:33:19,383 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-11-10 11:33:19,383 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-11-10 11:33:19,383 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-11-10 11:33:19,383 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-11-10 11:33:19,383 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-10 11:33:19,383 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-10 11:33:19,383 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-11-10 11:33:19,384 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-11-10 11:33:19,384 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-10 11:33:19,384 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-10 11:33:19,384 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-11-10 11:33:19,384 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-11-10 11:33:19,384 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-11-10 11:33:19,384 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-11-10 11:33:19,384 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-11-10 11:33:19,384 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-11-10 11:33:19,384 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-10 11:33:19,385 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-10 11:33:19,385 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-11-10 11:33:19,385 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-11-10 11:33:19,385 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-11-10 11:33:19,385 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-11-10 11:33:19,385 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-11-10 11:33:19,385 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-11-10 11:33:19,385 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-11-10 11:33:19,385 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-11-10 11:33:19,385 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-11-10 11:33:19,386 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-11-10 11:33:19,386 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-11-10 11:33:19,386 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-11-10 11:33:19,386 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-11-10 11:33:19,386 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-11-10 11:33:19,386 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-11-10 11:33:19,386 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-11-10 11:33:19,386 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-11-10 11:33:19,386 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-11-10 11:33:19,387 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-11-10 11:33:19,387 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-11-10 11:33:19,387 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-11-10 11:33:19,387 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-11-10 11:33:19,387 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-11-10 11:33:19,387 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-11-10 11:33:19,387 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-11-10 11:33:19,387 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-11-10 11:33:19,387 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-11-10 11:33:19,387 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-11-10 11:33:19,388 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-11-10 11:33:19,388 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-11-10 11:33:19,388 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-11-10 11:33:19,388 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-11-10 11:33:19,388 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-11-10 11:33:19,388 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-11-10 11:33:19,388 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-10 11:33:19,388 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-10 11:33:19,388 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-11-10 11:33:19,389 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-11-10 11:33:19,389 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 11:33:19,389 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 11:33:22,888 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 11:33:22,889 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 11:33:22 BoogieIcfgContainer [2018-11-10 11:33:22,889 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 11:33:22,890 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-10 11:33:22,890 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-10 11:33:22,893 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-10 11:33:22,893 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.11 11:33:16" (1/3) ... [2018-11-10 11:33:22,894 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2300e8e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 11:33:22, skipping insertion in model container [2018-11-10 11:33:22,894 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:33:19" (2/3) ... [2018-11-10 11:33:22,894 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2300e8e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 11:33:22, skipping insertion in model container [2018-11-10 11:33:22,894 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 11:33:22" (3/3) ... [2018-11-10 11:33:22,896 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-10 11:33:22,905 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-10 11:33:22,912 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-10 11:33:22,924 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-10 11:33:22,950 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 11:33:22,950 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-10 11:33:22,950 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-10 11:33:22,950 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-10 11:33:22,950 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 11:33:22,951 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 11:33:22,951 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-10 11:33:22,951 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 11:33:22,951 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-10 11:33:22,970 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states. [2018-11-10 11:33:22,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-10 11:33:22,977 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:22,977 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:22,980 INFO L424 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:22,985 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:22,985 INFO L82 PathProgramCache]: Analyzing trace with hash 273110255, now seen corresponding path program 1 times [2018-11-10 11:33:22,990 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:22,991 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:23,020 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:23,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:23,184 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:23,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:23,210 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:33:23,217 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:33:23,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:33:23,220 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:33:23,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:33:23,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:33:23,231 INFO L87 Difference]: Start difference. First operand 362 states. Second operand 3 states. [2018-11-10 11:33:23,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:23,307 INFO L93 Difference]: Finished difference Result 612 states and 814 transitions. [2018-11-10 11:33:23,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:33:23,308 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-10 11:33:23,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:23,317 INFO L225 Difference]: With dead ends: 612 [2018-11-10 11:33:23,317 INFO L226 Difference]: Without dead ends: 248 [2018-11-10 11:33:23,321 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:33:23,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-11-10 11:33:23,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 248. [2018-11-10 11:33:23,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-11-10 11:33:23,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 314 transitions. [2018-11-10 11:33:23,370 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 314 transitions. Word has length 34 [2018-11-10 11:33:23,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:23,371 INFO L481 AbstractCegarLoop]: Abstraction has 248 states and 314 transitions. [2018-11-10 11:33:23,371 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:33:23,371 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 314 transitions. [2018-11-10 11:33:23,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-10 11:33:23,373 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:23,374 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:23,374 INFO L424 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:23,374 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:23,374 INFO L82 PathProgramCache]: Analyzing trace with hash 1454992326, now seen corresponding path program 1 times [2018-11-10 11:33:23,375 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:23,375 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:23,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:23,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:23,500 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:23,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:23,525 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:33:23,527 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:33:23,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:33:23,529 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:33:23,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:33:23,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:33:23,529 INFO L87 Difference]: Start difference. First operand 248 states and 314 transitions. Second operand 5 states. [2018-11-10 11:33:23,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:23,683 INFO L93 Difference]: Finished difference Result 727 states and 939 transitions. [2018-11-10 11:33:23,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 11:33:23,683 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-11-10 11:33:23,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:23,688 INFO L225 Difference]: With dead ends: 727 [2018-11-10 11:33:23,688 INFO L226 Difference]: Without dead ends: 493 [2018-11-10 11:33:23,690 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:33:23,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493 states. [2018-11-10 11:33:23,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493 to 480. [2018-11-10 11:33:23,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2018-11-10 11:33:23,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 615 transitions. [2018-11-10 11:33:23,731 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 615 transitions. Word has length 47 [2018-11-10 11:33:23,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:23,731 INFO L481 AbstractCegarLoop]: Abstraction has 480 states and 615 transitions. [2018-11-10 11:33:23,731 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:33:23,732 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 615 transitions. [2018-11-10 11:33:23,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 11:33:23,734 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:23,734 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:23,734 INFO L424 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:23,734 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:23,734 INFO L82 PathProgramCache]: Analyzing trace with hash -1690200814, now seen corresponding path program 1 times [2018-11-10 11:33:23,735 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:23,735 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:23,761 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:23,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:23,896 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:23,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:23,927 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:33:23,930 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:33:23,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:33:23,930 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:33:23,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:33:23,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:33:23,931 INFO L87 Difference]: Start difference. First operand 480 states and 615 transitions. Second operand 5 states. [2018-11-10 11:33:24,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:24,043 INFO L93 Difference]: Finished difference Result 962 states and 1247 transitions. [2018-11-10 11:33:24,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:33:24,043 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-11-10 11:33:24,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:24,046 INFO L225 Difference]: With dead ends: 962 [2018-11-10 11:33:24,046 INFO L226 Difference]: Without dead ends: 496 [2018-11-10 11:33:24,048 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:33:24,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-11-10 11:33:24,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 484. [2018-11-10 11:33:24,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-11-10 11:33:24,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 615 transitions. [2018-11-10 11:33:24,076 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 615 transitions. Word has length 48 [2018-11-10 11:33:24,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:24,076 INFO L481 AbstractCegarLoop]: Abstraction has 484 states and 615 transitions. [2018-11-10 11:33:24,076 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:33:24,077 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 615 transitions. [2018-11-10 11:33:24,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-10 11:33:24,078 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:24,078 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:24,079 INFO L424 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:24,079 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:24,079 INFO L82 PathProgramCache]: Analyzing trace with hash 284618944, now seen corresponding path program 1 times [2018-11-10 11:33:24,079 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:24,079 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:24,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:24,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:24,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:24,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:24,220 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:33:24,223 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:33:24,223 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:33:24,223 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:33:24,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:33:24,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:33:24,224 INFO L87 Difference]: Start difference. First operand 484 states and 615 transitions. Second operand 3 states. [2018-11-10 11:33:24,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:24,360 INFO L93 Difference]: Finished difference Result 1146 states and 1460 transitions. [2018-11-10 11:33:24,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:33:24,360 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-10 11:33:24,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:24,363 INFO L225 Difference]: With dead ends: 1146 [2018-11-10 11:33:24,364 INFO L226 Difference]: Without dead ends: 676 [2018-11-10 11:33:24,366 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:33:24,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states. [2018-11-10 11:33:24,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 673. [2018-11-10 11:33:24,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2018-11-10 11:33:24,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 857 transitions. [2018-11-10 11:33:24,404 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 857 transitions. Word has length 45 [2018-11-10 11:33:24,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:24,404 INFO L481 AbstractCegarLoop]: Abstraction has 673 states and 857 transitions. [2018-11-10 11:33:24,405 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:33:24,405 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 857 transitions. [2018-11-10 11:33:24,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-10 11:33:24,406 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:24,406 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:24,406 INFO L424 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:24,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:24,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1747554851, now seen corresponding path program 1 times [2018-11-10 11:33:24,407 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:24,407 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:24,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:24,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:24,531 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:24,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:24,557 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:33:24,560 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:33:24,561 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:33:24,561 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:33:24,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:33:24,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:33:24,562 INFO L87 Difference]: Start difference. First operand 673 states and 857 transitions. Second operand 5 states. [2018-11-10 11:33:24,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:24,673 INFO L93 Difference]: Finished difference Result 1354 states and 1739 transitions. [2018-11-10 11:33:24,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:33:24,674 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-11-10 11:33:24,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:24,678 INFO L225 Difference]: With dead ends: 1354 [2018-11-10 11:33:24,678 INFO L226 Difference]: Without dead ends: 705 [2018-11-10 11:33:24,680 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:33:24,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states. [2018-11-10 11:33:24,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 681. [2018-11-10 11:33:24,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2018-11-10 11:33:24,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 859 transitions. [2018-11-10 11:33:24,713 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 859 transitions. Word has length 49 [2018-11-10 11:33:24,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:24,713 INFO L481 AbstractCegarLoop]: Abstraction has 681 states and 859 transitions. [2018-11-10 11:33:24,713 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:33:24,714 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 859 transitions. [2018-11-10 11:33:24,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-10 11:33:24,715 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:24,715 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:24,715 INFO L424 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:24,715 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:24,716 INFO L82 PathProgramCache]: Analyzing trace with hash -1196674033, now seen corresponding path program 1 times [2018-11-10 11:33:24,716 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:24,716 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:24,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:24,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:24,908 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:24,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:24,945 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:33:24,948 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:33:24,949 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 11:33:24,949 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 11:33:24,949 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 11:33:24,949 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:33:24,950 INFO L87 Difference]: Start difference. First operand 681 states and 859 transitions. Second operand 5 states. [2018-11-10 11:33:25,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:25,067 INFO L93 Difference]: Finished difference Result 1297 states and 1651 transitions. [2018-11-10 11:33:25,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 11:33:25,068 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-10 11:33:25,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:25,071 INFO L225 Difference]: With dead ends: 1297 [2018-11-10 11:33:25,071 INFO L226 Difference]: Without dead ends: 640 [2018-11-10 11:33:25,074 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:33:25,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-11-10 11:33:25,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 622. [2018-11-10 11:33:25,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-11-10 11:33:25,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 777 transitions. [2018-11-10 11:33:25,114 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 777 transitions. Word has length 50 [2018-11-10 11:33:25,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:25,115 INFO L481 AbstractCegarLoop]: Abstraction has 622 states and 777 transitions. [2018-11-10 11:33:25,115 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 11:33:25,115 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 777 transitions. [2018-11-10 11:33:25,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-10 11:33:25,116 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:25,117 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:25,117 INFO L424 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:25,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:25,117 INFO L82 PathProgramCache]: Analyzing trace with hash -922844006, now seen corresponding path program 1 times [2018-11-10 11:33:25,118 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:25,118 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:25,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:25,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:25,305 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:25,388 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-10 11:33:25,388 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:25,642 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-10 11:33:25,645 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 11:33:25,645 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 13 [2018-11-10 11:33:25,646 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-10 11:33:25,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-10 11:33:25,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-11-10 11:33:25,647 INFO L87 Difference]: Start difference. First operand 622 states and 777 transitions. Second operand 13 states. [2018-11-10 11:33:35,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:35,141 INFO L93 Difference]: Finished difference Result 1689 states and 2183 transitions. [2018-11-10 11:33:35,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-10 11:33:35,145 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 62 [2018-11-10 11:33:35,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:35,151 INFO L225 Difference]: With dead ends: 1689 [2018-11-10 11:33:35,151 INFO L226 Difference]: Without dead ends: 1091 [2018-11-10 11:33:35,153 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 112 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=152, Invalid=498, Unknown=0, NotChecked=0, Total=650 [2018-11-10 11:33:35,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1091 states. [2018-11-10 11:33:35,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1091 to 882. [2018-11-10 11:33:35,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 882 states. [2018-11-10 11:33:35,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 882 states to 882 states and 1106 transitions. [2018-11-10 11:33:35,204 INFO L78 Accepts]: Start accepts. Automaton has 882 states and 1106 transitions. Word has length 62 [2018-11-10 11:33:35,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:35,204 INFO L481 AbstractCegarLoop]: Abstraction has 882 states and 1106 transitions. [2018-11-10 11:33:35,205 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-10 11:33:35,205 INFO L276 IsEmpty]: Start isEmpty. Operand 882 states and 1106 transitions. [2018-11-10 11:33:35,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-10 11:33:35,206 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:35,206 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:35,206 INFO L424 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:35,206 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:35,207 INFO L82 PathProgramCache]: Analyzing trace with hash -330411799, now seen corresponding path program 1 times [2018-11-10 11:33:35,207 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:35,207 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:35,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:35,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:35,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:35,389 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:35,389 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:35,542 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:35,545 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:35,545 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:33:35,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:35,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:35,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:35,636 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:35,636 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:35,739 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:35,767 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-10 11:33:35,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-11-10 11:33:35,768 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-10 11:33:35,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-10 11:33:35,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-10 11:33:35,768 INFO L87 Difference]: Start difference. First operand 882 states and 1106 transitions. Second operand 14 states. [2018-11-10 11:33:49,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:33:49,549 INFO L93 Difference]: Finished difference Result 2048 states and 2577 transitions. [2018-11-10 11:33:49,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-10 11:33:49,550 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-11-10 11:33:49,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:33:49,553 INFO L225 Difference]: With dead ends: 2048 [2018-11-10 11:33:49,554 INFO L226 Difference]: Without dead ends: 1190 [2018-11-10 11:33:49,556 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-11-10 11:33:49,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1190 states. [2018-11-10 11:33:49,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1190 to 1121. [2018-11-10 11:33:49,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-11-10 11:33:49,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1418 transitions. [2018-11-10 11:33:49,642 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1418 transitions. Word has length 63 [2018-11-10 11:33:49,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:33:49,643 INFO L481 AbstractCegarLoop]: Abstraction has 1121 states and 1418 transitions. [2018-11-10 11:33:49,643 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-10 11:33:49,643 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1418 transitions. [2018-11-10 11:33:49,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-10 11:33:49,644 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:33:49,644 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:33:49,645 INFO L424 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:33:49,645 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:33:49,645 INFO L82 PathProgramCache]: Analyzing trace with hash -1401051437, now seen corresponding path program 1 times [2018-11-10 11:33:49,646 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:33:49,646 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:33:49,669 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:49,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:49,810 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:49,934 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:49,934 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:50,124 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:50,129 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:33:50,129 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:33:50,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:33:50,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:33:50,222 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:33:50,230 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:50,230 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:33:50,378 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:33:50,410 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-10 11:33:50,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-11-10 11:33:50,411 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-10 11:33:50,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-10 11:33:50,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-10 11:33:50,411 INFO L87 Difference]: Start difference. First operand 1121 states and 1418 transitions. Second operand 14 states. [2018-11-10 11:34:02,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:34:02,016 INFO L93 Difference]: Finished difference Result 2526 states and 3205 transitions. [2018-11-10 11:34:02,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-10 11:34:02,017 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 64 [2018-11-10 11:34:02,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:34:02,020 INFO L225 Difference]: With dead ends: 2526 [2018-11-10 11:34:02,021 INFO L226 Difference]: Without dead ends: 1429 [2018-11-10 11:34:02,023 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 241 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-11-10 11:34:02,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1429 states. [2018-11-10 11:34:02,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1429 to 1121. [2018-11-10 11:34:02,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-11-10 11:34:02,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1418 transitions. [2018-11-10 11:34:02,066 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1418 transitions. Word has length 64 [2018-11-10 11:34:02,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:34:02,066 INFO L481 AbstractCegarLoop]: Abstraction has 1121 states and 1418 transitions. [2018-11-10 11:34:02,066 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-10 11:34:02,066 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1418 transitions. [2018-11-10 11:34:02,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-10 11:34:02,067 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:34:02,067 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:34:02,068 INFO L424 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:34:02,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:34:02,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1807656578, now seen corresponding path program 1 times [2018-11-10 11:34:02,068 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:34:02,068 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:34:02,086 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:02,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:02,188 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:02,263 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:34:02,263 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:34:02,418 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:34:02,420 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:34:02,420 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:34:02,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:02,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:02,513 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:02,518 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:34:02,518 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:34:02,646 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:34:02,666 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-10 11:34:02,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-11-10 11:34:02,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-10 11:34:02,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-10 11:34:02,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-10 11:34:02,668 INFO L87 Difference]: Start difference. First operand 1121 states and 1418 transitions. Second operand 14 states. [2018-11-10 11:34:09,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:34:09,951 INFO L93 Difference]: Finished difference Result 2197 states and 2774 transitions. [2018-11-10 11:34:09,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-10 11:34:09,952 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 65 [2018-11-10 11:34:09,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:34:09,956 INFO L225 Difference]: With dead ends: 2197 [2018-11-10 11:34:09,956 INFO L226 Difference]: Without dead ends: 1100 [2018-11-10 11:34:09,959 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 245 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2018-11-10 11:34:09,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1100 states. [2018-11-10 11:34:09,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1100 to 318. [2018-11-10 11:34:09,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 318 states. [2018-11-10 11:34:09,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 383 transitions. [2018-11-10 11:34:09,994 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 383 transitions. Word has length 65 [2018-11-10 11:34:09,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:34:09,994 INFO L481 AbstractCegarLoop]: Abstraction has 318 states and 383 transitions. [2018-11-10 11:34:09,994 INFO L482 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-10 11:34:09,994 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 383 transitions. [2018-11-10 11:34:09,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 11:34:09,995 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:34:09,995 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:34:09,995 INFO L424 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:34:09,995 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:34:09,996 INFO L82 PathProgramCache]: Analyzing trace with hash -265251566, now seen corresponding path program 1 times [2018-11-10 11:34:09,996 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:34:09,996 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:34:10,014 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:10,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:10,128 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:10,138 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 11:34:10,139 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:34:10,141 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:34:10,141 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:34:10,141 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:34:10,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:34:10,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:34:10,142 INFO L87 Difference]: Start difference. First operand 318 states and 383 transitions. Second operand 3 states. [2018-11-10 11:34:12,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:34:12,258 INFO L93 Difference]: Finished difference Result 689 states and 844 transitions. [2018-11-10 11:34:12,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:34:12,259 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2018-11-10 11:34:12,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:34:12,260 INFO L225 Difference]: With dead ends: 689 [2018-11-10 11:34:12,260 INFO L226 Difference]: Without dead ends: 395 [2018-11-10 11:34:12,261 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:34:12,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states. [2018-11-10 11:34:12,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2018-11-10 11:34:12,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395 states. [2018-11-10 11:34:12,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 479 transitions. [2018-11-10 11:34:12,307 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 479 transitions. Word has length 69 [2018-11-10 11:34:12,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:34:12,307 INFO L481 AbstractCegarLoop]: Abstraction has 395 states and 479 transitions. [2018-11-10 11:34:12,307 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:34:12,307 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 479 transitions. [2018-11-10 11:34:12,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-10 11:34:12,308 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:34:12,309 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:34:12,309 INFO L424 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:34:12,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:34:12,309 INFO L82 PathProgramCache]: Analyzing trace with hash -2005824742, now seen corresponding path program 1 times [2018-11-10 11:34:12,310 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:34:12,310 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:34:12,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:12,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:12,502 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:12,542 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-10 11:34:12,543 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:34:12,546 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:34:12,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 11:34:12,546 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 11:34:12,546 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 11:34:12,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:34:12,547 INFO L87 Difference]: Start difference. First operand 395 states and 479 transitions. Second operand 3 states. [2018-11-10 11:34:14,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:34:14,654 INFO L93 Difference]: Finished difference Result 936 states and 1133 transitions. [2018-11-10 11:34:14,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 11:34:14,655 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2018-11-10 11:34:14,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:34:14,656 INFO L225 Difference]: With dead ends: 936 [2018-11-10 11:34:14,656 INFO L226 Difference]: Without dead ends: 565 [2018-11-10 11:34:14,657 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 11:34:14,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 565 states. [2018-11-10 11:34:14,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 565 to 562. [2018-11-10 11:34:14,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-11-10 11:34:14,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 670 transitions. [2018-11-10 11:34:14,691 INFO L78 Accepts]: Start accepts. Automaton has 562 states and 670 transitions. Word has length 81 [2018-11-10 11:34:14,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:34:14,691 INFO L481 AbstractCegarLoop]: Abstraction has 562 states and 670 transitions. [2018-11-10 11:34:14,691 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 11:34:14,691 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 670 transitions. [2018-11-10 11:34:14,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-10 11:34:14,692 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:34:14,692 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:34:14,692 INFO L424 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:34:14,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:34:14,693 INFO L82 PathProgramCache]: Analyzing trace with hash -251117116, now seen corresponding path program 1 times [2018-11-10 11:34:14,693 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:34:14,693 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:34:14,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:14,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:15,043 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:15,074 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 11:34:15,074 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-10 11:34:15,077 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 11:34:15,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 11:34:15,077 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 11:34:15,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 11:34:15,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 11:34:15,078 INFO L87 Difference]: Start difference. First operand 562 states and 670 transitions. Second operand 4 states. [2018-11-10 11:34:15,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:34:15,159 INFO L93 Difference]: Finished difference Result 1104 states and 1318 transitions. [2018-11-10 11:34:15,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 11:34:15,159 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2018-11-10 11:34:15,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:34:15,161 INFO L225 Difference]: With dead ends: 1104 [2018-11-10 11:34:15,161 INFO L226 Difference]: Without dead ends: 563 [2018-11-10 11:34:15,162 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-10 11:34:15,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-11-10 11:34:15,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 563. [2018-11-10 11:34:15,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 563 states. [2018-11-10 11:34:15,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 671 transitions. [2018-11-10 11:34:15,212 INFO L78 Accepts]: Start accepts. Automaton has 563 states and 671 transitions. Word has length 82 [2018-11-10 11:34:15,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:34:15,212 INFO L481 AbstractCegarLoop]: Abstraction has 563 states and 671 transitions. [2018-11-10 11:34:15,213 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 11:34:15,213 INFO L276 IsEmpty]: Start isEmpty. Operand 563 states and 671 transitions. [2018-11-10 11:34:15,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-10 11:34:15,214 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:34:15,214 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:34:15,214 INFO L424 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:34:15,214 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:34:15,214 INFO L82 PathProgramCache]: Analyzing trace with hash 913353771, now seen corresponding path program 1 times [2018-11-10 11:34:15,214 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:34:15,215 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:34:15,237 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:15,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:15,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:15,585 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 11:34:15,585 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:34:15,661 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:34:15,663 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 11:34:15,663 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 11:34:15,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 11:34:15,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 11:34:15,758 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 11:34:15,762 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 11:34:15,762 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-10 11:34:15,832 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-10 11:34:15,857 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-10 11:34:15,857 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5] total 8 [2018-11-10 11:34:15,857 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-10 11:34:15,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-10 11:34:15,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 11:34:15,858 INFO L87 Difference]: Start difference. First operand 563 states and 671 transitions. Second operand 8 states. [2018-11-10 11:34:15,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 11:34:15,991 INFO L93 Difference]: Finished difference Result 1109 states and 1325 transitions. [2018-11-10 11:34:15,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-10 11:34:15,991 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 83 [2018-11-10 11:34:15,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 11:34:15,992 INFO L225 Difference]: With dead ends: 1109 [2018-11-10 11:34:15,992 INFO L226 Difference]: Without dead ends: 566 [2018-11-10 11:34:15,993 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-10 11:34:15,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 566 states. [2018-11-10 11:34:16,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 566 to 566. [2018-11-10 11:34:16,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 566 states. [2018-11-10 11:34:16,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 566 states to 566 states and 674 transitions. [2018-11-10 11:34:16,048 INFO L78 Accepts]: Start accepts. Automaton has 566 states and 674 transitions. Word has length 83 [2018-11-10 11:34:16,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 11:34:16,049 INFO L481 AbstractCegarLoop]: Abstraction has 566 states and 674 transitions. [2018-11-10 11:34:16,049 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-10 11:34:16,049 INFO L276 IsEmpty]: Start isEmpty. Operand 566 states and 674 transitions. [2018-11-10 11:34:16,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-10 11:34:16,050 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 11:34:16,050 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 11:34:16,050 INFO L424 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 11:34:16,050 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 11:34:16,050 INFO L82 PathProgramCache]: Analyzing trace with hash 1023615876, now seen corresponding path program 2 times [2018-11-10 11:34:16,051 INFO L225 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-10 11:34:16,051 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-10 11:34:16,075 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-10 11:34:17,881 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 11:34:17,881 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-11-10 11:34:19,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 11:34:19,472 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-10 11:34:19,496 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,498 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,499 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,500 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,503 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,503 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,506 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,506 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,507 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,507 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,511 WARN L387 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-10 11:34:19,512 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,513 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,513 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,513 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,514 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,514 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,515 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,515 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,515 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,515 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,516 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,518 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,518 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,518 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,519 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,519 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,519 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,519 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,520 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,520 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,520 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,521 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,521 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,521 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,523 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,523 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,523 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,523 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,524 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,524 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,524 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,524 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,525 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,525 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,525 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,525 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,526 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,526 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,526 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,526 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,527 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,527 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,527 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,527 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,528 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,528 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,528 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,529 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,529 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,529 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,530 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,530 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,530 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,530 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,531 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,531 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,531 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,531 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,531 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,531 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,532 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,532 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,532 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,532 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,535 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,535 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,535 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,535 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,536 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,536 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,568 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,569 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,571 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,571 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,574 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,575 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,576 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,577 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,578 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,579 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,581 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,581 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,583 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,583 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,585 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,586 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,587 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,587 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,589 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,589 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,591 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,591 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,592 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-11-10 11:34:19,593 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,593 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,594 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,594 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,596 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,596 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,597 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,597 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,598 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,598 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,599 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,599 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,602 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,602 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,603 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,603 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,603 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,603 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,604 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,604 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,605 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,605 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,606 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,606 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,607 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,607 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,607 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,608 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,608 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,608 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,609 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,609 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,610 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,610 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,611 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,612 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,613 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,614 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,614 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,614 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,615 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,615 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,615 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,616 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,616 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,616 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,617 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,617 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,618 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,618 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,619 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,619 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,619 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,620 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,620 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,620 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,621 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,621 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,621 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,622 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,622 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,623 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,623 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,624 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,624 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,625 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,625 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,644 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.11 11:34:19 BoogieIcfgContainer [2018-11-10 11:34:19,644 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-10 11:34:19,645 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 11:34:19,645 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 11:34:19,646 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 11:34:19,646 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 11:33:22" (3/4) ... [2018-11-10 11:34:19,648 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-10 11:34:19,652 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,652 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,653 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,653 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,654 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,654 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,655 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,655 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,655 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,655 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,657 WARN L387 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-11-10 11:34:19,657 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,658 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,658 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,658 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,658 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,659 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,659 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,659 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,659 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,660 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,660 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,660 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,660 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,661 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,661 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,661 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,662 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,662 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,662 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,663 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,663 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,663 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,663 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,663 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,667 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,667 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,667 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,667 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,668 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,668 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,668 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,668 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,669 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,669 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,669 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,669 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,670 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,670 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,670 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,670 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,671 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,671 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,671 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,671 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,671 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,672 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,672 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,672 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,672 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,673 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,673 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,673 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,673 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,673 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,674 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,674 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,674 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,674 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,675 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,675 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,675 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,675 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,676 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,676 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,676 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,676 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,677 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,677 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,677 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,677 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled [2018-11-10 11:34:19,697 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,697 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,698 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,698 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,699 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,699 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,700 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,700 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,701 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,701 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,701 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,701 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,702 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,702 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,703 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,703 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,703 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,703 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,704 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,704 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,705 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-11-10 11:34:19,705 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,705 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,706 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,706 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,706 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,706 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,707 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,707 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,708 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,708 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,708 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,708 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,709 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,709 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,710 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,710 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,710 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,710 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,711 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,711 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,712 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,712 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,712 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,712 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,713 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,713 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,714 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,714 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,714 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,714 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,715 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,715 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,716 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,716 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,716 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,716 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,717 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,717 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,718 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,718 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,718 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,719 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,719 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,719 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,719 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,720 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,720 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,720 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,721 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,721 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,722 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,722 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,722 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,722 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,723 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,723 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,723 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,723 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,724 WARN L1239 BoogieBacktranslator]: unknown boogie variable dev_get_drvdata_#res [2018-11-10 11:34:19,724 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,724 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,725 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,725 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,725 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,726 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,726 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,726 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,727 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,727 WARN L1239 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-10 11:34:19,782 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_7139b5ec-03ec-4e02-99fc-0658d9d5a155/bin-2019/utaipan/witness.graphml [2018-11-10 11:34:19,783 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 11:34:19,783 INFO L168 Benchmark]: Toolchain (without parser) took 62835.14 ms. Allocated memory was 1.0 GB in the beginning and 1.7 GB in the end (delta: 633.9 MB). Free memory was 944.4 MB in the beginning and 1.1 GB in the end (delta: -139.1 MB). Peak memory consumption was 494.8 MB. Max. memory is 11.5 GB. [2018-11-10 11:34:19,784 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 11:34:19,784 INFO L168 Benchmark]: CACSL2BoogieTranslator took 2222.40 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 236.5 MB). Free memory was 944.4 MB in the beginning and 870.0 MB in the end (delta: 74.3 MB). Peak memory consumption was 442.5 MB. Max. memory is 11.5 GB. [2018-11-10 11:34:19,785 INFO L168 Benchmark]: Boogie Procedure Inliner took 81.02 ms. Allocated memory is still 1.3 GB. Free memory was 870.0 MB in the beginning and 857.5 MB in the end (delta: 12.5 MB). Peak memory consumption was 12.5 MB. Max. memory is 11.5 GB. [2018-11-10 11:34:19,785 INFO L168 Benchmark]: Boogie Preprocessor took 73.70 ms. Allocated memory is still 1.3 GB. Free memory is still 857.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 11:34:19,785 INFO L168 Benchmark]: RCFGBuilder took 3561.92 ms. Allocated memory was 1.3 GB in the beginning and 1.4 GB in the end (delta: 162.0 MB). Free memory was 857.5 MB in the beginning and 1.2 GB in the end (delta: -362.2 MB). Peak memory consumption was 117.8 MB. Max. memory is 11.5 GB. [2018-11-10 11:34:19,785 INFO L168 Benchmark]: TraceAbstraction took 56754.68 ms. Allocated memory was 1.4 GB in the beginning and 1.7 GB in the end (delta: 235.4 MB). Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 86.1 MB). Peak memory consumption was 321.5 MB. Max. memory is 11.5 GB. [2018-11-10 11:34:19,786 INFO L168 Benchmark]: Witness Printer took 138.01 ms. Allocated memory is still 1.7 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.1 MB). Peak memory consumption was 50.1 MB. Max. memory is 11.5 GB. [2018-11-10 11:34:19,787 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 2222.40 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 236.5 MB). Free memory was 944.4 MB in the beginning and 870.0 MB in the end (delta: 74.3 MB). Peak memory consumption was 442.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 81.02 ms. Allocated memory is still 1.3 GB. Free memory was 870.0 MB in the beginning and 857.5 MB in the end (delta: 12.5 MB). Peak memory consumption was 12.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 73.70 ms. Allocated memory is still 1.3 GB. Free memory is still 857.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 3561.92 ms. Allocated memory was 1.3 GB in the beginning and 1.4 GB in the end (delta: 162.0 MB). Free memory was 857.5 MB in the beginning and 1.2 GB in the end (delta: -362.2 MB). Peak memory consumption was 117.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 56754.68 ms. Allocated memory was 1.4 GB in the beginning and 1.7 GB in the end (delta: 235.4 MB). Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 86.1 MB). Peak memory consumption was 321.5 MB. Max. memory is 11.5 GB. * Witness Printer took 138.01 ms. Allocated memory is still 1.7 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.1 MB). Peak memory consumption was 50.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.alloc_#res : $Pointer$ not handled * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation unknown boogie variable dev_get_drvdata_#res - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 1684]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L1905] CALL "write failed:retry count exceeded.\n" [L1905] RET "write failed:retry count exceeded.\n" [L2072] CALL "name\t\t: %s\n" [L2072] RET "name\t\t: %s\n" [L2150] CALL "Unable to allocate resources for device.\n" [L2150] RET "Unable to allocate resources for device.\n" [L2159] CALL "Unable to request mem region for device.\n" [L2159] RET "Unable to request mem region for device.\n" [L2175] CALL "Unable to grab IOs for device.\n" [L2175] RET "Unable to grab IOs for device.\n" [L2189] CALL "info->tegra_rtc_lock" [L2189] RET "info->tegra_rtc_lock" [L2211] CALL "Unable to register device (err=%d).\n" [L2211] RET "Unable to register device (err=%d).\n" [L2218] CALL "rtc alarm" [L2218] RET "rtc alarm" [L2220] CALL "Unable to request interrupt for device (err=%d).\n" [L2220] RET "Unable to request interrupt for device (err=%d).\n" [L2226] CALL "Tegra internal Real Time Clock\n" [L2226] RET "Tegra internal Real Time Clock\n" [L2323] CALL, EXPR "tegra_rtc" [L2323] RET, EXPR "tegra_rtc" [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] CALL static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2123-L2125] RET static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] CALL static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] CALL pm_message_t ldvarg2 ; [L2522] RET pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2533] FCALL ldv_initialize() [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] CALL, EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] EXPR, FCALL platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] RET return (tmp); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] EXPR tegra_rtc_init() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2569] CALL ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] RET tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] ldv_initialize_platform_driver_2() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2766] FCALL ldv_probe_2() [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={1195909131:129}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] CALL, EXPR info->rtc_base [L1867] RET, EXPR info->rtc_base [L1867] CALL, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] RET, EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] RET return (__v & 1U); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] EXPR tegra_rtc_check_busy(info) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={1195909131:129}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] RET return (0); VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={1195909131:129}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev_get_drvdata_#res={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2017] CALL ldv_spin_lock_check() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL ["info->tegra_rtc_lock"={1162354703:0}, "name\t\t: %s\n"={1678550531:0}, "rtc alarm"={1162355211:0}, "Tegra internal Real Time Clock\n"={609005060:0}, "tegra_rtc"={609005056:0}, "Unable to allocate resources for device.\n"={1632184838:0}, "Unable to grab IOs for device.\n"={-513103864:0}, "Unable to register device (err=%d).\n"={1162354699:0}, "Unable to request interrupt for device (err=%d).\n"={537964034:0}, "Unable to request mem region for device.\n"={609005058:0}, "write failed:retry count exceeded.\n"={1682745879:0}, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1195909131:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={1162354701:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 42 procedures, 364 locations, 1 error locations. UNSAFE Result, 56.6s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 47.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4554 SDtfs, 4949 SDslu, 12011 SDs, 0 SdLazy, 4949 SolverSat, 642 SolverUnsat, 19 SolverUnknown, 0 SolverNotchecked, 44.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1771 GetRequests, 1635 SyntacticMatches, 9 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1121occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 14 MinimizatonAttempts, 1441 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.6s SsaConstructionTime, 3.2s SatisfiabilityAnalysisTime, 2.2s InterpolantComputationTime, 1203 NumberOfCodeBlocks, 1203 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 1702 ConstructedInterpolants, 0 QuantifiedInterpolants, 231860 SizeOfPredicates, 60 NumberOfNonLiveVariables, 8478 ConjunctsInSsa, 138 ConjunctsInUnsatCore, 27 InterpolantComputations, 10 PerfectInterpolantSequences, 147/227 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...