./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -s /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9af739900018493f70ca6be86d814e194413d937 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 16:09:28,918 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 16:09:28,920 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 16:09:28,927 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 16:09:28,927 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 16:09:28,927 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 16:09:28,928 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 16:09:28,929 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 16:09:28,930 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 16:09:28,931 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 16:09:28,931 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 16:09:28,932 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 16:09:28,932 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 16:09:28,933 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 16:09:28,934 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 16:09:28,934 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 16:09:28,935 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 16:09:28,936 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 16:09:28,937 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 16:09:28,939 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 16:09:28,939 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 16:09:28,940 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 16:09:28,942 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 16:09:28,942 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 16:09:28,942 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 16:09:28,943 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 16:09:28,943 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 16:09:28,944 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 16:09:28,945 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 16:09:28,945 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 16:09:28,945 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 16:09:28,946 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 16:09:28,946 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 16:09:28,946 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 16:09:28,947 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 16:09:28,947 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 16:09:28,948 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf [2018-11-18 16:09:28,957 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 16:09:28,957 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 16:09:28,958 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 16:09:28,958 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-18 16:09:28,958 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-18 16:09:28,958 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-18 16:09:28,958 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-18 16:09:28,958 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-18 16:09:28,959 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-18 16:09:28,959 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-18 16:09:28,959 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-18 16:09:28,959 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-18 16:09:28,959 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-18 16:09:28,960 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 16:09:28,960 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 16:09:28,960 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 16:09:28,960 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 16:09:28,960 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-18 16:09:28,961 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 16:09:28,962 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 16:09:28,962 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 16:09:28,962 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 16:09:28,962 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 16:09:28,962 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 16:09:28,962 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 16:09:28,963 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 16:09:28,963 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 16:09:28,963 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 16:09:28,963 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-18 16:09:28,963 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 16:09:28,963 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 16:09:28,963 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9af739900018493f70ca6be86d814e194413d937 [2018-11-18 16:09:28,986 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 16:09:28,993 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 16:09:28,995 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 16:09:28,996 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 16:09:28,996 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 16:09:28,996 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-11-18 16:09:29,033 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/data/52f6d4b0c/cb51cf331b494512ac2b846a61a6b2ea/FLAGaaea77c7d [2018-11-18 16:09:29,429 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 16:09:29,429 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-11-18 16:09:29,433 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/data/52f6d4b0c/cb51cf331b494512ac2b846a61a6b2ea/FLAGaaea77c7d [2018-11-18 16:09:29,441 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/data/52f6d4b0c/cb51cf331b494512ac2b846a61a6b2ea [2018-11-18 16:09:29,443 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 16:09:29,444 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 16:09:29,444 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 16:09:29,444 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 16:09:29,446 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 16:09:29,447 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,449 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44c038ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29, skipping insertion in model container [2018-11-18 16:09:29,449 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,457 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 16:09:29,470 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 16:09:29,570 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 16:09:29,575 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 16:09:29,585 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 16:09:29,594 INFO L195 MainTranslator]: Completed translation [2018-11-18 16:09:29,594 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29 WrapperNode [2018-11-18 16:09:29,594 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 16:09:29,595 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 16:09:29,595 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 16:09:29,595 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 16:09:29,602 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,609 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,615 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 16:09:29,615 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 16:09:29,615 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 16:09:29,615 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 16:09:29,621 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,621 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,622 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,623 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,628 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,668 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,669 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... [2018-11-18 16:09:29,670 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 16:09:29,671 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 16:09:29,671 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 16:09:29,671 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 16:09:29,672 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 16:09:29,720 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-18 16:09:29,721 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 16:09:29,721 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 16:09:29,721 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 16:09:29,721 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-11-18 16:09:29,721 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-11-18 16:09:29,721 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 16:09:29,721 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 16:09:29,721 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-18 16:09:29,722 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 16:09:29,722 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 16:09:29,722 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 16:09:29,883 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 16:09:29,883 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:09:29 BoogieIcfgContainer [2018-11-18 16:09:29,883 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 16:09:29,883 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 16:09:29,884 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 16:09:29,886 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 16:09:29,886 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 04:09:29" (1/3) ... [2018-11-18 16:09:29,887 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a821329 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 04:09:29, skipping insertion in model container [2018-11-18 16:09:29,887 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:09:29" (2/3) ... [2018-11-18 16:09:29,887 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a821329 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 04:09:29, skipping insertion in model container [2018-11-18 16:09:29,888 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:09:29" (3/3) ... [2018-11-18 16:09:29,889 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-11-18 16:09:29,897 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 16:09:29,904 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-11-18 16:09:29,918 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-11-18 16:09:29,943 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 16:09:29,944 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-18 16:09:29,944 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 16:09:29,944 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 16:09:29,944 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 16:09:29,944 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 16:09:29,944 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 16:09:29,944 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 16:09:29,958 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states. [2018-11-18 16:09:29,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-18 16:09:29,966 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:29,966 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:29,968 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:29,971 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:29,971 INFO L82 PathProgramCache]: Analyzing trace with hash 1597032710, now seen corresponding path program 1 times [2018-11-18 16:09:29,973 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,011 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,011 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:30,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:30,060 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:09:30,061 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:30,063 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 16:09:30,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 16:09:30,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 16:09:30,073 INFO L87 Difference]: Start difference. First operand 43 states. Second operand 2 states. [2018-11-18 16:09:30,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:30,083 INFO L93 Difference]: Finished difference Result 43 states and 46 transitions. [2018-11-18 16:09:30,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 16:09:30,084 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 11 [2018-11-18 16:09:30,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:30,091 INFO L225 Difference]: With dead ends: 43 [2018-11-18 16:09:30,091 INFO L226 Difference]: Without dead ends: 40 [2018-11-18 16:09:30,093 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 16:09:30,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-11-18 16:09:30,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-11-18 16:09:30,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-11-18 16:09:30,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 43 transitions. [2018-11-18 16:09:30,118 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 43 transitions. Word has length 11 [2018-11-18 16:09:30,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:30,119 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 43 transitions. [2018-11-18 16:09:30,119 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 16:09:30,119 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 43 transitions. [2018-11-18 16:09:30,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-18 16:09:30,119 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:30,120 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:30,120 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:30,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:30,120 INFO L82 PathProgramCache]: Analyzing trace with hash 1820883224, now seen corresponding path program 1 times [2018-11-18 16:09:30,120 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,122 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:30,174 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:30,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:09:30,174 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:30,175 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:09:30,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:09:30,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:09:30,176 INFO L87 Difference]: Start difference. First operand 40 states and 43 transitions. Second operand 3 states. [2018-11-18 16:09:30,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:30,234 INFO L93 Difference]: Finished difference Result 59 states and 63 transitions. [2018-11-18 16:09:30,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:09:30,234 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-18 16:09:30,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:30,236 INFO L225 Difference]: With dead ends: 59 [2018-11-18 16:09:30,236 INFO L226 Difference]: Without dead ends: 59 [2018-11-18 16:09:30,237 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:09:30,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-11-18 16:09:30,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 44. [2018-11-18 16:09:30,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-18 16:09:30,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 47 transitions. [2018-11-18 16:09:30,242 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 47 transitions. Word has length 12 [2018-11-18 16:09:30,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:30,243 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 47 transitions. [2018-11-18 16:09:30,243 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:09:30,243 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 47 transitions. [2018-11-18 16:09:30,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-18 16:09:30,243 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:30,243 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:30,243 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:30,244 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:30,244 INFO L82 PathProgramCache]: Analyzing trace with hash 697121729, now seen corresponding path program 1 times [2018-11-18 16:09:30,244 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,245 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:30,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:30,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:09:30,324 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:30,324 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 16:09:30,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 16:09:30,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:09:30,325 INFO L87 Difference]: Start difference. First operand 44 states and 47 transitions. Second operand 6 states. [2018-11-18 16:09:30,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:30,430 INFO L93 Difference]: Finished difference Result 91 states and 96 transitions. [2018-11-18 16:09:30,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:09:30,431 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 13 [2018-11-18 16:09:30,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:30,432 INFO L225 Difference]: With dead ends: 91 [2018-11-18 16:09:30,432 INFO L226 Difference]: Without dead ends: 91 [2018-11-18 16:09:30,433 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 16:09:30,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-11-18 16:09:30,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 61. [2018-11-18 16:09:30,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-11-18 16:09:30,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 69 transitions. [2018-11-18 16:09:30,439 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 69 transitions. Word has length 13 [2018-11-18 16:09:30,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:30,440 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 69 transitions. [2018-11-18 16:09:30,440 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 16:09:30,440 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 69 transitions. [2018-11-18 16:09:30,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 16:09:30,440 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:30,440 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:30,440 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:30,440 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:30,440 INFO L82 PathProgramCache]: Analyzing trace with hash 135937166, now seen corresponding path program 1 times [2018-11-18 16:09:30,441 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,441 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,441 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:30,563 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:30,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 16:09:30,563 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:30,563 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 16:09:30,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 16:09:30,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-18 16:09:30,564 INFO L87 Difference]: Start difference. First operand 61 states and 69 transitions. Second operand 7 states. [2018-11-18 16:09:30,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:30,748 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2018-11-18 16:09:30,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 16:09:30,749 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 14 [2018-11-18 16:09:30,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:30,749 INFO L225 Difference]: With dead ends: 69 [2018-11-18 16:09:30,749 INFO L226 Difference]: Without dead ends: 69 [2018-11-18 16:09:30,750 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-18 16:09:30,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-11-18 16:09:30,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 61. [2018-11-18 16:09:30,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-11-18 16:09:30,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 68 transitions. [2018-11-18 16:09:30,754 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 68 transitions. Word has length 14 [2018-11-18 16:09:30,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:30,755 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 68 transitions. [2018-11-18 16:09:30,755 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 16:09:30,755 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 68 transitions. [2018-11-18 16:09:30,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 16:09:30,755 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:30,755 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:30,756 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:30,756 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:30,756 INFO L82 PathProgramCache]: Analyzing trace with hash 135937165, now seen corresponding path program 1 times [2018-11-18 16:09:30,756 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,757 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:30,789 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:30,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 16:09:30,789 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:30,789 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 16:09:30,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:09:30,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:09:30,790 INFO L87 Difference]: Start difference. First operand 61 states and 68 transitions. Second operand 5 states. [2018-11-18 16:09:30,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:30,826 INFO L93 Difference]: Finished difference Result 60 states and 66 transitions. [2018-11-18 16:09:30,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:09:30,827 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-11-18 16:09:30,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:30,827 INFO L225 Difference]: With dead ends: 60 [2018-11-18 16:09:30,827 INFO L226 Difference]: Without dead ends: 60 [2018-11-18 16:09:30,828 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:09:30,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-11-18 16:09:30,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-11-18 16:09:30,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-11-18 16:09:30,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 66 transitions. [2018-11-18 16:09:30,832 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 66 transitions. Word has length 14 [2018-11-18 16:09:30,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:30,832 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 66 transitions. [2018-11-18 16:09:30,832 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 16:09:30,832 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 66 transitions. [2018-11-18 16:09:30,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-18 16:09:30,832 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:30,833 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:30,833 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:30,833 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:30,833 INFO L82 PathProgramCache]: Analyzing trace with hash 1254753657, now seen corresponding path program 1 times [2018-11-18 16:09:30,833 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,834 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,923 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:30,923 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:30,923 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:30,924 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 20 with the following transitions: [2018-11-18 16:09:30,925 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [11], [12], [13], [14], [17], [19], [28], [32], [37], [76], [77], [78], [80] [2018-11-18 16:09:30,945 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:09:30,946 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:09:31,065 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:09:31,066 INFO L272 AbstractInterpreter]: Visited 17 different actions 31 times. Merged at 6 different actions 12 times. Never widened. Performed 152 root evaluator evaluations with a maximum evaluation depth of 3. Performed 152 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 20 variables. [2018-11-18 16:09:31,077 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:31,078 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:09:31,078 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:31,079 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:31,086 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:31,086 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:31,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,103 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:31,124 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:31,124 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:31,153 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:31,168 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:31,168 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3, 3] total 11 [2018-11-18 16:09:31,168 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:31,169 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 16:09:31,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 16:09:31,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-11-18 16:09:31,169 INFO L87 Difference]: Start difference. First operand 60 states and 66 transitions. Second operand 10 states. [2018-11-18 16:09:31,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:31,338 INFO L93 Difference]: Finished difference Result 100 states and 109 transitions. [2018-11-18 16:09:31,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 16:09:31,342 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 19 [2018-11-18 16:09:31,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:31,342 INFO L225 Difference]: With dead ends: 100 [2018-11-18 16:09:31,342 INFO L226 Difference]: Without dead ends: 100 [2018-11-18 16:09:31,343 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=70, Invalid=170, Unknown=0, NotChecked=0, Total=240 [2018-11-18 16:09:31,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-11-18 16:09:31,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 71. [2018-11-18 16:09:31,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-18 16:09:31,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 78 transitions. [2018-11-18 16:09:31,348 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 78 transitions. Word has length 19 [2018-11-18 16:09:31,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:31,348 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 78 transitions. [2018-11-18 16:09:31,348 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 16:09:31,348 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 78 transitions. [2018-11-18 16:09:31,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-18 16:09:31,349 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:31,349 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:31,349 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:31,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:31,349 INFO L82 PathProgramCache]: Analyzing trace with hash 539365409, now seen corresponding path program 1 times [2018-11-18 16:09:31,350 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:31,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:31,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,351 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:31,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,425 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:31,425 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:31,425 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:31,425 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 24 with the following transitions: [2018-11-18 16:09:31,425 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [37], [39], [41], [76], [77], [78], [80], [81] [2018-11-18 16:09:31,427 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:09:31,427 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:09:31,489 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:09:31,489 INFO L272 AbstractInterpreter]: Visited 22 different actions 55 times. Merged at 12 different actions 30 times. Never widened. Performed 256 root evaluator evaluations with a maximum evaluation depth of 3. Performed 256 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 21 variables. [2018-11-18 16:09:31,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:31,490 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:09:31,490 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:31,491 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:31,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:31,497 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:31,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:31,539 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:31,539 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:31,621 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:09:31,645 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:31,645 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2018-11-18 16:09:31,645 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:31,645 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 16:09:31,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 16:09:31,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-11-18 16:09:31,645 INFO L87 Difference]: Start difference. First operand 71 states and 78 transitions. Second operand 10 states. [2018-11-18 16:09:31,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:31,767 INFO L93 Difference]: Finished difference Result 104 states and 109 transitions. [2018-11-18 16:09:31,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 16:09:31,767 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 23 [2018-11-18 16:09:31,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:31,768 INFO L225 Difference]: With dead ends: 104 [2018-11-18 16:09:31,768 INFO L226 Difference]: Without dead ends: 95 [2018-11-18 16:09:31,769 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 38 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=171, Unknown=0, NotChecked=0, Total=240 [2018-11-18 16:09:31,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-11-18 16:09:31,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 77. [2018-11-18 16:09:31,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-18 16:09:31,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-11-18 16:09:31,773 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 23 [2018-11-18 16:09:31,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:31,773 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-11-18 16:09:31,773 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 16:09:31,773 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-11-18 16:09:31,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-18 16:09:31,774 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:31,774 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:31,774 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:31,774 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:31,775 INFO L82 PathProgramCache]: Analyzing trace with hash 2065437657, now seen corresponding path program 2 times [2018-11-18 16:09:31,775 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:31,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,775 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:31,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,776 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:31,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,806 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:31,807 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:31,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:09:31,807 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:31,807 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:09:31,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:09:31,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:09:31,807 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 3 states. [2018-11-18 16:09:31,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:31,816 INFO L93 Difference]: Finished difference Result 75 states and 80 transitions. [2018-11-18 16:09:31,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:09:31,816 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2018-11-18 16:09:31,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:31,817 INFO L225 Difference]: With dead ends: 75 [2018-11-18 16:09:31,817 INFO L226 Difference]: Without dead ends: 75 [2018-11-18 16:09:31,817 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:09:31,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-11-18 16:09:31,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2018-11-18 16:09:31,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-11-18 16:09:31,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 80 transitions. [2018-11-18 16:09:31,820 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 80 transitions. Word has length 29 [2018-11-18 16:09:31,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:31,821 INFO L480 AbstractCegarLoop]: Abstraction has 75 states and 80 transitions. [2018-11-18 16:09:31,821 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:09:31,821 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 80 transitions. [2018-11-18 16:09:31,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-18 16:09:31,821 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:31,821 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:31,822 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:31,822 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:31,822 INFO L82 PathProgramCache]: Analyzing trace with hash 2065437658, now seen corresponding path program 1 times [2018-11-18 16:09:31,822 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:31,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,823 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:31,823 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,823 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:31,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,851 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:31,851 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:31,851 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:09:31,851 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:31,852 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:09:31,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:09:31,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:09:31,852 INFO L87 Difference]: Start difference. First operand 75 states and 80 transitions. Second operand 3 states. [2018-11-18 16:09:31,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:31,867 INFO L93 Difference]: Finished difference Result 79 states and 84 transitions. [2018-11-18 16:09:31,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:09:31,867 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2018-11-18 16:09:31,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:31,868 INFO L225 Difference]: With dead ends: 79 [2018-11-18 16:09:31,868 INFO L226 Difference]: Without dead ends: 79 [2018-11-18 16:09:31,868 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:09:31,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-11-18 16:09:31,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 77. [2018-11-18 16:09:31,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-18 16:09:31,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-11-18 16:09:31,871 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 29 [2018-11-18 16:09:31,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:31,871 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-11-18 16:09:31,871 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:09:31,871 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-11-18 16:09:31,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-18 16:09:31,872 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:31,872 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:31,872 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:31,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:31,872 INFO L82 PathProgramCache]: Analyzing trace with hash -989786460, now seen corresponding path program 1 times [2018-11-18 16:09:31,872 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:31,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:31,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:31,873 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:31,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,914 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:31,914 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:31,914 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:31,914 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 38 with the following transitions: [2018-11-18 16:09:31,914 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [35], [37], [39], [40], [43], [45], [49], [53], [58], [61], [76], [77], [78], [80], [81] [2018-11-18 16:09:31,916 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:09:31,916 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:09:32,076 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:09:32,076 INFO L272 AbstractInterpreter]: Visited 29 different actions 193 times. Merged at 17 different actions 106 times. Never widened. Performed 916 root evaluator evaluations with a maximum evaluation depth of 4. Performed 916 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 15 fixpoints after 6 different actions. Largest state had 21 variables. [2018-11-18 16:09:32,094 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:32,094 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:09:32,094 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:32,094 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:32,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:32,103 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:32,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:32,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:32,129 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:32,129 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:32,158 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:32,174 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:32,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2018-11-18 16:09:32,174 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:32,174 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 16:09:32,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:09:32,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-18 16:09:32,175 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 5 states. [2018-11-18 16:09:32,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:32,208 INFO L93 Difference]: Finished difference Result 103 states and 109 transitions. [2018-11-18 16:09:32,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 16:09:32,209 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 37 [2018-11-18 16:09:32,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:32,210 INFO L225 Difference]: With dead ends: 103 [2018-11-18 16:09:32,210 INFO L226 Difference]: Without dead ends: 103 [2018-11-18 16:09:32,210 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-18 16:09:32,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-11-18 16:09:32,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 86. [2018-11-18 16:09:32,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-11-18 16:09:32,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 93 transitions. [2018-11-18 16:09:32,214 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 93 transitions. Word has length 37 [2018-11-18 16:09:32,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:32,214 INFO L480 AbstractCegarLoop]: Abstraction has 86 states and 93 transitions. [2018-11-18 16:09:32,214 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 16:09:32,214 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 93 transitions. [2018-11-18 16:09:32,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-18 16:09:32,215 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:32,215 INFO L375 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:32,215 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:32,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:32,215 INFO L82 PathProgramCache]: Analyzing trace with hash -982129233, now seen corresponding path program 1 times [2018-11-18 16:09:32,216 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:32,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:32,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:32,216 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:32,216 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:32,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:32,287 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 39 proven. 13 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 16:09:32,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:32,287 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:32,287 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 55 with the following transitions: [2018-11-18 16:09:32,287 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [37], [39], [40], [42], [43], [45], [76], [77], [78], [80], [81] [2018-11-18 16:09:32,288 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:09:32,288 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:09:32,371 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:09:32,371 INFO L272 AbstractInterpreter]: Visited 25 different actions 159 times. Merged at 17 different actions 92 times. Never widened. Performed 754 root evaluator evaluations with a maximum evaluation depth of 4. Performed 754 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 11 fixpoints after 4 different actions. Largest state had 21 variables. [2018-11-18 16:09:32,386 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:32,386 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:09:32,386 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:32,386 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:32,396 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:32,396 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:32,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:32,415 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:32,479 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 16:09:32,479 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:32,551 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 16:09:32,566 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:32,566 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2018-11-18 16:09:32,566 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:32,566 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 16:09:32,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 16:09:32,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=149, Unknown=0, NotChecked=0, Total=210 [2018-11-18 16:09:32,567 INFO L87 Difference]: Start difference. First operand 86 states and 93 transitions. Second operand 12 states. [2018-11-18 16:09:32,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:32,695 INFO L93 Difference]: Finished difference Result 108 states and 113 transitions. [2018-11-18 16:09:32,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 16:09:32,696 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 54 [2018-11-18 16:09:32,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:32,697 INFO L225 Difference]: With dead ends: 108 [2018-11-18 16:09:32,697 INFO L226 Difference]: Without dead ends: 105 [2018-11-18 16:09:32,697 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 98 SyntacticMatches, 4 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=129, Invalid=291, Unknown=0, NotChecked=0, Total=420 [2018-11-18 16:09:32,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-11-18 16:09:32,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 86. [2018-11-18 16:09:32,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-11-18 16:09:32,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 92 transitions. [2018-11-18 16:09:32,701 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 92 transitions. Word has length 54 [2018-11-18 16:09:32,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:32,701 INFO L480 AbstractCegarLoop]: Abstraction has 86 states and 92 transitions. [2018-11-18 16:09:32,701 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 16:09:32,701 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 92 transitions. [2018-11-18 16:09:32,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-18 16:09:32,702 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:32,702 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 6, 5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:32,703 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:32,703 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:32,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1295131761, now seen corresponding path program 1 times [2018-11-18 16:09:32,703 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:32,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:32,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:32,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:32,704 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:32,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:32,824 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 53 proven. 30 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-18 16:09:32,825 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:32,825 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:32,825 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 58 with the following transitions: [2018-11-18 16:09:32,825 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [16], [17], [19], [23], [24], [28], [32], [37], [39], [40], [43], [45], [76], [77], [78], [80], [81] [2018-11-18 16:09:32,826 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:09:32,826 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:09:32,906 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:09:32,906 INFO L272 AbstractInterpreter]: Visited 25 different actions 179 times. Merged at 17 different actions 108 times. Never widened. Performed 859 root evaluator evaluations with a maximum evaluation depth of 4. Performed 859 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 12 fixpoints after 4 different actions. Largest state had 21 variables. [2018-11-18 16:09:32,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:32,908 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:09:32,908 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:32,908 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:32,929 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:32,929 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:32,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:32,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:33,016 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 83 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:33,016 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:33,073 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 83 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:09:33,088 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:33,088 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9, 9] total 20 [2018-11-18 16:09:33,088 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:33,088 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-18 16:09:33,088 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-18 16:09:33,089 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=312, Unknown=0, NotChecked=0, Total=380 [2018-11-18 16:09:33,089 INFO L87 Difference]: Start difference. First operand 86 states and 92 transitions. Second operand 16 states. [2018-11-18 16:09:33,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:33,428 INFO L93 Difference]: Finished difference Result 147 states and 152 transitions. [2018-11-18 16:09:33,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-18 16:09:33,429 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 57 [2018-11-18 16:09:33,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:33,432 INFO L225 Difference]: With dead ends: 147 [2018-11-18 16:09:33,432 INFO L226 Difference]: Without dead ends: 147 [2018-11-18 16:09:33,433 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 100 SyntacticMatches, 3 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 191 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=190, Invalid=802, Unknown=0, NotChecked=0, Total=992 [2018-11-18 16:09:33,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-11-18 16:09:33,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 123. [2018-11-18 16:09:33,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-11-18 16:09:33,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 130 transitions. [2018-11-18 16:09:33,439 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 130 transitions. Word has length 57 [2018-11-18 16:09:33,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:33,439 INFO L480 AbstractCegarLoop]: Abstraction has 123 states and 130 transitions. [2018-11-18 16:09:33,439 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-18 16:09:33,439 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 130 transitions. [2018-11-18 16:09:33,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-18 16:09:33,440 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:33,440 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:33,441 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:33,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:33,441 INFO L82 PathProgramCache]: Analyzing trace with hash 1531366311, now seen corresponding path program 2 times [2018-11-18 16:09:33,441 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:33,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:33,442 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:33,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:33,442 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:33,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:33,499 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:09:33,499 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:33,499 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:33,499 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:33,500 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:33,500 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:33,500 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:33,512 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:33,513 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:33,534 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-18 16:09:33,534 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:33,537 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:33,574 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:33,576 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:33,577 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 16:09:33,578 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 16:09:33,582 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 16:09:33,595 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 16:09:33,596 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 16:09:33,602 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 16:09:33,602 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-11-18 16:09:33,743 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:09:33,743 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:33,808 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:09:33,833 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:33,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 4, 3] total 8 [2018-11-18 16:09:33,833 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:33,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 16:09:33,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 16:09:33,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-18 16:09:33,834 INFO L87 Difference]: Start difference. First operand 123 states and 130 transitions. Second operand 7 states. [2018-11-18 16:09:33,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:33,910 INFO L93 Difference]: Finished difference Result 127 states and 134 transitions. [2018-11-18 16:09:33,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:09:33,911 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 60 [2018-11-18 16:09:33,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:33,911 INFO L225 Difference]: With dead ends: 127 [2018-11-18 16:09:33,912 INFO L226 Difference]: Without dead ends: 127 [2018-11-18 16:09:33,912 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 112 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-18 16:09:33,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-11-18 16:09:33,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 125. [2018-11-18 16:09:33,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-11-18 16:09:33,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 132 transitions. [2018-11-18 16:09:33,915 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 132 transitions. Word has length 60 [2018-11-18 16:09:33,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:33,916 INFO L480 AbstractCegarLoop]: Abstraction has 125 states and 132 transitions. [2018-11-18 16:09:33,916 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 16:09:33,916 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 132 transitions. [2018-11-18 16:09:33,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-18 16:09:33,916 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:33,916 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:33,917 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:33,917 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:33,917 INFO L82 PathProgramCache]: Analyzing trace with hash -2125354639, now seen corresponding path program 2 times [2018-11-18 16:09:33,917 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:33,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:33,920 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:33,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:33,920 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:33,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:34,065 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 51 proven. 26 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 16:09:34,066 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:34,066 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:34,066 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:34,066 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:34,066 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:34,066 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:34,073 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:34,073 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:34,080 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2018-11-18 16:09:34,081 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:34,082 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:34,104 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 16:09:34,104 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-18 16:09:34,108 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:34,109 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:34,110 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 16:09:34,110 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 16:09:34,114 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 16:09:34,118 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 16:09:34,118 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2018-11-18 16:09:34,253 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2018-11-18 16:09:34,253 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:34,349 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2018-11-18 16:09:34,371 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-18 16:09:34,371 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5, 4] imperfect sequences [10] total 17 [2018-11-18 16:09:34,371 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:34,372 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 16:09:34,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 16:09:34,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-11-18 16:09:34,372 INFO L87 Difference]: Start difference. First operand 125 states and 132 transitions. Second operand 6 states. [2018-11-18 16:09:34,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:34,401 INFO L93 Difference]: Finished difference Result 123 states and 129 transitions. [2018-11-18 16:09:34,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:09:34,401 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2018-11-18 16:09:34,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:34,402 INFO L225 Difference]: With dead ends: 123 [2018-11-18 16:09:34,402 INFO L226 Difference]: Without dead ends: 123 [2018-11-18 16:09:34,402 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 127 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-11-18 16:09:34,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-11-18 16:09:34,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 121. [2018-11-18 16:09:34,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2018-11-18 16:09:34,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 127 transitions. [2018-11-18 16:09:34,406 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 127 transitions. Word has length 68 [2018-11-18 16:09:34,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:34,406 INFO L480 AbstractCegarLoop]: Abstraction has 121 states and 127 transitions. [2018-11-18 16:09:34,406 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 16:09:34,407 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 127 transitions. [2018-11-18 16:09:34,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-11-18 16:09:34,407 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:34,408 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:34,408 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:34,408 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:34,408 INFO L82 PathProgramCache]: Analyzing trace with hash -32168774, now seen corresponding path program 1 times [2018-11-18 16:09:34,408 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:34,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:34,409 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:34,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:34,409 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:34,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:34,562 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 51 proven. 26 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 16:09:34,562 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:34,562 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:34,562 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 72 with the following transitions: [2018-11-18 16:09:34,562 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [35], [37], [39], [40], [43], [45], [49], [53], [58], [59], [64], [66], [75], [76], [77], [78], [80], [81] [2018-11-18 16:09:34,563 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:09:34,563 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:09:34,635 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:09:34,636 INFO L272 AbstractInterpreter]: Visited 32 different actions 146 times. Merged at 16 different actions 71 times. Never widened. Performed 652 root evaluator evaluations with a maximum evaluation depth of 4. Performed 652 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 10 fixpoints after 3 different actions. Largest state had 21 variables. [2018-11-18 16:09:34,661 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:34,662 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:09:34,662 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:34,662 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:34,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:34,672 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:34,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:34,692 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:34,729 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:09:34,729 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:34,767 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:09:34,792 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:34,792 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5, 5] total 14 [2018-11-18 16:09:34,792 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:34,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-18 16:09:34,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-18 16:09:34,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2018-11-18 16:09:34,793 INFO L87 Difference]: Start difference. First operand 121 states and 127 transitions. Second operand 13 states. [2018-11-18 16:09:34,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:34,981 INFO L93 Difference]: Finished difference Result 148 states and 155 transitions. [2018-11-18 16:09:34,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-18 16:09:34,981 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 71 [2018-11-18 16:09:34,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:34,983 INFO L225 Difference]: With dead ends: 148 [2018-11-18 16:09:34,983 INFO L226 Difference]: Without dead ends: 148 [2018-11-18 16:09:34,983 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 139 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=114, Invalid=392, Unknown=0, NotChecked=0, Total=506 [2018-11-18 16:09:34,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-11-18 16:09:34,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 104. [2018-11-18 16:09:34,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-11-18 16:09:34,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 107 transitions. [2018-11-18 16:09:34,987 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 107 transitions. Word has length 71 [2018-11-18 16:09:34,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:34,987 INFO L480 AbstractCegarLoop]: Abstraction has 104 states and 107 transitions. [2018-11-18 16:09:34,987 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-18 16:09:34,987 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 107 transitions. [2018-11-18 16:09:34,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-18 16:09:34,988 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:34,988 INFO L375 BasicCegarLoop]: trace histogram [12, 10, 10, 9, 9, 9, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:34,989 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:34,989 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:34,989 INFO L82 PathProgramCache]: Analyzing trace with hash 809132038, now seen corresponding path program 2 times [2018-11-18 16:09:34,989 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:34,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:34,989 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:34,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:34,990 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:34,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:35,083 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 203 proven. 24 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:09:35,084 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:35,084 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:35,084 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:35,084 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:35,084 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:35,084 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:35,096 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:35,096 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:35,116 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-18 16:09:35,116 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:35,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:35,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:35,126 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:35,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:35,134 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:35,140 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:35,153 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:35,153 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 16:09:35,313 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 162 proven. 21 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2018-11-18 16:09:35,314 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:35,462 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 162 proven. 21 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2018-11-18 16:09:35,486 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:35,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 9, 8] total 27 [2018-11-18 16:09:35,486 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:35,486 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-18 16:09:35,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-18 16:09:35,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=602, Unknown=0, NotChecked=0, Total=702 [2018-11-18 16:09:35,487 INFO L87 Difference]: Start difference. First operand 104 states and 107 transitions. Second operand 20 states. [2018-11-18 16:09:35,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:35,783 INFO L93 Difference]: Finished difference Result 145 states and 149 transitions. [2018-11-18 16:09:35,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-18 16:09:35,784 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 94 [2018-11-18 16:09:35,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:35,785 INFO L225 Difference]: With dead ends: 145 [2018-11-18 16:09:35,785 INFO L226 Difference]: Without dead ends: 145 [2018-11-18 16:09:35,785 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 212 GetRequests, 171 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 373 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=308, Invalid=1252, Unknown=0, NotChecked=0, Total=1560 [2018-11-18 16:09:35,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-11-18 16:09:35,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 141. [2018-11-18 16:09:35,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-18 16:09:35,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2018-11-18 16:09:35,788 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 94 [2018-11-18 16:09:35,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:35,788 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2018-11-18 16:09:35,788 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-18 16:09:35,788 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2018-11-18 16:09:35,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-11-18 16:09:35,789 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:35,789 INFO L375 BasicCegarLoop]: trace histogram [16, 13, 13, 12, 12, 12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:35,789 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:35,792 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:35,792 INFO L82 PathProgramCache]: Analyzing trace with hash -1481733671, now seen corresponding path program 3 times [2018-11-18 16:09:35,792 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:35,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:35,793 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:35,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:35,793 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:35,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:35,909 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 257 proven. 52 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-11-18 16:09:35,909 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:35,909 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:35,910 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:35,910 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:35,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:35,910 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:35,918 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:35,918 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:35,945 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:35,945 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:35,948 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:36,059 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 360 proven. 134 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-11-18 16:09:36,059 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:36,240 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 368 proven. 126 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-11-18 16:09:36,256 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:36,256 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 13, 13] total 27 [2018-11-18 16:09:36,256 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:36,256 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-18 16:09:36,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-18 16:09:36,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=603, Unknown=0, NotChecked=0, Total=702 [2018-11-18 16:09:36,257 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 21 states. [2018-11-18 16:09:36,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:36,605 INFO L93 Difference]: Finished difference Result 161 states and 164 transitions. [2018-11-18 16:09:36,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 16:09:36,606 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 125 [2018-11-18 16:09:36,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:36,607 INFO L225 Difference]: With dead ends: 161 [2018-11-18 16:09:36,607 INFO L226 Difference]: Without dead ends: 155 [2018-11-18 16:09:36,607 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 274 GetRequests, 230 SyntacticMatches, 7 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 325 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=272, Invalid=1210, Unknown=0, NotChecked=0, Total=1482 [2018-11-18 16:09:36,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-11-18 16:09:36,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 147. [2018-11-18 16:09:36,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-18 16:09:36,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 150 transitions. [2018-11-18 16:09:36,611 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 150 transitions. Word has length 125 [2018-11-18 16:09:36,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:36,611 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 150 transitions. [2018-11-18 16:09:36,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-18 16:09:36,611 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 150 transitions. [2018-11-18 16:09:36,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-11-18 16:09:36,612 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:36,612 INFO L375 BasicCegarLoop]: trace histogram [18, 15, 15, 14, 14, 14, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:36,612 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:36,612 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:36,612 INFO L82 PathProgramCache]: Analyzing trace with hash 1551273113, now seen corresponding path program 4 times [2018-11-18 16:09:36,612 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:36,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:36,613 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:36,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:36,613 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:36,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:36,772 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 345 proven. 86 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-11-18 16:09:36,772 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:36,772 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:36,772 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:36,773 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:36,773 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:36,773 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:36,782 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:36,782 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:36,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:36,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:36,968 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 425 proven. 30 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-11-18 16:09:36,968 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:37,068 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 425 proven. 30 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-11-18 16:09:37,083 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:37,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 13, 13] total 29 [2018-11-18 16:09:37,083 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:37,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-11-18 16:09:37,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-11-18 16:09:37,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=133, Invalid=679, Unknown=0, NotChecked=0, Total=812 [2018-11-18 16:09:37,084 INFO L87 Difference]: Start difference. First operand 147 states and 150 transitions. Second operand 23 states. [2018-11-18 16:09:37,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:37,504 INFO L93 Difference]: Finished difference Result 200 states and 204 transitions. [2018-11-18 16:09:37,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 16:09:37,505 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 137 [2018-11-18 16:09:37,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:37,506 INFO L225 Difference]: With dead ends: 200 [2018-11-18 16:09:37,506 INFO L226 Difference]: Without dead ends: 200 [2018-11-18 16:09:37,506 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 294 GetRequests, 252 SyntacticMatches, 5 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=318, Invalid=1164, Unknown=0, NotChecked=0, Total=1482 [2018-11-18 16:09:37,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2018-11-18 16:09:37,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 190. [2018-11-18 16:09:37,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-11-18 16:09:37,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 194 transitions. [2018-11-18 16:09:37,511 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 194 transitions. Word has length 137 [2018-11-18 16:09:37,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:37,511 INFO L480 AbstractCegarLoop]: Abstraction has 190 states and 194 transitions. [2018-11-18 16:09:37,511 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-11-18 16:09:37,511 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 194 transitions. [2018-11-18 16:09:37,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-11-18 16:09:37,513 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:37,513 INFO L375 BasicCegarLoop]: trace histogram [23, 19, 19, 18, 18, 18, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:37,513 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:37,513 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:37,514 INFO L82 PathProgramCache]: Analyzing trace with hash -1930439122, now seen corresponding path program 5 times [2018-11-18 16:09:37,514 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:37,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:37,514 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:37,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:37,515 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:37,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:37,643 INFO L134 CoverageAnalysis]: Checked inductivity of 1236 backedges. 863 proven. 189 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2018-11-18 16:09:37,643 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:37,644 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:37,644 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:37,644 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:37,644 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:37,644 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:37,651 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:37,651 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:37,684 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-11-18 16:09:37,684 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:37,686 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:37,689 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:37,701 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:37,708 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:37,708 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:37,725 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:37,733 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:37,733 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 16:09:38,012 INFO L134 CoverageAnalysis]: Checked inductivity of 1236 backedges. 494 proven. 64 refuted. 0 times theorem prover too weak. 678 trivial. 0 not checked. [2018-11-18 16:09:38,012 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:38,226 INFO L134 CoverageAnalysis]: Checked inductivity of 1236 backedges. 494 proven. 64 refuted. 0 times theorem prover too weak. 678 trivial. 0 not checked. [2018-11-18 16:09:38,242 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:38,242 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 11, 10] total 35 [2018-11-18 16:09:38,242 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:38,242 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 16:09:38,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 16:09:38,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=145, Invalid=1045, Unknown=0, NotChecked=0, Total=1190 [2018-11-18 16:09:38,243 INFO L87 Difference]: Start difference. First operand 190 states and 194 transitions. Second operand 26 states. [2018-11-18 16:09:39,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:39,175 INFO L93 Difference]: Finished difference Result 261 states and 265 transitions. [2018-11-18 16:09:39,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-18 16:09:39,176 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 174 [2018-11-18 16:09:39,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:39,176 INFO L225 Difference]: With dead ends: 261 [2018-11-18 16:09:39,176 INFO L226 Difference]: Without dead ends: 252 [2018-11-18 16:09:39,177 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 324 SyntacticMatches, 7 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 923 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=610, Invalid=3296, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 16:09:39,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-11-18 16:09:39,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 233. [2018-11-18 16:09:39,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-11-18 16:09:39,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 236 transitions. [2018-11-18 16:09:39,181 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 236 transitions. Word has length 174 [2018-11-18 16:09:39,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:39,181 INFO L480 AbstractCegarLoop]: Abstraction has 233 states and 236 transitions. [2018-11-18 16:09:39,181 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 16:09:39,181 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 236 transitions. [2018-11-18 16:09:39,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2018-11-18 16:09:39,182 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:39,182 INFO L375 BasicCegarLoop]: trace histogram [30, 25, 25, 24, 24, 24, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:39,182 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:39,182 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:39,183 INFO L82 PathProgramCache]: Analyzing trace with hash -665225607, now seen corresponding path program 6 times [2018-11-18 16:09:39,183 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:39,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:39,183 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:39,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:39,183 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:39,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:39,381 INFO L134 CoverageAnalysis]: Checked inductivity of 2152 backedges. 1246 proven. 402 refuted. 0 times theorem prover too weak. 504 trivial. 0 not checked. [2018-11-18 16:09:39,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:39,381 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:39,381 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:39,381 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:39,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:39,381 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:39,391 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:39,391 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:39,450 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:39,450 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:39,454 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:39,635 INFO L134 CoverageAnalysis]: Checked inductivity of 2152 backedges. 1227 proven. 352 refuted. 0 times theorem prover too weak. 573 trivial. 0 not checked. [2018-11-18 16:09:39,635 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:39,858 INFO L134 CoverageAnalysis]: Checked inductivity of 2152 backedges. 1235 proven. 344 refuted. 0 times theorem prover too weak. 573 trivial. 0 not checked. [2018-11-18 16:09:39,874 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:39,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 36 [2018-11-18 16:09:39,874 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:39,874 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-18 16:09:39,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-18 16:09:39,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=221, Invalid=1039, Unknown=0, NotChecked=0, Total=1260 [2018-11-18 16:09:39,875 INFO L87 Difference]: Start difference. First operand 233 states and 236 transitions. Second operand 28 states. [2018-11-18 16:09:40,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:40,271 INFO L93 Difference]: Finished difference Result 282 states and 287 transitions. [2018-11-18 16:09:40,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-18 16:09:40,271 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 223 [2018-11-18 16:09:40,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:40,272 INFO L225 Difference]: With dead ends: 282 [2018-11-18 16:09:40,272 INFO L226 Difference]: Without dead ends: 246 [2018-11-18 16:09:40,273 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 479 GetRequests, 422 SyntacticMatches, 9 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 736 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=559, Invalid=1891, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 16:09:40,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-11-18 16:09:40,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 237. [2018-11-18 16:09:40,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-11-18 16:09:40,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 239 transitions. [2018-11-18 16:09:40,278 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 239 transitions. Word has length 223 [2018-11-18 16:09:40,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:40,278 INFO L480 AbstractCegarLoop]: Abstraction has 237 states and 239 transitions. [2018-11-18 16:09:40,278 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-18 16:09:40,278 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 239 transitions. [2018-11-18 16:09:40,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 230 [2018-11-18 16:09:40,279 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:40,279 INFO L375 BasicCegarLoop]: trace histogram [31, 26, 26, 25, 25, 25, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:40,279 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:40,279 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:40,279 INFO L82 PathProgramCache]: Analyzing trace with hash -1346609615, now seen corresponding path program 7 times [2018-11-18 16:09:40,279 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:40,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:40,280 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:40,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:40,280 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:40,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:40,440 INFO L134 CoverageAnalysis]: Checked inductivity of 2310 backedges. 745 proven. 80 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:40,440 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:40,440 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:40,440 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:40,440 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:40,440 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:40,440 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:40,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:40,447 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:40,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:40,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:40,487 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:40,489 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:40,496 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:40,496 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:40,501 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:40,507 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:40,507 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:09:40,712 INFO L134 CoverageAnalysis]: Checked inductivity of 2310 backedges. 745 proven. 80 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:40,712 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:40,840 INFO L134 CoverageAnalysis]: Checked inductivity of 2310 backedges. 745 proven. 80 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:40,855 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:40,855 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 24 [2018-11-18 16:09:40,855 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:40,856 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-18 16:09:40,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-18 16:09:40,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=458, Unknown=0, NotChecked=0, Total=600 [2018-11-18 16:09:40,856 INFO L87 Difference]: Start difference. First operand 237 states and 239 transitions. Second operand 17 states. [2018-11-18 16:09:41,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:41,014 INFO L93 Difference]: Finished difference Result 245 states and 247 transitions. [2018-11-18 16:09:41,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 16:09:41,014 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 229 [2018-11-18 16:09:41,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:41,015 INFO L225 Difference]: With dead ends: 245 [2018-11-18 16:09:41,015 INFO L226 Difference]: Without dead ends: 245 [2018-11-18 16:09:41,016 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 473 GetRequests, 432 SyntacticMatches, 12 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 249 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=240, Invalid=690, Unknown=0, NotChecked=0, Total=930 [2018-11-18 16:09:41,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-11-18 16:09:41,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 239. [2018-11-18 16:09:41,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-11-18 16:09:41,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 241 transitions. [2018-11-18 16:09:41,019 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 241 transitions. Word has length 229 [2018-11-18 16:09:41,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:41,020 INFO L480 AbstractCegarLoop]: Abstraction has 239 states and 241 transitions. [2018-11-18 16:09:41,020 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-18 16:09:41,020 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 241 transitions. [2018-11-18 16:09:41,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 236 [2018-11-18 16:09:41,021 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:41,021 INFO L375 BasicCegarLoop]: trace histogram [32, 27, 27, 26, 26, 26, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:41,021 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:41,021 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:41,021 INFO L82 PathProgramCache]: Analyzing trace with hash 1356055865, now seen corresponding path program 8 times [2018-11-18 16:09:41,021 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:41,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:41,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:41,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:41,022 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:41,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:41,229 INFO L134 CoverageAnalysis]: Checked inductivity of 2474 backedges. 875 proven. 114 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:41,229 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:41,229 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:41,229 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:41,229 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:41,230 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:41,230 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:41,236 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:41,236 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:41,281 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-18 16:09:41,281 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:41,284 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:41,286 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:41,288 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:41,291 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:41,291 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:41,297 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:41,304 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:41,304 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:09:41,474 INFO L134 CoverageAnalysis]: Checked inductivity of 2474 backedges. 875 proven. 114 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:41,474 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:41,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2474 backedges. 875 proven. 114 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:41,697 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:41,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 11] total 23 [2018-11-18 16:09:41,697 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:41,698 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 16:09:41,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 16:09:41,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=175, Invalid=377, Unknown=0, NotChecked=0, Total=552 [2018-11-18 16:09:41,698 INFO L87 Difference]: Start difference. First operand 239 states and 241 transitions. Second operand 14 states. [2018-11-18 16:09:41,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:41,870 INFO L93 Difference]: Finished difference Result 263 states and 267 transitions. [2018-11-18 16:09:41,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-18 16:09:41,872 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 235 [2018-11-18 16:09:41,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:41,873 INFO L225 Difference]: With dead ends: 263 [2018-11-18 16:09:41,873 INFO L226 Difference]: Without dead ends: 263 [2018-11-18 16:09:41,873 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 446 SyntacticMatches, 12 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 168 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=323, Invalid=607, Unknown=0, NotChecked=0, Total=930 [2018-11-18 16:09:41,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states. [2018-11-18 16:09:41,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 245. [2018-11-18 16:09:41,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-11-18 16:09:41,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 248 transitions. [2018-11-18 16:09:41,877 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 248 transitions. Word has length 235 [2018-11-18 16:09:41,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:41,878 INFO L480 AbstractCegarLoop]: Abstraction has 245 states and 248 transitions. [2018-11-18 16:09:41,878 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 16:09:41,878 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 248 transitions. [2018-11-18 16:09:41,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2018-11-18 16:09:41,879 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:41,879 INFO L375 BasicCegarLoop]: trace histogram [33, 28, 28, 27, 27, 27, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:41,880 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:41,880 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:41,880 INFO L82 PathProgramCache]: Analyzing trace with hash -843856319, now seen corresponding path program 9 times [2018-11-18 16:09:41,880 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:41,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:41,881 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:41,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:41,881 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:41,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:42,061 INFO L134 CoverageAnalysis]: Checked inductivity of 2644 backedges. 1005 proven. 154 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-11-18 16:09:42,061 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:42,061 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:42,061 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:42,062 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:42,062 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:42,062 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:42,070 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:42,070 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:42,108 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:42,108 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:42,111 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:42,337 INFO L134 CoverageAnalysis]: Checked inductivity of 2644 backedges. 1070 proven. 472 refuted. 0 times theorem prover too weak. 1102 trivial. 0 not checked. [2018-11-18 16:09:42,337 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:42,599 INFO L134 CoverageAnalysis]: Checked inductivity of 2644 backedges. 1070 proven. 472 refuted. 0 times theorem prover too weak. 1102 trivial. 0 not checked. [2018-11-18 16:09:42,615 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:42,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 21, 21] total 43 [2018-11-18 16:09:42,615 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:42,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-18 16:09:42,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-18 16:09:42,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=1570, Unknown=0, NotChecked=0, Total=1806 [2018-11-18 16:09:42,616 INFO L87 Difference]: Start difference. First operand 245 states and 248 transitions. Second operand 32 states. [2018-11-18 16:09:43,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:43,540 INFO L93 Difference]: Finished difference Result 330 states and 335 transitions. [2018-11-18 16:09:43,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-18 16:09:43,541 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 241 [2018-11-18 16:09:43,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:43,542 INFO L225 Difference]: With dead ends: 330 [2018-11-18 16:09:43,542 INFO L226 Difference]: Without dead ends: 330 [2018-11-18 16:09:43,543 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 528 GetRequests, 449 SyntacticMatches, 9 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1293 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=751, Invalid=4361, Unknown=0, NotChecked=0, Total=5112 [2018-11-18 16:09:43,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-11-18 16:09:43,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 312. [2018-11-18 16:09:43,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-11-18 16:09:43,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 317 transitions. [2018-11-18 16:09:43,550 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 317 transitions. Word has length 241 [2018-11-18 16:09:43,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:43,551 INFO L480 AbstractCegarLoop]: Abstraction has 312 states and 317 transitions. [2018-11-18 16:09:43,551 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-18 16:09:43,551 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 317 transitions. [2018-11-18 16:09:43,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 297 [2018-11-18 16:09:43,552 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:43,553 INFO L375 BasicCegarLoop]: trace histogram [41, 35, 35, 34, 34, 34, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:43,553 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:43,553 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:43,553 INFO L82 PathProgramCache]: Analyzing trace with hash 1300512094, now seen corresponding path program 10 times [2018-11-18 16:09:43,553 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:43,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:43,558 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:43,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:43,559 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:43,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:43,849 INFO L134 CoverageAnalysis]: Checked inductivity of 4141 backedges. 2791 proven. 393 refuted. 0 times theorem prover too weak. 957 trivial. 0 not checked. [2018-11-18 16:09:43,849 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:43,849 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:43,849 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:43,850 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:43,850 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:43,850 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:43,855 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:43,856 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:43,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:43,923 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:44,063 INFO L134 CoverageAnalysis]: Checked inductivity of 4141 backedges. 2434 proven. 102 refuted. 0 times theorem prover too weak. 1605 trivial. 0 not checked. [2018-11-18 16:09:44,063 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:44,270 INFO L134 CoverageAnalysis]: Checked inductivity of 4141 backedges. 2434 proven. 102 refuted. 0 times theorem prover too weak. 1605 trivial. 0 not checked. [2018-11-18 16:09:44,285 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:44,285 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 16, 16] total 38 [2018-11-18 16:09:44,285 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:44,286 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-18 16:09:44,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-18 16:09:44,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=263, Invalid=1143, Unknown=0, NotChecked=0, Total=1406 [2018-11-18 16:09:44,286 INFO L87 Difference]: Start difference. First operand 312 states and 317 transitions. Second operand 31 states. [2018-11-18 16:09:44,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:44,820 INFO L93 Difference]: Finished difference Result 321 states and 324 transitions. [2018-11-18 16:09:44,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-18 16:09:44,821 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 296 [2018-11-18 16:09:44,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:44,823 INFO L225 Difference]: With dead ends: 321 [2018-11-18 16:09:44,823 INFO L226 Difference]: Without dead ends: 315 [2018-11-18 16:09:44,823 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 631 GetRequests, 568 SyntacticMatches, 8 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1052 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=657, Invalid=2535, Unknown=0, NotChecked=0, Total=3192 [2018-11-18 16:09:44,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 315 states. [2018-11-18 16:09:44,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 315 to 312. [2018-11-18 16:09:44,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-11-18 16:09:44,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 315 transitions. [2018-11-18 16:09:44,833 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 315 transitions. Word has length 296 [2018-11-18 16:09:44,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:44,833 INFO L480 AbstractCegarLoop]: Abstraction has 312 states and 315 transitions. [2018-11-18 16:09:44,833 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-18 16:09:44,833 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 315 transitions. [2018-11-18 16:09:44,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 303 [2018-11-18 16:09:44,835 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:44,835 INFO L375 BasicCegarLoop]: trace histogram [42, 36, 36, 35, 35, 35, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:44,839 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:44,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:44,839 INFO L82 PathProgramCache]: Analyzing trace with hash -586720938, now seen corresponding path program 11 times [2018-11-18 16:09:44,839 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:44,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:44,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:44,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:44,840 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:44,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:45,053 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 1695 proven. 146 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-11-18 16:09:45,054 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:45,054 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:45,054 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:45,054 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:45,054 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:45,054 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:45,065 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:45,065 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:45,166 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-11-18 16:09:45,166 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:45,172 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:45,558 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 2363 proven. 508 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 16:09:45,559 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:45,907 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 2363 proven. 508 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 16:09:45,923 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:45,923 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 23, 23] total 46 [2018-11-18 16:09:45,923 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:45,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-11-18 16:09:45,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-11-18 16:09:45,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=337, Invalid=1733, Unknown=0, NotChecked=0, Total=2070 [2018-11-18 16:09:45,924 INFO L87 Difference]: Start difference. First operand 312 states and 315 transitions. Second operand 38 states. [2018-11-18 16:09:46,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:46,492 INFO L93 Difference]: Finished difference Result 388 states and 392 transitions. [2018-11-18 16:09:46,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-11-18 16:09:46,492 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 302 [2018-11-18 16:09:46,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:46,493 INFO L225 Difference]: With dead ends: 388 [2018-11-18 16:09:46,493 INFO L226 Difference]: Without dead ends: 388 [2018-11-18 16:09:46,494 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 646 GetRequests, 565 SyntacticMatches, 14 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1274 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=957, Invalid=3735, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 16:09:46,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states. [2018-11-18 16:09:46,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 379. [2018-11-18 16:09:46,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 379 states. [2018-11-18 16:09:46,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 379 states to 379 states and 383 transitions. [2018-11-18 16:09:46,500 INFO L78 Accepts]: Start accepts. Automaton has 379 states and 383 transitions. Word has length 302 [2018-11-18 16:09:46,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:46,501 INFO L480 AbstractCegarLoop]: Abstraction has 379 states and 383 transitions. [2018-11-18 16:09:46,501 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-11-18 16:09:46,501 INFO L276 IsEmpty]: Start isEmpty. Operand 379 states and 383 transitions. [2018-11-18 16:09:46,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 364 [2018-11-18 16:09:46,502 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:46,503 INFO L375 BasicCegarLoop]: trace histogram [51, 44, 44, 43, 43, 43, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:46,503 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:46,503 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:46,503 INFO L82 PathProgramCache]: Analyzing trace with hash 1640746593, now seen corresponding path program 12 times [2018-11-18 16:09:46,503 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:46,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:46,504 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:46,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:46,504 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:46,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:46,977 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-11-18 16:09:46,978 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:46,978 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:46,978 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:46,978 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:46,978 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:46,978 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:46,988 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:46,988 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:47,095 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:47,095 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:47,103 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:47,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:47,109 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:47,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:47,115 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:47,126 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:47,136 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:47,136 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:09:47,719 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-11-18 16:09:47,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:47,991 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-11-18 16:09:48,007 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:48,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 12] total 33 [2018-11-18 16:09:48,008 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:48,008 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-11-18 16:09:48,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-11-18 16:09:48,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=259, Invalid=863, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 16:09:48,009 INFO L87 Difference]: Start difference. First operand 379 states and 383 transitions. Second operand 23 states. [2018-11-18 16:09:48,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:48,343 INFO L93 Difference]: Finished difference Result 393 states and 398 transitions. [2018-11-18 16:09:48,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 16:09:48,344 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 363 [2018-11-18 16:09:48,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:48,345 INFO L225 Difference]: With dead ends: 393 [2018-11-18 16:09:48,345 INFO L226 Difference]: Without dead ends: 393 [2018-11-18 16:09:48,346 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 747 GetRequests, 690 SyntacticMatches, 16 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 531 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=447, Invalid=1359, Unknown=0, NotChecked=0, Total=1806 [2018-11-18 16:09:48,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2018-11-18 16:09:48,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 385. [2018-11-18 16:09:48,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2018-11-18 16:09:48,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 390 transitions. [2018-11-18 16:09:48,351 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 390 transitions. Word has length 363 [2018-11-18 16:09:48,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:48,351 INFO L480 AbstractCegarLoop]: Abstraction has 385 states and 390 transitions. [2018-11-18 16:09:48,352 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-11-18 16:09:48,352 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 390 transitions. [2018-11-18 16:09:48,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 370 [2018-11-18 16:09:48,354 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:48,354 INFO L375 BasicCegarLoop]: trace histogram [52, 45, 45, 44, 44, 44, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:48,354 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:48,354 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:48,354 INFO L82 PathProgramCache]: Analyzing trace with hash -1598402199, now seen corresponding path program 13 times [2018-11-18 16:09:48,354 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:48,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:48,355 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:48,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:48,355 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:48,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:48,660 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2403 proven. 194 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 16:09:48,661 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:48,661 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:48,661 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:48,661 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:48,661 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:48,661 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:48,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:48,672 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:48,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:48,758 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:49,160 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2429 proven. 168 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 16:09:49,160 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:49,467 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2429 proven. 168 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 16:09:49,492 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:49,492 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 33 [2018-11-18 16:09:49,492 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:49,493 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-18 16:09:49,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-18 16:09:49,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=802, Unknown=0, NotChecked=0, Total=1056 [2018-11-18 16:09:49,494 INFO L87 Difference]: Start difference. First operand 385 states and 390 transitions. Second operand 33 states. [2018-11-18 16:09:49,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:49,946 INFO L93 Difference]: Finished difference Result 540 states and 550 transitions. [2018-11-18 16:09:49,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-18 16:09:49,947 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 369 [2018-11-18 16:09:49,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:49,948 INFO L225 Difference]: With dead ends: 540 [2018-11-18 16:09:49,948 INFO L226 Difference]: Without dead ends: 540 [2018-11-18 16:09:49,948 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 776 GetRequests, 709 SyntacticMatches, 19 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 735 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=659, Invalid=1791, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 16:09:49,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-11-18 16:09:49,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 526. [2018-11-18 16:09:49,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 526 states. [2018-11-18 16:09:49,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 536 transitions. [2018-11-18 16:09:49,954 INFO L78 Accepts]: Start accepts. Automaton has 526 states and 536 transitions. Word has length 369 [2018-11-18 16:09:49,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:49,955 INFO L480 AbstractCegarLoop]: Abstraction has 526 states and 536 transitions. [2018-11-18 16:09:49,955 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-18 16:09:49,955 INFO L276 IsEmpty]: Start isEmpty. Operand 526 states and 536 transitions. [2018-11-18 16:09:49,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 425 [2018-11-18 16:09:49,958 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:49,958 INFO L375 BasicCegarLoop]: trace histogram [60, 52, 52, 51, 51, 51, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:49,958 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:49,959 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:49,959 INFO L82 PathProgramCache]: Analyzing trace with hash -1604237514, now seen corresponding path program 14 times [2018-11-18 16:09:49,959 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:49,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:49,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:49,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:49,960 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:49,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:50,245 INFO L134 CoverageAnalysis]: Checked inductivity of 9082 backedges. 4021 proven. 1336 refuted. 0 times theorem prover too weak. 3725 trivial. 0 not checked. [2018-11-18 16:09:50,245 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:50,245 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:50,245 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:50,246 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:50,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:50,246 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:50,265 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:50,265 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:50,389 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-11-18 16:09:50,389 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:50,396 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:50,863 INFO L134 CoverageAnalysis]: Checked inductivity of 9082 backedges. 3836 proven. 930 refuted. 0 times theorem prover too weak. 4316 trivial. 0 not checked. [2018-11-18 16:09:50,864 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:51,399 INFO L134 CoverageAnalysis]: Checked inductivity of 9082 backedges. 3836 proven. 930 refuted. 0 times theorem prover too weak. 4316 trivial. 0 not checked. [2018-11-18 16:09:51,415 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:51,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25, 25] total 62 [2018-11-18 16:09:51,416 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:51,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-11-18 16:09:51,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-11-18 16:09:51,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=495, Invalid=3287, Unknown=0, NotChecked=0, Total=3782 [2018-11-18 16:09:51,417 INFO L87 Difference]: Start difference. First operand 526 states and 536 transitions. Second operand 44 states. [2018-11-18 16:09:52,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:52,541 INFO L93 Difference]: Finished difference Result 465 states and 469 transitions. [2018-11-18 16:09:52,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 16:09:52,541 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 424 [2018-11-18 16:09:52,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:52,542 INFO L225 Difference]: With dead ends: 465 [2018-11-18 16:09:52,543 INFO L226 Difference]: Without dead ends: 456 [2018-11-18 16:09:52,545 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 913 GetRequests, 804 SyntacticMatches, 6 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3442 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1601, Invalid=9319, Unknown=0, NotChecked=0, Total=10920 [2018-11-18 16:09:52,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 456 states. [2018-11-18 16:09:52,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 456 to 446. [2018-11-18 16:09:52,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-11-18 16:09:52,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 450 transitions. [2018-11-18 16:09:52,552 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 450 transitions. Word has length 424 [2018-11-18 16:09:52,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:52,552 INFO L480 AbstractCegarLoop]: Abstraction has 446 states and 450 transitions. [2018-11-18 16:09:52,552 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-11-18 16:09:52,553 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 450 transitions. [2018-11-18 16:09:52,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-11-18 16:09:52,555 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:52,555 INFO L375 BasicCegarLoop]: trace histogram [61, 53, 53, 52, 52, 52, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:52,555 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:52,555 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:52,555 INFO L82 PathProgramCache]: Analyzing trace with hash -762866562, now seen corresponding path program 15 times [2018-11-18 16:09:52,556 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:52,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:52,556 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:52,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:52,556 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:52,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:52,878 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 5831 proven. 669 refuted. 0 times theorem prover too weak. 2908 trivial. 0 not checked. [2018-11-18 16:09:52,879 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:52,879 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:52,879 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:52,879 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:52,879 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:52,879 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:52,887 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:52,887 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:52,949 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:52,949 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:52,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:53,273 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 4660 proven. 829 refuted. 0 times theorem prover too weak. 3919 trivial. 0 not checked. [2018-11-18 16:09:53,274 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:53,686 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 4668 proven. 821 refuted. 0 times theorem prover too weak. 3919 trivial. 0 not checked. [2018-11-18 16:09:53,710 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:53,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23, 23] total 53 [2018-11-18 16:09:53,710 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:53,711 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-11-18 16:09:53,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-11-18 16:09:53,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=2307, Unknown=0, NotChecked=0, Total=2756 [2018-11-18 16:09:53,712 INFO L87 Difference]: Start difference. First operand 446 states and 450 transitions. Second operand 42 states. [2018-11-18 16:09:54,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:54,459 INFO L93 Difference]: Finished difference Result 457 states and 459 transitions. [2018-11-18 16:09:54,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-11-18 16:09:54,459 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 430 [2018-11-18 16:09:54,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:54,461 INFO L225 Difference]: With dead ends: 457 [2018-11-18 16:09:54,461 INFO L226 Difference]: Without dead ends: 451 [2018-11-18 16:09:54,462 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 909 GetRequests, 821 SyntacticMatches, 12 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2249 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1199, Invalid=4807, Unknown=0, NotChecked=0, Total=6006 [2018-11-18 16:09:54,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states. [2018-11-18 16:09:54,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 446. [2018-11-18 16:09:54,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-11-18 16:09:54,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 448 transitions. [2018-11-18 16:09:54,467 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 448 transitions. Word has length 430 [2018-11-18 16:09:54,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:54,468 INFO L480 AbstractCegarLoop]: Abstraction has 446 states and 448 transitions. [2018-11-18 16:09:54,468 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-11-18 16:09:54,468 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 448 transitions. [2018-11-18 16:09:54,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 437 [2018-11-18 16:09:54,470 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:54,470 INFO L375 BasicCegarLoop]: trace histogram [62, 54, 54, 53, 53, 53, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:54,470 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:54,471 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:54,471 INFO L82 PathProgramCache]: Analyzing trace with hash -1603398538, now seen corresponding path program 16 times [2018-11-18 16:09:54,471 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:54,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:54,471 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:54,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:54,471 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:54,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:54,781 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-11-18 16:09:54,781 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:54,781 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:54,781 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:54,781 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:54,781 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:54,782 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:54,789 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:54,789 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:54,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:54,856 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:54,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:54,865 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:54,872 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:54,872 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:54,884 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:54,894 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:54,894 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:09:55,290 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-11-18 16:09:55,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:55,598 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-11-18 16:09:55,613 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:55,613 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 13] total 36 [2018-11-18 16:09:55,614 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:55,614 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-18 16:09:55,614 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-18 16:09:55,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=1026, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 16:09:55,615 INFO L87 Difference]: Start difference. First operand 446 states and 448 transitions. Second operand 25 states. [2018-11-18 16:09:55,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:55,989 INFO L93 Difference]: Finished difference Result 460 states and 463 transitions. [2018-11-18 16:09:55,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 16:09:55,990 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 436 [2018-11-18 16:09:55,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:55,991 INFO L225 Difference]: With dead ends: 460 [2018-11-18 16:09:55,991 INFO L226 Difference]: Without dead ends: 460 [2018-11-18 16:09:55,991 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 895 GetRequests, 832 SyntacticMatches, 18 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 650 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=530, Invalid=1632, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 16:09:55,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states. [2018-11-18 16:09:55,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 452. [2018-11-18 16:09:55,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 452 states. [2018-11-18 16:09:55,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 452 states to 452 states and 455 transitions. [2018-11-18 16:09:55,996 INFO L78 Accepts]: Start accepts. Automaton has 452 states and 455 transitions. Word has length 436 [2018-11-18 16:09:55,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:55,997 INFO L480 AbstractCegarLoop]: Abstraction has 452 states and 455 transitions. [2018-11-18 16:09:55,997 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-18 16:09:55,997 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 455 transitions. [2018-11-18 16:09:55,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 443 [2018-11-18 16:09:55,999 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:55,999 INFO L375 BasicCegarLoop]: trace histogram [63, 55, 55, 54, 54, 54, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:56,000 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:56,000 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:56,000 INFO L82 PathProgramCache]: Analyzing trace with hash 687010750, now seen corresponding path program 17 times [2018-11-18 16:09:56,000 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:56,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:56,001 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:56,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:56,001 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:56,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:56,399 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 3281 proven. 249 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-11-18 16:09:56,399 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:56,399 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:56,399 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:56,400 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:56,400 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:56,400 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:56,416 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:56,416 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:56,584 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-11-18 16:09:56,584 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:56,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:57,162 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 4903 proven. 814 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 16:09:57,162 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:57,569 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 4903 proven. 814 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 16:09:57,584 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:57,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27, 27] total 56 [2018-11-18 16:09:57,584 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:57,585 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-11-18 16:09:57,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-11-18 16:09:57,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=488, Invalid=2592, Unknown=0, NotChecked=0, Total=3080 [2018-11-18 16:09:57,585 INFO L87 Difference]: Start difference. First operand 452 states and 455 transitions. Second operand 46 states. [2018-11-18 16:09:58,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:58,405 INFO L93 Difference]: Finished difference Result 540 states and 544 transitions. [2018-11-18 16:09:58,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 16:09:58,405 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 442 [2018-11-18 16:09:58,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:58,407 INFO L225 Difference]: With dead ends: 540 [2018-11-18 16:09:58,407 INFO L226 Difference]: Without dead ends: 540 [2018-11-18 16:09:58,408 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 936 GetRequests, 837 SyntacticMatches, 16 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1994 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1417, Invalid=5723, Unknown=0, NotChecked=0, Total=7140 [2018-11-18 16:09:58,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-11-18 16:09:58,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 531. [2018-11-18 16:09:58,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 531 states. [2018-11-18 16:09:58,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 531 states to 531 states and 535 transitions. [2018-11-18 16:09:58,414 INFO L78 Accepts]: Start accepts. Automaton has 531 states and 535 transitions. Word has length 442 [2018-11-18 16:09:58,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:58,415 INFO L480 AbstractCegarLoop]: Abstraction has 531 states and 535 transitions. [2018-11-18 16:09:58,415 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-11-18 16:09:58,415 INFO L276 IsEmpty]: Start isEmpty. Operand 531 states and 535 transitions. [2018-11-18 16:09:58,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 516 [2018-11-18 16:09:58,417 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:58,418 INFO L375 BasicCegarLoop]: trace histogram [74, 65, 65, 64, 64, 64, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:58,418 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:09:58,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:58,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1692616969, now seen corresponding path program 18 times [2018-11-18 16:09:58,418 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:58,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:58,419 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:58,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:58,419 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:58,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:58,805 INFO L134 CoverageAnalysis]: Checked inductivity of 14026 backedges. 3663 proven. 299 refuted. 0 times theorem prover too weak. 10064 trivial. 0 not checked. [2018-11-18 16:09:58,805 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:58,805 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:58,805 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:58,805 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:58,805 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:58,806 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:58,814 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:58,814 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:58,923 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:58,923 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:58,929 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:58,942 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:09:58,944 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:09:58,947 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:09:58,948 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:09:58,952 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:09:58,958 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:09:58,958 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:09:59,600 INFO L134 CoverageAnalysis]: Checked inductivity of 14026 backedges. 3663 proven. 310 refuted. 0 times theorem prover too weak. 10053 trivial. 0 not checked. [2018-11-18 16:09:59,601 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:59,975 INFO L134 CoverageAnalysis]: Checked inductivity of 14026 backedges. 3663 proven. 310 refuted. 0 times theorem prover too weak. 10053 trivial. 0 not checked. [2018-11-18 16:09:59,990 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:59,991 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 14] total 42 [2018-11-18 16:09:59,991 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:59,991 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 16:09:59,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 16:09:59,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=334, Invalid=1472, Unknown=0, NotChecked=0, Total=1806 [2018-11-18 16:09:59,992 INFO L87 Difference]: Start difference. First operand 531 states and 535 transitions. Second operand 30 states. [2018-11-18 16:10:01,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:01,126 INFO L93 Difference]: Finished difference Result 725 states and 736 transitions. [2018-11-18 16:10:01,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-18 16:10:01,126 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 515 [2018-11-18 16:10:01,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:01,128 INFO L225 Difference]: With dead ends: 725 [2018-11-18 16:10:01,128 INFO L226 Difference]: Without dead ends: 725 [2018-11-18 16:10:01,129 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1071 GetRequests, 986 SyntacticMatches, 17 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1064 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=900, Invalid=3930, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 16:10:01,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 725 states. [2018-11-18 16:10:01,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 725 to 696. [2018-11-18 16:10:01,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 696 states. [2018-11-18 16:10:01,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 696 states to 696 states and 706 transitions. [2018-11-18 16:10:01,137 INFO L78 Accepts]: Start accepts. Automaton has 696 states and 706 transitions. Word has length 515 [2018-11-18 16:10:01,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:01,138 INFO L480 AbstractCegarLoop]: Abstraction has 696 states and 706 transitions. [2018-11-18 16:10:01,138 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 16:10:01,138 INFO L276 IsEmpty]: Start isEmpty. Operand 696 states and 706 transitions. [2018-11-18 16:10:01,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 589 [2018-11-18 16:10:01,141 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:01,141 INFO L375 BasicCegarLoop]: trace histogram [85, 75, 75, 74, 74, 74, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:01,141 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:01,141 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:01,142 INFO L82 PathProgramCache]: Analyzing trace with hash 2007370270, now seen corresponding path program 19 times [2018-11-18 16:10:01,142 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:01,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:01,142 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:01,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:01,142 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:01,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:01,497 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 7508 proven. 2084 refuted. 0 times theorem prover too weak. 9035 trivial. 0 not checked. [2018-11-18 16:10:01,497 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:01,497 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:01,498 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:01,498 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:01,498 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:01,498 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:01,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:01,506 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:01,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:01,599 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:01,870 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 10441 proven. 234 refuted. 0 times theorem prover too weak. 7952 trivial. 0 not checked. [2018-11-18 16:10:01,870 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:02,319 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 7646 proven. 817 refuted. 0 times theorem prover too weak. 10164 trivial. 0 not checked. [2018-11-18 16:10:02,334 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:02,335 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 22, 22] total 47 [2018-11-18 16:10:02,335 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:02,335 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 16:10:02,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 16:10:02,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1713, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 16:10:02,336 INFO L87 Difference]: Start difference. First operand 696 states and 706 transitions. Second operand 37 states. [2018-11-18 16:10:02,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:02,908 INFO L93 Difference]: Finished difference Result 620 states and 624 transitions. [2018-11-18 16:10:02,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-18 16:10:02,909 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 588 [2018-11-18 16:10:02,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:02,910 INFO L225 Difference]: With dead ends: 620 [2018-11-18 16:10:02,910 INFO L226 Difference]: Without dead ends: 611 [2018-11-18 16:10:02,911 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1224 GetRequests, 1146 SyntacticMatches, 11 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1493 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1095, Invalid=3597, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 16:10:02,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 611 states. [2018-11-18 16:10:02,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 611 to 604. [2018-11-18 16:10:02,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 604 states. [2018-11-18 16:10:02,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 604 states to 604 states and 608 transitions. [2018-11-18 16:10:02,920 INFO L78 Accepts]: Start accepts. Automaton has 604 states and 608 transitions. Word has length 588 [2018-11-18 16:10:02,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:02,921 INFO L480 AbstractCegarLoop]: Abstraction has 604 states and 608 transitions. [2018-11-18 16:10:02,921 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 16:10:02,921 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 608 transitions. [2018-11-18 16:10:02,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 595 [2018-11-18 16:10:02,924 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:02,925 INFO L375 BasicCegarLoop]: trace histogram [86, 76, 76, 75, 75, 75, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:02,925 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:02,925 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:02,925 INFO L82 PathProgramCache]: Analyzing trace with hash -485027482, now seen corresponding path program 20 times [2018-11-18 16:10:02,925 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:02,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:02,926 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:02,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:02,926 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:02,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:03,340 INFO L134 CoverageAnalysis]: Checked inductivity of 19095 backedges. 10919 proven. 1017 refuted. 0 times theorem prover too weak. 7159 trivial. 0 not checked. [2018-11-18 16:10:03,340 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:03,340 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:03,340 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:03,340 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:03,340 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:03,340 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:03,350 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:03,350 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:03,465 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-18 16:10:03,465 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:03,470 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:03,935 INFO L134 CoverageAnalysis]: Checked inductivity of 19095 backedges. 8039 proven. 994 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 16:10:03,935 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:04,592 INFO L134 CoverageAnalysis]: Checked inductivity of 19095 backedges. 8039 proven. 994 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 16:10:04,607 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:04,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29, 29] total 77 [2018-11-18 16:10:04,607 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:04,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-18 16:10:04,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-18 16:10:04,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=793, Invalid=5059, Unknown=0, NotChecked=0, Total=5852 [2018-11-18 16:10:04,609 INFO L87 Difference]: Start difference. First operand 604 states and 608 transitions. Second operand 54 states. [2018-11-18 16:10:06,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:06,010 INFO L93 Difference]: Finished difference Result 625 states and 627 transitions. [2018-11-18 16:10:06,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 16:10:06,010 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 594 [2018-11-18 16:10:06,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:06,011 INFO L225 Difference]: With dead ends: 625 [2018-11-18 16:10:06,011 INFO L226 Difference]: Without dead ends: 619 [2018-11-18 16:10:06,013 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1264 GetRequests, 1136 SyntacticMatches, 5 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4820 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2588, Invalid=12912, Unknown=0, NotChecked=0, Total=15500 [2018-11-18 16:10:06,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 619 states. [2018-11-18 16:10:06,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 619 to 610. [2018-11-18 16:10:06,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2018-11-18 16:10:06,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 612 transitions. [2018-11-18 16:10:06,020 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 612 transitions. Word has length 594 [2018-11-18 16:10:06,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:06,021 INFO L480 AbstractCegarLoop]: Abstraction has 610 states and 612 transitions. [2018-11-18 16:10:06,021 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-18 16:10:06,021 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 612 transitions. [2018-11-18 16:10:06,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 601 [2018-11-18 16:10:06,026 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:06,026 INFO L375 BasicCegarLoop]: trace histogram [87, 77, 77, 76, 76, 76, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:06,027 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:06,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:06,027 INFO L82 PathProgramCache]: Analyzing trace with hash 296860510, now seen corresponding path program 21 times [2018-11-18 16:10:06,027 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:06,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:06,028 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:06,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:06,028 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:06,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:06,529 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-11-18 16:10:06,529 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:06,529 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:06,529 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:06,529 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:06,530 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:06,530 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:06,537 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:06,537 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:06,647 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:06,647 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:06,653 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:06,655 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:10:06,657 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:10:06,661 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:10:06,662 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:10:06,668 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:10:06,675 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:10:06,675 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:10:07,342 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-11-18 16:10:07,342 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:07,759 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-11-18 16:10:07,775 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:07,775 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 15] total 42 [2018-11-18 16:10:07,775 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:07,776 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 16:10:07,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 16:10:07,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=412, Invalid=1394, Unknown=0, NotChecked=0, Total=1806 [2018-11-18 16:10:07,776 INFO L87 Difference]: Start difference. First operand 610 states and 612 transitions. Second operand 29 states. [2018-11-18 16:10:08,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:08,337 INFO L93 Difference]: Finished difference Result 624 states and 627 transitions. [2018-11-18 16:10:08,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-18 16:10:08,337 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 600 [2018-11-18 16:10:08,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:08,338 INFO L225 Difference]: With dead ends: 624 [2018-11-18 16:10:08,339 INFO L226 Difference]: Without dead ends: 624 [2018-11-18 16:10:08,339 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1227 GetRequests, 1152 SyntacticMatches, 22 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 924 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=717, Invalid=2253, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 16:10:08,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 624 states. [2018-11-18 16:10:08,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 624 to 616. [2018-11-18 16:10:08,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. [2018-11-18 16:10:08,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 619 transitions. [2018-11-18 16:10:08,344 INFO L78 Accepts]: Start accepts. Automaton has 616 states and 619 transitions. Word has length 600 [2018-11-18 16:10:08,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:08,344 INFO L480 AbstractCegarLoop]: Abstraction has 616 states and 619 transitions. [2018-11-18 16:10:08,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 16:10:08,344 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 619 transitions. [2018-11-18 16:10:08,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 607 [2018-11-18 16:10:08,348 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:08,348 INFO L375 BasicCegarLoop]: trace histogram [88, 78, 78, 77, 77, 77, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:08,348 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:08,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:08,348 INFO L82 PathProgramCache]: Analyzing trace with hash -1761096538, now seen corresponding path program 22 times [2018-11-18 16:10:08,349 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:08,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:08,349 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:08,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:08,350 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:08,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:08,684 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5619 proven. 380 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-11-18 16:10:08,684 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:08,684 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:08,684 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:08,684 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:08,684 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:08,685 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:08,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:08,693 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:08,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:08,775 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:09,079 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5654 proven. 345 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-11-18 16:10:09,079 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:09,361 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5654 proven. 345 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-11-18 16:10:09,376 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:09,377 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27, 27] total 42 [2018-11-18 16:10:09,377 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:09,377 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-11-18 16:10:09,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-11-18 16:10:09,378 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=407, Invalid=1315, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 16:10:09,378 INFO L87 Difference]: Start difference. First operand 616 states and 619 transitions. Second operand 42 states. [2018-11-18 16:10:10,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:10,249 INFO L93 Difference]: Finished difference Result 711 states and 715 transitions. [2018-11-18 16:10:10,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-18 16:10:10,249 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 606 [2018-11-18 16:10:10,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:10,251 INFO L225 Difference]: With dead ends: 711 [2018-11-18 16:10:10,251 INFO L226 Difference]: Without dead ends: 711 [2018-11-18 16:10:10,251 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1262 GetRequests, 1174 SyntacticMatches, 25 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1272 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1094, Invalid=3066, Unknown=0, NotChecked=0, Total=4160 [2018-11-18 16:10:10,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2018-11-18 16:10:10,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 701. [2018-11-18 16:10:10,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 701 states. [2018-11-18 16:10:10,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 701 states to 701 states and 705 transitions. [2018-11-18 16:10:10,257 INFO L78 Accepts]: Start accepts. Automaton has 701 states and 705 transitions. Word has length 606 [2018-11-18 16:10:10,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:10,258 INFO L480 AbstractCegarLoop]: Abstraction has 701 states and 705 transitions. [2018-11-18 16:10:10,258 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-11-18 16:10:10,258 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 705 transitions. [2018-11-18 16:10:10,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 686 [2018-11-18 16:10:10,262 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:10,262 INFO L375 BasicCegarLoop]: trace histogram [100, 89, 89, 88, 88, 88, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:10,262 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:10,263 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:10,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1710123385, now seen corresponding path program 23 times [2018-11-18 16:10:10,263 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:10,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:10,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:10,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:10,264 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:10,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:10,689 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 11003 proven. 1890 refuted. 0 times theorem prover too weak. 13144 trivial. 0 not checked. [2018-11-18 16:10:10,689 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:10,689 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:10,690 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:10,690 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:10,690 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:10,690 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:10,698 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:10,698 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:10,832 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-18 16:10:10,832 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:10,837 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:11,386 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 10440 proven. 1192 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 16:10:11,387 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:12,157 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 10440 proven. 1192 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 16:10:12,173 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:12,173 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31, 31] total 83 [2018-11-18 16:10:12,173 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:12,173 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-18 16:10:12,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-18 16:10:12,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=915, Invalid=5891, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 16:10:12,174 INFO L87 Difference]: Start difference. First operand 701 states and 705 transitions. Second operand 58 states. [2018-11-18 16:10:13,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:13,741 INFO L93 Difference]: Finished difference Result 716 states and 718 transitions. [2018-11-18 16:10:13,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-11-18 16:10:13,741 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 685 [2018-11-18 16:10:13,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:13,742 INFO L225 Difference]: With dead ends: 716 [2018-11-18 16:10:13,742 INFO L226 Difference]: Without dead ends: 710 [2018-11-18 16:10:13,743 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1461 GetRequests, 1314 SyntacticMatches, 5 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6803 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2985, Invalid=17607, Unknown=0, NotChecked=0, Total=20592 [2018-11-18 16:10:13,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710 states. [2018-11-18 16:10:13,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710 to 701. [2018-11-18 16:10:13,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 701 states. [2018-11-18 16:10:13,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 701 states to 701 states and 703 transitions. [2018-11-18 16:10:13,748 INFO L78 Accepts]: Start accepts. Automaton has 701 states and 703 transitions. Word has length 685 [2018-11-18 16:10:13,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:13,749 INFO L480 AbstractCegarLoop]: Abstraction has 701 states and 703 transitions. [2018-11-18 16:10:13,749 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-18 16:10:13,749 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 703 transitions. [2018-11-18 16:10:13,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 692 [2018-11-18 16:10:13,754 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:13,755 INFO L375 BasicCegarLoop]: trace histogram [101, 90, 90, 89, 89, 89, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:13,755 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:13,755 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:13,755 INFO L82 PathProgramCache]: Analyzing trace with hash -1390430927, now seen corresponding path program 24 times [2018-11-18 16:10:13,755 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:13,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:13,756 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:13,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:13,756 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:13,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:14,315 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19998 trivial. 0 not checked. [2018-11-18 16:10:14,316 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:14,316 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:14,316 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:14,316 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:14,316 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:14,316 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:14,322 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:14,323 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:14,457 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:14,457 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:14,464 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:14,466 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:10:14,477 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:10:14,481 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:10:14,481 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:10:14,486 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:10:14,492 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:10:14,492 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:10:15,302 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19998 trivial. 0 not checked. [2018-11-18 16:10:15,302 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:15,802 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19998 trivial. 0 not checked. [2018-11-18 16:10:15,818 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:15,818 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 16] total 45 [2018-11-18 16:10:15,818 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:15,819 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-18 16:10:15,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-18 16:10:15,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=471, Invalid=1599, Unknown=0, NotChecked=0, Total=2070 [2018-11-18 16:10:15,819 INFO L87 Difference]: Start difference. First operand 701 states and 703 transitions. Second operand 31 states. [2018-11-18 16:10:16,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:16,294 INFO L93 Difference]: Finished difference Result 715 states and 718 transitions. [2018-11-18 16:10:16,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 16:10:16,294 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 691 [2018-11-18 16:10:16,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:16,296 INFO L225 Difference]: With dead ends: 715 [2018-11-18 16:10:16,296 INFO L226 Difference]: Without dead ends: 715 [2018-11-18 16:10:16,297 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1411 GetRequests, 1330 SyntacticMatches, 24 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1079 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=821, Invalid=2601, Unknown=0, NotChecked=0, Total=3422 [2018-11-18 16:10:16,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2018-11-18 16:10:16,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 707. [2018-11-18 16:10:16,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 707 states. [2018-11-18 16:10:16,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 707 states to 707 states and 710 transitions. [2018-11-18 16:10:16,302 INFO L78 Accepts]: Start accepts. Automaton has 707 states and 710 transitions. Word has length 691 [2018-11-18 16:10:16,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:16,303 INFO L480 AbstractCegarLoop]: Abstraction has 707 states and 710 transitions. [2018-11-18 16:10:16,303 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-18 16:10:16,303 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 710 transitions. [2018-11-18 16:10:16,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 698 [2018-11-18 16:10:16,306 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:16,306 INFO L375 BasicCegarLoop]: trace histogram [102, 91, 91, 90, 90, 90, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:16,306 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:16,306 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:16,307 INFO L82 PathProgramCache]: Analyzing trace with hash -1239819207, now seen corresponding path program 25 times [2018-11-18 16:10:16,307 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:16,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:16,307 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:16,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:16,307 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:16,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:16,709 INFO L134 CoverageAnalysis]: Checked inductivity of 27151 backedges. 7115 proven. 456 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-11-18 16:10:16,710 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:16,710 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:16,710 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:16,710 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:16,710 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:16,710 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:16,716 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:16,716 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:16,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:16,823 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:17,252 INFO L134 CoverageAnalysis]: Checked inductivity of 27151 backedges. 7153 proven. 418 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-11-18 16:10:17,252 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:17,579 INFO L134 CoverageAnalysis]: Checked inductivity of 27151 backedges. 7153 proven. 418 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-11-18 16:10:17,594 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:17,595 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29, 29] total 45 [2018-11-18 16:10:17,595 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:17,595 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-11-18 16:10:17,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-11-18 16:10:17,596 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=466, Invalid=1514, Unknown=0, NotChecked=0, Total=1980 [2018-11-18 16:10:17,596 INFO L87 Difference]: Start difference. First operand 707 states and 710 transitions. Second operand 45 states. [2018-11-18 16:10:18,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:18,125 INFO L93 Difference]: Finished difference Result 808 states and 812 transitions. [2018-11-18 16:10:18,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-18 16:10:18,125 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 697 [2018-11-18 16:10:18,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:18,126 INFO L225 Difference]: With dead ends: 808 [2018-11-18 16:10:18,126 INFO L226 Difference]: Without dead ends: 808 [2018-11-18 16:10:18,126 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1448 GetRequests, 1353 SyntacticMatches, 27 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1483 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1263, Invalid=3567, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 16:10:18,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-11-18 16:10:18,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 798. [2018-11-18 16:10:18,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 798 states. [2018-11-18 16:10:18,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 798 states to 798 states and 802 transitions. [2018-11-18 16:10:18,132 INFO L78 Accepts]: Start accepts. Automaton has 798 states and 802 transitions. Word has length 697 [2018-11-18 16:10:18,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:18,132 INFO L480 AbstractCegarLoop]: Abstraction has 798 states and 802 transitions. [2018-11-18 16:10:18,132 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-11-18 16:10:18,132 INFO L276 IsEmpty]: Start isEmpty. Operand 798 states and 802 transitions. [2018-11-18 16:10:18,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 783 [2018-11-18 16:10:18,137 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:18,137 INFO L375 BasicCegarLoop]: trace histogram [115, 103, 103, 102, 102, 102, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:18,137 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:18,139 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:18,139 INFO L82 PathProgramCache]: Analyzing trace with hash 1031851214, now seen corresponding path program 26 times [2018-11-18 16:10:18,139 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:18,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:18,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:18,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:18,140 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:18,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:18,732 INFO L134 CoverageAnalysis]: Checked inductivity of 34692 backedges. 18319 proven. 1437 refuted. 0 times theorem prover too weak. 14936 trivial. 0 not checked. [2018-11-18 16:10:18,732 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:18,732 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:18,732 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:18,732 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:18,732 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:18,732 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:18,739 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:18,739 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:18,925 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-11-18 16:10:18,925 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:18,931 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:19,564 INFO L134 CoverageAnalysis]: Checked inductivity of 34692 backedges. 13275 proven. 1408 refuted. 0 times theorem prover too weak. 20009 trivial. 0 not checked. [2018-11-18 16:10:19,564 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:20,422 INFO L134 CoverageAnalysis]: Checked inductivity of 34692 backedges. 13275 proven. 1408 refuted. 0 times theorem prover too weak. 20009 trivial. 0 not checked. [2018-11-18 16:10:20,437 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:20,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 33, 33] total 89 [2018-11-18 16:10:20,437 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:20,438 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-18 16:10:20,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-18 16:10:20,438 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1063, Invalid=6769, Unknown=0, NotChecked=0, Total=7832 [2018-11-18 16:10:20,438 INFO L87 Difference]: Start difference. First operand 798 states and 802 transitions. Second operand 62 states. [2018-11-18 16:10:22,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:22,052 INFO L93 Difference]: Finished difference Result 813 states and 815 transitions. [2018-11-18 16:10:22,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-11-18 16:10:22,052 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 782 [2018-11-18 16:10:22,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:22,053 INFO L225 Difference]: With dead ends: 813 [2018-11-18 16:10:22,054 INFO L226 Difference]: Without dead ends: 807 [2018-11-18 16:10:22,055 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1652 GetRequests, 1504 SyntacticMatches, 5 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6619 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3479, Invalid=17401, Unknown=0, NotChecked=0, Total=20880 [2018-11-18 16:10:22,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states. [2018-11-18 16:10:22,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 798. [2018-11-18 16:10:22,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 798 states. [2018-11-18 16:10:22,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 798 states to 798 states and 800 transitions. [2018-11-18 16:10:22,063 INFO L78 Accepts]: Start accepts. Automaton has 798 states and 800 transitions. Word has length 782 [2018-11-18 16:10:22,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:22,063 INFO L480 AbstractCegarLoop]: Abstraction has 798 states and 800 transitions. [2018-11-18 16:10:22,063 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-18 16:10:22,063 INFO L276 IsEmpty]: Start isEmpty. Operand 798 states and 800 transitions. [2018-11-18 16:10:22,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2018-11-18 16:10:22,066 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:22,066 INFO L375 BasicCegarLoop]: trace histogram [116, 104, 104, 103, 103, 103, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:22,066 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:22,067 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:22,067 INFO L82 PathProgramCache]: Analyzing trace with hash 290635974, now seen corresponding path program 27 times [2018-11-18 16:10:22,067 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:22,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:22,067 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:22,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:22,067 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:22,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:22,621 INFO L134 CoverageAnalysis]: Checked inductivity of 35332 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27084 trivial. 0 not checked. [2018-11-18 16:10:22,621 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:22,621 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:22,621 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:22,622 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:22,622 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:22,622 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:22,631 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:22,631 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:22,785 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:22,785 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:22,793 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:22,795 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:10:22,797 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:10:22,800 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:10:22,801 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:10:22,806 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:10:22,813 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:10:22,813 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:10:23,702 INFO L134 CoverageAnalysis]: Checked inductivity of 35332 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27084 trivial. 0 not checked. [2018-11-18 16:10:23,702 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:24,286 INFO L134 CoverageAnalysis]: Checked inductivity of 35332 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27084 trivial. 0 not checked. [2018-11-18 16:10:24,302 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:24,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 17] total 48 [2018-11-18 16:10:24,303 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:24,303 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-18 16:10:24,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-18 16:10:24,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=534, Invalid=1818, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 16:10:24,303 INFO L87 Difference]: Start difference. First operand 798 states and 800 transitions. Second operand 33 states. [2018-11-18 16:10:24,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:24,951 INFO L93 Difference]: Finished difference Result 812 states and 815 transitions. [2018-11-18 16:10:24,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-18 16:10:24,951 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 788 [2018-11-18 16:10:24,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:24,953 INFO L225 Difference]: With dead ends: 812 [2018-11-18 16:10:24,953 INFO L226 Difference]: Without dead ends: 812 [2018-11-18 16:10:24,954 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1607 GetRequests, 1520 SyntacticMatches, 26 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1246 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=932, Invalid=2974, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 16:10:24,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states. [2018-11-18 16:10:24,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 804. [2018-11-18 16:10:24,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 804 states. [2018-11-18 16:10:24,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 804 states to 804 states and 807 transitions. [2018-11-18 16:10:24,959 INFO L78 Accepts]: Start accepts. Automaton has 804 states and 807 transitions. Word has length 788 [2018-11-18 16:10:24,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:24,960 INFO L480 AbstractCegarLoop]: Abstraction has 804 states and 807 transitions. [2018-11-18 16:10:24,960 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-18 16:10:24,960 INFO L276 IsEmpty]: Start isEmpty. Operand 804 states and 807 transitions. [2018-11-18 16:10:24,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 795 [2018-11-18 16:10:24,964 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:24,964 INFO L375 BasicCegarLoop]: trace histogram [117, 105, 105, 104, 104, 104, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:24,964 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:24,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:24,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1768348658, now seen corresponding path program 28 times [2018-11-18 16:10:24,964 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:24,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:24,965 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:24,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:24,965 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:24,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:25,407 INFO L134 CoverageAnalysis]: Checked inductivity of 35978 backedges. 8853 proven. 539 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-11-18 16:10:25,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:25,407 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:25,407 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:25,407 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:25,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:25,407 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:25,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:25,415 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:25,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:25,522 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:25,990 INFO L134 CoverageAnalysis]: Checked inductivity of 35978 backedges. 8894 proven. 498 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-11-18 16:10:25,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:26,381 INFO L134 CoverageAnalysis]: Checked inductivity of 35978 backedges. 8894 proven. 498 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-11-18 16:10:26,396 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:26,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 31, 31] total 48 [2018-11-18 16:10:26,397 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:26,397 INFO L459 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-11-18 16:10:26,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-11-18 16:10:26,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=529, Invalid=1727, Unknown=0, NotChecked=0, Total=2256 [2018-11-18 16:10:26,398 INFO L87 Difference]: Start difference. First operand 804 states and 807 transitions. Second operand 48 states. [2018-11-18 16:10:27,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:27,155 INFO L93 Difference]: Finished difference Result 911 states and 915 transitions. [2018-11-18 16:10:27,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-11-18 16:10:27,155 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 794 [2018-11-18 16:10:27,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:27,158 INFO L225 Difference]: With dead ends: 911 [2018-11-18 16:10:27,158 INFO L226 Difference]: Without dead ends: 911 [2018-11-18 16:10:27,158 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1646 GetRequests, 1544 SyntacticMatches, 29 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1710 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1444, Invalid=4106, Unknown=0, NotChecked=0, Total=5550 [2018-11-18 16:10:27,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 911 states. [2018-11-18 16:10:27,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 911 to 901. [2018-11-18 16:10:27,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 901 states. [2018-11-18 16:10:27,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 901 states to 901 states and 905 transitions. [2018-11-18 16:10:27,165 INFO L78 Accepts]: Start accepts. Automaton has 901 states and 905 transitions. Word has length 794 [2018-11-18 16:10:27,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:27,165 INFO L480 AbstractCegarLoop]: Abstraction has 901 states and 905 transitions. [2018-11-18 16:10:27,166 INFO L481 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-11-18 16:10:27,166 INFO L276 IsEmpty]: Start isEmpty. Operand 901 states and 905 transitions. [2018-11-18 16:10:27,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 886 [2018-11-18 16:10:27,170 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:27,171 INFO L375 BasicCegarLoop]: trace histogram [131, 118, 118, 117, 117, 117, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:27,171 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:27,171 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:27,171 INFO L82 PathProgramCache]: Analyzing trace with hash 389655841, now seen corresponding path program 29 times [2018-11-18 16:10:27,171 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:27,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:27,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:27,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:27,172 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:27,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:27,722 INFO L134 CoverageAnalysis]: Checked inductivity of 45318 backedges. 17406 proven. 2594 refuted. 0 times theorem prover too weak. 25318 trivial. 0 not checked. [2018-11-18 16:10:27,722 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:27,722 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:27,722 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:27,722 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:27,722 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:27,722 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:27,729 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:27,729 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:27,921 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-11-18 16:10:27,921 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:27,927 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:28,655 INFO L134 CoverageAnalysis]: Checked inductivity of 45318 backedges. 16580 proven. 1642 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-18 16:10:28,655 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:29,644 INFO L134 CoverageAnalysis]: Checked inductivity of 45318 backedges. 16580 proven. 1642 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-18 16:10:29,660 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:29,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 35, 35] total 95 [2018-11-18 16:10:29,660 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:29,661 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-11-18 16:10:29,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-11-18 16:10:29,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1203, Invalid=7727, Unknown=0, NotChecked=0, Total=8930 [2018-11-18 16:10:29,662 INFO L87 Difference]: Start difference. First operand 901 states and 905 transitions. Second operand 66 states. [2018-11-18 16:10:31,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:31,553 INFO L93 Difference]: Finished difference Result 916 states and 918 transitions. [2018-11-18 16:10:31,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2018-11-18 16:10:31,553 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 885 [2018-11-18 16:10:31,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:31,554 INFO L225 Difference]: With dead ends: 916 [2018-11-18 16:10:31,555 INFO L226 Difference]: Without dead ends: 910 [2018-11-18 16:10:31,555 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1875 GetRequests, 1706 SyntacticMatches, 5 SemanticMatches, 164 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9218 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=3917, Invalid=23473, Unknown=0, NotChecked=0, Total=27390 [2018-11-18 16:10:31,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 910 states. [2018-11-18 16:10:31,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 910 to 901. [2018-11-18 16:10:31,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 901 states. [2018-11-18 16:10:31,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 901 states to 901 states and 903 transitions. [2018-11-18 16:10:31,560 INFO L78 Accepts]: Start accepts. Automaton has 901 states and 903 transitions. Word has length 885 [2018-11-18 16:10:31,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:31,561 INFO L480 AbstractCegarLoop]: Abstraction has 901 states and 903 transitions. [2018-11-18 16:10:31,561 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-11-18 16:10:31,561 INFO L276 IsEmpty]: Start isEmpty. Operand 901 states and 903 transitions. [2018-11-18 16:10:31,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 892 [2018-11-18 16:10:31,566 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:31,567 INFO L375 BasicCegarLoop]: trace histogram [132, 119, 119, 118, 118, 118, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:31,567 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:31,567 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:31,567 INFO L82 PathProgramCache]: Analyzing trace with hash 1383142105, now seen corresponding path program 30 times [2018-11-18 16:10:31,567 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:31,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:31,568 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:31,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:31,568 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:31,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:32,196 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 16:10:32,196 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:32,196 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:32,196 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:32,196 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:32,196 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:32,196 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:32,205 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:32,205 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:32,385 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:32,385 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:32,394 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:32,396 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:10:32,405 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:10:32,409 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:10:32,409 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:10:32,414 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:10:32,420 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:10:32,420 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:10:33,479 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 16:10:33,479 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:34,396 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 16:10:34,414 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:34,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 18] total 51 [2018-11-18 16:10:34,414 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:34,415 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-18 16:10:34,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-18 16:10:34,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=601, Invalid=2051, Unknown=0, NotChecked=0, Total=2652 [2018-11-18 16:10:34,415 INFO L87 Difference]: Start difference. First operand 901 states and 903 transitions. Second operand 35 states. [2018-11-18 16:10:35,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:35,127 INFO L93 Difference]: Finished difference Result 915 states and 918 transitions. [2018-11-18 16:10:35,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-18 16:10:35,127 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 891 [2018-11-18 16:10:35,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:35,129 INFO L225 Difference]: With dead ends: 915 [2018-11-18 16:10:35,129 INFO L226 Difference]: Without dead ends: 915 [2018-11-18 16:10:35,129 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1815 GetRequests, 1722 SyntacticMatches, 28 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1425 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1050, Invalid=3372, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 16:10:35,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 915 states. [2018-11-18 16:10:35,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 915 to 907. [2018-11-18 16:10:35,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 907 states. [2018-11-18 16:10:35,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 907 states to 907 states and 910 transitions. [2018-11-18 16:10:35,134 INFO L78 Accepts]: Start accepts. Automaton has 907 states and 910 transitions. Word has length 891 [2018-11-18 16:10:35,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:35,134 INFO L480 AbstractCegarLoop]: Abstraction has 907 states and 910 transitions. [2018-11-18 16:10:35,134 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-18 16:10:35,134 INFO L276 IsEmpty]: Start isEmpty. Operand 907 states and 910 transitions. [2018-11-18 16:10:35,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 898 [2018-11-18 16:10:35,138 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:35,138 INFO L375 BasicCegarLoop]: trace histogram [133, 120, 120, 119, 119, 119, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:35,138 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:35,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:35,138 INFO L82 PathProgramCache]: Analyzing trace with hash -1253549087, now seen corresponding path program 31 times [2018-11-18 16:10:35,138 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:35,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:35,139 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:35,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:35,139 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:35,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:35,669 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10851 proven. 629 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-11-18 16:10:35,669 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:35,670 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:35,670 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:35,670 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:35,670 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:35,670 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:35,678 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:35,678 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:35,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:35,802 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:36,313 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10895 proven. 585 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-11-18 16:10:36,313 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:36,780 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10895 proven. 585 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-11-18 16:10:36,795 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:36,796 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33, 33] total 51 [2018-11-18 16:10:36,796 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:36,796 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-11-18 16:10:36,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-11-18 16:10:36,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=596, Invalid=1954, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 16:10:36,797 INFO L87 Difference]: Start difference. First operand 907 states and 910 transitions. Second operand 51 states. [2018-11-18 16:10:37,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:37,475 INFO L93 Difference]: Finished difference Result 1020 states and 1024 transitions. [2018-11-18 16:10:37,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-18 16:10:37,476 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 897 [2018-11-18 16:10:37,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:37,477 INFO L225 Difference]: With dead ends: 1020 [2018-11-18 16:10:37,477 INFO L226 Difference]: Without dead ends: 1020 [2018-11-18 16:10:37,478 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1856 GetRequests, 1747 SyntacticMatches, 31 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1953 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1637, Invalid=4683, Unknown=0, NotChecked=0, Total=6320 [2018-11-18 16:10:37,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1020 states. [2018-11-18 16:10:37,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1020 to 1010. [2018-11-18 16:10:37,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1010 states. [2018-11-18 16:10:37,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1010 states to 1010 states and 1014 transitions. [2018-11-18 16:10:37,483 INFO L78 Accepts]: Start accepts. Automaton has 1010 states and 1014 transitions. Word has length 897 [2018-11-18 16:10:37,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:37,484 INFO L480 AbstractCegarLoop]: Abstraction has 1010 states and 1014 transitions. [2018-11-18 16:10:37,484 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-11-18 16:10:37,484 INFO L276 IsEmpty]: Start isEmpty. Operand 1010 states and 1014 transitions. [2018-11-18 16:10:37,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 995 [2018-11-18 16:10:37,490 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:37,490 INFO L375 BasicCegarLoop]: trace histogram [148, 134, 134, 133, 133, 133, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:37,490 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:37,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:37,490 INFO L82 PathProgramCache]: Analyzing trace with hash 620594870, now seen corresponding path program 32 times [2018-11-18 16:10:37,491 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:37,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:37,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:37,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:37,491 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:37,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:38,247 INFO L134 CoverageAnalysis]: Checked inductivity of 58191 backedges. 11554 proven. 690 refuted. 0 times theorem prover too weak. 45947 trivial. 0 not checked. [2018-11-18 16:10:38,247 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:38,247 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:38,247 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:38,247 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:38,247 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:38,248 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:38,268 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:38,268 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:38,470 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-11-18 16:10:38,470 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:38,477 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:39,290 INFO L134 CoverageAnalysis]: Checked inductivity of 58191 backedges. 20391 proven. 1894 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 16:10:39,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:40,501 INFO L134 CoverageAnalysis]: Checked inductivity of 58191 backedges. 20391 proven. 1894 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 16:10:40,517 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:40,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 37, 37] total 87 [2018-11-18 16:10:40,518 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:40,519 INFO L459 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-11-18 16:10:40,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-11-18 16:10:40,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1016, Invalid=6466, Unknown=0, NotChecked=0, Total=7482 [2018-11-18 16:10:40,519 INFO L87 Difference]: Start difference. First operand 1010 states and 1014 transitions. Second operand 56 states. [2018-11-18 16:10:42,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:42,700 INFO L93 Difference]: Finished difference Result 1140 states and 1146 transitions. [2018-11-18 16:10:42,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-11-18 16:10:42,700 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 994 [2018-11-18 16:10:42,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:42,702 INFO L225 Difference]: With dead ends: 1140 [2018-11-18 16:10:42,702 INFO L226 Difference]: Without dead ends: 1140 [2018-11-18 16:10:42,703 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2060 GetRequests, 1917 SyntacticMatches, 5 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5116 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=3566, Invalid=15894, Unknown=0, NotChecked=0, Total=19460 [2018-11-18 16:10:42,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1140 states. [2018-11-18 16:10:42,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1140 to 1022. [2018-11-18 16:10:42,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1022 states. [2018-11-18 16:10:42,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1022 states to 1022 states and 1027 transitions. [2018-11-18 16:10:42,709 INFO L78 Accepts]: Start accepts. Automaton has 1022 states and 1027 transitions. Word has length 994 [2018-11-18 16:10:42,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:42,710 INFO L480 AbstractCegarLoop]: Abstraction has 1022 states and 1027 transitions. [2018-11-18 16:10:42,710 INFO L481 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-11-18 16:10:42,710 INFO L276 IsEmpty]: Start isEmpty. Operand 1022 states and 1027 transitions. [2018-11-18 16:10:42,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1007 [2018-11-18 16:10:42,715 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:42,715 INFO L375 BasicCegarLoop]: trace histogram [150, 136, 136, 135, 135, 135, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:42,715 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:42,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:42,716 INFO L82 PathProgramCache]: Analyzing trace with hash -1447052810, now seen corresponding path program 33 times [2018-11-18 16:10:42,716 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:42,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:42,716 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:42,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:42,717 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:42,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:43,476 INFO L134 CoverageAnalysis]: Checked inductivity of 59857 backedges. 12390 proven. 784 refuted. 0 times theorem prover too weak. 46683 trivial. 0 not checked. [2018-11-18 16:10:43,477 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:43,477 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:43,477 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:43,477 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:43,477 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:43,477 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:43,486 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:43,486 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:43,601 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:43,601 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:43,609 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:44,437 INFO L134 CoverageAnalysis]: Checked inductivity of 59857 backedges. 12986 proven. 2632 refuted. 0 times theorem prover too weak. 44239 trivial. 0 not checked. [2018-11-18 16:10:44,437 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:45,344 INFO L134 CoverageAnalysis]: Checked inductivity of 59857 backedges. 12986 proven. 2632 refuted. 0 times theorem prover too weak. 44239 trivial. 0 not checked. [2018-11-18 16:10:45,359 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:45,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 39, 39] total 79 [2018-11-18 16:10:45,359 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:45,360 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-11-18 16:10:45,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-11-18 16:10:45,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=839, Invalid=5323, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:10:45,360 INFO L87 Difference]: Start difference. First operand 1022 states and 1027 transitions. Second operand 59 states. [2018-11-18 16:10:47,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:47,657 INFO L93 Difference]: Finished difference Result 1275 states and 1286 transitions. [2018-11-18 16:10:47,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-11-18 16:10:47,657 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 1006 [2018-11-18 16:10:47,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:47,660 INFO L225 Difference]: With dead ends: 1275 [2018-11-18 16:10:47,660 INFO L226 Difference]: Without dead ends: 1275 [2018-11-18 16:10:47,661 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2104 GetRequests, 1952 SyntacticMatches, 18 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5138 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=2457, Invalid=15903, Unknown=0, NotChecked=0, Total=18360 [2018-11-18 16:10:47,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1275 states. [2018-11-18 16:10:47,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1275 to 1253. [2018-11-18 16:10:47,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1253 states. [2018-11-18 16:10:47,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 1264 transitions. [2018-11-18 16:10:47,671 INFO L78 Accepts]: Start accepts. Automaton has 1253 states and 1264 transitions. Word has length 1006 [2018-11-18 16:10:47,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:47,672 INFO L480 AbstractCegarLoop]: Abstraction has 1253 states and 1264 transitions. [2018-11-18 16:10:47,672 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-11-18 16:10:47,672 INFO L276 IsEmpty]: Start isEmpty. Operand 1253 states and 1264 transitions. [2018-11-18 16:10:47,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1110 [2018-11-18 16:10:47,679 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:47,680 INFO L375 BasicCegarLoop]: trace histogram [166, 151, 151, 150, 150, 150, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:47,680 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:47,680 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:47,680 INFO L82 PathProgramCache]: Analyzing trace with hash 1762371657, now seen corresponding path program 34 times [2018-11-18 16:10:47,681 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:47,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:47,681 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:47,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:47,681 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:47,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:48,397 INFO L134 CoverageAnalysis]: Checked inductivity of 73605 backedges. 24561 proven. 4619 refuted. 0 times theorem prover too weak. 44425 trivial. 0 not checked. [2018-11-18 16:10:48,397 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:48,397 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:48,398 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:48,398 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:48,398 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:48,398 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:48,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:48,406 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:48,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:48,556 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:49,144 INFO L134 CoverageAnalysis]: Checked inductivity of 73605 backedges. 34532 proven. 574 refuted. 0 times theorem prover too weak. 38499 trivial. 0 not checked. [2018-11-18 16:10:49,144 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:49,986 INFO L134 CoverageAnalysis]: Checked inductivity of 73605 backedges. 24799 proven. 1897 refuted. 0 times theorem prover too weak. 46909 trivial. 0 not checked. [2018-11-18 16:10:50,002 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:50,002 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 32, 32] total 67 [2018-11-18 16:10:50,002 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:50,003 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-11-18 16:10:50,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-11-18 16:10:50,003 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=929, Invalid=3493, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 16:10:50,003 INFO L87 Difference]: Start difference. First operand 1253 states and 1264 transitions. Second operand 52 states. [2018-11-18 16:10:50,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:50,917 INFO L93 Difference]: Finished difference Result 1143 states and 1148 transitions. [2018-11-18 16:10:50,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-11-18 16:10:50,917 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 1109 [2018-11-18 16:10:50,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:50,920 INFO L225 Difference]: With dead ends: 1143 [2018-11-18 16:10:50,920 INFO L226 Difference]: Without dead ends: 1134 [2018-11-18 16:10:50,920 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2286 GetRequests, 2173 SyntacticMatches, 16 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3338 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2270, Invalid=7432, Unknown=0, NotChecked=0, Total=9702 [2018-11-18 16:10:50,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1134 states. [2018-11-18 16:10:50,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1134 to 1131. [2018-11-18 16:10:50,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1131 states. [2018-11-18 16:10:50,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 1131 states and 1136 transitions. [2018-11-18 16:10:50,928 INFO L78 Accepts]: Start accepts. Automaton has 1131 states and 1136 transitions. Word has length 1109 [2018-11-18 16:10:50,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:50,929 INFO L480 AbstractCegarLoop]: Abstraction has 1131 states and 1136 transitions. [2018-11-18 16:10:50,929 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-11-18 16:10:50,929 INFO L276 IsEmpty]: Start isEmpty. Operand 1131 states and 1136 transitions. [2018-11-18 16:10:50,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1116 [2018-11-18 16:10:50,941 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:50,941 INFO L375 BasicCegarLoop]: trace histogram [167, 152, 152, 151, 151, 151, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:50,941 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:50,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:50,942 INFO L82 PathProgramCache]: Analyzing trace with hash -511871151, now seen corresponding path program 35 times [2018-11-18 16:10:50,942 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:50,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:50,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:50,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:50,942 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:50,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:51,662 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 26719 proven. 3402 refuted. 0 times theorem prover too weak. 44418 trivial. 0 not checked. [2018-11-18 16:10:51,662 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:51,662 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:51,662 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:51,662 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:51,662 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:51,662 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:51,672 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:51,672 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:51,960 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-11-18 16:10:51,960 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:51,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:51,969 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:10:51,971 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:10:51,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:10:51,975 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:10:51,986 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:10:51,992 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:10:51,993 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:10:54,390 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 24672 proven. 2320 refuted. 0 times theorem prover too weak. 47547 trivial. 0 not checked. [2018-11-18 16:10:54,390 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:56,109 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 24571 proven. 2421 refuted. 0 times theorem prover too weak. 47547 trivial. 0 not checked. [2018-11-18 16:10:56,125 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:56,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 27, 25] total 88 [2018-11-18 16:10:56,125 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:56,126 INFO L459 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-11-18 16:10:56,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-11-18 16:10:56,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1146, Invalid=6510, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 16:10:56,126 INFO L87 Difference]: Start difference. First operand 1131 states and 1136 transitions. Second operand 64 states. [2018-11-18 16:10:59,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:59,517 INFO L93 Difference]: Finished difference Result 1144 states and 1147 transitions. [2018-11-18 16:10:59,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-11-18 16:10:59,517 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1115 [2018-11-18 16:10:59,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:59,519 INFO L225 Difference]: With dead ends: 1144 [2018-11-18 16:10:59,519 INFO L226 Difference]: Without dead ends: 1138 [2018-11-18 16:10:59,521 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2368 GetRequests, 2153 SyntacticMatches, 29 SemanticMatches, 186 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12710 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=6084, Invalid=29072, Unknown=0, NotChecked=0, Total=35156 [2018-11-18 16:10:59,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1138 states. [2018-11-18 16:10:59,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1138 to 1131. [2018-11-18 16:10:59,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1131 states. [2018-11-18 16:10:59,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 1131 states and 1134 transitions. [2018-11-18 16:10:59,528 INFO L78 Accepts]: Start accepts. Automaton has 1131 states and 1134 transitions. Word has length 1115 [2018-11-18 16:10:59,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:59,528 INFO L480 AbstractCegarLoop]: Abstraction has 1131 states and 1134 transitions. [2018-11-18 16:10:59,529 INFO L481 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-11-18 16:10:59,529 INFO L276 IsEmpty]: Start isEmpty. Operand 1131 states and 1134 transitions. [2018-11-18 16:10:59,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1122 [2018-11-18 16:10:59,535 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:59,535 INFO L375 BasicCegarLoop]: trace histogram [168, 153, 153, 152, 152, 152, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:59,535 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:10:59,535 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:59,536 INFO L82 PathProgramCache]: Analyzing trace with hash 1600859401, now seen corresponding path program 36 times [2018-11-18 16:10:59,536 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:59,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:59,536 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:59,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:59,536 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:59,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:00,278 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15699 proven. 830 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-11-18 16:11:00,278 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:00,278 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:00,278 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:00,278 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:00,278 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:00,278 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:00,288 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:00,288 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:00,416 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:00,416 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:00,425 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:01,199 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15550 proven. 2977 refuted. 0 times theorem prover too weak. 56952 trivial. 0 not checked. [2018-11-18 16:11:01,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:01,925 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15550 proven. 2977 refuted. 0 times theorem prover too weak. 56952 trivial. 0 not checked. [2018-11-18 16:11:01,940 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:01,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 41, 41] total 64 [2018-11-18 16:11:01,941 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:01,941 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-11-18 16:11:01,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-11-18 16:11:01,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=772, Invalid=3260, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 16:11:01,942 INFO L87 Difference]: Start difference. First operand 1131 states and 1134 transitions. Second operand 61 states. [2018-11-18 16:11:02,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:02,992 INFO L93 Difference]: Finished difference Result 1256 states and 1260 transitions. [2018-11-18 16:11:02,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-11-18 16:11:02,993 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 1121 [2018-11-18 16:11:02,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:02,996 INFO L225 Difference]: With dead ends: 1256 [2018-11-18 16:11:02,996 INFO L226 Difference]: Without dead ends: 1256 [2018-11-18 16:11:02,996 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2314 GetRequests, 2180 SyntacticMatches, 37 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3181 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=2058, Invalid=7644, Unknown=0, NotChecked=0, Total=9702 [2018-11-18 16:11:02,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1256 states. [2018-11-18 16:11:03,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1256 to 1246. [2018-11-18 16:11:03,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1246 states. [2018-11-18 16:11:03,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1246 states to 1246 states and 1250 transitions. [2018-11-18 16:11:03,004 INFO L78 Accepts]: Start accepts. Automaton has 1246 states and 1250 transitions. Word has length 1121 [2018-11-18 16:11:03,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:03,004 INFO L480 AbstractCegarLoop]: Abstraction has 1246 states and 1250 transitions. [2018-11-18 16:11:03,004 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-11-18 16:11:03,005 INFO L276 IsEmpty]: Start isEmpty. Operand 1246 states and 1250 transitions. [2018-11-18 16:11:03,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1231 [2018-11-18 16:11:03,015 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:03,015 INFO L375 BasicCegarLoop]: trace histogram [185, 169, 169, 168, 168, 168, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:03,015 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:03,015 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:03,016 INFO L82 PathProgramCache]: Analyzing trace with hash -779387106, now seen corresponding path program 37 times [2018-11-18 16:11:03,016 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:03,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:03,016 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:03,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:03,017 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:03,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:03,937 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 41783 proven. 2493 refuted. 0 times theorem prover too weak. 47596 trivial. 0 not checked. [2018-11-18 16:11:03,937 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:03,937 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:03,937 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:03,937 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:03,938 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:03,938 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:03,947 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:03,947 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:04,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:04,127 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:04,995 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 31271 proven. 752 refuted. 0 times theorem prover too weak. 59849 trivial. 0 not checked. [2018-11-18 16:11:04,995 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:06,092 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 31271 proven. 752 refuted. 0 times theorem prover too weak. 59849 trivial. 0 not checked. [2018-11-18 16:11:06,107 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:06,108 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 36, 36] total 88 [2018-11-18 16:11:06,108 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:06,109 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-11-18 16:11:06,109 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-11-18 16:11:06,110 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1313, Invalid=6343, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 16:11:06,110 INFO L87 Difference]: Start difference. First operand 1246 states and 1250 transitions. Second operand 71 states. [2018-11-18 16:11:07,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:07,879 INFO L93 Difference]: Finished difference Result 1257 states and 1259 transitions. [2018-11-18 16:11:07,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-18 16:11:07,879 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1230 [2018-11-18 16:11:07,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:07,882 INFO L225 Difference]: With dead ends: 1257 [2018-11-18 16:11:07,882 INFO L226 Difference]: Without dead ends: 1251 [2018-11-18 16:11:07,883 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2549 GetRequests, 2396 SyntacticMatches, 18 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7802 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3392, Invalid=15240, Unknown=0, NotChecked=0, Total=18632 [2018-11-18 16:11:07,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1251 states. [2018-11-18 16:11:07,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1251 to 1246. [2018-11-18 16:11:07,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1246 states. [2018-11-18 16:11:07,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1246 states to 1246 states and 1248 transitions. [2018-11-18 16:11:07,890 INFO L78 Accepts]: Start accepts. Automaton has 1246 states and 1248 transitions. Word has length 1230 [2018-11-18 16:11:07,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:07,891 INFO L480 AbstractCegarLoop]: Abstraction has 1246 states and 1248 transitions. [2018-11-18 16:11:07,891 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-11-18 16:11:07,891 INFO L276 IsEmpty]: Start isEmpty. Operand 1246 states and 1248 transitions. [2018-11-18 16:11:07,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1237 [2018-11-18 16:11:07,899 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:07,899 INFO L375 BasicCegarLoop]: trace histogram [186, 170, 170, 169, 169, 169, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:07,899 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:07,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:07,900 INFO L82 PathProgramCache]: Analyzing trace with hash 888497942, now seen corresponding path program 38 times [2018-11-18 16:11:07,900 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:07,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:07,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:07,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:07,900 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:07,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:08,894 INFO L134 CoverageAnalysis]: Checked inductivity of 92916 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75328 trivial. 0 not checked. [2018-11-18 16:11:08,894 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:08,894 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:08,895 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:08,895 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:08,895 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:08,895 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:08,902 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:08,902 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:09,160 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-11-18 16:11:09,160 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:09,169 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:09,171 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:11:09,174 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:11:09,177 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:11:09,178 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:11:09,190 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:11:09,196 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:11:09,196 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:11:10,945 INFO L134 CoverageAnalysis]: Checked inductivity of 92916 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75328 trivial. 0 not checked. [2018-11-18 16:11:10,945 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:12,250 INFO L134 CoverageAnalysis]: Checked inductivity of 92916 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75328 trivial. 0 not checked. [2018-11-18 16:11:12,266 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:12,266 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 22] total 45 [2018-11-18 16:11:12,266 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:12,267 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-18 16:11:12,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-18 16:11:12,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=793, Invalid=1277, Unknown=0, NotChecked=0, Total=2070 [2018-11-18 16:11:12,268 INFO L87 Difference]: Start difference. First operand 1246 states and 1248 transitions. Second operand 25 states. [2018-11-18 16:11:12,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:12,678 INFO L93 Difference]: Finished difference Result 1260 states and 1263 transitions. [2018-11-18 16:11:12,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-18 16:11:12,678 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 1236 [2018-11-18 16:11:12,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:12,680 INFO L225 Difference]: With dead ends: 1260 [2018-11-18 16:11:12,680 INFO L226 Difference]: Without dead ends: 1260 [2018-11-18 16:11:12,680 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2511 GetRequests, 2415 SyntacticMatches, 34 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 582 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1562, Invalid=2470, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 16:11:12,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1260 states. [2018-11-18 16:11:12,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1260 to 1252. [2018-11-18 16:11:12,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1252 states. [2018-11-18 16:11:12,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1252 states to 1252 states and 1255 transitions. [2018-11-18 16:11:12,687 INFO L78 Accepts]: Start accepts. Automaton has 1252 states and 1255 transitions. Word has length 1236 [2018-11-18 16:11:12,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:12,687 INFO L480 AbstractCegarLoop]: Abstraction has 1252 states and 1255 transitions. [2018-11-18 16:11:12,687 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-18 16:11:12,687 INFO L276 IsEmpty]: Start isEmpty. Operand 1252 states and 1255 transitions. [2018-11-18 16:11:12,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1243 [2018-11-18 16:11:12,694 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:12,694 INFO L375 BasicCegarLoop]: trace histogram [187, 171, 171, 170, 170, 170, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:12,694 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:12,694 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:12,694 INFO L82 PathProgramCache]: Analyzing trace with hash -887501218, now seen corresponding path program 39 times [2018-11-18 16:11:12,694 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:12,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:12,695 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:12,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:12,695 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:12,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:13,498 INFO L134 CoverageAnalysis]: Checked inductivity of 93966 backedges. 18585 proven. 941 refuted. 0 times theorem prover too weak. 74440 trivial. 0 not checked. [2018-11-18 16:11:13,499 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:13,499 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:13,499 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:13,499 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:13,499 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:13,499 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:13,509 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:13,509 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:13,674 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:13,674 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:13,683 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:14,572 INFO L134 CoverageAnalysis]: Checked inductivity of 93966 backedges. 18428 proven. 3343 refuted. 0 times theorem prover too weak. 72195 trivial. 0 not checked. [2018-11-18 16:11:14,572 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:15,419 INFO L134 CoverageAnalysis]: Checked inductivity of 93966 backedges. 18428 proven. 3343 refuted. 0 times theorem prover too weak. 72195 trivial. 0 not checked. [2018-11-18 16:11:15,435 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:15,435 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 43, 43] total 67 [2018-11-18 16:11:15,435 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:15,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-11-18 16:11:15,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-11-18 16:11:15,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=851, Invalid=3571, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 16:11:15,437 INFO L87 Difference]: Start difference. First operand 1252 states and 1255 transitions. Second operand 64 states. [2018-11-18 16:11:16,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:16,478 INFO L93 Difference]: Finished difference Result 1383 states and 1387 transitions. [2018-11-18 16:11:16,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-11-18 16:11:16,478 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1242 [2018-11-18 16:11:16,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:16,481 INFO L225 Difference]: With dead ends: 1383 [2018-11-18 16:11:16,481 INFO L226 Difference]: Without dead ends: 1383 [2018-11-18 16:11:16,482 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2560 GetRequests, 2419 SyntacticMatches, 39 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3513 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2282, Invalid=8430, Unknown=0, NotChecked=0, Total=10712 [2018-11-18 16:11:16,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1383 states. [2018-11-18 16:11:16,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1383 to 1373. [2018-11-18 16:11:16,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1373 states. [2018-11-18 16:11:16,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1373 states to 1373 states and 1377 transitions. [2018-11-18 16:11:16,490 INFO L78 Accepts]: Start accepts. Automaton has 1373 states and 1377 transitions. Word has length 1242 [2018-11-18 16:11:16,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:16,490 INFO L480 AbstractCegarLoop]: Abstraction has 1373 states and 1377 transitions. [2018-11-18 16:11:16,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-11-18 16:11:16,491 INFO L276 IsEmpty]: Start isEmpty. Operand 1373 states and 1377 transitions. [2018-11-18 16:11:16,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1358 [2018-11-18 16:11:16,499 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:16,499 INFO L375 BasicCegarLoop]: trace histogram [205, 188, 188, 187, 187, 187, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:16,500 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:16,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:16,500 INFO L82 PathProgramCache]: Analyzing trace with hash -1904678671, now seen corresponding path program 40 times [2018-11-18 16:11:16,500 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:16,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:16,501 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:16,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:16,501 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:16,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:17,511 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 36728 proven. 4314 refuted. 0 times theorem prover too weak. 72280 trivial. 0 not checked. [2018-11-18 16:11:17,511 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:17,512 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:17,512 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:17,512 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:17,512 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:17,512 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:17,520 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:17,520 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:17,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:17,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:18,524 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 37026 proven. 850 refuted. 0 times theorem prover too weak. 75446 trivial. 0 not checked. [2018-11-18 16:11:18,524 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:19,673 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 37026 proven. 850 refuted. 0 times theorem prover too weak. 75446 trivial. 0 not checked. [2018-11-18 16:11:19,689 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:19,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 38, 38] total 79 [2018-11-18 16:11:19,689 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:19,690 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-11-18 16:11:19,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-11-18 16:11:19,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1301, Invalid=4861, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:11:19,690 INFO L87 Difference]: Start difference. First operand 1373 states and 1377 transitions. Second operand 61 states. [2018-11-18 16:11:20,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:20,661 INFO L93 Difference]: Finished difference Result 1384 states and 1386 transitions. [2018-11-18 16:11:20,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-11-18 16:11:20,661 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 1357 [2018-11-18 16:11:20,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:20,664 INFO L225 Difference]: With dead ends: 1384 [2018-11-18 16:11:20,664 INFO L226 Difference]: Without dead ends: 1378 [2018-11-18 16:11:20,664 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2794 GetRequests, 2660 SyntacticMatches, 19 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4793 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3179, Invalid=10393, Unknown=0, NotChecked=0, Total=13572 [2018-11-18 16:11:20,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1378 states. [2018-11-18 16:11:20,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1378 to 1373. [2018-11-18 16:11:20,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1373 states. [2018-11-18 16:11:20,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1373 states to 1373 states and 1375 transitions. [2018-11-18 16:11:20,673 INFO L78 Accepts]: Start accepts. Automaton has 1373 states and 1375 transitions. Word has length 1357 [2018-11-18 16:11:20,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:20,674 INFO L480 AbstractCegarLoop]: Abstraction has 1373 states and 1375 transitions. [2018-11-18 16:11:20,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-11-18 16:11:20,674 INFO L276 IsEmpty]: Start isEmpty. Operand 1373 states and 1375 transitions. [2018-11-18 16:11:20,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1364 [2018-11-18 16:11:20,687 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:20,687 INFO L375 BasicCegarLoop]: trace histogram [206, 189, 189, 188, 188, 188, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:20,687 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:20,688 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:20,688 INFO L82 PathProgramCache]: Analyzing trace with hash -450420055, now seen corresponding path program 41 times [2018-11-18 16:11:20,688 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:20,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:20,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:20,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:20,689 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:20,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:21,804 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-11-18 16:11:21,804 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:21,804 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:21,804 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:21,804 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:21,804 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:21,804 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:21,814 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:21,814 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:22,166 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-11-18 16:11:22,166 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:22,176 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:22,178 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:11:22,182 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:11:22,190 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:11:22,191 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:11:22,196 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:11:22,206 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:11:22,206 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:11:24,327 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-11-18 16:11:24,327 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:25,791 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-11-18 16:11:25,806 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:25,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 23] total 47 [2018-11-18 16:11:25,807 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:25,807 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 16:11:25,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 16:11:25,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=863, Invalid=1393, Unknown=0, NotChecked=0, Total=2256 [2018-11-18 16:11:25,808 INFO L87 Difference]: Start difference. First operand 1373 states and 1375 transitions. Second operand 26 states. [2018-11-18 16:11:26,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:26,253 INFO L93 Difference]: Finished difference Result 1387 states and 1390 transitions. [2018-11-18 16:11:26,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-18 16:11:26,253 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 1363 [2018-11-18 16:11:26,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:26,255 INFO L225 Difference]: With dead ends: 1387 [2018-11-18 16:11:26,256 INFO L226 Difference]: Without dead ends: 1387 [2018-11-18 16:11:26,256 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2767 GetRequests, 2666 SyntacticMatches, 36 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 665 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1704, Invalid=2718, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 16:11:26,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1387 states. [2018-11-18 16:11:26,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1387 to 1379. [2018-11-18 16:11:26,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1379 states. [2018-11-18 16:11:26,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1379 states to 1379 states and 1382 transitions. [2018-11-18 16:11:26,265 INFO L78 Accepts]: Start accepts. Automaton has 1379 states and 1382 transitions. Word has length 1363 [2018-11-18 16:11:26,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:26,266 INFO L480 AbstractCegarLoop]: Abstraction has 1379 states and 1382 transitions. [2018-11-18 16:11:26,266 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 16:11:26,266 INFO L276 IsEmpty]: Start isEmpty. Operand 1379 states and 1382 transitions. [2018-11-18 16:11:26,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1370 [2018-11-18 16:11:26,273 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:26,273 INFO L375 BasicCegarLoop]: trace histogram [207, 190, 190, 189, 189, 189, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:26,273 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:26,274 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:26,274 INFO L82 PathProgramCache]: Analyzing trace with hash 1611091889, now seen corresponding path program 42 times [2018-11-18 16:11:26,274 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:26,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:26,274 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:26,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:26,274 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:26,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:27,268 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21803 proven. 1059 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-11-18 16:11:27,268 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:27,269 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:27,269 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:27,269 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:27,269 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:27,269 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:27,278 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:27,278 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:27,442 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:27,442 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:27,452 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:28,499 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21638 proven. 3730 refuted. 0 times theorem prover too weak. 90280 trivial. 0 not checked. [2018-11-18 16:11:28,499 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:29,429 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21638 proven. 3730 refuted. 0 times theorem prover too weak. 90280 trivial. 0 not checked. [2018-11-18 16:11:29,445 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:29,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 45, 45] total 70 [2018-11-18 16:11:29,445 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:29,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 16:11:29,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 16:11:29,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=934, Invalid=3896, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 16:11:29,447 INFO L87 Difference]: Start difference. First operand 1379 states and 1382 transitions. Second operand 67 states. [2018-11-18 16:11:30,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:30,609 INFO L93 Difference]: Finished difference Result 1516 states and 1520 transitions. [2018-11-18 16:11:30,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-18 16:11:30,609 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1369 [2018-11-18 16:11:30,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:30,613 INFO L225 Difference]: With dead ends: 1516 [2018-11-18 16:11:30,613 INFO L226 Difference]: Without dead ends: 1516 [2018-11-18 16:11:30,614 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2818 GetRequests, 2670 SyntacticMatches, 41 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3861 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2518, Invalid=9254, Unknown=0, NotChecked=0, Total=11772 [2018-11-18 16:11:30,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1516 states. [2018-11-18 16:11:30,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1516 to 1506. [2018-11-18 16:11:30,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1506 states. [2018-11-18 16:11:30,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1506 states to 1506 states and 1510 transitions. [2018-11-18 16:11:30,622 INFO L78 Accepts]: Start accepts. Automaton has 1506 states and 1510 transitions. Word has length 1369 [2018-11-18 16:11:30,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:30,623 INFO L480 AbstractCegarLoop]: Abstraction has 1506 states and 1510 transitions. [2018-11-18 16:11:30,623 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 16:11:30,623 INFO L276 IsEmpty]: Start isEmpty. Operand 1506 states and 1510 transitions. [2018-11-18 16:11:30,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1491 [2018-11-18 16:11:30,633 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:30,633 INFO L375 BasicCegarLoop]: trace histogram [226, 208, 208, 207, 207, 207, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:30,633 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:30,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:30,634 INFO L82 PathProgramCache]: Analyzing trace with hash 456029702, now seen corresponding path program 43 times [2018-11-18 16:11:30,634 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:30,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:30,634 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:30,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:30,635 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:30,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:31,854 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 58711 proven. 3129 refuted. 0 times theorem prover too weak. 76463 trivial. 0 not checked. [2018-11-18 16:11:31,854 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:31,854 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:31,854 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:31,854 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:31,854 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:31,854 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:31,865 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:31,865 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:32,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:32,064 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:33,255 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 43444 proven. 954 refuted. 0 times theorem prover too weak. 93905 trivial. 0 not checked. [2018-11-18 16:11:33,255 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:34,733 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 43444 proven. 954 refuted. 0 times theorem prover too weak. 93905 trivial. 0 not checked. [2018-11-18 16:11:34,749 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:34,749 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 40, 40] total 98 [2018-11-18 16:11:34,750 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:34,751 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-11-18 16:11:34,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-11-18 16:11:34,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1619, Invalid=7887, Unknown=0, NotChecked=0, Total=9506 [2018-11-18 16:11:34,751 INFO L87 Difference]: Start difference. First operand 1506 states and 1510 transitions. Second operand 79 states. [2018-11-18 16:11:36,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:36,603 INFO L93 Difference]: Finished difference Result 1517 states and 1519 transitions. [2018-11-18 16:11:36,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-11-18 16:11:36,604 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1490 [2018-11-18 16:11:36,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:36,607 INFO L225 Difference]: With dead ends: 1517 [2018-11-18 16:11:36,607 INFO L226 Difference]: Without dead ends: 1511 [2018-11-18 16:11:36,608 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3079 GetRequests, 2908 SyntacticMatches, 20 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9896 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=4191, Invalid=19065, Unknown=0, NotChecked=0, Total=23256 [2018-11-18 16:11:36,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1511 states. [2018-11-18 16:11:36,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1511 to 1506. [2018-11-18 16:11:36,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1506 states. [2018-11-18 16:11:36,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1506 states to 1506 states and 1508 transitions. [2018-11-18 16:11:36,617 INFO L78 Accepts]: Start accepts. Automaton has 1506 states and 1508 transitions. Word has length 1490 [2018-11-18 16:11:36,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:36,617 INFO L480 AbstractCegarLoop]: Abstraction has 1506 states and 1508 transitions. [2018-11-18 16:11:36,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-11-18 16:11:36,617 INFO L276 IsEmpty]: Start isEmpty. Operand 1506 states and 1508 transitions. [2018-11-18 16:11:36,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1497 [2018-11-18 16:11:36,626 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:36,626 INFO L375 BasicCegarLoop]: trace histogram [227, 209, 209, 208, 208, 208, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:36,626 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:36,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:36,627 INFO L82 PathProgramCache]: Analyzing trace with hash -75954178, now seen corresponding path program 44 times [2018-11-18 16:11:36,627 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:36,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:36,627 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:36,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:36,627 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:36,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:37,891 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-11-18 16:11:37,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:37,891 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:37,891 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:37,891 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:37,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:37,891 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:37,899 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:37,899 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:38,280 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-11-18 16:11:38,280 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:38,290 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:38,292 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:11:38,294 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:11:38,306 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:11:38,307 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:11:38,319 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:11:38,327 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:11:38,327 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:11:40,778 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-11-18 16:11:40,779 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:42,429 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-11-18 16:11:42,445 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:42,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 24] total 49 [2018-11-18 16:11:42,445 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:42,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-18 16:11:42,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-18 16:11:42,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=933, Invalid=1517, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 16:11:42,447 INFO L87 Difference]: Start difference. First operand 1506 states and 1508 transitions. Second operand 27 states. [2018-11-18 16:11:42,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:42,913 INFO L93 Difference]: Finished difference Result 1520 states and 1523 transitions. [2018-11-18 16:11:42,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-18 16:11:42,913 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 1496 [2018-11-18 16:11:42,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:42,916 INFO L225 Difference]: With dead ends: 1520 [2018-11-18 16:11:42,917 INFO L226 Difference]: Without dead ends: 1520 [2018-11-18 16:11:42,917 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3035 GetRequests, 2929 SyntacticMatches, 38 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 757 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1846, Invalid=2984, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 16:11:42,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1520 states. [2018-11-18 16:11:42,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1520 to 1512. [2018-11-18 16:11:42,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1512 states. [2018-11-18 16:11:42,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 1515 transitions. [2018-11-18 16:11:42,925 INFO L78 Accepts]: Start accepts. Automaton has 1512 states and 1515 transitions. Word has length 1496 [2018-11-18 16:11:42,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:42,925 INFO L480 AbstractCegarLoop]: Abstraction has 1512 states and 1515 transitions. [2018-11-18 16:11:42,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-18 16:11:42,925 INFO L276 IsEmpty]: Start isEmpty. Operand 1512 states and 1515 transitions. [2018-11-18 16:11:42,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1503 [2018-11-18 16:11:42,934 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:42,934 INFO L375 BasicCegarLoop]: trace histogram [228, 210, 210, 209, 209, 209, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:42,934 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:42,935 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:42,935 INFO L82 PathProgramCache]: Analyzing trace with hash 957030726, now seen corresponding path program 45 times [2018-11-18 16:11:42,935 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:42,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:42,935 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:42,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:42,935 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:43,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:43,996 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25371 proven. 1184 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-11-18 16:11:43,997 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:43,997 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:43,997 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:43,997 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:43,997 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:43,997 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:44,020 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:44,020 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:44,207 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:44,207 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:44,218 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:45,389 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25198 proven. 4138 refuted. 0 times theorem prover too weak. 111537 trivial. 0 not checked. [2018-11-18 16:11:45,390 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:46,459 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25198 proven. 4138 refuted. 0 times theorem prover too weak. 111537 trivial. 0 not checked. [2018-11-18 16:11:46,475 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:46,475 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 47, 47] total 73 [2018-11-18 16:11:46,475 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:46,476 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-18 16:11:46,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-18 16:11:46,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1021, Invalid=4235, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 16:11:46,476 INFO L87 Difference]: Start difference. First operand 1512 states and 1515 transitions. Second operand 70 states. [2018-11-18 16:11:47,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:47,659 INFO L93 Difference]: Finished difference Result 1655 states and 1659 transitions. [2018-11-18 16:11:47,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-18 16:11:47,660 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1502 [2018-11-18 16:11:47,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:47,662 INFO L225 Difference]: With dead ends: 1655 [2018-11-18 16:11:47,662 INFO L226 Difference]: Without dead ends: 1655 [2018-11-18 16:11:47,663 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3088 GetRequests, 2933 SyntacticMatches, 43 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4225 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2766, Invalid=10116, Unknown=0, NotChecked=0, Total=12882 [2018-11-18 16:11:47,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2018-11-18 16:11:47,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1645. [2018-11-18 16:11:47,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2018-11-18 16:11:47,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 1649 transitions. [2018-11-18 16:11:47,673 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 1649 transitions. Word has length 1502 [2018-11-18 16:11:47,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:47,674 INFO L480 AbstractCegarLoop]: Abstraction has 1645 states and 1649 transitions. [2018-11-18 16:11:47,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-18 16:11:47,675 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 1649 transitions. [2018-11-18 16:11:47,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1630 [2018-11-18 16:11:47,687 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:47,687 INFO L375 BasicCegarLoop]: trace histogram [248, 229, 229, 228, 228, 228, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:47,687 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:47,687 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:47,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1144954599, now seen corresponding path program 46 times [2018-11-18 16:11:47,687 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:47,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:47,688 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:47,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:47,688 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:47,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:48,993 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 50223 proven. 5330 refuted. 0 times theorem prover too weak. 111628 trivial. 0 not checked. [2018-11-18 16:11:48,993 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:48,993 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:48,993 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:48,993 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:48,993 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:48,993 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:49,002 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:49,002 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:49,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:49,237 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:50,310 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 50561 proven. 1064 refuted. 0 times theorem prover too weak. 115556 trivial. 0 not checked. [2018-11-18 16:11:50,311 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:51,761 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 50561 proven. 1064 refuted. 0 times theorem prover too weak. 115556 trivial. 0 not checked. [2018-11-18 16:11:51,777 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:51,778 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 42, 42] total 87 [2018-11-18 16:11:51,778 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:51,779 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 16:11:51,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 16:11:51,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1584, Invalid=5898, Unknown=0, NotChecked=0, Total=7482 [2018-11-18 16:11:51,779 INFO L87 Difference]: Start difference. First operand 1645 states and 1649 transitions. Second operand 67 states. [2018-11-18 16:11:53,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:53,087 INFO L93 Difference]: Finished difference Result 1656 states and 1658 transitions. [2018-11-18 16:11:53,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-11-18 16:11:53,087 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1629 [2018-11-18 16:11:53,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:53,090 INFO L225 Difference]: With dead ends: 1656 [2018-11-18 16:11:53,090 INFO L226 Difference]: Without dead ends: 1650 [2018-11-18 16:11:53,091 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3346 GetRequests, 3198 SyntacticMatches, 21 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5908 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3870, Invalid=12642, Unknown=0, NotChecked=0, Total=16512 [2018-11-18 16:11:53,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1650 states. [2018-11-18 16:11:53,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1650 to 1645. [2018-11-18 16:11:53,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2018-11-18 16:11:53,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 1647 transitions. [2018-11-18 16:11:53,100 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 1647 transitions. Word has length 1629 [2018-11-18 16:11:53,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:53,100 INFO L480 AbstractCegarLoop]: Abstraction has 1645 states and 1647 transitions. [2018-11-18 16:11:53,101 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 16:11:53,101 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 1647 transitions. [2018-11-18 16:11:53,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1636 [2018-11-18 16:11:53,111 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:53,111 INFO L375 BasicCegarLoop]: trace histogram [249, 230, 230, 229, 229, 229, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:53,111 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:11:53,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:53,112 INFO L82 PathProgramCache]: Analyzing trace with hash -1535093551, now seen corresponding path program 47 times [2018-11-18 16:11:53,112 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:53,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:53,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:53,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:53,112 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:53,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:54,589 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-11-18 16:11:54,590 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:54,590 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:54,590 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:54,590 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:54,590 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:54,590 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:54,599 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:54,599 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:54,999 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-11-18 16:11:54,999 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:55,010 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:55,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:11:55,021 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:11:55,027 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:11:55,028 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:11:55,033 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:11:55,039 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:11:55,039 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:11:57,722 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-11-18 16:11:57,722 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:59,606 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-11-18 16:11:59,622 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:59,623 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 25] total 51 [2018-11-18 16:11:59,623 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:59,623 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-18 16:11:59,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-18 16:11:59,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1003, Invalid=1649, Unknown=0, NotChecked=0, Total=2652 [2018-11-18 16:11:59,624 INFO L87 Difference]: Start difference. First operand 1645 states and 1647 transitions. Second operand 28 states. [2018-11-18 16:12:00,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:00,126 INFO L93 Difference]: Finished difference Result 1659 states and 1662 transitions. [2018-11-18 16:12:00,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-18 16:12:00,126 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 1635 [2018-11-18 16:12:00,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:00,128 INFO L225 Difference]: With dead ends: 1659 [2018-11-18 16:12:00,128 INFO L226 Difference]: Without dead ends: 1659 [2018-11-18 16:12:00,129 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3315 GetRequests, 3204 SyntacticMatches, 40 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 858 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1988, Invalid=3268, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 16:12:00,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1659 states. [2018-11-18 16:12:00,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1659 to 1651. [2018-11-18 16:12:00,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1651 states. [2018-11-18 16:12:00,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1651 states to 1651 states and 1654 transitions. [2018-11-18 16:12:00,137 INFO L78 Accepts]: Start accepts. Automaton has 1651 states and 1654 transitions. Word has length 1635 [2018-11-18 16:12:00,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:00,138 INFO L480 AbstractCegarLoop]: Abstraction has 1651 states and 1654 transitions. [2018-11-18 16:12:00,138 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-18 16:12:00,138 INFO L276 IsEmpty]: Start isEmpty. Operand 1651 states and 1654 transitions. [2018-11-18 16:12:00,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1642 [2018-11-18 16:12:00,148 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:00,148 INFO L375 BasicCegarLoop]: trace histogram [250, 231, 231, 230, 230, 230, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:00,148 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:00,149 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:00,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1272167463, now seen corresponding path program 48 times [2018-11-18 16:12:00,149 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:00,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:00,149 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:00,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:00,149 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:00,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:01,390 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29307 proven. 1316 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-18 16:12:01,390 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:01,390 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:01,390 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:01,390 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:01,390 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:01,390 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:01,399 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:12:01,399 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:12:01,586 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:12:01,586 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:01,598 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:02,943 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29126 proven. 4567 refuted. 0 times theorem prover too weak. 136314 trivial. 0 not checked. [2018-11-18 16:12:02,944 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:04,166 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29126 proven. 4567 refuted. 0 times theorem prover too weak. 136314 trivial. 0 not checked. [2018-11-18 16:12:04,182 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:04,183 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 49, 49] total 76 [2018-11-18 16:12:04,183 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:04,183 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 16:12:04,183 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 16:12:04,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1112, Invalid=4588, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 16:12:04,184 INFO L87 Difference]: Start difference. First operand 1651 states and 1654 transitions. Second operand 73 states. [2018-11-18 16:12:05,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:05,605 INFO L93 Difference]: Finished difference Result 1800 states and 1804 transitions. [2018-11-18 16:12:05,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 16:12:05,605 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1641 [2018-11-18 16:12:05,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:05,608 INFO L225 Difference]: With dead ends: 1800 [2018-11-18 16:12:05,608 INFO L226 Difference]: Without dead ends: 1800 [2018-11-18 16:12:05,609 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3370 GetRequests, 3208 SyntacticMatches, 45 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4605 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3026, Invalid=11016, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 16:12:05,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1800 states. [2018-11-18 16:12:05,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1800 to 1790. [2018-11-18 16:12:05,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1790 states. [2018-11-18 16:12:05,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 1794 transitions. [2018-11-18 16:12:05,618 INFO L78 Accepts]: Start accepts. Automaton has 1790 states and 1794 transitions. Word has length 1641 [2018-11-18 16:12:05,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:05,619 INFO L480 AbstractCegarLoop]: Abstraction has 1790 states and 1794 transitions. [2018-11-18 16:12:05,619 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 16:12:05,619 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 1794 transitions. [2018-11-18 16:12:05,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1775 [2018-11-18 16:12:05,635 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:05,635 INFO L375 BasicCegarLoop]: trace histogram [271, 251, 251, 250, 250, 250, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:05,636 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:05,636 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:05,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1968198802, now seen corresponding path program 49 times [2018-11-18 16:12:05,636 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:05,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:05,636 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:05,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:05,636 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:05,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:07,188 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 79679 proven. 3837 refuted. 0 times theorem prover too weak. 116824 trivial. 0 not checked. [2018-11-18 16:12:07,188 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:07,188 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:07,188 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:07,189 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:07,189 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:07,189 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:07,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:07,198 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:12:07,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:07,451 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:08,983 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 58413 proven. 1180 refuted. 0 times theorem prover too weak. 140747 trivial. 0 not checked. [2018-11-18 16:12:08,983 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:10,823 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 58413 proven. 1180 refuted. 0 times theorem prover too weak. 140747 trivial. 0 not checked. [2018-11-18 16:12:10,839 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:10,840 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 44, 44] total 108 [2018-11-18 16:12:10,840 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:10,840 INFO L459 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-11-18 16:12:10,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-11-18 16:12:10,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1957, Invalid=9599, Unknown=0, NotChecked=0, Total=11556 [2018-11-18 16:12:10,841 INFO L87 Difference]: Start difference. First operand 1790 states and 1794 transitions. Second operand 87 states. [2018-11-18 16:12:13,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:13,305 INFO L93 Difference]: Finished difference Result 1801 states and 1803 transitions. [2018-11-18 16:12:13,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-18 16:12:13,305 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 1774 [2018-11-18 16:12:13,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:13,309 INFO L225 Difference]: With dead ends: 1801 [2018-11-18 16:12:13,309 INFO L226 Difference]: Without dead ends: 1795 [2018-11-18 16:12:13,311 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3657 GetRequests, 3468 SyntacticMatches, 22 SemanticMatches, 167 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12238 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=5074, Invalid=23318, Unknown=0, NotChecked=0, Total=28392 [2018-11-18 16:12:13,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1795 states. [2018-11-18 16:12:13,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1795 to 1790. [2018-11-18 16:12:13,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1790 states. [2018-11-18 16:12:13,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 1792 transitions. [2018-11-18 16:12:13,324 INFO L78 Accepts]: Start accepts. Automaton has 1790 states and 1792 transitions. Word has length 1774 [2018-11-18 16:12:13,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:13,325 INFO L480 AbstractCegarLoop]: Abstraction has 1790 states and 1792 transitions. [2018-11-18 16:12:13,325 INFO L481 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-11-18 16:12:13,330 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 1792 transitions. [2018-11-18 16:12:13,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1781 [2018-11-18 16:12:13,350 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:13,350 INFO L375 BasicCegarLoop]: trace histogram [272, 252, 252, 251, 251, 251, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:13,350 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:13,351 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:13,351 INFO L82 PathProgramCache]: Analyzing trace with hash 1365116774, now seen corresponding path program 50 times [2018-11-18 16:12:13,351 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:13,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:13,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:13,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:13,352 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:13,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:15,084 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-11-18 16:12:15,084 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:15,084 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:15,084 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:15,084 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:15,084 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:15,084 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:15,094 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:12:15,094 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:12:15,577 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-11-18 16:12:15,577 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:15,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:15,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:12:15,597 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:12:15,601 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:12:15,601 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:12:15,610 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:12:15,616 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:12:15,617 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:12:19,005 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-11-18 16:12:19,005 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:21,127 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-11-18 16:12:21,144 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:21,145 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27, 26] total 53 [2018-11-18 16:12:21,145 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:21,146 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 16:12:21,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 16:12:21,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1073, Invalid=1789, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 16:12:21,146 INFO L87 Difference]: Start difference. First operand 1790 states and 1792 transitions. Second operand 29 states. [2018-11-18 16:12:21,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:21,667 INFO L93 Difference]: Finished difference Result 1804 states and 1807 transitions. [2018-11-18 16:12:21,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-18 16:12:21,667 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 1780 [2018-11-18 16:12:21,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:21,670 INFO L225 Difference]: With dead ends: 1804 [2018-11-18 16:12:21,670 INFO L226 Difference]: Without dead ends: 1804 [2018-11-18 16:12:21,671 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3607 GetRequests, 3491 SyntacticMatches, 42 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 968 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2130, Invalid=3570, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 16:12:21,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1804 states. [2018-11-18 16:12:21,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1804 to 1796. [2018-11-18 16:12:21,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-11-18 16:12:21,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 1799 transitions. [2018-11-18 16:12:21,681 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 1799 transitions. Word has length 1780 [2018-11-18 16:12:21,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:21,682 INFO L480 AbstractCegarLoop]: Abstraction has 1796 states and 1799 transitions. [2018-11-18 16:12:21,682 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 16:12:21,682 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 1799 transitions. [2018-11-18 16:12:21,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1787 [2018-11-18 16:12:21,694 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:21,695 INFO L375 BasicCegarLoop]: trace histogram [273, 253, 253, 252, 252, 252, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:21,695 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:21,695 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:21,695 INFO L82 PathProgramCache]: Analyzing trace with hash 1719464622, now seen corresponding path program 51 times [2018-11-18 16:12:21,695 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:21,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:21,696 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:21,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:21,696 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:21,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:23,105 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33629 proven. 1455 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-11-18 16:12:23,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:23,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:23,105 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:23,105 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:23,105 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:23,105 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:23,115 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:12:23,115 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:12:23,319 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:12:23,319 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:23,332 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:24,851 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33440 proven. 5017 refuted. 0 times theorem prover too weak. 164977 trivial. 0 not checked. [2018-11-18 16:12:24,851 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:26,215 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33440 proven. 5017 refuted. 0 times theorem prover too weak. 164977 trivial. 0 not checked. [2018-11-18 16:12:26,232 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:26,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 51, 51] total 79 [2018-11-18 16:12:26,232 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:26,233 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-11-18 16:12:26,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-11-18 16:12:26,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1207, Invalid=4955, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:12:26,233 INFO L87 Difference]: Start difference. First operand 1796 states and 1799 transitions. Second operand 76 states. [2018-11-18 16:12:27,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:27,732 INFO L93 Difference]: Finished difference Result 1951 states and 1955 transitions. [2018-11-18 16:12:27,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-11-18 16:12:27,732 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1786 [2018-11-18 16:12:27,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:27,735 INFO L225 Difference]: With dead ends: 1951 [2018-11-18 16:12:27,736 INFO L226 Difference]: Without dead ends: 1951 [2018-11-18 16:12:27,737 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3664 GetRequests, 3495 SyntacticMatches, 47 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5001 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3298, Invalid=11954, Unknown=0, NotChecked=0, Total=15252 [2018-11-18 16:12:27,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1951 states. [2018-11-18 16:12:27,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1951 to 1941. [2018-11-18 16:12:27,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1941 states. [2018-11-18 16:12:27,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1941 states to 1941 states and 1945 transitions. [2018-11-18 16:12:27,746 INFO L78 Accepts]: Start accepts. Automaton has 1941 states and 1945 transitions. Word has length 1786 [2018-11-18 16:12:27,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:27,747 INFO L480 AbstractCegarLoop]: Abstraction has 1941 states and 1945 transitions. [2018-11-18 16:12:27,748 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-11-18 16:12:27,748 INFO L276 IsEmpty]: Start isEmpty. Operand 1941 states and 1945 transitions. [2018-11-18 16:12:27,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1926 [2018-11-18 16:12:27,762 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:27,763 INFO L375 BasicCegarLoop]: trace histogram [295, 274, 274, 273, 273, 273, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:27,763 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:27,763 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:27,764 INFO L82 PathProgramCache]: Analyzing trace with hash 1907288769, now seen corresponding path program 52 times [2018-11-18 16:12:27,764 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:27,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:27,764 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:27,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:27,764 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:27,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:29,431 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 66658 proven. 6450 refuted. 0 times theorem prover too weak. 165074 trivial. 0 not checked. [2018-11-18 16:12:29,431 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:29,431 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:29,431 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:29,431 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:29,431 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:29,431 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:29,439 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:29,439 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:12:29,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:29,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:31,082 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 67036 proven. 1302 refuted. 0 times theorem prover too weak. 169844 trivial. 0 not checked. [2018-11-18 16:12:31,082 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:32,919 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 67036 proven. 1302 refuted. 0 times theorem prover too weak. 169844 trivial. 0 not checked. [2018-11-18 16:12:32,935 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:32,936 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 46, 46] total 95 [2018-11-18 16:12:32,936 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:32,937 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 16:12:32,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 16:12:32,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1895, Invalid=7035, Unknown=0, NotChecked=0, Total=8930 [2018-11-18 16:12:32,937 INFO L87 Difference]: Start difference. First operand 1941 states and 1945 transitions. Second operand 73 states. [2018-11-18 16:12:34,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:34,287 INFO L93 Difference]: Finished difference Result 1952 states and 1954 transitions. [2018-11-18 16:12:34,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-11-18 16:12:34,288 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1925 [2018-11-18 16:12:34,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:34,290 INFO L225 Difference]: With dead ends: 1952 [2018-11-18 16:12:34,290 INFO L226 Difference]: Without dead ends: 1946 [2018-11-18 16:12:34,291 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3946 GetRequests, 3784 SyntacticMatches, 23 SemanticMatches, 139 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7139 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=4629, Invalid=15111, Unknown=0, NotChecked=0, Total=19740 [2018-11-18 16:12:34,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1946 states. [2018-11-18 16:12:34,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1946 to 1941. [2018-11-18 16:12:34,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1941 states. [2018-11-18 16:12:34,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1941 states to 1941 states and 1943 transitions. [2018-11-18 16:12:34,300 INFO L78 Accepts]: Start accepts. Automaton has 1941 states and 1943 transitions. Word has length 1925 [2018-11-18 16:12:34,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:34,300 INFO L480 AbstractCegarLoop]: Abstraction has 1941 states and 1943 transitions. [2018-11-18 16:12:34,300 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 16:12:34,300 INFO L276 IsEmpty]: Start isEmpty. Operand 1941 states and 1943 transitions. [2018-11-18 16:12:34,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1932 [2018-11-18 16:12:34,314 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:34,315 INFO L375 BasicCegarLoop]: trace histogram [296, 275, 275, 274, 274, 274, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:34,315 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:34,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:34,315 INFO L82 PathProgramCache]: Analyzing trace with hash 1398241401, now seen corresponding path program 53 times [2018-11-18 16:12:34,315 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:34,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:34,316 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:34,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:34,316 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:34,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:36,211 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-11-18 16:12:36,211 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:36,211 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:36,211 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:36,211 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:36,211 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:36,211 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:36,222 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:12:36,222 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:12:36,901 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-11-18 16:12:36,901 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:36,915 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:36,917 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:12:36,919 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:12:36,923 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:12:36,923 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:12:36,932 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:12:36,938 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:12:36,938 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:12:40,877 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-11-18 16:12:40,878 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:43,249 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-11-18 16:12:43,265 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:43,266 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 27] total 55 [2018-11-18 16:12:43,266 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:43,266 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 16:12:43,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 16:12:43,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1143, Invalid=1937, Unknown=0, NotChecked=0, Total=3080 [2018-11-18 16:12:43,267 INFO L87 Difference]: Start difference. First operand 1941 states and 1943 transitions. Second operand 30 states. [2018-11-18 16:12:43,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:43,842 INFO L93 Difference]: Finished difference Result 1955 states and 1958 transitions. [2018-11-18 16:12:43,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-18 16:12:43,842 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 1931 [2018-11-18 16:12:43,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:43,844 INFO L225 Difference]: With dead ends: 1955 [2018-11-18 16:12:43,844 INFO L226 Difference]: Without dead ends: 1955 [2018-11-18 16:12:43,845 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3911 GetRequests, 3790 SyntacticMatches, 44 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1087 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2272, Invalid=3890, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:12:43,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1955 states. [2018-11-18 16:12:43,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1955 to 1947. [2018-11-18 16:12:43,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1947 states. [2018-11-18 16:12:43,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1947 states to 1947 states and 1950 transitions. [2018-11-18 16:12:43,853 INFO L78 Accepts]: Start accepts. Automaton has 1947 states and 1950 transitions. Word has length 1931 [2018-11-18 16:12:43,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:43,854 INFO L480 AbstractCegarLoop]: Abstraction has 1947 states and 1950 transitions. [2018-11-18 16:12:43,854 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 16:12:43,854 INFO L276 IsEmpty]: Start isEmpty. Operand 1947 states and 1950 transitions. [2018-11-18 16:12:43,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1938 [2018-11-18 16:12:43,868 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:43,868 INFO L375 BasicCegarLoop]: trace histogram [297, 276, 276, 275, 275, 275, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:43,869 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:43,869 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:43,869 INFO L82 PathProgramCache]: Analyzing trace with hash -688649855, now seen corresponding path program 54 times [2018-11-18 16:12:43,869 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:43,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:43,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:43,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:43,870 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:43,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:45,471 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38355 proven. 1601 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-11-18 16:12:45,471 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:45,471 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:45,471 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:45,471 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:45,471 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:45,471 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:45,481 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:12:45,482 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:12:45,715 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:12:45,715 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:45,729 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:47,440 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38158 proven. 5488 refuted. 0 times theorem prover too weak. 197910 trivial. 0 not checked. [2018-11-18 16:12:47,440 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:49,006 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38158 proven. 5488 refuted. 0 times theorem prover too weak. 197910 trivial. 0 not checked. [2018-11-18 16:12:49,022 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:49,023 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 53, 53] total 82 [2018-11-18 16:12:49,023 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:49,023 INFO L459 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-11-18 16:12:49,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-11-18 16:12:49,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1306, Invalid=5336, Unknown=0, NotChecked=0, Total=6642 [2018-11-18 16:12:49,024 INFO L87 Difference]: Start difference. First operand 1947 states and 1950 transitions. Second operand 79 states. [2018-11-18 16:12:50,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:50,419 INFO L93 Difference]: Finished difference Result 2108 states and 2112 transitions. [2018-11-18 16:12:50,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-11-18 16:12:50,420 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 1937 [2018-11-18 16:12:50,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:50,424 INFO L225 Difference]: With dead ends: 2108 [2018-11-18 16:12:50,424 INFO L226 Difference]: Without dead ends: 2108 [2018-11-18 16:12:50,425 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3970 GetRequests, 3794 SyntacticMatches, 49 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5413 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3582, Invalid=12930, Unknown=0, NotChecked=0, Total=16512 [2018-11-18 16:12:50,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2108 states. [2018-11-18 16:12:50,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2108 to 2098. [2018-11-18 16:12:50,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2098 states. [2018-11-18 16:12:50,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2098 states to 2098 states and 2102 transitions. [2018-11-18 16:12:50,436 INFO L78 Accepts]: Start accepts. Automaton has 2098 states and 2102 transitions. Word has length 1937 [2018-11-18 16:12:50,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:50,437 INFO L480 AbstractCegarLoop]: Abstraction has 2098 states and 2102 transitions. [2018-11-18 16:12:50,437 INFO L481 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-11-18 16:12:50,437 INFO L276 IsEmpty]: Start isEmpty. Operand 2098 states and 2102 transitions. [2018-11-18 16:12:50,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2083 [2018-11-18 16:12:50,454 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:50,455 INFO L375 BasicCegarLoop]: trace histogram [320, 298, 298, 297, 297, 297, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:50,455 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:50,455 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:50,455 INFO L82 PathProgramCache]: Analyzing trace with hash 266198870, now seen corresponding path program 55 times [2018-11-18 16:12:50,455 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:50,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:50,456 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:50,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:50,456 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:50,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:52,588 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 39986 proven. 1610 refuted. 0 times theorem prover too weak. 239531 trivial. 0 not checked. [2018-11-18 16:12:52,588 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:52,588 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:52,589 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:52,589 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:52,589 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:52,589 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:52,599 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:52,599 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:12:52,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:52,879 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:54,853 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 76466 proven. 1430 refuted. 0 times theorem prover too weak. 203231 trivial. 0 not checked. [2018-11-18 16:12:54,854 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:57,200 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 76466 proven. 1430 refuted. 0 times theorem prover too weak. 203231 trivial. 0 not checked. [2018-11-18 16:12:57,217 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:57,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 48, 48] total 98 [2018-11-18 16:12:57,217 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:57,218 INFO L459 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-11-18 16:12:57,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-11-18 16:12:57,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1507, Invalid=7999, Unknown=0, NotChecked=0, Total=9506 [2018-11-18 16:12:57,218 INFO L87 Difference]: Start difference. First operand 2098 states and 2102 transitions. Second operand 75 states. [2018-11-18 16:12:59,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:59,661 INFO L93 Difference]: Finished difference Result 2118 states and 2121 transitions. [2018-11-18 16:12:59,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-11-18 16:12:59,661 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 2082 [2018-11-18 16:12:59,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:59,663 INFO L225 Difference]: With dead ends: 2118 [2018-11-18 16:12:59,663 INFO L226 Difference]: Without dead ends: 2112 [2018-11-18 16:12:59,664 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4258 GetRequests, 4071 SyntacticMatches, 24 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8193 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=4814, Invalid=22246, Unknown=0, NotChecked=0, Total=27060 [2018-11-18 16:12:59,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2112 states. [2018-11-18 16:12:59,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2112 to 2104. [2018-11-18 16:12:59,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2104 states. [2018-11-18 16:12:59,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2104 states to 2104 states and 2107 transitions. [2018-11-18 16:12:59,673 INFO L78 Accepts]: Start accepts. Automaton has 2104 states and 2107 transitions. Word has length 2082 [2018-11-18 16:12:59,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:59,674 INFO L480 AbstractCegarLoop]: Abstraction has 2104 states and 2107 transitions. [2018-11-18 16:12:59,674 INFO L481 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-11-18 16:12:59,674 INFO L276 IsEmpty]: Start isEmpty. Operand 2104 states and 2107 transitions. [2018-11-18 16:12:59,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2095 [2018-11-18 16:12:59,690 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:59,690 INFO L375 BasicCegarLoop]: trace histogram [322, 300, 300, 299, 299, 299, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:59,690 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:12:59,690 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:59,691 INFO L82 PathProgramCache]: Analyzing trace with hash 1360921238, now seen corresponding path program 56 times [2018-11-18 16:12:59,691 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:59,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:59,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:59,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:59,691 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:59,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:01,848 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 41822 proven. 1752 refuted. 0 times theorem prover too weak. 241219 trivial. 0 not checked. [2018-11-18 16:13:01,849 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:01,849 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:01,849 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:01,849 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:01,849 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:01,849 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:01,859 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:13:01,859 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:13:02,643 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-11-18 16:13:02,643 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:02,657 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:05,045 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 72398 proven. 7830 refuted. 0 times theorem prover too weak. 204565 trivial. 0 not checked. [2018-11-18 16:13:05,045 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:08,130 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 72398 proven. 7830 refuted. 0 times theorem prover too weak. 204565 trivial. 0 not checked. [2018-11-18 16:13:08,147 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:08,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 55, 55] total 131 [2018-11-18 16:13:08,148 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:08,148 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-18 16:13:08,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-18 16:13:08,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2295, Invalid=14735, Unknown=0, NotChecked=0, Total=17030 [2018-11-18 16:13:08,150 INFO L87 Difference]: Start difference. First operand 2104 states and 2107 transitions. Second operand 83 states. [2018-11-18 16:13:11,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:11,894 INFO L93 Difference]: Finished difference Result 2285 states and 2290 transitions. [2018-11-18 16:13:11,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-18 16:13:11,894 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2094 [2018-11-18 16:13:11,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:11,897 INFO L225 Difference]: With dead ends: 2285 [2018-11-18 16:13:11,897 INFO L226 Difference]: Without dead ends: 2285 [2018-11-18 16:13:11,898 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4296 GetRequests, 4081 SyntacticMatches, 6 SemanticMatches, 209 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12206 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=7947, Invalid=36363, Unknown=0, NotChecked=0, Total=44310 [2018-11-18 16:13:11,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2285 states. [2018-11-18 16:13:11,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2285 to 2267. [2018-11-18 16:13:11,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2018-11-18 16:13:11,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 2272 transitions. [2018-11-18 16:13:11,908 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 2272 transitions. Word has length 2094 [2018-11-18 16:13:11,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:11,909 INFO L480 AbstractCegarLoop]: Abstraction has 2267 states and 2272 transitions. [2018-11-18 16:13:11,909 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-18 16:13:11,909 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 2272 transitions. [2018-11-18 16:13:11,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2252 [2018-11-18 16:13:11,927 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:11,928 INFO L375 BasicCegarLoop]: trace histogram [347, 324, 324, 323, 323, 323, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:11,928 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:13:11,928 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:11,928 INFO L82 PathProgramCache]: Analyzing trace with hash 698270449, now seen corresponding path program 57 times [2018-11-18 16:13:11,928 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:11,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:11,928 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:11,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:11,929 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:12,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:14,068 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 88155 proven. 7674 refuted. 0 times theorem prover too weak. 235766 trivial. 0 not checked. [2018-11-18 16:13:14,068 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:14,068 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:14,069 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:14,069 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:14,069 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:14,069 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:14,081 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:13:14,081 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:13:14,347 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:13:14,347 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:14,363 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:16,256 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 88244 proven. 5914 refuted. 0 times theorem prover too weak. 237437 trivial. 0 not checked. [2018-11-18 16:13:16,257 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:18,733 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 88252 proven. 5906 refuted. 0 times theorem prover too weak. 237437 trivial. 0 not checked. [2018-11-18 16:13:18,750 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:18,751 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53, 53] total 108 [2018-11-18 16:13:18,751 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:18,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-11-18 16:13:18,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-11-18 16:13:18,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2264, Invalid=9292, Unknown=0, NotChecked=0, Total=11556 [2018-11-18 16:13:18,753 INFO L87 Difference]: Start difference. First operand 2267 states and 2272 transitions. Second operand 82 states. [2018-11-18 16:13:20,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:20,521 INFO L93 Difference]: Finished difference Result 2276 states and 2279 transitions. [2018-11-18 16:13:20,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-11-18 16:13:20,521 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2251 [2018-11-18 16:13:20,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:20,525 INFO L225 Difference]: With dead ends: 2276 [2018-11-18 16:13:20,525 INFO L226 Difference]: Without dead ends: 2270 [2018-11-18 16:13:20,527 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4606 GetRequests, 4423 SyntacticMatches, 27 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9259 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=5734, Invalid=19072, Unknown=0, NotChecked=0, Total=24806 [2018-11-18 16:13:20,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2270 states. [2018-11-18 16:13:20,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2270 to 2267. [2018-11-18 16:13:20,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2018-11-18 16:13:20,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 2270 transitions. [2018-11-18 16:13:20,538 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 2270 transitions. Word has length 2251 [2018-11-18 16:13:20,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:20,539 INFO L480 AbstractCegarLoop]: Abstraction has 2267 states and 2270 transitions. [2018-11-18 16:13:20,539 INFO L481 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-11-18 16:13:20,539 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 2270 transitions. [2018-11-18 16:13:20,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2258 [2018-11-18 16:13:20,559 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:20,560 INFO L375 BasicCegarLoop]: trace histogram [348, 325, 325, 324, 324, 324, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:20,560 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:13:20,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:20,561 INFO L82 PathProgramCache]: Analyzing trace with hash -1199365975, now seen corresponding path program 58 times [2018-11-18 16:13:20,561 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:20,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:20,561 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:20,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:20,561 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:20,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:22,593 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49091 proven. 1914 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-11-18 16:13:22,593 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:22,594 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:22,594 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:22,594 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:22,594 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:22,594 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:22,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:22,602 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:13:22,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:22,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:24,942 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49165 proven. 1840 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-11-18 16:13:24,943 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:26,782 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49165 proven. 1840 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-11-18 16:13:26,799 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:26,800 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53, 53] total 81 [2018-11-18 16:13:26,800 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:26,801 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-11-18 16:13:26,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-11-18 16:13:26,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-11-18 16:13:26,802 INFO L87 Difference]: Start difference. First operand 2267 states and 2270 transitions. Second operand 81 states. [2018-11-18 16:13:28,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:28,044 INFO L93 Difference]: Finished difference Result 2440 states and 2444 transitions. [2018-11-18 16:13:28,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-11-18 16:13:28,044 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2257 [2018-11-18 16:13:28,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:28,046 INFO L225 Difference]: With dead ends: 2440 [2018-11-18 16:13:28,047 INFO L226 Difference]: Without dead ends: 2440 [2018-11-18 16:13:28,047 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4616 GetRequests, 4437 SyntacticMatches, 51 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5263 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-11-18 16:13:28,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2440 states. [2018-11-18 16:13:28,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2440 to 2430. [2018-11-18 16:13:28,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2430 states. [2018-11-18 16:13:28,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2430 states to 2430 states and 2434 transitions. [2018-11-18 16:13:28,059 INFO L78 Accepts]: Start accepts. Automaton has 2430 states and 2434 transitions. Word has length 2257 [2018-11-18 16:13:28,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:28,060 INFO L480 AbstractCegarLoop]: Abstraction has 2430 states and 2434 transitions. [2018-11-18 16:13:28,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-11-18 16:13:28,060 INFO L276 IsEmpty]: Start isEmpty. Operand 2430 states and 2434 transitions. [2018-11-18 16:13:28,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2415 [2018-11-18 16:13:28,080 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:28,081 INFO L375 BasicCegarLoop]: trace histogram [373, 349, 349, 348, 348, 348, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:28,081 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:13:28,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:28,081 INFO L82 PathProgramCache]: Analyzing trace with hash 491606462, now seen corresponding path program 59 times [2018-11-18 16:13:28,081 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:28,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:28,082 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:28,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:28,082 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:28,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:30,610 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 135463 proven. 5469 refuted. 0 times theorem prover too weak. 243164 trivial. 0 not checked. [2018-11-18 16:13:30,610 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:30,610 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:30,610 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:30,611 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:30,611 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:30,611 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:30,621 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:13:30,621 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:13:31,637 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-11-18 16:13:31,637 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:31,654 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:34,565 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 94251 proven. 5404 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 16:13:34,565 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:38,176 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 94251 proven. 5404 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 16:13:38,194 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:38,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 57, 57] total 161 [2018-11-18 16:13:38,194 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:38,195 INFO L459 AbstractCegarLoop]: Interpolant automaton has 110 states [2018-11-18 16:13:38,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2018-11-18 16:13:38,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3523, Invalid=22237, Unknown=0, NotChecked=0, Total=25760 [2018-11-18 16:13:38,197 INFO L87 Difference]: Start difference. First operand 2430 states and 2434 transitions. Second operand 110 states. [2018-11-18 16:13:42,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:42,312 INFO L93 Difference]: Finished difference Result 2445 states and 2447 transitions. [2018-11-18 16:13:42,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2018-11-18 16:13:42,312 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 2414 [2018-11-18 16:13:42,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:42,315 INFO L225 Difference]: With dead ends: 2445 [2018-11-18 16:13:42,315 INFO L226 Difference]: Without dead ends: 2439 [2018-11-18 16:13:42,318 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4988 GetRequests, 4720 SyntacticMatches, 5 SemanticMatches, 263 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23377 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=11597, Invalid=58363, Unknown=0, NotChecked=0, Total=69960 [2018-11-18 16:13:42,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2439 states. [2018-11-18 16:13:42,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2439 to 2430. [2018-11-18 16:13:42,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2430 states. [2018-11-18 16:13:42,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2430 states to 2430 states and 2432 transitions. [2018-11-18 16:13:42,329 INFO L78 Accepts]: Start accepts. Automaton has 2430 states and 2432 transitions. Word has length 2414 [2018-11-18 16:13:42,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:42,329 INFO L480 AbstractCegarLoop]: Abstraction has 2430 states and 2432 transitions. [2018-11-18 16:13:42,329 INFO L481 AbstractCegarLoop]: Interpolant automaton has 110 states. [2018-11-18 16:13:42,329 INFO L276 IsEmpty]: Start isEmpty. Operand 2430 states and 2432 transitions. [2018-11-18 16:13:42,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2421 [2018-11-18 16:13:42,350 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:42,351 INFO L375 BasicCegarLoop]: trace histogram [374, 350, 350, 349, 349, 349, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:42,351 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:13:42,351 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:42,351 INFO L82 PathProgramCache]: Analyzing trace with hash -1024679498, now seen corresponding path program 60 times [2018-11-18 16:13:42,351 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:42,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:42,351 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:42,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:42,352 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:42,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:45,091 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-11-18 16:13:45,092 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:45,092 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:45,092 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:45,092 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:45,092 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:45,092 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:45,098 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:13:45,098 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:13:45,879 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:13:45,879 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:45,906 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:45,908 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:13:45,914 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:13:45,918 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:13:45,919 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:13:45,924 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:13:45,931 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:13:45,931 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:13:52,310 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-11-18 16:13:52,310 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:55,367 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-11-18 16:13:55,389 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:55,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 29] total 84 [2018-11-18 16:13:55,390 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:55,390 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-18 16:13:55,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-18 16:13:55,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1393, Invalid=5747, Unknown=0, NotChecked=0, Total=7140 [2018-11-18 16:13:55,391 INFO L87 Difference]: Start difference. First operand 2430 states and 2432 transitions. Second operand 57 states. [2018-11-18 16:13:56,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:56,922 INFO L93 Difference]: Finished difference Result 2444 states and 2447 transitions. [2018-11-18 16:13:56,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-18 16:13:56,922 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 2420 [2018-11-18 16:13:56,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:56,925 INFO L225 Difference]: With dead ends: 2444 [2018-11-18 16:13:56,925 INFO L226 Difference]: Without dead ends: 2444 [2018-11-18 16:13:56,926 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4895 GetRequests, 4736 SyntacticMatches, 50 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4015 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=2411, Invalid=9799, Unknown=0, NotChecked=0, Total=12210 [2018-11-18 16:13:56,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2444 states. [2018-11-18 16:13:56,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2444 to 2436. [2018-11-18 16:13:56,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2436 states. [2018-11-18 16:13:56,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2436 states to 2436 states and 2439 transitions. [2018-11-18 16:13:56,938 INFO L78 Accepts]: Start accepts. Automaton has 2436 states and 2439 transitions. Word has length 2420 [2018-11-18 16:13:56,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:56,940 INFO L480 AbstractCegarLoop]: Abstraction has 2436 states and 2439 transitions. [2018-11-18 16:13:56,940 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-18 16:13:56,940 INFO L276 IsEmpty]: Start isEmpty. Operand 2436 states and 2439 transitions. [2018-11-18 16:13:56,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2427 [2018-11-18 16:13:56,960 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:56,961 INFO L375 BasicCegarLoop]: trace histogram [375, 351, 351, 350, 350, 350, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:56,961 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:13:56,961 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:56,961 INFO L82 PathProgramCache]: Analyzing trace with hash -48066306, now seen corresponding path program 61 times [2018-11-18 16:13:56,962 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:56,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:56,962 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:56,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:56,962 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:57,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:59,272 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 55137 proven. 2081 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-11-18 16:13:59,272 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:59,273 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:59,273 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:59,273 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:59,273 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:59,273 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:59,282 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:59,282 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:13:59,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:59,618 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:01,890 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 55214 proven. 2004 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-11-18 16:14:01,890 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:03,957 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 55214 proven. 2004 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-11-18 16:14:03,974 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:03,975 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 55, 55] total 84 [2018-11-18 16:14:03,975 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:03,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 84 states [2018-11-18 16:14:03,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2018-11-18 16:14:03,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1597, Invalid=5375, Unknown=0, NotChecked=0, Total=6972 [2018-11-18 16:14:03,976 INFO L87 Difference]: Start difference. First operand 2436 states and 2439 transitions. Second operand 84 states. [2018-11-18 16:14:05,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:05,287 INFO L93 Difference]: Finished difference Result 2615 states and 2619 transitions. [2018-11-18 16:14:05,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-11-18 16:14:05,288 INFO L78 Accepts]: Start accepts. Automaton has 84 states. Word has length 2426 [2018-11-18 16:14:05,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:05,291 INFO L225 Difference]: With dead ends: 2615 [2018-11-18 16:14:05,291 INFO L226 Difference]: Without dead ends: 2615 [2018-11-18 16:14:05,292 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4958 GetRequests, 4772 SyntacticMatches, 53 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5682 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=4552, Invalid=13538, Unknown=0, NotChecked=0, Total=18090 [2018-11-18 16:14:05,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states. [2018-11-18 16:14:05,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2605. [2018-11-18 16:14:05,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2605 states. [2018-11-18 16:14:05,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2605 states to 2605 states and 2609 transitions. [2018-11-18 16:14:05,304 INFO L78 Accepts]: Start accepts. Automaton has 2605 states and 2609 transitions. Word has length 2426 [2018-11-18 16:14:05,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:05,305 INFO L480 AbstractCegarLoop]: Abstraction has 2605 states and 2609 transitions. [2018-11-18 16:14:05,305 INFO L481 AbstractCegarLoop]: Interpolant automaton has 84 states. [2018-11-18 16:14:05,305 INFO L276 IsEmpty]: Start isEmpty. Operand 2605 states and 2609 transitions. [2018-11-18 16:14:05,330 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2590 [2018-11-18 16:14:05,330 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:05,330 INFO L375 BasicCegarLoop]: trace histogram [401, 376, 376, 375, 375, 375, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:05,331 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:14:05,331 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:05,331 INFO L82 PathProgramCache]: Analyzing trace with hash -1655328111, now seen corresponding path program 62 times [2018-11-18 16:14:05,331 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:05,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:05,332 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:14:05,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:05,332 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:05,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:08,005 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 109500 proven. 9002 refuted. 0 times theorem prover too weak. 326548 trivial. 0 not checked. [2018-11-18 16:14:08,005 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:08,005 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:08,005 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:08,005 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:08,005 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:08,005 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:08,017 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:14:08,017 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:14:09,835 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-11-18 16:14:09,836 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:14:09,853 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:13,015 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 106004 proven. 5854 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 16:14:13,016 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:17,011 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 106004 proven. 5854 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 16:14:17,029 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:17,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 59, 59] total 167 [2018-11-18 16:14:17,030 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:17,030 INFO L459 AbstractCegarLoop]: Interpolant automaton has 114 states [2018-11-18 16:14:17,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 114 interpolants. [2018-11-18 16:14:17,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3771, Invalid=23951, Unknown=0, NotChecked=0, Total=27722 [2018-11-18 16:14:17,031 INFO L87 Difference]: Start difference. First operand 2605 states and 2609 transitions. Second operand 114 states. [2018-11-18 16:14:21,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:21,713 INFO L93 Difference]: Finished difference Result 2620 states and 2622 transitions. [2018-11-18 16:14:21,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 139 states. [2018-11-18 16:14:21,714 INFO L78 Accepts]: Start accepts. Automaton has 114 states. Word has length 2589 [2018-11-18 16:14:21,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:21,716 INFO L225 Difference]: With dead ends: 2620 [2018-11-18 16:14:21,717 INFO L226 Difference]: Without dead ends: 2614 [2018-11-18 16:14:21,720 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5367 GetRequests, 5066 SyntacticMatches, 5 SemanticMatches, 296 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31352 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=12197, Invalid=76309, Unknown=0, NotChecked=0, Total=88506 [2018-11-18 16:14:21,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2614 states. [2018-11-18 16:14:21,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2614 to 2605. [2018-11-18 16:14:21,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2605 states. [2018-11-18 16:14:21,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2605 states to 2605 states and 2607 transitions. [2018-11-18 16:14:21,732 INFO L78 Accepts]: Start accepts. Automaton has 2605 states and 2607 transitions. Word has length 2589 [2018-11-18 16:14:21,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:21,733 INFO L480 AbstractCegarLoop]: Abstraction has 2605 states and 2607 transitions. [2018-11-18 16:14:21,733 INFO L481 AbstractCegarLoop]: Interpolant automaton has 114 states. [2018-11-18 16:14:21,733 INFO L276 IsEmpty]: Start isEmpty. Operand 2605 states and 2607 transitions. [2018-11-18 16:14:21,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2596 [2018-11-18 16:14:21,757 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:21,758 INFO L375 BasicCegarLoop]: trace histogram [402, 377, 377, 376, 376, 376, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:21,758 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:14:21,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:21,758 INFO L82 PathProgramCache]: Analyzing trace with hash 637277257, now seen corresponding path program 63 times [2018-11-18 16:14:21,758 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:21,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:21,759 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:14:21,759 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:21,759 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:21,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:24,768 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-11-18 16:14:24,769 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:24,769 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:24,769 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:24,769 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:24,769 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:24,769 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:24,798 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:14:24,799 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:14:25,667 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:14:25,667 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:14:25,694 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:25,695 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:14:25,701 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:14:25,709 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:14:25,710 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:14:25,715 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:14:25,721 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:14:25,721 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:14:32,929 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-11-18 16:14:32,929 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:36,331 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-11-18 16:14:36,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:36,354 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 30] total 87 [2018-11-18 16:14:36,354 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:36,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-11-18 16:14:36,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-11-18 16:14:36,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1465, Invalid=6191, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 16:14:36,355 INFO L87 Difference]: Start difference. First operand 2605 states and 2607 transitions. Second operand 59 states. [2018-11-18 16:14:38,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:38,635 INFO L93 Difference]: Finished difference Result 2619 states and 2622 transitions. [2018-11-18 16:14:38,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-11-18 16:14:38,635 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 2595 [2018-11-18 16:14:38,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:38,638 INFO L225 Difference]: With dead ends: 2619 [2018-11-18 16:14:38,638 INFO L226 Difference]: Without dead ends: 2619 [2018-11-18 16:14:38,639 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5247 GetRequests, 5082 SyntacticMatches, 52 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4299 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=2529, Invalid=10581, Unknown=0, NotChecked=0, Total=13110 [2018-11-18 16:14:38,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2619 states. [2018-11-18 16:14:38,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2619 to 2611. [2018-11-18 16:14:38,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2611 states. [2018-11-18 16:14:38,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2611 states to 2611 states and 2614 transitions. [2018-11-18 16:14:38,649 INFO L78 Accepts]: Start accepts. Automaton has 2611 states and 2614 transitions. Word has length 2595 [2018-11-18 16:14:38,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:38,650 INFO L480 AbstractCegarLoop]: Abstraction has 2611 states and 2614 transitions. [2018-11-18 16:14:38,650 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-11-18 16:14:38,650 INFO L276 IsEmpty]: Start isEmpty. Operand 2611 states and 2614 transitions. [2018-11-18 16:14:38,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2602 [2018-11-18 16:14:38,674 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:38,674 INFO L375 BasicCegarLoop]: trace histogram [403, 378, 378, 377, 377, 377, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:38,674 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:14:38,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:38,674 INFO L82 PathProgramCache]: Analyzing trace with hash 2139654481, now seen corresponding path program 64 times [2018-11-18 16:14:38,674 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:38,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:38,675 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:14:38,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:38,675 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:38,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:41,293 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61659 proven. 2255 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 16:14:41,294 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:41,294 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:41,294 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:41,294 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:41,294 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:41,294 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:41,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:14:41,305 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:14:41,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:41,659 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:44,218 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61739 proven. 2175 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 16:14:44,218 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:46,567 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61739 proven. 2175 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 16:14:46,584 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:46,585 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57, 57] total 87 [2018-11-18 16:14:46,585 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:46,585 INFO L459 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-11-18 16:14:46,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-11-18 16:14:46,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1712, Invalid=5770, Unknown=0, NotChecked=0, Total=7482 [2018-11-18 16:14:46,586 INFO L87 Difference]: Start difference. First operand 2611 states and 2614 transitions. Second operand 87 states. [2018-11-18 16:14:47,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:47,924 INFO L93 Difference]: Finished difference Result 2796 states and 2800 transitions. [2018-11-18 16:14:47,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-11-18 16:14:47,924 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2601 [2018-11-18 16:14:47,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:47,927 INFO L225 Difference]: With dead ends: 2796 [2018-11-18 16:14:47,927 INFO L226 Difference]: Without dead ends: 2796 [2018-11-18 16:14:47,928 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5312 GetRequests, 5119 SyntacticMatches, 55 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6117 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=4889, Invalid=14571, Unknown=0, NotChecked=0, Total=19460 [2018-11-18 16:14:47,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2796 states. [2018-11-18 16:14:47,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2796 to 2786. [2018-11-18 16:14:47,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2786 states. [2018-11-18 16:14:47,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 2790 transitions. [2018-11-18 16:14:47,941 INFO L78 Accepts]: Start accepts. Automaton has 2786 states and 2790 transitions. Word has length 2601 [2018-11-18 16:14:47,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:47,943 INFO L480 AbstractCegarLoop]: Abstraction has 2786 states and 2790 transitions. [2018-11-18 16:14:47,943 INFO L481 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-11-18 16:14:47,943 INFO L276 IsEmpty]: Start isEmpty. Operand 2786 states and 2790 transitions. [2018-11-18 16:14:47,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2771 [2018-11-18 16:14:47,971 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:47,971 INFO L375 BasicCegarLoop]: trace histogram [430, 404, 404, 403, 403, 403, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:47,972 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:14:47,972 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:47,972 INFO L82 PathProgramCache]: Analyzing trace with hash 1771553446, now seen corresponding path program 65 times [2018-11-18 16:14:47,972 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:47,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:47,973 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:14:47,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:47,973 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:48,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:51,214 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 171143 proven. 6393 refuted. 0 times theorem prover too weak. 335431 trivial. 0 not checked. [2018-11-18 16:14:51,214 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:51,214 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:51,214 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:51,214 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:51,214 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:51,214 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:51,225 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:14:51,225 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:14:52,460 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-11-18 16:14:52,460 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:14:52,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:55,991 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 118695 proven. 6322 refuted. 0 times theorem prover too weak. 387950 trivial. 0 not checked. [2018-11-18 16:14:55,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:00,430 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 118695 proven. 6322 refuted. 0 times theorem prover too weak. 387950 trivial. 0 not checked. [2018-11-18 16:15:00,448 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:00,449 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 61, 61] total 173 [2018-11-18 16:15:00,449 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:00,449 INFO L459 AbstractCegarLoop]: Interpolant automaton has 118 states [2018-11-18 16:15:00,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2018-11-18 16:15:00,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4073, Invalid=25683, Unknown=0, NotChecked=0, Total=29756 [2018-11-18 16:15:00,450 INFO L87 Difference]: Start difference. First operand 2786 states and 2790 transitions. Second operand 118 states. [2018-11-18 16:15:04,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:04,711 INFO L93 Difference]: Finished difference Result 2801 states and 2803 transitions. [2018-11-18 16:15:04,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 120 states. [2018-11-18 16:15:04,711 INFO L78 Accepts]: Start accepts. Automaton has 118 states. Word has length 2770 [2018-11-18 16:15:04,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:04,715 INFO L225 Difference]: With dead ends: 2801 [2018-11-18 16:15:04,716 INFO L226 Difference]: Without dead ends: 2795 [2018-11-18 16:15:04,719 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5712 GetRequests, 5424 SyntacticMatches, 5 SemanticMatches, 283 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27164 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=13412, Invalid=67528, Unknown=0, NotChecked=0, Total=80940 [2018-11-18 16:15:04,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2795 states. [2018-11-18 16:15:04,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2795 to 2786. [2018-11-18 16:15:04,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2786 states. [2018-11-18 16:15:04,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 2788 transitions. [2018-11-18 16:15:04,732 INFO L78 Accepts]: Start accepts. Automaton has 2786 states and 2788 transitions. Word has length 2770 [2018-11-18 16:15:04,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:04,734 INFO L480 AbstractCegarLoop]: Abstraction has 2786 states and 2788 transitions. [2018-11-18 16:15:04,734 INFO L481 AbstractCegarLoop]: Interpolant automaton has 118 states. [2018-11-18 16:15:04,734 INFO L276 IsEmpty]: Start isEmpty. Operand 2786 states and 2788 transitions. [2018-11-18 16:15:04,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2777 [2018-11-18 16:15:04,761 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:04,762 INFO L375 BasicCegarLoop]: trace histogram [431, 405, 405, 404, 404, 404, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:04,762 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:15:04,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:04,763 INFO L82 PathProgramCache]: Analyzing trace with hash 155466910, now seen corresponding path program 66 times [2018-11-18 16:15:04,763 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:04,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:04,763 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:04,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:04,763 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:04,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:08,172 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-11-18 16:15:08,173 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:08,173 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:08,173 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:08,173 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:08,173 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:08,173 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:08,183 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:15:08,183 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:15:09,147 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:15:09,147 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:15:09,176 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:09,178 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:15:09,179 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:15:09,183 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:15:09,184 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:15:09,195 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:15:09,202 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:15:09,202 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:15:17,361 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-11-18 16:15:17,361 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:21,211 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-11-18 16:15:21,234 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:21,235 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 31] total 90 [2018-11-18 16:15:21,235 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:21,236 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-11-18 16:15:21,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-11-18 16:15:21,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1537, Invalid=6653, Unknown=0, NotChecked=0, Total=8190 [2018-11-18 16:15:21,236 INFO L87 Difference]: Start difference. First operand 2786 states and 2788 transitions. Second operand 61 states. [2018-11-18 16:15:23,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:23,455 INFO L93 Difference]: Finished difference Result 2800 states and 2803 transitions. [2018-11-18 16:15:23,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-18 16:15:23,455 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 2776 [2018-11-18 16:15:23,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:23,459 INFO L225 Difference]: With dead ends: 2800 [2018-11-18 16:15:23,459 INFO L226 Difference]: Without dead ends: 2800 [2018-11-18 16:15:23,460 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5611 GetRequests, 5440 SyntacticMatches, 54 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4591 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2646, Invalid=11396, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 16:15:23,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2800 states. [2018-11-18 16:15:23,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2800 to 2792. [2018-11-18 16:15:23,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2792 states. [2018-11-18 16:15:23,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2792 states to 2792 states and 2795 transitions. [2018-11-18 16:15:23,479 INFO L78 Accepts]: Start accepts. Automaton has 2792 states and 2795 transitions. Word has length 2776 [2018-11-18 16:15:23,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:23,480 INFO L480 AbstractCegarLoop]: Abstraction has 2792 states and 2795 transitions. [2018-11-18 16:15:23,480 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-11-18 16:15:23,480 INFO L276 IsEmpty]: Start isEmpty. Operand 2792 states and 2795 transitions. [2018-11-18 16:15:23,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2783 [2018-11-18 16:15:23,522 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:23,523 INFO L375 BasicCegarLoop]: trace histogram [432, 406, 406, 405, 405, 405, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:23,523 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:15:23,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:23,523 INFO L82 PathProgramCache]: Analyzing trace with hash 1451515366, now seen corresponding path program 67 times [2018-11-18 16:15:23,523 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:23,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:23,524 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:23,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:23,524 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:23,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:26,426 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68675 proven. 2436 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-11-18 16:15:26,427 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:26,427 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:26,427 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:26,427 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:26,427 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:26,427 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:26,434 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:26,434 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:15:26,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:26,842 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:29,714 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68758 proven. 2353 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-11-18 16:15:29,714 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:32,285 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68758 proven. 2353 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-11-18 16:15:32,303 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:32,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 59, 59] total 90 [2018-11-18 16:15:32,303 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:32,304 INFO L459 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-11-18 16:15:32,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-11-18 16:15:32,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1831, Invalid=6179, Unknown=0, NotChecked=0, Total=8010 [2018-11-18 16:15:32,304 INFO L87 Difference]: Start difference. First operand 2792 states and 2795 transitions. Second operand 90 states. [2018-11-18 16:15:34,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:34,085 INFO L93 Difference]: Finished difference Result 2983 states and 2987 transitions. [2018-11-18 16:15:34,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-11-18 16:15:34,086 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 2782 [2018-11-18 16:15:34,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:34,090 INFO L225 Difference]: With dead ends: 2983 [2018-11-18 16:15:34,090 INFO L226 Difference]: Without dead ends: 2983 [2018-11-18 16:15:34,091 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5678 GetRequests, 5478 SyntacticMatches, 57 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6568 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=5238, Invalid=15642, Unknown=0, NotChecked=0, Total=20880 [2018-11-18 16:15:34,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2983 states. [2018-11-18 16:15:34,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2983 to 2973. [2018-11-18 16:15:34,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2973 states. [2018-11-18 16:15:34,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2973 states to 2973 states and 2977 transitions. [2018-11-18 16:15:34,103 INFO L78 Accepts]: Start accepts. Automaton has 2973 states and 2977 transitions. Word has length 2782 [2018-11-18 16:15:34,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:34,104 INFO L480 AbstractCegarLoop]: Abstraction has 2973 states and 2977 transitions. [2018-11-18 16:15:34,104 INFO L481 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-11-18 16:15:34,104 INFO L276 IsEmpty]: Start isEmpty. Operand 2973 states and 2977 transitions. [2018-11-18 16:15:34,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2958 [2018-11-18 16:15:34,134 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:34,134 INFO L375 BasicCegarLoop]: trace histogram [460, 433, 433, 432, 432, 432, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:34,135 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:15:34,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:34,135 INFO L82 PathProgramCache]: Analyzing trace with hash -1078497095, now seen corresponding path program 68 times [2018-11-18 16:15:34,135 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:34,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:34,136 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:34,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:34,136 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:34,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:37,506 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 136483 proven. 10434 refuted. 0 times theorem prover too weak. 441440 trivial. 0 not checked. [2018-11-18 16:15:37,506 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:37,506 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:37,506 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:37,506 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:37,507 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:37,507 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:37,518 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:15:37,518 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:15:40,378 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-11-18 16:15:40,378 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:15:40,397 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:44,287 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 132360 proven. 6808 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 16:15:44,287 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:49,139 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 132360 proven. 6808 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 16:15:49,158 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:49,159 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 63, 63] total 179 [2018-11-18 16:15:49,159 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:49,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 122 states [2018-11-18 16:15:49,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2018-11-18 16:15:49,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4339, Invalid=27523, Unknown=0, NotChecked=0, Total=31862 [2018-11-18 16:15:49,161 INFO L87 Difference]: Start difference. First operand 2973 states and 2977 transitions. Second operand 122 states. [2018-11-18 16:15:54,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:54,437 INFO L93 Difference]: Finished difference Result 2988 states and 2990 transitions. [2018-11-18 16:15:54,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2018-11-18 16:15:54,437 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 2957 [2018-11-18 16:15:54,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:54,442 INFO L225 Difference]: With dead ends: 2988 [2018-11-18 16:15:54,442 INFO L226 Difference]: Without dead ends: 2982 [2018-11-18 16:15:54,446 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6117 GetRequests, 5794 SyntacticMatches, 5 SemanticMatches, 318 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36315 ImplicationChecksByTransitivity, 7.5s TimeCoverageRelationStatistics Valid=14025, Invalid=88055, Unknown=0, NotChecked=0, Total=102080 [2018-11-18 16:15:54,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2982 states. [2018-11-18 16:15:54,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2982 to 2973. [2018-11-18 16:15:54,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2973 states. [2018-11-18 16:15:54,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2973 states to 2973 states and 2975 transitions. [2018-11-18 16:15:54,460 INFO L78 Accepts]: Start accepts. Automaton has 2973 states and 2975 transitions. Word has length 2957 [2018-11-18 16:15:54,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:54,461 INFO L480 AbstractCegarLoop]: Abstraction has 2973 states and 2975 transitions. [2018-11-18 16:15:54,461 INFO L481 AbstractCegarLoop]: Interpolant automaton has 122 states. [2018-11-18 16:15:54,461 INFO L276 IsEmpty]: Start isEmpty. Operand 2973 states and 2975 transitions. [2018-11-18 16:15:54,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2964 [2018-11-18 16:15:54,493 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:54,493 INFO L375 BasicCegarLoop]: trace histogram [461, 434, 434, 433, 433, 433, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,494 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:15:54,494 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,494 INFO L82 PathProgramCache]: Analyzing trace with hash 303172721, now seen corresponding path program 69 times [2018-11-18 16:15:54,494 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:54,495 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,495 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:54,495 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,495 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:54,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:58,307 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-11-18 16:15:58,307 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:58,307 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:58,307 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:58,307 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:58,307 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:58,308 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:58,320 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:15:58,320 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:15:59,463 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:15:59,464 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:15:59,496 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:59,498 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:15:59,501 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:15:59,505 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:15:59,505 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:15:59,510 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:15:59,516 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:15:59,517 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:16:08,399 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-11-18 16:16:08,399 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:16:12,683 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-11-18 16:16:12,709 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:16:12,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 32] total 93 [2018-11-18 16:16:12,709 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:16:12,710 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-18 16:16:12,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-18 16:16:12,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1609, Invalid=7133, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 16:16:12,711 INFO L87 Difference]: Start difference. First operand 2973 states and 2975 transitions. Second operand 63 states. [2018-11-18 16:16:15,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:15,368 INFO L93 Difference]: Finished difference Result 2987 states and 2990 transitions. [2018-11-18 16:16:15,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-18 16:16:15,368 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 2963 [2018-11-18 16:16:15,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:15,372 INFO L225 Difference]: With dead ends: 2987 [2018-11-18 16:16:15,372 INFO L226 Difference]: Without dead ends: 2987 [2018-11-18 16:16:15,373 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5987 GetRequests, 5810 SyntacticMatches, 56 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4891 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=2762, Invalid=12244, Unknown=0, NotChecked=0, Total=15006 [2018-11-18 16:16:15,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2987 states. [2018-11-18 16:16:15,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2987 to 2979. [2018-11-18 16:16:15,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2979 states. [2018-11-18 16:16:15,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2979 states to 2979 states and 2982 transitions. [2018-11-18 16:16:15,389 INFO L78 Accepts]: Start accepts. Automaton has 2979 states and 2982 transitions. Word has length 2963 [2018-11-18 16:16:15,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:15,390 INFO L480 AbstractCegarLoop]: Abstraction has 2979 states and 2982 transitions. [2018-11-18 16:16:15,390 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-18 16:16:15,391 INFO L276 IsEmpty]: Start isEmpty. Operand 2979 states and 2982 transitions. [2018-11-18 16:16:15,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2970 [2018-11-18 16:16:15,427 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:15,427 INFO L375 BasicCegarLoop]: trace histogram [462, 435, 435, 434, 434, 434, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:15,428 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:16:15,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:15,428 INFO L82 PathProgramCache]: Analyzing trace with hash -1791114375, now seen corresponding path program 70 times [2018-11-18 16:16:15,428 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:15,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:15,428 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:15,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:15,429 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:15,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:18,812 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76203 proven. 2624 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-18 16:16:18,812 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:18,813 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:16:18,813 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:16:18,813 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:16:18,813 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:18,813 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:16:18,822 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:18,822 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:16:19,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:19,235 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:16:22,472 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76289 proven. 2538 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-18 16:16:22,472 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:16:25,431 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76289 proven. 2538 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-18 16:16:25,449 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:16:25,450 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 61, 61] total 93 [2018-11-18 16:16:25,450 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:16:25,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-18 16:16:25,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-18 16:16:25,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1954, Invalid=6602, Unknown=0, NotChecked=0, Total=8556 [2018-11-18 16:16:25,451 INFO L87 Difference]: Start difference. First operand 2979 states and 2982 transitions. Second operand 93 states. [2018-11-18 16:16:27,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:27,485 INFO L93 Difference]: Finished difference Result 3176 states and 3180 transitions. [2018-11-18 16:16:27,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 16:16:27,485 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2969 [2018-11-18 16:16:27,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:27,490 INFO L225 Difference]: With dead ends: 3176 [2018-11-18 16:16:27,490 INFO L226 Difference]: Without dead ends: 3176 [2018-11-18 16:16:27,492 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6056 GetRequests, 5849 SyntacticMatches, 59 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7035 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=5599, Invalid=16751, Unknown=0, NotChecked=0, Total=22350 [2018-11-18 16:16:27,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3176 states. [2018-11-18 16:16:27,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3176 to 3166. [2018-11-18 16:16:27,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3166 states. [2018-11-18 16:16:27,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3166 states to 3166 states and 3170 transitions. [2018-11-18 16:16:27,507 INFO L78 Accepts]: Start accepts. Automaton has 3166 states and 3170 transitions. Word has length 2969 [2018-11-18 16:16:27,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:27,509 INFO L480 AbstractCegarLoop]: Abstraction has 3166 states and 3170 transitions. [2018-11-18 16:16:27,509 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-18 16:16:27,509 INFO L276 IsEmpty]: Start isEmpty. Operand 3166 states and 3170 transitions. [2018-11-18 16:16:27,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3151 [2018-11-18 16:16:27,544 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:27,545 INFO L375 BasicCegarLoop]: trace histogram [491, 463, 463, 462, 462, 462, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:27,545 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:16:27,545 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:27,545 INFO L82 PathProgramCache]: Analyzing trace with hash 370962958, now seen corresponding path program 71 times [2018-11-18 16:16:27,545 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:27,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:27,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:27,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:27,546 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:27,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:31,569 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 212591 proven. 7389 refuted. 0 times theorem prover too weak. 451768 trivial. 0 not checked. [2018-11-18 16:16:31,569 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:31,569 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:16:31,569 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:16:31,569 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:16:31,569 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:31,569 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:16:31,577 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:16:31,577 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:16:34,250 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-11-18 16:16:34,250 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:16:34,271 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:16:38,600 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 147035 proven. 7312 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 16:16:38,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:16:43,911 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 147035 proven. 7312 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 16:16:43,930 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:16:43,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 65, 65] total 185 [2018-11-18 16:16:43,930 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:16:43,931 INFO L459 AbstractCegarLoop]: Interpolant automaton has 126 states [2018-11-18 16:16:43,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 126 interpolants. [2018-11-18 16:16:43,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4663, Invalid=29377, Unknown=0, NotChecked=0, Total=34040 [2018-11-18 16:16:43,932 INFO L87 Difference]: Start difference. First operand 3166 states and 3170 transitions. Second operand 126 states. [2018-11-18 16:16:48,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:48,466 INFO L93 Difference]: Finished difference Result 3181 states and 3183 transitions. [2018-11-18 16:16:48,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-11-18 16:16:48,466 INFO L78 Accepts]: Start accepts. Automaton has 126 states. Word has length 3150 [2018-11-18 16:16:48,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:48,471 INFO L225 Difference]: With dead ends: 3181 [2018-11-18 16:16:48,471 INFO L226 Difference]: Without dead ends: 3175 [2018-11-18 16:16:48,474 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6484 GetRequests, 6176 SyntacticMatches, 5 SemanticMatches, 303 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31235 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=15359, Invalid=77361, Unknown=0, NotChecked=0, Total=92720 [2018-11-18 16:16:48,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3175 states. [2018-11-18 16:16:48,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3175 to 3166. [2018-11-18 16:16:48,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3166 states. [2018-11-18 16:16:48,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3166 states to 3166 states and 3168 transitions. [2018-11-18 16:16:48,490 INFO L78 Accepts]: Start accepts. Automaton has 3166 states and 3168 transitions. Word has length 3150 [2018-11-18 16:16:48,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:48,491 INFO L480 AbstractCegarLoop]: Abstraction has 3166 states and 3168 transitions. [2018-11-18 16:16:48,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 126 states. [2018-11-18 16:16:48,491 INFO L276 IsEmpty]: Start isEmpty. Operand 3166 states and 3168 transitions. [2018-11-18 16:16:48,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3157 [2018-11-18 16:16:48,525 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:48,525 INFO L375 BasicCegarLoop]: trace histogram [492, 464, 464, 463, 463, 463, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:48,525 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:16:48,525 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:48,526 INFO L82 PathProgramCache]: Analyzing trace with hash 475608582, now seen corresponding path program 72 times [2018-11-18 16:16:48,526 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:48,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:48,526 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:48,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:48,526 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:48,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:52,724 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-11-18 16:16:52,724 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:52,724 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:16:52,724 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:16:52,725 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:16:52,725 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:52,725 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:16:52,734 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:16:52,734 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:16:53,948 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:16:53,948 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:16:53,984 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:16:53,986 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:16:53,994 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:16:53,999 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:16:54,000 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:16:54,007 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:16:54,014 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:16:54,014 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:17:04,467 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-11-18 16:17:04,468 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:17:09,108 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-11-18 16:17:09,133 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:17:09,134 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 33] total 96 [2018-11-18 16:17:09,134 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:17:09,135 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-11-18 16:17:09,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-11-18 16:17:09,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1681, Invalid=7631, Unknown=0, NotChecked=0, Total=9312 [2018-11-18 16:17:09,136 INFO L87 Difference]: Start difference. First operand 3166 states and 3168 transitions. Second operand 65 states. [2018-11-18 16:17:11,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:17:11,100 INFO L93 Difference]: Finished difference Result 3180 states and 3183 transitions. [2018-11-18 16:17:11,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-18 16:17:11,100 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 3156 [2018-11-18 16:17:11,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:17:11,104 INFO L225 Difference]: With dead ends: 3180 [2018-11-18 16:17:11,104 INFO L226 Difference]: Without dead ends: 3180 [2018-11-18 16:17:11,105 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6375 GetRequests, 6192 SyntacticMatches, 58 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5199 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=2877, Invalid=13125, Unknown=0, NotChecked=0, Total=16002 [2018-11-18 16:17:11,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3180 states. [2018-11-18 16:17:11,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3180 to 3172. [2018-11-18 16:17:11,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3172 states. [2018-11-18 16:17:11,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3172 states to 3172 states and 3175 transitions. [2018-11-18 16:17:11,119 INFO L78 Accepts]: Start accepts. Automaton has 3172 states and 3175 transitions. Word has length 3156 [2018-11-18 16:17:11,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:17:11,120 INFO L480 AbstractCegarLoop]: Abstraction has 3172 states and 3175 transitions. [2018-11-18 16:17:11,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-11-18 16:17:11,120 INFO L276 IsEmpty]: Start isEmpty. Operand 3172 states and 3175 transitions. [2018-11-18 16:17:11,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3163 [2018-11-18 16:17:11,154 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:17:11,154 INFO L375 BasicCegarLoop]: trace histogram [493, 465, 465, 464, 464, 464, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:17:11,154 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:17:11,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:17:11,155 INFO L82 PathProgramCache]: Analyzing trace with hash 935504206, now seen corresponding path program 73 times [2018-11-18 16:17:11,155 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:17:11,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:11,155 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:17:11,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:11,155 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:17:11,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:14,747 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84261 proven. 2819 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-11-18 16:17:14,747 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:14,747 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:14,747 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:14,748 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:14,748 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:14,748 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:14,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:17:14,758 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:17:15,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:15,199 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:17:18,748 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84350 proven. 2730 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-11-18 16:17:18,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:17:21,963 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84350 proven. 2730 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-11-18 16:17:21,981 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:17:21,982 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 63, 63] total 96 [2018-11-18 16:17:21,982 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:17:21,983 INFO L459 AbstractCegarLoop]: Interpolant automaton has 96 states [2018-11-18 16:17:21,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2018-11-18 16:17:21,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2081, Invalid=7039, Unknown=0, NotChecked=0, Total=9120 [2018-11-18 16:17:21,984 INFO L87 Difference]: Start difference. First operand 3172 states and 3175 transitions. Second operand 96 states. [2018-11-18 16:17:23,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:17:23,808 INFO L93 Difference]: Finished difference Result 3375 states and 3379 transitions. [2018-11-18 16:17:23,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-11-18 16:17:23,808 INFO L78 Accepts]: Start accepts. Automaton has 96 states. Word has length 3162 [2018-11-18 16:17:23,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:17:23,812 INFO L225 Difference]: With dead ends: 3375 [2018-11-18 16:17:23,812 INFO L226 Difference]: Without dead ends: 3375 [2018-11-18 16:17:23,813 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6446 GetRequests, 6232 SyntacticMatches, 61 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7518 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=5972, Invalid=17898, Unknown=0, NotChecked=0, Total=23870 [2018-11-18 16:17:23,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3375 states. [2018-11-18 16:17:23,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3375 to 3365. [2018-11-18 16:17:23,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3365 states. [2018-11-18 16:17:23,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3365 states to 3365 states and 3369 transitions. [2018-11-18 16:17:23,828 INFO L78 Accepts]: Start accepts. Automaton has 3365 states and 3369 transitions. Word has length 3162 [2018-11-18 16:17:23,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:17:23,830 INFO L480 AbstractCegarLoop]: Abstraction has 3365 states and 3369 transitions. [2018-11-18 16:17:23,830 INFO L481 AbstractCegarLoop]: Interpolant automaton has 96 states. [2018-11-18 16:17:23,830 INFO L276 IsEmpty]: Start isEmpty. Operand 3365 states and 3369 transitions. [2018-11-18 16:17:23,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3350 [2018-11-18 16:17:23,869 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:17:23,870 INFO L375 BasicCegarLoop]: trace histogram [523, 494, 494, 493, 493, 493, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:17:23,870 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:17:23,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:17:23,870 INFO L82 PathProgramCache]: Analyzing trace with hash -426819487, now seen corresponding path program 74 times [2018-11-18 16:17:23,870 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:17:23,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:23,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:17:23,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:23,871 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:17:24,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:28,023 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 167558 proven. 11970 refuted. 0 times theorem prover too weak. 584158 trivial. 0 not checked. [2018-11-18 16:17:28,023 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:28,023 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:28,023 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:28,023 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:28,023 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:28,023 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:28,029 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:17:28,029 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:17:33,027 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-11-18 16:17:33,028 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:17:33,052 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:17:37,835 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 162756 proven. 7834 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 16:17:37,835 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:17:43,614 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 162756 proven. 7834 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 16:17:43,633 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:17:43,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 67, 67] total 191 [2018-11-18 16:17:43,634 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:17:43,635 INFO L459 AbstractCegarLoop]: Interpolant automaton has 130 states [2018-11-18 16:17:43,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 130 interpolants. [2018-11-18 16:17:43,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4947, Invalid=31343, Unknown=0, NotChecked=0, Total=36290 [2018-11-18 16:17:43,636 INFO L87 Difference]: Start difference. First operand 3365 states and 3369 transitions. Second operand 130 states. [2018-11-18 16:17:49,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:17:49,782 INFO L93 Difference]: Finished difference Result 3380 states and 3382 transitions. [2018-11-18 16:17:49,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 159 states. [2018-11-18 16:17:49,782 INFO L78 Accepts]: Start accepts. Automaton has 130 states. Word has length 3349 [2018-11-18 16:17:49,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:17:49,787 INFO L225 Difference]: With dead ends: 3380 [2018-11-18 16:17:49,787 INFO L226 Difference]: Without dead ends: 3374 [2018-11-18 16:17:49,791 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6915 GetRequests, 6570 SyntacticMatches, 5 SemanticMatches, 340 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41642 ImplicationChecksByTransitivity, 8.5s TimeCoverageRelationStatistics Valid=15981, Invalid=100641, Unknown=0, NotChecked=0, Total=116622 [2018-11-18 16:17:49,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3374 states. [2018-11-18 16:17:49,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3374 to 3365. [2018-11-18 16:17:49,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3365 states. [2018-11-18 16:17:49,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3365 states to 3365 states and 3367 transitions. [2018-11-18 16:17:49,806 INFO L78 Accepts]: Start accepts. Automaton has 3365 states and 3367 transitions. Word has length 3349 [2018-11-18 16:17:49,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:17:49,808 INFO L480 AbstractCegarLoop]: Abstraction has 3365 states and 3367 transitions. [2018-11-18 16:17:49,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 130 states. [2018-11-18 16:17:49,808 INFO L276 IsEmpty]: Start isEmpty. Operand 3365 states and 3367 transitions. [2018-11-18 16:17:49,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3356 [2018-11-18 16:17:49,847 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:17:49,848 INFO L375 BasicCegarLoop]: trace histogram [524, 495, 495, 494, 494, 494, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:17:49,848 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:17:49,848 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:17:49,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1061751271, now seen corresponding path program 75 times [2018-11-18 16:17:49,849 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:17:49,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:49,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:17:49,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:49,849 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:17:50,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:54,489 INFO L134 CoverageAnalysis]: Checked inductivity of 766706 backedges. 87203 proven. 2730 refuted. 0 times theorem prover too weak. 676773 trivial. 0 not checked. [2018-11-18 16:17:54,489 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:54,490 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:54,490 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:54,490 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:54,490 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:54,490 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:54,499 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:17:54,499 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:17:55,920 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:17:55,920 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:17:55,958 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:17:55,960 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:17:55,978 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:17:55,983 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:17:55,983 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:17:55,989 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:17:55,995 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:17:55,995 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:18:07,665 INFO L134 CoverageAnalysis]: Checked inductivity of 766706 backedges. 87203 proven. 2730 refuted. 0 times theorem prover too weak. 676773 trivial. 0 not checked. [2018-11-18 16:18:07,665 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:18:12,897 INFO L134 CoverageAnalysis]: Checked inductivity of 766706 backedges. 87203 proven. 2730 refuted. 0 times theorem prover too weak. 676773 trivial. 0 not checked. [2018-11-18 16:18:12,923 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:18:12,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 34] total 99 [2018-11-18 16:18:12,924 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:18:12,925 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 16:18:12,925 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 16:18:12,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1753, Invalid=8147, Unknown=0, NotChecked=0, Total=9900 [2018-11-18 16:18:12,926 INFO L87 Difference]: Start difference. First operand 3365 states and 3367 transitions. Second operand 67 states. [2018-11-18 16:18:14,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:18:14,915 INFO L93 Difference]: Finished difference Result 3379 states and 3382 transitions. [2018-11-18 16:18:14,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-18 16:18:14,916 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 3355 [2018-11-18 16:18:14,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:18:14,919 INFO L225 Difference]: With dead ends: 3379 [2018-11-18 16:18:14,919 INFO L226 Difference]: Without dead ends: 3379 [2018-11-18 16:18:14,920 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6775 GetRequests, 6586 SyntacticMatches, 60 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5515 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=2991, Invalid=14039, Unknown=0, NotChecked=0, Total=17030 [2018-11-18 16:18:14,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3379 states. [2018-11-18 16:18:14,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3379 to 3371. [2018-11-18 16:18:14,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3371 states. [2018-11-18 16:18:14,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3371 states to 3371 states and 3374 transitions. [2018-11-18 16:18:14,937 INFO L78 Accepts]: Start accepts. Automaton has 3371 states and 3374 transitions. Word has length 3355 [2018-11-18 16:18:14,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:18:14,938 INFO L480 AbstractCegarLoop]: Abstraction has 3371 states and 3374 transitions. [2018-11-18 16:18:14,939 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 16:18:14,939 INFO L276 IsEmpty]: Start isEmpty. Operand 3371 states and 3374 transitions. [2018-11-18 16:18:14,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3362 [2018-11-18 16:18:14,994 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:18:14,994 INFO L375 BasicCegarLoop]: trace histogram [525, 496, 496, 495, 495, 495, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:18:14,994 INFO L423 AbstractCegarLoop]: === Iteration 90 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:18:14,994 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:18:14,994 INFO L82 PathProgramCache]: Analyzing trace with hash -68759775, now seen corresponding path program 76 times [2018-11-18 16:18:14,994 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:18:14,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:14,995 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:18:14,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:14,995 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:18:15,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:18,993 INFO L134 CoverageAnalysis]: Checked inductivity of 769732 backedges. 92867 proven. 3021 refuted. 0 times theorem prover too weak. 673844 trivial. 0 not checked. [2018-11-18 16:18:18,993 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:18,994 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:18:18,994 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:18:18,994 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:18:18,994 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:18,994 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:18:19,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:18:19,003 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:18:19,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:19,497 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:18:23,407 INFO L134 CoverageAnalysis]: Checked inductivity of 769732 backedges. 92959 proven. 2929 refuted. 0 times theorem prover too weak. 673844 trivial. 0 not checked. [2018-11-18 16:18:23,407 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:18:26,953 INFO L134 CoverageAnalysis]: Checked inductivity of 769732 backedges. 92959 proven. 2929 refuted. 0 times theorem prover too weak. 673844 trivial. 0 not checked. [2018-11-18 16:18:26,971 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:18:26,972 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 65, 65] total 99 [2018-11-18 16:18:26,972 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:18:26,973 INFO L459 AbstractCegarLoop]: Interpolant automaton has 99 states [2018-11-18 16:18:26,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2018-11-18 16:18:26,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2212, Invalid=7490, Unknown=0, NotChecked=0, Total=9702 [2018-11-18 16:18:26,973 INFO L87 Difference]: Start difference. First operand 3371 states and 3374 transitions. Second operand 99 states. [2018-11-18 16:18:28,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:18:28,875 INFO L93 Difference]: Finished difference Result 3580 states and 3584 transitions. [2018-11-18 16:18:28,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-11-18 16:18:28,875 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 3361 [2018-11-18 16:18:28,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:18:28,879 INFO L225 Difference]: With dead ends: 3580 [2018-11-18 16:18:28,879 INFO L226 Difference]: Without dead ends: 3580 [2018-11-18 16:18:28,880 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6848 GetRequests, 6627 SyntacticMatches, 63 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8017 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=6357, Invalid=19083, Unknown=0, NotChecked=0, Total=25440 [2018-11-18 16:18:28,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3580 states. [2018-11-18 16:18:28,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3580 to 3570. [2018-11-18 16:18:28,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2018-11-18 16:18:28,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 3574 transitions. [2018-11-18 16:18:28,895 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 3574 transitions. Word has length 3361 [2018-11-18 16:18:28,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:18:28,896 INFO L480 AbstractCegarLoop]: Abstraction has 3570 states and 3574 transitions. [2018-11-18 16:18:28,896 INFO L481 AbstractCegarLoop]: Interpolant automaton has 99 states. [2018-11-18 16:18:28,896 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 3574 transitions. [2018-11-18 16:18:28,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3555 [2018-11-18 16:18:28,938 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:18:28,938 INFO L375 BasicCegarLoop]: trace histogram [556, 526, 526, 525, 525, 525, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:18:28,938 INFO L423 AbstractCegarLoop]: === Iteration 91 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:18:28,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:18:28,939 INFO L82 PathProgramCache]: Analyzing trace with hash 2067800054, now seen corresponding path program 77 times [2018-11-18 16:18:28,939 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:18:28,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:28,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:18:28,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:28,940 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:18:29,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:33,820 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 260239 proven. 8457 refuted. 0 times theorem prover too weak. 596039 trivial. 0 not checked. [2018-11-18 16:18:33,820 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:33,820 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:18:33,820 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:18:33,820 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:18:33,820 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:33,820 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:18:33,830 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:18:33,830 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:18:36,685 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-11-18 16:18:36,685 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:18:36,717 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:18:42,107 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 179559 proven. 8374 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 16:18:42,107 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:18:48,503 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 179559 proven. 8374 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 16:18:48,522 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:18:48,523 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 69, 69] total 197 [2018-11-18 16:18:48,523 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:18:48,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 134 states [2018-11-18 16:18:48,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 134 interpolants. [2018-11-18 16:18:48,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5293, Invalid=33319, Unknown=0, NotChecked=0, Total=38612 [2018-11-18 16:18:48,525 INFO L87 Difference]: Start difference. First operand 3570 states and 3574 transitions. Second operand 134 states. [2018-11-18 16:18:53,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:18:53,957 INFO L93 Difference]: Finished difference Result 3585 states and 3587 transitions. [2018-11-18 16:18:53,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 136 states. [2018-11-18 16:18:53,957 INFO L78 Accepts]: Start accepts. Automaton has 134 states. Word has length 3554 [2018-11-18 16:18:53,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:18:53,962 INFO L225 Difference]: With dead ends: 3585 [2018-11-18 16:18:53,962 INFO L226 Difference]: Without dead ends: 3579 [2018-11-18 16:18:53,966 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7304 GetRequests, 6976 SyntacticMatches, 5 SemanticMatches, 323 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35590 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=17438, Invalid=87862, Unknown=0, NotChecked=0, Total=105300 [2018-11-18 16:18:53,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3579 states. [2018-11-18 16:18:53,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3579 to 3570. [2018-11-18 16:18:53,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2018-11-18 16:18:53,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 3572 transitions. [2018-11-18 16:18:53,981 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 3572 transitions. Word has length 3554 [2018-11-18 16:18:53,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:18:53,983 INFO L480 AbstractCegarLoop]: Abstraction has 3570 states and 3572 transitions. [2018-11-18 16:18:53,983 INFO L481 AbstractCegarLoop]: Interpolant automaton has 134 states. [2018-11-18 16:18:53,983 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 3572 transitions. [2018-11-18 16:18:54,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3561 [2018-11-18 16:18:54,027 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:18:54,027 INFO L375 BasicCegarLoop]: trace histogram [557, 527, 527, 526, 526, 526, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:18:54,027 INFO L423 AbstractCegarLoop]: === Iteration 92 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:18:54,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:18:54,028 INFO L82 PathProgramCache]: Analyzing trace with hash -1275048466, now seen corresponding path program 78 times [2018-11-18 16:18:54,028 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:18:54,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:54,028 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:18:54,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:54,029 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:18:54,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:59,245 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-11-18 16:18:59,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:59,246 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:18:59,246 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:18:59,246 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:18:59,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:59,246 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:18:59,252 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:18:59,252 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:19:00,713 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:19:00,713 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:19:00,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:19:00,754 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:19:00,761 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:19:00,771 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 16:19:00,771 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 16:19:00,777 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 16:19:00,784 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 16:19:00,784 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 16:19:13,304 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-11-18 16:19:13,304 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:19:18,962 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-11-18 16:19:18,989 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:19:18,990 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 35] total 102 [2018-11-18 16:19:18,990 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:19:18,991 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-18 16:19:18,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-18 16:19:18,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1825, Invalid=8681, Unknown=0, NotChecked=0, Total=10506 [2018-11-18 16:19:18,991 INFO L87 Difference]: Start difference. First operand 3570 states and 3572 transitions. Second operand 69 states. [2018-11-18 16:19:21,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:19:21,422 INFO L93 Difference]: Finished difference Result 3584 states and 3587 transitions. [2018-11-18 16:19:21,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 16:19:21,423 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3560 [2018-11-18 16:19:21,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:19:21,427 INFO L225 Difference]: With dead ends: 3584 [2018-11-18 16:19:21,427 INFO L226 Difference]: Without dead ends: 3584 [2018-11-18 16:19:21,427 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7187 GetRequests, 6992 SyntacticMatches, 62 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5839 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=3104, Invalid=14986, Unknown=0, NotChecked=0, Total=18090 [2018-11-18 16:19:21,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3584 states. [2018-11-18 16:19:21,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3584 to 3576. [2018-11-18 16:19:21,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3576 states. [2018-11-18 16:19:21,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3576 states to 3576 states and 3579 transitions. [2018-11-18 16:19:21,441 INFO L78 Accepts]: Start accepts. Automaton has 3576 states and 3579 transitions. Word has length 3560 [2018-11-18 16:19:21,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:19:21,442 INFO L480 AbstractCegarLoop]: Abstraction has 3576 states and 3579 transitions. [2018-11-18 16:19:21,443 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-18 16:19:21,443 INFO L276 IsEmpty]: Start isEmpty. Operand 3576 states and 3579 transitions. [2018-11-18 16:19:21,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3567 [2018-11-18 16:19:21,485 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:19:21,485 INFO L375 BasicCegarLoop]: trace histogram [558, 528, 528, 527, 527, 527, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:19:21,485 INFO L423 AbstractCegarLoop]: === Iteration 93 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:19:21,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:19:21,485 INFO L82 PathProgramCache]: Analyzing trace with hash -702401738, now seen corresponding path program 79 times [2018-11-18 16:19:21,485 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:19:21,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:21,486 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:19:21,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:21,486 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:19:21,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:25,900 INFO L134 CoverageAnalysis]: Checked inductivity of 871169 backedges. 102039 proven. 3230 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-11-18 16:19:25,900 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:25,900 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:19:25,900 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:19:25,900 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:19:25,900 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:25,900 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:19:25,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:19:25,906 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:19:26,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:26,417 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:19:30,752 INFO L134 CoverageAnalysis]: Checked inductivity of 871169 backedges. 102134 proven. 3135 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-11-18 16:19:30,752 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:19:34,701 INFO L134 CoverageAnalysis]: Checked inductivity of 871169 backedges. 102134 proven. 3135 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-11-18 16:19:34,720 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:19:34,721 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 67, 67] total 102 [2018-11-18 16:19:34,721 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:19:34,721 INFO L459 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-11-18 16:19:34,722 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-11-18 16:19:34,722 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2347, Invalid=7955, Unknown=0, NotChecked=0, Total=10302 [2018-11-18 16:19:34,722 INFO L87 Difference]: Start difference. First operand 3576 states and 3579 transitions. Second operand 102 states. [2018-11-18 16:19:36,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:19:36,798 INFO L93 Difference]: Finished difference Result 3791 states and 3795 transitions. [2018-11-18 16:19:36,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-11-18 16:19:36,799 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 3566 [2018-11-18 16:19:36,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:19:36,804 INFO L225 Difference]: With dead ends: 3791 [2018-11-18 16:19:36,804 INFO L226 Difference]: Without dead ends: 3791 [2018-11-18 16:19:36,806 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7262 GetRequests, 7034 SyntacticMatches, 65 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8532 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=6754, Invalid=20306, Unknown=0, NotChecked=0, Total=27060 [2018-11-18 16:19:36,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3791 states. [2018-11-18 16:19:36,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3791 to 3781. [2018-11-18 16:19:36,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3781 states. [2018-11-18 16:19:36,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3781 states to 3781 states and 3785 transitions. [2018-11-18 16:19:36,823 INFO L78 Accepts]: Start accepts. Automaton has 3781 states and 3785 transitions. Word has length 3566 [2018-11-18 16:19:36,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:19:36,825 INFO L480 AbstractCegarLoop]: Abstraction has 3781 states and 3785 transitions. [2018-11-18 16:19:36,825 INFO L481 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-11-18 16:19:36,825 INFO L276 IsEmpty]: Start isEmpty. Operand 3781 states and 3785 transitions. [2018-11-18 16:19:36,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3766 [2018-11-18 16:19:36,873 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:19:36,873 INFO L375 BasicCegarLoop]: trace histogram [590, 559, 559, 558, 558, 558, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:19:36,874 INFO L423 AbstractCegarLoop]: === Iteration 94 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:19:36,874 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:19:36,874 INFO L82 PathProgramCache]: Analyzing trace with hash 1642832265, now seen corresponding path program 80 times [2018-11-18 16:19:36,874 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:19:36,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:36,875 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:19:36,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:36,875 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:19:37,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:41,969 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 203013 proven. 13610 refuted. 0 times theorem prover too weak. 758854 trivial. 0 not checked. [2018-11-18 16:19:41,969 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:41,969 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:19:41,969 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:19:41,969 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:19:41,969 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:41,969 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:19:41,979 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:19:41,980 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:19:48,469 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-11-18 16:19:48,469 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:19:48,492 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:19:54,198 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 197480 proven. 8932 refuted. 0 times theorem prover too weak. 769065 trivial. 0 not checked. [2018-11-18 16:19:54,198 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:20:01,038 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 197480 proven. 8932 refuted. 0 times theorem prover too weak. 769065 trivial. 0 not checked. [2018-11-18 16:20:01,058 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:20:01,059 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 71, 71] total 203 [2018-11-18 16:20:01,059 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:20:01,059 INFO L459 AbstractCegarLoop]: Interpolant automaton has 138 states [2018-11-18 16:20:01,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2018-11-18 16:20:01,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5595, Invalid=35411, Unknown=0, NotChecked=0, Total=41006 [2018-11-18 16:20:01,061 INFO L87 Difference]: Start difference. First operand 3781 states and 3785 transitions. Second operand 138 states. [2018-11-18 16:20:07,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:20:07,457 INFO L93 Difference]: Finished difference Result 3796 states and 3798 transitions. [2018-11-18 16:20:07,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 169 states. [2018-11-18 16:20:07,457 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 3765 [2018-11-18 16:20:07,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:20:07,461 INFO L225 Difference]: With dead ends: 3796 [2018-11-18 16:20:07,461 INFO L226 Difference]: Without dead ends: 3790 [2018-11-18 16:20:07,464 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7761 GetRequests, 7394 SyntacticMatches, 5 SemanticMatches, 362 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47333 ImplicationChecksByTransitivity, 9.4s TimeCoverageRelationStatistics Valid=18065, Invalid=114067, Unknown=0, NotChecked=0, Total=132132 [2018-11-18 16:20:07,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3790 states. [2018-11-18 16:20:07,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3790 to 3781. [2018-11-18 16:20:07,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3781 states. [2018-11-18 16:20:07,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3781 states to 3781 states and 3783 transitions. [2018-11-18 16:20:07,478 INFO L78 Accepts]: Start accepts. Automaton has 3781 states and 3783 transitions. Word has length 3765 [2018-11-18 16:20:07,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:20:07,479 INFO L480 AbstractCegarLoop]: Abstraction has 3781 states and 3783 transitions. [2018-11-18 16:20:07,479 INFO L481 AbstractCegarLoop]: Interpolant automaton has 138 states. [2018-11-18 16:20:07,479 INFO L276 IsEmpty]: Start isEmpty. Operand 3781 states and 3783 transitions. [2018-11-18 16:20:07,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3772 [2018-11-18 16:20:07,526 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:20:07,526 INFO L375 BasicCegarLoop]: trace histogram [591, 560, 560, 559, 559, 559, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:20:07,526 INFO L423 AbstractCegarLoop]: === Iteration 95 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 16:20:07,526 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:20:07,526 INFO L82 PathProgramCache]: Analyzing trace with hash -350662335, now seen corresponding path program 81 times [2018-11-18 16:20:07,526 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:20:07,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:20:07,527 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:20:07,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:20:07,527 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:20:08,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:20:09,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:20:09,775 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 16:20:10,197 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 04:20:10 BoogieIcfgContainer [2018-11-18 16:20:10,197 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 16:20:10,197 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 16:20:10,197 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 16:20:10,198 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 16:20:10,198 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:09:29" (3/4) ... [2018-11-18 16:20:10,200 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 16:20:10,540 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_e3ccd909-5917-45af-a0a6-1001eecfc96b/bin-2019/utaipan/witness.graphml [2018-11-18 16:20:10,540 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 16:20:10,541 INFO L168 Benchmark]: Toolchain (without parser) took 641097.62 ms. Allocated memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: 4.1 GB). Free memory was 958.1 MB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.5 GB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,542 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 16:20:10,542 INFO L168 Benchmark]: CACSL2BoogieTranslator took 150.13 ms. Allocated memory is still 1.0 GB. Free memory was 958.1 MB in the beginning and 947.3 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,543 INFO L168 Benchmark]: Boogie Procedure Inliner took 20.44 ms. Allocated memory is still 1.0 GB. Free memory was 947.3 MB in the beginning and 944.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,543 INFO L168 Benchmark]: Boogie Preprocessor took 55.40 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 158.9 MB). Free memory was 944.6 MB in the beginning and 1.2 GB in the end (delta: -208.9 MB). Peak memory consumption was 14.6 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,543 INFO L168 Benchmark]: RCFGBuilder took 212.31 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 17.9 MB). Peak memory consumption was 17.9 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,543 INFO L168 Benchmark]: TraceAbstraction took 640313.62 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.7 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,544 INFO L168 Benchmark]: Witness Printer took 342.82 ms. Allocated memory is still 5.1 GB. Free memory was 2.7 GB in the beginning and 2.6 GB in the end (delta: 166.7 MB). Peak memory consumption was 166.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:10,545 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 150.13 ms. Allocated memory is still 1.0 GB. Free memory was 958.1 MB in the beginning and 947.3 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 20.44 ms. Allocated memory is still 1.0 GB. Free memory was 947.3 MB in the beginning and 944.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.40 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 158.9 MB). Free memory was 944.6 MB in the beginning and 1.2 GB in the end (delta: -208.9 MB). Peak memory consumption was 14.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 212.31 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 17.9 MB). Peak memory consumption was 17.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 640313.62 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.7 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 342.82 ms. Allocated memory is still 5.1 GB. Free memory was 2.7 GB in the beginning and 2.6 GB in the end (delta: 166.7 MB). Peak memory consumption was 166.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; [L26] i = 0 VAL [b={159:0}, i=0, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=0, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={143:0}, b={143:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={143:0}, b={143:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={143:0}, b={143:0}, i=0, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={143:0}, b={143:0}, b[i]=160, i=0, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={143:0}, b={143:0}, i=1, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={143:0}, b={143:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={143:0}, b={143:0}, i=1, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={143:0}, b={143:0}, b[i]=131, i=1, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={143:0}, b={143:0}, i=2, size=0] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={143:0}, b={143:0}, i=2, size=0] [L20] RET return i; VAL [\old(size)=0, \result=2, b={143:0}, b={143:0}, i=2, size=0] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=2, i=0, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=2, i=0, mask={143:0}] [L26] i++ VAL [b={159:0}, i=1, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=1, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=160, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=131, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=133, i=2, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=3, size=1] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={143:0}, b={143:0}, i=3, size=1] [L20] RET return i; VAL [\old(size)=1, \result=3, b={143:0}, b={143:0}, i=3, size=1] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=3, i=1, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=3, i=1, mask={143:0}] [L26] i++ VAL [b={159:0}, i=2, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=2, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=160, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=131, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=133, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=135, i=3, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=4, size=2] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={143:0}, b={143:0}, i=4, size=2] [L20] RET return i; VAL [\old(size)=2, \result=4, b={143:0}, b={143:0}, i=4, size=2] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=4, i=2, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=4, i=2, mask={143:0}] [L26] i++ VAL [b={159:0}, i=3, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=3, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=160, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=131, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=133, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=135, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=151, i=4, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=5, size=3] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={143:0}, b={143:0}, i=5, size=3] [L20] RET return i; VAL [\old(size)=3, \result=5, b={143:0}, b={143:0}, i=5, size=3] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=5, i=3, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=5, i=3, mask={143:0}] [L26] i++ VAL [b={159:0}, i=4, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=4, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=160, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=131, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=133, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=135, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=151, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=137, i=5, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=6, size=4] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={143:0}, b={143:0}, i=6, size=4] [L20] RET return i; VAL [\old(size)=4, \result=6, b={143:0}, b={143:0}, i=6, size=4] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=6, i=4, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=6, i=4, mask={143:0}] [L26] i++ VAL [b={159:0}, i=5, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=5, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=160, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=131, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=133, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=135, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=151, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=137, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=136, i=6, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=7, size=5] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={143:0}, b={143:0}, i=7, size=5] [L20] RET return i; VAL [\old(size)=5, \result=7, b={143:0}, b={143:0}, i=7, size=5] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=7, i=5, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=7, i=5, mask={143:0}] [L26] i++ VAL [b={159:0}, i=6, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=6, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=160, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=131, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=133, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=135, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=151, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=137, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=136, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=154, i=7, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=8, size=6] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={143:0}, b={143:0}, i=8, size=6] [L20] RET return i; VAL [\old(size)=6, \result=8, b={143:0}, b={143:0}, i=8, size=6] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=8, i=6, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=8, i=6, mask={143:0}] [L26] i++ VAL [b={159:0}, i=7, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=7, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=160, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=131, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=133, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=135, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=151, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=137, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=136, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=154, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=132, i=8, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=9, size=7] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={143:0}, b={143:0}, i=9, size=7] [L20] RET return i; VAL [\old(size)=7, \result=9, b={143:0}, b={143:0}, i=9, size=7] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=9, i=7, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=9, i=7, mask={143:0}] [L26] i++ VAL [b={159:0}, i=8, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=8, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=160, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=131, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=133, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=135, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=151, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=137, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=136, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=154, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=132, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=138, i=9, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=10, size=8] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={143:0}, b={143:0}, i=10, size=8] [L20] RET return i; VAL [\old(size)=8, \result=10, b={143:0}, b={143:0}, i=10, size=8] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=10, i=8, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=10, i=8, mask={143:0}] [L26] i++ VAL [b={159:0}, i=9, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=9, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=160, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=131, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=133, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=135, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=151, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=137, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=136, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=154, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=132, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=138, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=150, i=10, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=11, size=9] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={143:0}, b={143:0}, i=11, size=9] [L20] RET return i; VAL [\old(size)=9, \result=11, b={143:0}, b={143:0}, i=11, size=9] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=11, i=9, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=11, i=9, mask={143:0}] [L26] i++ VAL [b={159:0}, i=10, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=10, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=160, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=131, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=133, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=135, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=151, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=137, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=136, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=154, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=132, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=138, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=129, i=11, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=12, size=10] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={143:0}, b={143:0}, i=12, size=10] [L20] RET return i; VAL [\old(size)=10, \result=12, b={143:0}, b={143:0}, i=12, size=10] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=12, i=10, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=12, i=10, mask={143:0}] [L26] i++ VAL [b={159:0}, i=11, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=11, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=160, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=131, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=133, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=135, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=151, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=137, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=136, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=154, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=132, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=138, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=129, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=144, i=12, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=13, size=11] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={143:0}, b={143:0}, i=13, size=11] [L20] RET return i; VAL [\old(size)=11, \result=13, b={143:0}, b={143:0}, i=13, size=11] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=13, i=11, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=13, i=11, mask={143:0}] [L26] i++ VAL [b={159:0}, i=12, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=12, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=160, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=131, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=133, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=135, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=151, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=137, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=136, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=154, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=132, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=138, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=129, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=144, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=134, i=13, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=14, size=12] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={143:0}, b={143:0}, i=14, size=12] [L20] RET return i; VAL [\old(size)=12, \result=14, b={143:0}, b={143:0}, i=14, size=12] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=14, i=12, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=14, i=12, mask={143:0}] [L26] i++ VAL [b={159:0}, i=13, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=13, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=160, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=131, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=133, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=135, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=151, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=137, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=136, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=154, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=132, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=138, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=129, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=144, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=134, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=155, i=14, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=15, size=13] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={143:0}, b={143:0}, i=15, size=13] [L20] RET return i; VAL [\old(size)=13, \result=15, b={143:0}, b={143:0}, i=15, size=13] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=15, i=13, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=15, i=13, mask={143:0}] [L26] i++ VAL [b={159:0}, i=14, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=14, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=160, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=131, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=133, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=135, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=151, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=137, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=136, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=154, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=132, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=138, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=129, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=144, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=134, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=155, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=142, i=15, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=16, size=14] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={143:0}, b={143:0}, i=16, size=14] [L20] RET return i; VAL [\old(size)=14, \result=16, b={143:0}, b={143:0}, i=16, size=14] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=16, i=14, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=16, i=14, mask={143:0}] [L26] i++ VAL [b={159:0}, i=15, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=15, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=160, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=131, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=133, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=135, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=151, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=137, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=136, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=154, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=132, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=138, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=129, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=144, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=134, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=155, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=142, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=148, i=16, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=17, size=15] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={143:0}, b={143:0}, i=17, size=15] [L20] RET return i; VAL [\old(size)=15, \result=17, b={143:0}, b={143:0}, i=17, size=15] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=17, i=15, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=17, i=15, mask={143:0}] [L26] i++ VAL [b={159:0}, i=16, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=16, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=160, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=131, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=133, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=135, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=151, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=137, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=136, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=154, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=132, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=138, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=129, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=144, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=134, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=155, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=142, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=148, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=163, i=17, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=18, size=16] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={143:0}, b={143:0}, i=18, size=16] [L20] RET return i; VAL [\old(size)=16, \result=18, b={143:0}, b={143:0}, i=18, size=16] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=18, i=16, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=18, i=16, mask={143:0}] [L26] i++ VAL [b={159:0}, i=17, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=17, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=160, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=131, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=133, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=135, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=151, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=137, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=136, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=154, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=132, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=138, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=129, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=144, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=134, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=155, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=142, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=148, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=163, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=146, i=18, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=19, size=17] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={143:0}, b={143:0}, i=19, size=17] [L20] RET return i; VAL [\old(size)=17, \result=19, b={143:0}, b={143:0}, i=19, size=17] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=19, i=17, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=19, i=17, mask={143:0}] [L26] i++ VAL [b={159:0}, i=18, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=18, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=160, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=131, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=133, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=135, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=151, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=137, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=136, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=154, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=132, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=138, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=129, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=144, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=134, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=155, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=142, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=148, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=163, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=146, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=140, i=19, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=20, size=18] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={143:0}, b={143:0}, i=20, size=18] [L20] RET return i; VAL [\old(size)=18, \result=20, b={143:0}, b={143:0}, i=20, size=18] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=20, i=18, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=20, i=18, mask={143:0}] [L26] i++ VAL [b={159:0}, i=19, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=19, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=160, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=131, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=133, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=135, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=151, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=137, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=136, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=154, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=132, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=138, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=129, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=144, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=134, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=155, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=142, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=148, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=163, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=146, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=140, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=156, i=20, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=21, size=19] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={143:0}, b={143:0}, i=21, size=19] [L20] RET return i; VAL [\old(size)=19, \result=21, b={143:0}, b={143:0}, i=21, size=19] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=21, i=19, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=21, i=19, mask={143:0}] [L26] i++ VAL [b={159:0}, i=20, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=20, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=160, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=131, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=133, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=135, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=151, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=137, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=136, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=154, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=132, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=138, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=129, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=144, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=134, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=155, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=142, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=148, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=163, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=146, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=140, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=156, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=139, i=21, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=22, size=20] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={143:0}, b={143:0}, i=22, size=20] [L20] RET return i; VAL [\old(size)=20, \result=22, b={143:0}, b={143:0}, i=22, size=20] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=22, i=20, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=22, i=20, mask={143:0}] [L26] i++ VAL [b={159:0}, i=21, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=21, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=160, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=131, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=133, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=135, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=151, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=137, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=136, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=154, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=132, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=138, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=129, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=144, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=134, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=155, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=142, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=148, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=163, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=146, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=140, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=156, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=139, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=157, i=22, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=23, size=21] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={143:0}, b={143:0}, i=23, size=21] [L20] RET return i; VAL [\old(size)=21, \result=23, b={143:0}, b={143:0}, i=23, size=21] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=23, i=21, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=23, i=21, mask={143:0}] [L26] i++ VAL [b={159:0}, i=22, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=22, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=160, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=131, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=133, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=135, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=151, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=137, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=136, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=154, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=132, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=138, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=129, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=144, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=134, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=155, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=142, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=148, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=163, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=146, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=140, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=156, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=139, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=157, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=152, i=23, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=24, size=22] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={143:0}, b={143:0}, i=24, size=22] [L20] RET return i; VAL [\old(size)=22, \result=24, b={143:0}, b={143:0}, i=24, size=22] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=24, i=22, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=24, i=22, mask={143:0}] [L26] i++ VAL [b={159:0}, i=23, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=23, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=160, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=131, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=133, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=135, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=151, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=137, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=136, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=154, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=132, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=138, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=129, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=144, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=134, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=155, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=142, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=148, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=163, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=146, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=140, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=156, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=139, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=157, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=152, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=162, i=24, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=25, size=23] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={143:0}, b={143:0}, i=25, size=23] [L20] RET return i; VAL [\old(size)=23, \result=25, b={143:0}, b={143:0}, i=25, size=23] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=25, i=23, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=25, i=23, mask={143:0}] [L26] i++ VAL [b={159:0}, i=24, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=24, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=160, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=131, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=133, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=135, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=151, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=137, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=136, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=154, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=132, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=138, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=129, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=144, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=134, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=155, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=142, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=148, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=163, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=146, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=140, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=156, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=139, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=157, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=152, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=162, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=164, i=25, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=26, size=24] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={143:0}, b={143:0}, i=26, size=24] [L20] RET return i; VAL [\old(size)=24, \result=26, b={143:0}, b={143:0}, i=26, size=24] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=26, i=24, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=26, i=24, mask={143:0}] [L26] i++ VAL [b={159:0}, i=25, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=25, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=160, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=131, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=133, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=135, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=151, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=137, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=136, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=154, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=132, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=138, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=129, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=144, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=134, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=155, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=142, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=148, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=163, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=146, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=140, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=156, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=139, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=157, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=152, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=162, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=164, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=161, i=26, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=27, size=25] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={143:0}, b={143:0}, i=27, size=25] [L20] RET return i; VAL [\old(size)=25, \result=27, b={143:0}, b={143:0}, i=27, size=25] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=27, i=25, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=27, i=25, mask={143:0}] [L26] i++ VAL [b={159:0}, i=26, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=26, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=160, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=131, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=133, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=135, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=151, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=137, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=136, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=154, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=132, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=138, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=129, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=144, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=134, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=155, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=142, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=148, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=163, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=146, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=140, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=156, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=139, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=157, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=152, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=162, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=164, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=161, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=141, i=27, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=28, size=26] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={143:0}, b={143:0}, i=28, size=26] [L20] RET return i; VAL [\old(size)=26, \result=28, b={143:0}, b={143:0}, i=28, size=26] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=28, i=26, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=28, i=26, mask={143:0}] [L26] i++ VAL [b={159:0}, i=27, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=27, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=160, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=131, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=133, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=135, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=151, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=137, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=136, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=154, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=132, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=138, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=129, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=144, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=134, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=155, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=142, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=148, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=163, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=146, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=140, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=156, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=139, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=157, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=152, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=162, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=164, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=161, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=141, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=130, i=28, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=29, size=27] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={143:0}, b={143:0}, i=29, size=27] [L20] RET return i; VAL [\old(size)=27, \result=29, b={143:0}, b={143:0}, i=29, size=27] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=29, i=27, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=29, i=27, mask={143:0}] [L26] i++ VAL [b={159:0}, i=28, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=28, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=160, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=131, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=133, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=135, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=151, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=137, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=136, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=154, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=132, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=138, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=129, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=144, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=134, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=155, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=142, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=148, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=163, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=146, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=140, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=156, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=139, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=157, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=152, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=162, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=164, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=161, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=141, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=130, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=147, i=29, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=30, size=28] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={143:0}, b={143:0}, i=30, size=28] [L20] RET return i; VAL [\old(size)=28, \result=30, b={143:0}, b={143:0}, i=30, size=28] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=30, i=28, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=30, i=28, mask={143:0}] [L26] i++ VAL [b={159:0}, i=29, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=29, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=160, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=131, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=133, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=135, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=151, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=137, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=136, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=154, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=132, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=138, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=129, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=144, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=134, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=155, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=142, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=148, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=163, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=146, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=140, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=156, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=139, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=157, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=152, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=162, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=164, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=161, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=141, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=130, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=147, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=153, i=30, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=31, size=29] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={143:0}, b={143:0}, i=31, size=29] [L20] RET return i; VAL [\old(size)=29, \result=31, b={143:0}, b={143:0}, i=31, size=29] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=31, i=29, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=31, i=29, mask={143:0}] [L26] i++ VAL [b={159:0}, i=30, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=30, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=160, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=131, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=133, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=135, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=151, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=137, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=136, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=154, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=132, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=138, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=129, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=144, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=134, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=155, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=142, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=148, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=163, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=146, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=140, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=156, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=139, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=157, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=152, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=162, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=164, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=161, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=141, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=130, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=147, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=153, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=145, i=31, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=32, size=30] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={143:0}, b={143:0}, i=32, size=30] [L20] RET return i; VAL [\old(size)=30, \result=32, b={143:0}, b={143:0}, i=32, size=30] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=32, i=30, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=32, i=30, mask={143:0}] [L26] i++ VAL [b={159:0}, i=31, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=31, mask={143:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=160, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=131, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=133, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=135, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=151, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=137, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=136, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=154, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=132, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=138, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=129, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=144, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=134, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=155, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=142, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=148, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=163, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=146, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=140, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=156, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=139, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=157, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=152, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=162, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=164, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=161, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=141, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=130, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=147, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=153, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=145, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L18] FCALL b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 43 locations, 8 error locations. UNSAFE Result, 640.2s OverallTime, 95 OverallIterations, 591 TraceHistogramMax, 131.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5312 SDtfs, 53111 SDslu, 74125 SDs, 0 SdLazy, 208910 SolverSat, 6693 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 51.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 253485 GetRequests, 241500 SyntacticMatches, 2131 SemanticMatches, 9854 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 559427 ImplicationChecksByTransitivity, 191.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3781occurred in iteration=93, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.6s AbstIntTime, 6 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 94 MinimizatonAttempts, 1047 StatesRemovedByMinimization, 91 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 4.1s SsaConstructionTime, 49.0s SatisfiabilityAnalysisTime, 367.1s InterpolantComputationTime, 250921 NumberOfCodeBlocks, 224365 NumberOfCodeBlocksAsserted, 685 NumberOfCheckSat, 370396 ConstructedInterpolants, 30906 QuantifiedInterpolants, 1913766541 SizeOfPredicates, 395 NumberOfNonLiveVariables, 220936 ConjunctsInSsa, 3502 ConjunctsInUnsatCore, 268 InterpolantComputations, 9 PerfectInterpolantSequences, 55432213/55969292 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...