./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/config/TaipanMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -s /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 16:08:51,365 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 16:08:51,367 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 16:08:51,376 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 16:08:51,376 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 16:08:51,377 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 16:08:51,378 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 16:08:51,379 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 16:08:51,381 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 16:08:51,382 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 16:08:51,383 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 16:08:51,383 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 16:08:51,384 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 16:08:51,385 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 16:08:51,385 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 16:08:51,386 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 16:08:51,387 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 16:08:51,389 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 16:08:51,390 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 16:08:51,392 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 16:08:51,393 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 16:08:51,394 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 16:08:51,396 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 16:08:51,396 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 16:08:51,397 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 16:08:51,397 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 16:08:51,398 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 16:08:51,399 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 16:08:51,400 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 16:08:51,400 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 16:08:51,401 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 16:08:51,401 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 16:08:51,401 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 16:08:51,402 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 16:08:51,402 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 16:08:51,407 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 16:08:51,408 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/config/svcomp-DerefFreeMemtrack-32bit-Taipan_Default.epf [2018-11-18 16:08:51,419 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 16:08:51,419 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 16:08:51,426 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 16:08:51,426 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-18 16:08:51,426 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-18 16:08:51,427 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-18 16:08:51,427 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-18 16:08:51,428 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 16:08:51,428 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 16:08:51,428 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 16:08:51,428 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-18 16:08:51,429 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 16:08:51,430 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 16:08:51,430 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 16:08:51,430 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 16:08:51,430 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 16:08:51,430 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 16:08:51,430 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 16:08:51,430 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 16:08:51,431 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 16:08:51,431 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 16:08:51,431 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-18 16:08:51,431 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 16:08:51,436 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 16:08:51,436 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2018-11-18 16:08:51,475 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 16:08:51,486 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 16:08:51,492 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 16:08:51,494 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 16:08:51,494 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 16:08:51,495 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-18 16:08:51,551 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/data/5423adc99/25fa7ae12bb340858043e7e2fcfc01c6/FLAGe36372429 [2018-11-18 16:08:51,891 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 16:08:51,892 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-18 16:08:51,896 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/data/5423adc99/25fa7ae12bb340858043e7e2fcfc01c6/FLAGe36372429 [2018-11-18 16:08:51,905 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/data/5423adc99/25fa7ae12bb340858043e7e2fcfc01c6 [2018-11-18 16:08:51,907 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 16:08:51,908 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 16:08:51,909 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 16:08:51,909 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 16:08:51,912 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 16:08:51,913 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 04:08:51" (1/1) ... [2018-11-18 16:08:51,915 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7be20a0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:51, skipping insertion in model container [2018-11-18 16:08:51,916 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 04:08:51" (1/1) ... [2018-11-18 16:08:51,924 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 16:08:51,939 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 16:08:52,071 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 16:08:52,078 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 16:08:52,091 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 16:08:52,103 INFO L195 MainTranslator]: Completed translation [2018-11-18 16:08:52,103 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52 WrapperNode [2018-11-18 16:08:52,103 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 16:08:52,104 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 16:08:52,104 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 16:08:52,104 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 16:08:52,109 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,115 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,121 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 16:08:52,122 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 16:08:52,122 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 16:08:52,122 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 16:08:52,130 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,131 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,132 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,132 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,138 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,143 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,144 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... [2018-11-18 16:08:52,146 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 16:08:52,146 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 16:08:52,146 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 16:08:52,146 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 16:08:52,147 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 16:08:52,232 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-18 16:08:52,233 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 16:08:52,233 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 16:08:52,233 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 16:08:52,233 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-11-18 16:08:52,233 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-11-18 16:08:52,233 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 16:08:52,233 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 16:08:52,233 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-18 16:08:52,234 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 16:08:52,234 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 16:08:52,234 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 16:08:52,460 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 16:08:52,461 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:08:52 BoogieIcfgContainer [2018-11-18 16:08:52,461 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 16:08:52,461 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 16:08:52,461 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 16:08:52,464 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 16:08:52,465 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 04:08:51" (1/3) ... [2018-11-18 16:08:52,465 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3bc42072 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 04:08:52, skipping insertion in model container [2018-11-18 16:08:52,465 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:08:52" (2/3) ... [2018-11-18 16:08:52,466 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3bc42072 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 04:08:52, skipping insertion in model container [2018-11-18 16:08:52,466 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:08:52" (3/3) ... [2018-11-18 16:08:52,469 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-18 16:08:52,477 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 16:08:52,483 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-11-18 16:08:52,497 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-11-18 16:08:52,517 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 16:08:52,517 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-18 16:08:52,517 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 16:08:52,517 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 16:08:52,518 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 16:08:52,518 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 16:08:52,518 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 16:08:52,518 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 16:08:52,530 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states. [2018-11-18 16:08:52,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-18 16:08:52,537 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:52,538 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:52,540 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:52,544 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:52,544 INFO L82 PathProgramCache]: Analyzing trace with hash 1597032710, now seen corresponding path program 1 times [2018-11-18 16:08:52,546 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:52,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:52,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,578 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:52,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:52,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:52,630 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:52,630 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:08:52,630 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:52,633 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 16:08:52,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 16:08:52,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 16:08:52,643 INFO L87 Difference]: Start difference. First operand 43 states. Second operand 2 states. [2018-11-18 16:08:52,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:52,656 INFO L93 Difference]: Finished difference Result 43 states and 46 transitions. [2018-11-18 16:08:52,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 16:08:52,657 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 11 [2018-11-18 16:08:52,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:52,663 INFO L225 Difference]: With dead ends: 43 [2018-11-18 16:08:52,663 INFO L226 Difference]: Without dead ends: 40 [2018-11-18 16:08:52,665 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 16:08:52,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-11-18 16:08:52,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-11-18 16:08:52,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-11-18 16:08:52,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 43 transitions. [2018-11-18 16:08:52,693 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 43 transitions. Word has length 11 [2018-11-18 16:08:52,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:52,694 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 43 transitions. [2018-11-18 16:08:52,694 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 16:08:52,694 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 43 transitions. [2018-11-18 16:08:52,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-18 16:08:52,695 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:52,695 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:52,696 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:52,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:52,696 INFO L82 PathProgramCache]: Analyzing trace with hash 1820883224, now seen corresponding path program 1 times [2018-11-18 16:08:52,696 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:52,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,697 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:52,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,697 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:52,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:52,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:52,752 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:52,753 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:08:52,753 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:52,754 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:08:52,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:08:52,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:52,755 INFO L87 Difference]: Start difference. First operand 40 states and 43 transitions. Second operand 3 states. [2018-11-18 16:08:52,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:52,821 INFO L93 Difference]: Finished difference Result 59 states and 63 transitions. [2018-11-18 16:08:52,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:08:52,821 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-18 16:08:52,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:52,823 INFO L225 Difference]: With dead ends: 59 [2018-11-18 16:08:52,823 INFO L226 Difference]: Without dead ends: 59 [2018-11-18 16:08:52,824 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:52,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-11-18 16:08:52,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 44. [2018-11-18 16:08:52,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-18 16:08:52,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 47 transitions. [2018-11-18 16:08:52,831 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 47 transitions. Word has length 12 [2018-11-18 16:08:52,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:52,832 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 47 transitions. [2018-11-18 16:08:52,832 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:08:52,832 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 47 transitions. [2018-11-18 16:08:52,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-18 16:08:52,832 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:52,832 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:52,833 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:52,833 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:52,833 INFO L82 PathProgramCache]: Analyzing trace with hash 697121729, now seen corresponding path program 1 times [2018-11-18 16:08:52,833 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:52,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:52,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,835 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:52,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:52,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:52,877 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:52,877 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:08:52,878 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:52,878 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:08:52,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:08:52,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:52,879 INFO L87 Difference]: Start difference. First operand 44 states and 47 transitions. Second operand 3 states. [2018-11-18 16:08:52,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:52,980 INFO L93 Difference]: Finished difference Result 55 states and 59 transitions. [2018-11-18 16:08:52,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:08:52,981 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-11-18 16:08:52,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:52,983 INFO L225 Difference]: With dead ends: 55 [2018-11-18 16:08:52,983 INFO L226 Difference]: Without dead ends: 55 [2018-11-18 16:08:52,984 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:52,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-11-18 16:08:52,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 47. [2018-11-18 16:08:52,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-11-18 16:08:52,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 51 transitions. [2018-11-18 16:08:52,988 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 51 transitions. Word has length 13 [2018-11-18 16:08:52,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:52,988 INFO L480 AbstractCegarLoop]: Abstraction has 47 states and 51 transitions. [2018-11-18 16:08:52,988 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:08:52,989 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 51 transitions. [2018-11-18 16:08:52,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 16:08:52,989 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:52,989 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:52,989 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:52,989 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:52,990 INFO L82 PathProgramCache]: Analyzing trace with hash 135937166, now seen corresponding path program 1 times [2018-11-18 16:08:52,990 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:52,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,990 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:52,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:52,990 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:53,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:53,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:53,211 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:53,211 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:08:53,212 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:53,212 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 16:08:53,212 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 16:08:53,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:08:53,212 INFO L87 Difference]: Start difference. First operand 47 states and 51 transitions. Second operand 6 states. [2018-11-18 16:08:53,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:53,324 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-11-18 16:08:53,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:08:53,325 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 14 [2018-11-18 16:08:53,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:53,325 INFO L225 Difference]: With dead ends: 49 [2018-11-18 16:08:53,325 INFO L226 Difference]: Without dead ends: 49 [2018-11-18 16:08:53,326 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-18 16:08:53,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-11-18 16:08:53,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 46. [2018-11-18 16:08:53,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-11-18 16:08:53,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-11-18 16:08:53,332 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 14 [2018-11-18 16:08:53,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:53,332 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-11-18 16:08:53,332 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 16:08:53,332 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-11-18 16:08:53,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 16:08:53,333 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:53,333 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:53,333 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:53,333 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:53,333 INFO L82 PathProgramCache]: Analyzing trace with hash 135937165, now seen corresponding path program 1 times [2018-11-18 16:08:53,333 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:53,334 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,334 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:53,334 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,334 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:53,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:53,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:53,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:53,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 16:08:53,376 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:53,376 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 16:08:53,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:08:53,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:08:53,377 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 5 states. [2018-11-18 16:08:53,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:53,475 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2018-11-18 16:08:53,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:08:53,476 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-11-18 16:08:53,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:53,476 INFO L225 Difference]: With dead ends: 45 [2018-11-18 16:08:53,476 INFO L226 Difference]: Without dead ends: 45 [2018-11-18 16:08:53,476 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:08:53,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-11-18 16:08:53,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-11-18 16:08:53,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-11-18 16:08:53,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2018-11-18 16:08:53,480 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 14 [2018-11-18 16:08:53,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:53,480 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2018-11-18 16:08:53,480 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 16:08:53,480 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2018-11-18 16:08:53,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-18 16:08:53,480 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:53,481 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:53,481 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:53,481 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:53,481 INFO L82 PathProgramCache]: Analyzing trace with hash -497753495, now seen corresponding path program 1 times [2018-11-18 16:08:53,481 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:53,482 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,482 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:53,482 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,482 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:53,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:53,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:53,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:53,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:08:53,528 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:53,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:08:53,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:08:53,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:53,529 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 3 states. [2018-11-18 16:08:53,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:53,556 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-11-18 16:08:53,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:08:53,556 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-11-18 16:08:53,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:53,557 INFO L225 Difference]: With dead ends: 43 [2018-11-18 16:08:53,557 INFO L226 Difference]: Without dead ends: 43 [2018-11-18 16:08:53,557 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:53,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-11-18 16:08:53,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-11-18 16:08:53,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-11-18 16:08:53,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-11-18 16:08:53,560 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 17 [2018-11-18 16:08:53,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:53,561 INFO L480 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-11-18 16:08:53,561 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:08:53,561 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-11-18 16:08:53,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-18 16:08:53,561 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:53,561 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:53,562 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:53,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:53,562 INFO L82 PathProgramCache]: Analyzing trace with hash -497753494, now seen corresponding path program 1 times [2018-11-18 16:08:53,562 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:53,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:53,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,563 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:53,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:53,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:53,662 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:53,662 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 16:08:53,662 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:53,663 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 16:08:53,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 16:08:53,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:08:53,663 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 6 states. [2018-11-18 16:08:53,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:53,863 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions. [2018-11-18 16:08:53,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:08:53,867 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-18 16:08:53,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:53,867 INFO L225 Difference]: With dead ends: 62 [2018-11-18 16:08:53,868 INFO L226 Difference]: Without dead ends: 62 [2018-11-18 16:08:53,868 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 16:08:53,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-11-18 16:08:53,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 47. [2018-11-18 16:08:53,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-11-18 16:08:53,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-11-18 16:08:53,871 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 17 [2018-11-18 16:08:53,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:53,871 INFO L480 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-11-18 16:08:53,871 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 16:08:53,871 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-11-18 16:08:53,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-18 16:08:53,872 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:53,872 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:53,872 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:53,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:53,872 INFO L82 PathProgramCache]: Analyzing trace with hash 1254753657, now seen corresponding path program 1 times [2018-11-18 16:08:53,872 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:53,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:53,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:53,873 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:53,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:53,964 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:53,964 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:53,964 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:53,965 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 20 with the following transitions: [2018-11-18 16:08:53,966 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [11], [12], [13], [14], [17], [19], [28], [32], [37], [76], [77], [78], [80] [2018-11-18 16:08:53,990 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:08:53,990 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:08:54,135 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:08:54,136 INFO L272 AbstractInterpreter]: Visited 17 different actions 31 times. Merged at 6 different actions 12 times. Never widened. Performed 152 root evaluator evaluations with a maximum evaluation depth of 3. Performed 152 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 20 variables. [2018-11-18 16:08:54,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:54,141 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:08:54,142 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:54,142 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:54,149 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:54,149 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:08:54,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:54,173 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:54,200 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:54,200 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:54,260 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:54,283 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:54,283 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 5 [2018-11-18 16:08:54,283 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:54,284 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 16:08:54,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 16:08:54,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:08:54,284 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 4 states. [2018-11-18 16:08:54,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:54,342 INFO L93 Difference]: Finished difference Result 59 states and 66 transitions. [2018-11-18 16:08:54,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 16:08:54,343 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2018-11-18 16:08:54,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:54,343 INFO L225 Difference]: With dead ends: 59 [2018-11-18 16:08:54,344 INFO L226 Difference]: Without dead ends: 59 [2018-11-18 16:08:54,344 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 34 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:08:54,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-11-18 16:08:54,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 53. [2018-11-18 16:08:54,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-11-18 16:08:54,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 59 transitions. [2018-11-18 16:08:54,349 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 59 transitions. Word has length 19 [2018-11-18 16:08:54,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:54,349 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 59 transitions. [2018-11-18 16:08:54,349 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 16:08:54,350 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 59 transitions. [2018-11-18 16:08:54,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-18 16:08:54,350 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:54,350 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:54,351 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:54,351 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:54,351 INFO L82 PathProgramCache]: Analyzing trace with hash 539365410, now seen corresponding path program 1 times [2018-11-18 16:08:54,351 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:54,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:54,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:54,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:54,352 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:54,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:54,427 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:54,427 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:54,428 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:54,428 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 24 with the following transitions: [2018-11-18 16:08:54,428 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [37], [39], [42], [76], [77], [78], [80], [81] [2018-11-18 16:08:54,429 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:08:54,430 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:08:54,522 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:08:54,522 INFO L272 AbstractInterpreter]: Visited 22 different actions 60 times. Merged at 12 different actions 36 times. Never widened. Performed 270 root evaluator evaluations with a maximum evaluation depth of 4. Performed 270 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 1 fixpoints after 1 different actions. Largest state had 21 variables. [2018-11-18 16:08:54,528 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:54,528 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:08:54,529 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:54,529 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:54,547 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:54,548 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:08:54,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:54,564 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:54,622 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:54,623 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:54,746 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:54,772 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:54,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2018-11-18 16:08:54,772 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:54,772 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-18 16:08:54,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-18 16:08:54,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-18 16:08:54,773 INFO L87 Difference]: Start difference. First operand 53 states and 59 transitions. Second operand 9 states. [2018-11-18 16:08:54,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:54,997 INFO L93 Difference]: Finished difference Result 71 states and 75 transitions. [2018-11-18 16:08:54,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 16:08:54,998 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 23 [2018-11-18 16:08:54,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:54,999 INFO L225 Difference]: With dead ends: 71 [2018-11-18 16:08:54,999 INFO L226 Difference]: Without dead ends: 65 [2018-11-18 16:08:54,999 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 38 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=104, Unknown=0, NotChecked=0, Total=156 [2018-11-18 16:08:54,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-11-18 16:08:55,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 49. [2018-11-18 16:08:55,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-11-18 16:08:55,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 52 transitions. [2018-11-18 16:08:55,002 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 52 transitions. Word has length 23 [2018-11-18 16:08:55,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:55,002 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 52 transitions. [2018-11-18 16:08:55,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-18 16:08:55,002 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 52 transitions. [2018-11-18 16:08:55,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-18 16:08:55,003 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:55,006 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:55,006 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:55,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:55,006 INFO L82 PathProgramCache]: Analyzing trace with hash 1493607729, now seen corresponding path program 2 times [2018-11-18 16:08:55,006 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:55,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:55,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:55,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:55,007 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:55,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:55,106 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:08:55,106 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:55,106 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:55,106 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:08:55,107 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:08:55,107 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:55,107 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:55,114 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:08:55,114 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:08:55,130 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-18 16:08:55,130 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:08:55,132 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:55,225 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 16:08:55,225 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:55,343 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 16:08:55,358 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:55,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 18 [2018-11-18 16:08:55,359 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:55,359 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 16:08:55,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 16:08:55,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=247, Unknown=0, NotChecked=0, Total=306 [2018-11-18 16:08:55,360 INFO L87 Difference]: Start difference. First operand 49 states and 52 transitions. Second operand 12 states. [2018-11-18 16:08:55,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:55,609 INFO L93 Difference]: Finished difference Result 80 states and 83 transitions. [2018-11-18 16:08:55,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 16:08:55,610 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 25 [2018-11-18 16:08:55,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:55,610 INFO L225 Difference]: With dead ends: 80 [2018-11-18 16:08:55,610 INFO L226 Difference]: Without dead ends: 80 [2018-11-18 16:08:55,611 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=113, Invalid=349, Unknown=0, NotChecked=0, Total=462 [2018-11-18 16:08:55,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-11-18 16:08:55,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 68. [2018-11-18 16:08:55,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-11-18 16:08:55,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 71 transitions. [2018-11-18 16:08:55,614 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 71 transitions. Word has length 25 [2018-11-18 16:08:55,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:55,614 INFO L480 AbstractCegarLoop]: Abstraction has 68 states and 71 transitions. [2018-11-18 16:08:55,614 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 16:08:55,614 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 71 transitions. [2018-11-18 16:08:55,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-18 16:08:55,615 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:55,615 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:55,615 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:55,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:55,615 INFO L82 PathProgramCache]: Analyzing trace with hash 2065437658, now seen corresponding path program 2 times [2018-11-18 16:08:55,615 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:55,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:55,616 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:08:55,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:55,616 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:55,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:55,672 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:08:55,672 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:08:55,672 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:08:55,673 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:08:55,673 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 16:08:55,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:08:55,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:55,673 INFO L87 Difference]: Start difference. First operand 68 states and 71 transitions. Second operand 3 states. [2018-11-18 16:08:55,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:55,718 INFO L93 Difference]: Finished difference Result 72 states and 75 transitions. [2018-11-18 16:08:55,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:08:55,718 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2018-11-18 16:08:55,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:55,719 INFO L225 Difference]: With dead ends: 72 [2018-11-18 16:08:55,719 INFO L226 Difference]: Without dead ends: 72 [2018-11-18 16:08:55,719 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:08:55,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-11-18 16:08:55,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 70. [2018-11-18 16:08:55,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-11-18 16:08:55,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 73 transitions. [2018-11-18 16:08:55,722 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 73 transitions. Word has length 29 [2018-11-18 16:08:55,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:55,722 INFO L480 AbstractCegarLoop]: Abstraction has 70 states and 73 transitions. [2018-11-18 16:08:55,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 16:08:55,722 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 73 transitions. [2018-11-18 16:08:55,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-18 16:08:55,726 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:55,726 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:55,727 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:55,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:55,727 INFO L82 PathProgramCache]: Analyzing trace with hash -989786460, now seen corresponding path program 1 times [2018-11-18 16:08:55,727 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:55,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:55,728 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:08:55,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:55,728 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:55,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:55,791 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 16:08:55,791 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:55,792 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:55,792 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 38 with the following transitions: [2018-11-18 16:08:55,792 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [35], [37], [39], [40], [43], [45], [49], [53], [58], [61], [76], [77], [78], [80], [81] [2018-11-18 16:08:55,793 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:08:55,793 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:08:56,025 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:08:56,025 INFO L272 AbstractInterpreter]: Visited 29 different actions 197 times. Merged at 17 different actions 120 times. Never widened. Performed 887 root evaluator evaluations with a maximum evaluation depth of 4. Performed 887 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 15 fixpoints after 4 different actions. Largest state had 21 variables. [2018-11-18 16:08:56,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:56,055 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:08:56,055 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:56,055 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:56,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:56,064 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:08:56,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:56,085 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:56,100 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:08:56,100 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:56,119 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:08:56,151 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:56,151 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4, 4] total 10 [2018-11-18 16:08:56,152 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:56,152 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 16:08:56,152 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 16:08:56,153 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-18 16:08:56,153 INFO L87 Difference]: Start difference. First operand 70 states and 73 transitions. Second operand 10 states. [2018-11-18 16:08:56,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:56,300 INFO L93 Difference]: Finished difference Result 87 states and 91 transitions. [2018-11-18 16:08:56,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-18 16:08:56,301 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 37 [2018-11-18 16:08:56,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:56,302 INFO L225 Difference]: With dead ends: 87 [2018-11-18 16:08:56,302 INFO L226 Difference]: Without dead ends: 87 [2018-11-18 16:08:56,302 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 87 GetRequests, 73 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-11-18 16:08:56,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-11-18 16:08:56,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 57. [2018-11-18 16:08:56,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-11-18 16:08:56,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2018-11-18 16:08:56,306 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 58 transitions. Word has length 37 [2018-11-18 16:08:56,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:56,306 INFO L480 AbstractCegarLoop]: Abstraction has 57 states and 58 transitions. [2018-11-18 16:08:56,306 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 16:08:56,306 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 58 transitions. [2018-11-18 16:08:56,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-18 16:08:56,307 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:56,307 INFO L375 BasicCegarLoop]: trace histogram [6, 5, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:56,308 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:56,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:56,308 INFO L82 PathProgramCache]: Analyzing trace with hash 1028958598, now seen corresponding path program 1 times [2018-11-18 16:08:56,308 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:56,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:56,309 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:56,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:56,309 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:56,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:56,560 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 16:08:56,561 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:56,561 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:56,561 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 51 with the following transitions: [2018-11-18 16:08:56,561 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [12], [13], [14], [17], [19], [23], [24], [28], [32], [37], [39], [40], [43], [45], [76], [77], [78], [80], [81] [2018-11-18 16:08:56,562 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:08:56,562 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:08:56,661 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:08:56,661 INFO L272 AbstractInterpreter]: Visited 25 different actions 137 times. Merged at 17 different actions 76 times. Never widened. Performed 618 root evaluator evaluations with a maximum evaluation depth of 4. Performed 618 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 8 fixpoints after 4 different actions. Largest state had 21 variables. [2018-11-18 16:08:56,703 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:56,703 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:08:56,703 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:56,704 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:56,717 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:56,717 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:08:56,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:56,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:56,784 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 16:08:56,784 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:57,001 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 16:08:57,026 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:57,027 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2018-11-18 16:08:57,027 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:57,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 16:08:57,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:08:57,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-18 16:08:57,028 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. Second operand 5 states. [2018-11-18 16:08:57,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:57,088 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2018-11-18 16:08:57,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:08:57,088 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-18 16:08:57,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:57,089 INFO L225 Difference]: With dead ends: 69 [2018-11-18 16:08:57,089 INFO L226 Difference]: Without dead ends: 69 [2018-11-18 16:08:57,089 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 95 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-18 16:08:57,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-11-18 16:08:57,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 63. [2018-11-18 16:08:57,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-11-18 16:08:57,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 65 transitions. [2018-11-18 16:08:57,093 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 65 transitions. Word has length 50 [2018-11-18 16:08:57,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:57,093 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 65 transitions. [2018-11-18 16:08:57,093 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 16:08:57,093 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 65 transitions. [2018-11-18 16:08:57,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-18 16:08:57,094 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:57,094 INFO L375 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:57,094 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:57,095 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:57,095 INFO L82 PathProgramCache]: Analyzing trace with hash -982129233, now seen corresponding path program 1 times [2018-11-18 16:08:57,095 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:57,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:57,096 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:57,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:57,096 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:57,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:57,289 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 5 proven. 57 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-18 16:08:57,290 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:57,290 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:57,290 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 55 with the following transitions: [2018-11-18 16:08:57,290 INFO L202 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [13], [14], [17], [19], [23], [24], [28], [32], [37], [39], [40], [42], [43], [45], [76], [77], [78], [80], [81] [2018-11-18 16:08:57,291 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 16:08:57,291 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 16:08:57,397 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 16:08:57,397 INFO L272 AbstractInterpreter]: Visited 25 different actions 176 times. Merged at 17 different actions 108 times. Never widened. Performed 794 root evaluator evaluations with a maximum evaluation depth of 4. Performed 794 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 12 fixpoints after 3 different actions. Largest state had 21 variables. [2018-11-18 16:08:57,423 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:57,424 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 16:08:57,424 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:57,424 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:57,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:57,436 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:08:57,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:57,461 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:57,616 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 16:08:57,616 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:57,711 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 16:08:57,726 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:57,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 18 [2018-11-18 16:08:57,727 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:57,727 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-18 16:08:57,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-18 16:08:57,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2018-11-18 16:08:57,728 INFO L87 Difference]: Start difference. First operand 63 states and 65 transitions. Second operand 15 states. [2018-11-18 16:08:57,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:57,894 INFO L93 Difference]: Finished difference Result 71 states and 72 transitions. [2018-11-18 16:08:57,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 16:08:57,894 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 54 [2018-11-18 16:08:57,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:57,895 INFO L225 Difference]: With dead ends: 71 [2018-11-18 16:08:57,895 INFO L226 Difference]: Without dead ends: 68 [2018-11-18 16:08:57,895 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 100 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=125, Invalid=381, Unknown=0, NotChecked=0, Total=506 [2018-11-18 16:08:57,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-11-18 16:08:57,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 63. [2018-11-18 16:08:57,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-11-18 16:08:57,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2018-11-18 16:08:57,898 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 64 transitions. Word has length 54 [2018-11-18 16:08:57,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:57,898 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 64 transitions. [2018-11-18 16:08:57,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-18 16:08:57,898 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 64 transitions. [2018-11-18 16:08:57,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-18 16:08:57,899 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:57,899 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 5, 5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:57,899 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:57,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:57,900 INFO L82 PathProgramCache]: Analyzing trace with hash -373863554, now seen corresponding path program 2 times [2018-11-18 16:08:57,900 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:57,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:57,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:08:57,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:57,900 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:57,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:57,989 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 70 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 16:08:57,989 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:57,990 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:57,990 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:08:57,990 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:08:57,990 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:57,990 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:57,999 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:08:57,999 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:08:58,024 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-18 16:08:58,024 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:08:58,026 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:58,114 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 63 proven. 6 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-18 16:08:58,114 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:58,205 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 51 proven. 18 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-18 16:08:58,220 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:58,220 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8] total 21 [2018-11-18 16:08:58,221 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:58,221 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 16:08:58,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 16:08:58,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-11-18 16:08:58,221 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. Second operand 14 states. [2018-11-18 16:08:58,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:58,409 INFO L93 Difference]: Finished difference Result 97 states and 98 transitions. [2018-11-18 16:08:58,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-18 16:08:58,410 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 56 [2018-11-18 16:08:58,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:58,411 INFO L225 Difference]: With dead ends: 97 [2018-11-18 16:08:58,411 INFO L226 Difference]: Without dead ends: 97 [2018-11-18 16:08:58,411 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 102 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 124 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=165, Invalid=537, Unknown=0, NotChecked=0, Total=702 [2018-11-18 16:08:58,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-11-18 16:08:58,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 92. [2018-11-18 16:08:58,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-11-18 16:08:58,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 93 transitions. [2018-11-18 16:08:58,416 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 93 transitions. Word has length 56 [2018-11-18 16:08:58,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:58,416 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 93 transitions. [2018-11-18 16:08:58,416 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 16:08:58,416 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 93 transitions. [2018-11-18 16:08:58,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-18 16:08:58,423 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:58,423 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:58,424 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:58,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:58,424 INFO L82 PathProgramCache]: Analyzing trace with hash 1531366311, now seen corresponding path program 2 times [2018-11-18 16:08:58,424 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:58,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:58,424 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:08:58,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:58,425 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:58,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:58,614 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:08:58,614 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:58,614 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:58,614 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:08:58,614 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:08:58,614 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:58,615 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:58,628 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:08:58,628 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:08:58,644 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-18 16:08:58,644 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:08:58,646 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:58,673 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 16:08:58,696 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 16:08:58,697 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 16:08:58,698 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-18 16:08:58,759 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 16:08:58,843 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 16:08:58,844 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 16:08:58,881 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 16:08:58,882 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-11-18 16:08:59,175 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:08:59,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:59,306 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 16:08:59,330 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:59,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 4, 3] total 8 [2018-11-18 16:08:59,331 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:59,331 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 16:08:59,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 16:08:59,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-18 16:08:59,332 INFO L87 Difference]: Start difference. First operand 92 states and 93 transitions. Second operand 7 states. [2018-11-18 16:08:59,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:59,354 INFO L93 Difference]: Finished difference Result 96 states and 97 transitions. [2018-11-18 16:08:59,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:08:59,354 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 60 [2018-11-18 16:08:59,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:59,355 INFO L225 Difference]: With dead ends: 96 [2018-11-18 16:08:59,355 INFO L226 Difference]: Without dead ends: 96 [2018-11-18 16:08:59,355 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 112 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-18 16:08:59,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-11-18 16:08:59,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 94. [2018-11-18 16:08:59,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-11-18 16:08:59,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 95 transitions. [2018-11-18 16:08:59,358 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 95 transitions. Word has length 60 [2018-11-18 16:08:59,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:59,358 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 95 transitions. [2018-11-18 16:08:59,358 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 16:08:59,358 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 95 transitions. [2018-11-18 16:08:59,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-11-18 16:08:59,359 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:59,359 INFO L375 BasicCegarLoop]: trace histogram [11, 9, 8, 8, 8, 8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:59,364 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:59,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:59,364 INFO L82 PathProgramCache]: Analyzing trace with hash -2097865839, now seen corresponding path program 3 times [2018-11-18 16:08:59,364 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:59,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:59,365 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:08:59,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:59,365 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:59,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:08:59,474 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 135 proven. 16 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-11-18 16:08:59,474 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:59,474 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:08:59,475 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:08:59,475 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:08:59,475 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:08:59,475 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:08:59,483 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:08:59,483 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:08:59,504 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:08:59,504 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:08:59,510 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:08:59,544 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 121 proven. 27 refuted. 0 times theorem prover too weak. 101 trivial. 0 not checked. [2018-11-18 16:08:59,544 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:08:59,688 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 121 proven. 27 refuted. 0 times theorem prover too weak. 101 trivial. 0 not checked. [2018-11-18 16:08:59,706 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:08:59,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 5, 5] total 17 [2018-11-18 16:08:59,706 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:08:59,706 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 16:08:59,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 16:08:59,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=244, Unknown=0, NotChecked=0, Total=306 [2018-11-18 16:08:59,707 INFO L87 Difference]: Start difference. First operand 94 states and 95 transitions. Second operand 14 states. [2018-11-18 16:08:59,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:08:59,946 INFO L93 Difference]: Finished difference Result 153 states and 157 transitions. [2018-11-18 16:08:59,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 16:08:59,947 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-11-18 16:08:59,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:08:59,948 INFO L225 Difference]: With dead ends: 153 [2018-11-18 16:08:59,948 INFO L226 Difference]: Without dead ends: 153 [2018-11-18 16:08:59,949 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=144, Invalid=456, Unknown=0, NotChecked=0, Total=600 [2018-11-18 16:08:59,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-11-18 16:08:59,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 129. [2018-11-18 16:08:59,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-11-18 16:08:59,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 132 transitions. [2018-11-18 16:08:59,957 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 132 transitions. Word has length 87 [2018-11-18 16:08:59,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:08:59,957 INFO L480 AbstractCegarLoop]: Abstraction has 129 states and 132 transitions. [2018-11-18 16:08:59,957 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 16:08:59,957 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 132 transitions. [2018-11-18 16:08:59,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-18 16:08:59,958 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:08:59,958 INFO L375 BasicCegarLoop]: trace histogram [11, 8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:08:59,958 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:08:59,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:08:59,958 INFO L82 PathProgramCache]: Analyzing trace with hash -2111284678, now seen corresponding path program 3 times [2018-11-18 16:08:59,958 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:08:59,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:59,966 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:08:59,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:08:59,966 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:08:59,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:00,306 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 88 proven. 136 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-18 16:09:00,306 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:00,306 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:00,306 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:00,306 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:00,307 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:00,307 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:00,323 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:00,324 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:00,346 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:00,346 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:00,349 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:00,453 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 90 proven. 134 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-18 16:09:00,454 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:00,653 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 98 proven. 126 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-18 16:09:00,668 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:00,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2018-11-18 16:09:00,668 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:00,669 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-18 16:09:00,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-18 16:09:00,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=527, Unknown=0, NotChecked=0, Total=650 [2018-11-18 16:09:00,669 INFO L87 Difference]: Start difference. First operand 129 states and 132 transitions. Second operand 20 states. [2018-11-18 16:09:00,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:00,846 INFO L93 Difference]: Finished difference Result 148 states and 150 transitions. [2018-11-18 16:09:00,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 16:09:00,847 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 91 [2018-11-18 16:09:00,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:00,848 INFO L225 Difference]: With dead ends: 148 [2018-11-18 16:09:00,848 INFO L226 Difference]: Without dead ends: 142 [2018-11-18 16:09:00,848 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 165 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 265 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=249, Invalid=807, Unknown=0, NotChecked=0, Total=1056 [2018-11-18 16:09:00,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-18 16:09:00,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 135. [2018-11-18 16:09:00,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-11-18 16:09:00,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 137 transitions. [2018-11-18 16:09:00,851 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 137 transitions. Word has length 91 [2018-11-18 16:09:00,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:00,851 INFO L480 AbstractCegarLoop]: Abstraction has 135 states and 137 transitions. [2018-11-18 16:09:00,851 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-18 16:09:00,851 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 137 transitions. [2018-11-18 16:09:00,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-18 16:09:00,854 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:00,854 INFO L375 BasicCegarLoop]: trace histogram [12, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:00,854 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:00,854 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:00,854 INFO L82 PathProgramCache]: Analyzing trace with hash 1448373234, now seen corresponding path program 4 times [2018-11-18 16:09:00,854 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:00,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:00,855 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:00,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:00,855 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:00,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:00,930 INFO L134 CoverageAnalysis]: Checked inductivity of 305 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 293 trivial. 0 not checked. [2018-11-18 16:09:00,930 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:09:00,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:09:00,931 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 16:09:00,931 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 16:09:00,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 16:09:00,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:09:00,931 INFO L87 Difference]: Start difference. First operand 135 states and 137 transitions. Second operand 6 states. [2018-11-18 16:09:00,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:00,954 INFO L93 Difference]: Finished difference Result 134 states and 136 transitions. [2018-11-18 16:09:00,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 16:09:00,955 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 97 [2018-11-18 16:09:00,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:00,956 INFO L225 Difference]: With dead ends: 134 [2018-11-18 16:09:00,956 INFO L226 Difference]: Without dead ends: 134 [2018-11-18 16:09:00,956 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-18 16:09:00,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-18 16:09:00,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-11-18 16:09:00,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-18 16:09:00,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-11-18 16:09:00,959 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 97 [2018-11-18 16:09:00,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:00,960 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-11-18 16:09:00,960 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 16:09:00,960 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-11-18 16:09:00,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-11-18 16:09:00,961 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:00,961 INFO L375 BasicCegarLoop]: trace histogram [17, 14, 13, 13, 13, 13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:00,961 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:00,961 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:00,961 INFO L82 PathProgramCache]: Analyzing trace with hash 1628675678, now seen corresponding path program 4 times [2018-11-18 16:09:00,962 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:00,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:00,962 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:00,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:00,962 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:00,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:01,289 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 320 proven. 34 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-11-18 16:09:01,290 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:01,290 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:01,290 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:01,290 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:01,290 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:01,290 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:01,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:01,299 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:01,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:01,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:01,394 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 16:09:01,394 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:01,554 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 16:09:01,579 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:01,579 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6] total 22 [2018-11-18 16:09:01,579 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:01,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-18 16:09:01,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-18 16:09:01,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=417, Unknown=0, NotChecked=0, Total=506 [2018-11-18 16:09:01,580 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 18 states. [2018-11-18 16:09:01,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:01,851 INFO L93 Difference]: Finished difference Result 205 states and 211 transitions. [2018-11-18 16:09:01,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-18 16:09:01,851 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 130 [2018-11-18 16:09:01,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:01,852 INFO L225 Difference]: With dead ends: 205 [2018-11-18 16:09:01,852 INFO L226 Difference]: Without dead ends: 205 [2018-11-18 16:09:01,852 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 250 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=179, Invalid=691, Unknown=0, NotChecked=0, Total=870 [2018-11-18 16:09:01,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-11-18 16:09:01,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 177. [2018-11-18 16:09:01,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-11-18 16:09:01,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 181 transitions. [2018-11-18 16:09:01,857 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 181 transitions. Word has length 130 [2018-11-18 16:09:01,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:01,857 INFO L480 AbstractCegarLoop]: Abstraction has 177 states and 181 transitions. [2018-11-18 16:09:01,857 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-18 16:09:01,857 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 181 transitions. [2018-11-18 16:09:01,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-11-18 16:09:01,858 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:01,859 INFO L375 BasicCegarLoop]: trace histogram [23, 19, 18, 18, 18, 18, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:01,859 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:01,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:01,859 INFO L82 PathProgramCache]: Analyzing trace with hash 214822433, now seen corresponding path program 5 times [2018-11-18 16:09:01,859 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:01,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:01,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:01,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:01,860 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:01,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:02,098 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 699 proven. 198 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 16:09:02,098 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:02,098 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:02,099 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:02,099 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:02,099 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:02,099 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:02,106 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:02,106 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:02,146 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-11-18 16:09:02,146 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:02,149 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:02,252 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 503 proven. 59 refuted. 0 times theorem prover too weak. 656 trivial. 0 not checked. [2018-11-18 16:09:02,253 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:02,420 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 481 proven. 81 refuted. 0 times theorem prover too weak. 656 trivial. 0 not checked. [2018-11-18 16:09:02,435 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:02,436 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 11, 11] total 36 [2018-11-18 16:09:02,436 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:02,436 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 16:09:02,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 16:09:02,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=1094, Unknown=0, NotChecked=0, Total=1260 [2018-11-18 16:09:02,436 INFO L87 Difference]: Start difference. First operand 177 states and 181 transitions. Second operand 26 states. [2018-11-18 16:09:03,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:03,156 INFO L93 Difference]: Finished difference Result 294 states and 300 transitions. [2018-11-18 16:09:03,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-18 16:09:03,156 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 173 [2018-11-18 16:09:03,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:03,157 INFO L225 Difference]: With dead ends: 294 [2018-11-18 16:09:03,157 INFO L226 Difference]: Without dead ends: 294 [2018-11-18 16:09:03,158 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 395 GetRequests, 329 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1150 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=858, Invalid=3698, Unknown=0, NotChecked=0, Total=4556 [2018-11-18 16:09:03,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-11-18 16:09:03,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 241. [2018-11-18 16:09:03,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 241 states. [2018-11-18 16:09:03,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 246 transitions. [2018-11-18 16:09:03,165 INFO L78 Accepts]: Start accepts. Automaton has 241 states and 246 transitions. Word has length 173 [2018-11-18 16:09:03,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:03,165 INFO L480 AbstractCegarLoop]: Abstraction has 241 states and 246 transitions. [2018-11-18 16:09:03,165 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 16:09:03,165 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 246 transitions. [2018-11-18 16:09:03,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-11-18 16:09:03,167 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:03,167 INFO L375 BasicCegarLoop]: trace histogram [30, 25, 24, 24, 24, 24, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:03,168 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:03,168 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:03,168 INFO L82 PathProgramCache]: Analyzing trace with hash -2099668874, now seen corresponding path program 6 times [2018-11-18 16:09:03,168 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:03,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:03,169 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:03,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:03,169 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:03,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:04,176 INFO L134 CoverageAnalysis]: Checked inductivity of 2128 backedges. 1206 proven. 354 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2018-11-18 16:09:04,176 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:04,176 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:04,176 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:04,176 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:04,176 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:04,176 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:04,183 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:04,183 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:04,216 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:04,216 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:04,220 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:04,357 INFO L134 CoverageAnalysis]: Checked inductivity of 2128 backedges. 1208 proven. 352 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2018-11-18 16:09:04,358 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:04,564 INFO L134 CoverageAnalysis]: Checked inductivity of 2128 backedges. 1216 proven. 344 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2018-11-18 16:09:04,580 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:04,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 34 [2018-11-18 16:09:04,580 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:04,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 16:09:04,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 16:09:04,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=912, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 16:09:04,581 INFO L87 Difference]: Start difference. First operand 241 states and 246 transitions. Second operand 26 states. [2018-11-18 16:09:04,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:04,881 INFO L93 Difference]: Finished difference Result 263 states and 265 transitions. [2018-11-18 16:09:04,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-18 16:09:04,882 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 222 [2018-11-18 16:09:04,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:04,883 INFO L225 Difference]: With dead ends: 263 [2018-11-18 16:09:04,883 INFO L226 Difference]: Without dead ends: 241 [2018-11-18 16:09:04,884 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 473 GetRequests, 421 SyntacticMatches, 9 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 572 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=464, Invalid=1516, Unknown=0, NotChecked=0, Total=1980 [2018-11-18 16:09:04,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241 states. [2018-11-18 16:09:04,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241 to 238. [2018-11-18 16:09:04,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-11-18 16:09:04,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 239 transitions. [2018-11-18 16:09:04,892 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 239 transitions. Word has length 222 [2018-11-18 16:09:04,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:04,892 INFO L480 AbstractCegarLoop]: Abstraction has 238 states and 239 transitions. [2018-11-18 16:09:04,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 16:09:04,892 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 239 transitions. [2018-11-18 16:09:04,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-11-18 16:09:04,895 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:04,895 INFO L375 BasicCegarLoop]: trace histogram [32, 27, 26, 26, 26, 26, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:04,895 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:04,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:04,895 INFO L82 PathProgramCache]: Analyzing trace with hash 2121953718, now seen corresponding path program 7 times [2018-11-18 16:09:04,895 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:04,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:04,896 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:04,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:04,896 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:04,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:05,101 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 909 proven. 91 refuted. 0 times theorem prover too weak. 1448 trivial. 0 not checked. [2018-11-18 16:09:05,101 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:05,101 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:05,101 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:05,101 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:05,101 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:05,102 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:05,111 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:05,111 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:05,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:05,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:05,247 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 16:09:05,247 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:05,343 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 16:09:05,358 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:05,358 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8, 8] total 27 [2018-11-18 16:09:05,358 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:05,358 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-18 16:09:05,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-18 16:09:05,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=621, Unknown=0, NotChecked=0, Total=756 [2018-11-18 16:09:05,359 INFO L87 Difference]: Start difference. First operand 238 states and 239 transitions. Second operand 21 states. [2018-11-18 16:09:05,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:05,911 INFO L93 Difference]: Finished difference Result 316 states and 320 transitions. [2018-11-18 16:09:05,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-18 16:09:05,911 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 234 [2018-11-18 16:09:05,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:05,912 INFO L225 Difference]: With dead ends: 316 [2018-11-18 16:09:05,912 INFO L226 Difference]: Without dead ends: 316 [2018-11-18 16:09:05,913 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 454 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 275 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=291, Invalid=1115, Unknown=0, NotChecked=0, Total=1406 [2018-11-18 16:09:05,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316 states. [2018-11-18 16:09:05,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316 to 293. [2018-11-18 16:09:05,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 293 states. [2018-11-18 16:09:05,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 296 transitions. [2018-11-18 16:09:05,919 INFO L78 Accepts]: Start accepts. Automaton has 293 states and 296 transitions. Word has length 234 [2018-11-18 16:09:05,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:05,919 INFO L480 AbstractCegarLoop]: Abstraction has 293 states and 296 transitions. [2018-11-18 16:09:05,919 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-18 16:09:05,919 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 296 transitions. [2018-11-18 16:09:05,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2018-11-18 16:09:05,920 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:05,921 INFO L375 BasicCegarLoop]: trace histogram [40, 34, 33, 33, 33, 33, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:05,921 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:05,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:05,921 INFO L82 PathProgramCache]: Analyzing trace with hash 1623396665, now seen corresponding path program 8 times [2018-11-18 16:09:05,921 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:05,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:05,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:05,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:05,921 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:05,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:06,249 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 2002 proven. 402 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 16:09:06,249 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:06,249 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:06,250 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:06,250 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:06,250 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:06,250 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:06,257 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:06,257 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:06,317 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-11-18 16:09:06,318 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:06,322 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:06,474 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 1901 proven. 395 refuted. 0 times theorem prover too weak. 1598 trivial. 0 not checked. [2018-11-18 16:09:06,474 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:06,854 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 1869 proven. 427 refuted. 0 times theorem prover too weak. 1598 trivial. 0 not checked. [2018-11-18 16:09:06,879 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:06,879 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 16, 16] total 47 [2018-11-18 16:09:06,880 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:06,880 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-18 16:09:06,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-18 16:09:06,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=368, Invalid=1794, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 16:09:06,881 INFO L87 Difference]: Start difference. First operand 293 states and 296 transitions. Second operand 32 states. [2018-11-18 16:09:07,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:07,389 INFO L93 Difference]: Finished difference Result 367 states and 372 transitions. [2018-11-18 16:09:07,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-18 16:09:07,390 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 289 [2018-11-18 16:09:07,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:07,391 INFO L225 Difference]: With dead ends: 367 [2018-11-18 16:09:07,391 INFO L226 Difference]: Without dead ends: 367 [2018-11-18 16:09:07,392 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 621 GetRequests, 553 SyntacticMatches, 1 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1244 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1109, Invalid=3583, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 16:09:07,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2018-11-18 16:09:07,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 360. [2018-11-18 16:09:07,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2018-11-18 16:09:07,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 365 transitions. [2018-11-18 16:09:07,401 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 365 transitions. Word has length 289 [2018-11-18 16:09:07,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:07,401 INFO L480 AbstractCegarLoop]: Abstraction has 360 states and 365 transitions. [2018-11-18 16:09:07,401 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-18 16:09:07,401 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 365 transitions. [2018-11-18 16:09:07,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 296 [2018-11-18 16:09:07,406 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:07,406 INFO L375 BasicCegarLoop]: trace histogram [41, 35, 34, 34, 34, 34, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:07,406 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:07,407 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:07,407 INFO L82 PathProgramCache]: Analyzing trace with hash 345701441, now seen corresponding path program 9 times [2018-11-18 16:09:07,407 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:07,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:07,407 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:07,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:07,408 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:07,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:07,730 INFO L134 CoverageAnalysis]: Checked inductivity of 4107 backedges. 1349 proven. 130 refuted. 0 times theorem prover too weak. 2628 trivial. 0 not checked. [2018-11-18 16:09:07,731 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:07,731 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:07,731 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:07,731 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:07,732 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:07,733 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:07,743 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:07,743 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:07,830 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:07,830 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:07,836 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:07,951 INFO L134 CoverageAnalysis]: Checked inductivity of 4107 backedges. 1311 proven. 147 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-11-18 16:09:07,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:08,143 INFO L134 CoverageAnalysis]: Checked inductivity of 4107 backedges. 1311 proven. 147 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-11-18 16:09:08,159 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:08,159 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9, 9] total 29 [2018-11-18 16:09:08,159 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:08,160 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 16:09:08,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 16:09:08,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=710, Unknown=0, NotChecked=0, Total=870 [2018-11-18 16:09:08,160 INFO L87 Difference]: Start difference. First operand 360 states and 365 transitions. Second operand 22 states. [2018-11-18 16:09:09,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:09,604 INFO L93 Difference]: Finished difference Result 506 states and 517 transitions. [2018-11-18 16:09:09,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-18 16:09:09,604 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 295 [2018-11-18 16:09:09,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:09,606 INFO L225 Difference]: With dead ends: 506 [2018-11-18 16:09:09,606 INFO L226 Difference]: Without dead ends: 506 [2018-11-18 16:09:09,607 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 614 GetRequests, 574 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 351 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=354, Invalid=1368, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 16:09:09,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2018-11-18 16:09:09,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 479. [2018-11-18 16:09:09,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 479 states. [2018-11-18 16:09:09,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 479 states to 479 states and 489 transitions. [2018-11-18 16:09:09,615 INFO L78 Accepts]: Start accepts. Automaton has 479 states and 489 transitions. Word has length 295 [2018-11-18 16:09:09,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:09,616 INFO L480 AbstractCegarLoop]: Abstraction has 479 states and 489 transitions. [2018-11-18 16:09:09,616 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 16:09:09,616 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 489 transitions. [2018-11-18 16:09:09,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 351 [2018-11-18 16:09:09,618 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:09,618 INFO L375 BasicCegarLoop]: trace histogram [49, 42, 41, 41, 41, 41, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:09,618 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:09,618 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:09,618 INFO L82 PathProgramCache]: Analyzing trace with hash 1198964814, now seen corresponding path program 10 times [2018-11-18 16:09:09,618 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:09,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:09,619 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:09,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:09,621 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:09,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:09,988 INFO L134 CoverageAnalysis]: Checked inductivity of 5932 backedges. 2588 proven. 733 refuted. 0 times theorem prover too weak. 2611 trivial. 0 not checked. [2018-11-18 16:09:09,988 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:09,988 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:09,988 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:09,988 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:09,988 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:09,988 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:09,996 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:09,996 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:10,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:10,054 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:11,013 INFO L134 CoverageAnalysis]: Checked inductivity of 5932 backedges. 3710 proven. 102 refuted. 0 times theorem prover too weak. 2120 trivial. 0 not checked. [2018-11-18 16:09:11,013 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:11,297 INFO L134 CoverageAnalysis]: Checked inductivity of 5932 backedges. 2822 proven. 385 refuted. 0 times theorem prover too weak. 2725 trivial. 0 not checked. [2018-11-18 16:09:11,314 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:11,314 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 16, 16] total 44 [2018-11-18 16:09:11,314 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:11,314 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 16:09:11,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 16:09:11,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=1592, Unknown=0, NotChecked=0, Total=1892 [2018-11-18 16:09:11,315 INFO L87 Difference]: Start difference. First operand 479 states and 489 transitions. Second operand 37 states. [2018-11-18 16:09:12,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:12,236 INFO L93 Difference]: Finished difference Result 379 states and 382 transitions. [2018-11-18 16:09:12,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-18 16:09:12,236 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 350 [2018-11-18 16:09:12,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:12,238 INFO L225 Difference]: With dead ends: 379 [2018-11-18 16:09:12,238 INFO L226 Difference]: Without dead ends: 370 [2018-11-18 16:09:12,239 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 751 GetRequests, 673 SyntacticMatches, 8 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1700 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=850, Invalid=4262, Unknown=0, NotChecked=0, Total=5112 [2018-11-18 16:09:12,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states. [2018-11-18 16:09:12,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 366. [2018-11-18 16:09:12,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 366 states. [2018-11-18 16:09:12,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 366 states to 366 states and 369 transitions. [2018-11-18 16:09:12,248 INFO L78 Accepts]: Start accepts. Automaton has 366 states and 369 transitions. Word has length 350 [2018-11-18 16:09:12,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:12,248 INFO L480 AbstractCegarLoop]: Abstraction has 366 states and 369 transitions. [2018-11-18 16:09:12,248 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 16:09:12,249 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 369 transitions. [2018-11-18 16:09:12,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 357 [2018-11-18 16:09:12,250 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:12,250 INFO L375 BasicCegarLoop]: trace histogram [50, 43, 42, 42, 42, 42, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:12,250 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:12,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:12,251 INFO L82 PathProgramCache]: Analyzing trace with hash 627716678, now seen corresponding path program 11 times [2018-11-18 16:09:12,251 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:12,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:12,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:12,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:12,259 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:12,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:12,639 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 3015 proven. 531 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-11-18 16:09:12,639 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:12,639 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:12,639 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:12,639 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:12,639 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:12,639 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:12,647 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:12,648 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:12,836 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-11-18 16:09:12,836 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:12,842 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:13,585 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2876 proven. 523 refuted. 0 times theorem prover too weak. 2796 trivial. 0 not checked. [2018-11-18 16:09:13,585 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:14,313 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2839 proven. 560 refuted. 0 times theorem prover too weak. 2796 trivial. 0 not checked. [2018-11-18 16:09:14,338 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:14,339 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 17, 17] total 51 [2018-11-18 16:09:14,339 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:14,339 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-18 16:09:14,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-18 16:09:14,340 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=2103, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 16:09:14,340 INFO L87 Difference]: Start difference. First operand 366 states and 369 transitions. Second operand 35 states. [2018-11-18 16:09:15,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:15,080 INFO L93 Difference]: Finished difference Result 440 states and 445 transitions. [2018-11-18 16:09:15,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-18 16:09:15,081 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 356 [2018-11-18 16:09:15,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:15,082 INFO L225 Difference]: With dead ends: 440 [2018-11-18 16:09:15,083 INFO L226 Difference]: Without dead ends: 440 [2018-11-18 16:09:15,084 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 760 GetRequests, 685 SyntacticMatches, 1 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1536 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1370, Invalid=4330, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 16:09:15,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2018-11-18 16:09:15,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 433. [2018-11-18 16:09:15,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 433 states. [2018-11-18 16:09:15,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 438 transitions. [2018-11-18 16:09:15,089 INFO L78 Accepts]: Start accepts. Automaton has 433 states and 438 transitions. Word has length 356 [2018-11-18 16:09:15,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:15,090 INFO L480 AbstractCegarLoop]: Abstraction has 433 states and 438 transitions. [2018-11-18 16:09:15,090 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-18 16:09:15,090 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 438 transitions. [2018-11-18 16:09:15,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 363 [2018-11-18 16:09:15,092 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:15,092 INFO L375 BasicCegarLoop]: trace histogram [51, 44, 43, 43, 43, 43, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:15,092 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:15,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:15,093 INFO L82 PathProgramCache]: Analyzing trace with hash -2025282674, now seen corresponding path program 12 times [2018-11-18 16:09:15,093 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:15,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:15,093 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:15,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:15,094 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:15,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:15,566 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 2102 proven. 176 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 16:09:15,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:15,566 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:15,566 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:15,566 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:15,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:15,566 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:15,574 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:15,574 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:15,661 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:15,661 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:15,667 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:15,866 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 16:09:15,866 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:16,156 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 16:09:16,181 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:16,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10, 10] total 38 [2018-11-18 16:09:16,182 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:16,182 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 16:09:16,183 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 16:09:16,183 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=229, Invalid=1253, Unknown=0, NotChecked=0, Total=1482 [2018-11-18 16:09:16,183 INFO L87 Difference]: Start difference. First operand 433 states and 438 transitions. Second operand 30 states. [2018-11-18 16:09:16,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:16,829 INFO L93 Difference]: Finished difference Result 587 states and 598 transitions. [2018-11-18 16:09:16,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-18 16:09:16,829 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 362 [2018-11-18 16:09:16,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:16,831 INFO L225 Difference]: With dead ends: 587 [2018-11-18 16:09:16,831 INFO L226 Difference]: Without dead ends: 587 [2018-11-18 16:09:16,831 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 756 GetRequests, 706 SyntacticMatches, 1 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 475 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=459, Invalid=2091, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 16:09:16,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 587 states. [2018-11-18 16:09:16,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 587 to 564. [2018-11-18 16:09:16,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2018-11-18 16:09:16,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 574 transitions. [2018-11-18 16:09:16,840 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 574 transitions. Word has length 362 [2018-11-18 16:09:16,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:16,840 INFO L480 AbstractCegarLoop]: Abstraction has 564 states and 574 transitions. [2018-11-18 16:09:16,840 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 16:09:16,840 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 574 transitions. [2018-11-18 16:09:16,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 424 [2018-11-18 16:09:16,843 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:16,843 INFO L375 BasicCegarLoop]: trace histogram [60, 52, 51, 51, 51, 51, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:16,847 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:16,847 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:16,848 INFO L82 PathProgramCache]: Analyzing trace with hash -328844263, now seen corresponding path program 13 times [2018-11-18 16:09:16,848 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:16,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:16,848 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:16,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:16,849 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:16,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:17,593 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 3759 proven. 956 refuted. 0 times theorem prover too weak. 4316 trivial. 0 not checked. [2018-11-18 16:09:17,594 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:17,594 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:17,594 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:17,594 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:17,594 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:17,594 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:17,601 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:17,601 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:17,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:17,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:18,029 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 5454 proven. 140 refuted. 0 times theorem prover too weak. 3437 trivial. 0 not checked. [2018-11-18 16:09:18,029 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:18,462 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 4077 proven. 511 refuted. 0 times theorem prover too weak. 4443 trivial. 0 not checked. [2018-11-18 16:09:18,488 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:18,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18, 18] total 49 [2018-11-18 16:09:18,488 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:18,488 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 16:09:18,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 16:09:18,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=372, Invalid=1980, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 16:09:18,489 INFO L87 Difference]: Start difference. First operand 564 states and 574 transitions. Second operand 41 states. [2018-11-18 16:09:19,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:19,330 INFO L93 Difference]: Finished difference Result 452 states and 455 transitions. [2018-11-18 16:09:19,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-18 16:09:19,331 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 423 [2018-11-18 16:09:19,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:19,332 INFO L225 Difference]: With dead ends: 452 [2018-11-18 16:09:19,332 INFO L226 Difference]: Without dead ends: 443 [2018-11-18 16:09:19,333 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 903 GetRequests, 815 SyntacticMatches, 9 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2225 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1065, Invalid=5415, Unknown=0, NotChecked=0, Total=6480 [2018-11-18 16:09:19,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 443 states. [2018-11-18 16:09:19,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 443 to 439. [2018-11-18 16:09:19,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 439 states. [2018-11-18 16:09:19,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 442 transitions. [2018-11-18 16:09:19,338 INFO L78 Accepts]: Start accepts. Automaton has 439 states and 442 transitions. Word has length 423 [2018-11-18 16:09:19,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:19,338 INFO L480 AbstractCegarLoop]: Abstraction has 439 states and 442 transitions. [2018-11-18 16:09:19,338 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 16:09:19,338 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 442 transitions. [2018-11-18 16:09:19,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 430 [2018-11-18 16:09:19,340 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:19,340 INFO L375 BasicCegarLoop]: trace histogram [61, 53, 52, 52, 52, 52, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:19,341 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:19,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:19,341 INFO L82 PathProgramCache]: Analyzing trace with hash 1360864721, now seen corresponding path program 14 times [2018-11-18 16:09:19,341 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:19,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:19,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:19,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:19,342 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:19,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:19,854 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 4317 proven. 678 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 16:09:19,855 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:19,855 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:19,855 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:19,855 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:19,855 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:19,855 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:19,862 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:19,863 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:19,960 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-11-18 16:09:19,960 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:19,964 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:20,185 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 4134 proven. 669 refuted. 0 times theorem prover too weak. 4553 trivial. 0 not checked. [2018-11-18 16:09:20,185 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:20,621 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 4092 proven. 711 refuted. 0 times theorem prover too weak. 4553 trivial. 0 not checked. [2018-11-18 16:09:20,636 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:20,637 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18, 18] total 55 [2018-11-18 16:09:20,637 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:20,637 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-11-18 16:09:20,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-11-18 16:09:20,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=535, Invalid=2435, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 16:09:20,638 INFO L87 Difference]: Start difference. First operand 439 states and 442 transitions. Second operand 38 states. [2018-11-18 16:09:21,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:21,277 INFO L93 Difference]: Finished difference Result 519 states and 524 transitions. [2018-11-18 16:09:21,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 16:09:21,278 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 429 [2018-11-18 16:09:21,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:21,279 INFO L225 Difference]: With dead ends: 519 [2018-11-18 16:09:21,279 INFO L226 Difference]: Without dead ends: 519 [2018-11-18 16:09:21,281 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 911 GetRequests, 829 SyntacticMatches, 1 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1858 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1660, Invalid=5146, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 16:09:21,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 519 states. [2018-11-18 16:09:21,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 519 to 512. [2018-11-18 16:09:21,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 512 states. [2018-11-18 16:09:21,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 517 transitions. [2018-11-18 16:09:21,288 INFO L78 Accepts]: Start accepts. Automaton has 512 states and 517 transitions. Word has length 429 [2018-11-18 16:09:21,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:21,288 INFO L480 AbstractCegarLoop]: Abstraction has 512 states and 517 transitions. [2018-11-18 16:09:21,289 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-11-18 16:09:21,289 INFO L276 IsEmpty]: Start isEmpty. Operand 512 states and 517 transitions. [2018-11-18 16:09:21,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 436 [2018-11-18 16:09:21,291 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:21,291 INFO L375 BasicCegarLoop]: trace histogram [62, 54, 53, 53, 53, 53, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:21,291 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:21,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:21,292 INFO L82 PathProgramCache]: Analyzing trace with hash -51722535, now seen corresponding path program 15 times [2018-11-18 16:09:21,292 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:21,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:21,292 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:21,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:21,292 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:21,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:21,745 INFO L134 CoverageAnalysis]: Checked inductivity of 9687 backedges. 2718 proven. 229 refuted. 0 times theorem prover too weak. 6740 trivial. 0 not checked. [2018-11-18 16:09:21,745 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:21,745 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:21,745 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:21,745 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:21,746 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:21,746 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:21,753 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:21,753 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:21,868 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:21,868 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:21,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:22,038 INFO L134 CoverageAnalysis]: Checked inductivity of 9687 backedges. 2668 proven. 243 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-11-18 16:09:22,038 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:22,429 INFO L134 CoverageAnalysis]: Checked inductivity of 9687 backedges. 2668 proven. 243 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-11-18 16:09:22,445 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:22,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11, 11] total 35 [2018-11-18 16:09:22,445 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:22,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 16:09:22,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 16:09:22,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=227, Invalid=1033, Unknown=0, NotChecked=0, Total=1260 [2018-11-18 16:09:22,446 INFO L87 Difference]: Start difference. First operand 512 states and 517 transitions. Second operand 26 states. [2018-11-18 16:09:23,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:23,118 INFO L93 Difference]: Finished difference Result 682 states and 693 transitions. [2018-11-18 16:09:23,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 16:09:23,119 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 435 [2018-11-18 16:09:23,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:23,121 INFO L225 Difference]: With dead ends: 682 [2018-11-18 16:09:23,121 INFO L226 Difference]: Without dead ends: 682 [2018-11-18 16:09:23,121 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 898 GetRequests, 850 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 530 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=483, Invalid=1967, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 16:09:23,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 682 states. [2018-11-18 16:09:23,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 682 to 655. [2018-11-18 16:09:23,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 655 states. [2018-11-18 16:09:23,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 655 states to 655 states and 665 transitions. [2018-11-18 16:09:23,130 INFO L78 Accepts]: Start accepts. Automaton has 655 states and 665 transitions. Word has length 435 [2018-11-18 16:09:23,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:23,131 INFO L480 AbstractCegarLoop]: Abstraction has 655 states and 665 transitions. [2018-11-18 16:09:23,131 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 16:09:23,131 INFO L276 IsEmpty]: Start isEmpty. Operand 655 states and 665 transitions. [2018-11-18 16:09:23,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 503 [2018-11-18 16:09:23,138 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:23,139 INFO L375 BasicCegarLoop]: trace histogram [72, 63, 62, 62, 62, 62, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:23,140 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:23,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:23,141 INFO L82 PathProgramCache]: Analyzing trace with hash -94038874, now seen corresponding path program 16 times [2018-11-18 16:09:23,141 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:23,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:23,141 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:23,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:23,141 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:23,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:23,808 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 5237 proven. 1209 refuted. 0 times theorem prover too weak. 6724 trivial. 0 not checked. [2018-11-18 16:09:23,808 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:23,808 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:23,808 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:23,809 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:23,809 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:23,809 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:23,821 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:23,821 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:23,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:23,942 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:24,420 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 7662 proven. 184 refuted. 0 times theorem prover too weak. 5324 trivial. 0 not checked. [2018-11-18 16:09:24,420 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:24,860 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 5652 proven. 655 refuted. 0 times theorem prover too weak. 6863 trivial. 0 not checked. [2018-11-18 16:09:24,885 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:24,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 20, 20] total 54 [2018-11-18 16:09:24,885 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:24,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-11-18 16:09:24,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-11-18 16:09:24,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=452, Invalid=2410, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 16:09:24,886 INFO L87 Difference]: Start difference. First operand 655 states and 665 transitions. Second operand 45 states. [2018-11-18 16:09:25,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:25,852 INFO L93 Difference]: Finished difference Result 531 states and 534 transitions. [2018-11-18 16:09:25,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 16:09:25,852 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 502 [2018-11-18 16:09:25,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:25,854 INFO L225 Difference]: With dead ends: 531 [2018-11-18 16:09:25,854 INFO L226 Difference]: Without dead ends: 522 [2018-11-18 16:09:25,855 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1067 GetRequests, 969 SyntacticMatches, 10 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2820 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1305, Invalid=6705, Unknown=0, NotChecked=0, Total=8010 [2018-11-18 16:09:25,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-11-18 16:09:25,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 518. [2018-11-18 16:09:25,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2018-11-18 16:09:25,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 521 transitions. [2018-11-18 16:09:25,860 INFO L78 Accepts]: Start accepts. Automaton has 518 states and 521 transitions. Word has length 502 [2018-11-18 16:09:25,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:25,860 INFO L480 AbstractCegarLoop]: Abstraction has 518 states and 521 transitions. [2018-11-18 16:09:25,860 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-11-18 16:09:25,860 INFO L276 IsEmpty]: Start isEmpty. Operand 518 states and 521 transitions. [2018-11-18 16:09:25,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 509 [2018-11-18 16:09:25,863 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:25,863 INFO L375 BasicCegarLoop]: trace histogram [73, 64, 63, 63, 63, 63, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:25,863 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:25,863 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:25,863 INFO L82 PathProgramCache]: Analyzing trace with hash 225205406, now seen corresponding path program 17 times [2018-11-18 16:09:25,863 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:25,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:25,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:25,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:25,864 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:25,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:26,307 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5944 proven. 843 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-11-18 16:09:26,308 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:26,308 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:26,308 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:26,308 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:26,308 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:26,308 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:26,316 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:26,316 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:26,423 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-11-18 16:09:26,423 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:26,429 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:26,734 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5711 proven. 833 refuted. 0 times theorem prover too weak. 7019 trivial. 0 not checked. [2018-11-18 16:09:26,735 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:27,228 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5664 proven. 880 refuted. 0 times theorem prover too weak. 7019 trivial. 0 not checked. [2018-11-18 16:09:27,243 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:27,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 19, 19] total 59 [2018-11-18 16:09:27,244 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:27,244 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 16:09:27,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 16:09:27,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=632, Invalid=2790, Unknown=0, NotChecked=0, Total=3422 [2018-11-18 16:09:27,246 INFO L87 Difference]: Start difference. First operand 518 states and 521 transitions. Second operand 41 states. [2018-11-18 16:09:28,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:28,141 INFO L93 Difference]: Finished difference Result 604 states and 609 transitions. [2018-11-18 16:09:28,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-18 16:09:28,142 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 508 [2018-11-18 16:09:28,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:28,144 INFO L225 Difference]: With dead ends: 604 [2018-11-18 16:09:28,144 INFO L226 Difference]: Without dead ends: 604 [2018-11-18 16:09:28,145 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1074 GetRequests, 985 SyntacticMatches, 1 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2210 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1979, Invalid=6031, Unknown=0, NotChecked=0, Total=8010 [2018-11-18 16:09:28,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 604 states. [2018-11-18 16:09:28,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 604 to 597. [2018-11-18 16:09:28,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2018-11-18 16:09:28,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 602 transitions. [2018-11-18 16:09:28,152 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 602 transitions. Word has length 508 [2018-11-18 16:09:28,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:28,152 INFO L480 AbstractCegarLoop]: Abstraction has 597 states and 602 transitions. [2018-11-18 16:09:28,152 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 16:09:28,152 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 602 transitions. [2018-11-18 16:09:28,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 515 [2018-11-18 16:09:28,155 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:28,160 INFO L375 BasicCegarLoop]: trace histogram [74, 65, 64, 64, 64, 64, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:28,160 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:28,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:28,160 INFO L82 PathProgramCache]: Analyzing trace with hash 193147878, now seen corresponding path program 18 times [2018-11-18 16:09:28,160 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:28,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:28,161 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:28,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:28,161 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:28,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:28,831 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3707 proven. 289 refuted. 0 times theorem prover too weak. 9966 trivial. 0 not checked. [2018-11-18 16:09:28,831 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:28,831 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:28,831 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:28,831 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:28,831 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:28,831 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:28,840 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:28,840 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:28,944 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:28,944 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:28,950 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:29,295 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3600 proven. 300 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 16:09:29,295 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:29,625 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3600 proven. 300 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 16:09:29,640 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:29,640 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12, 12] total 39 [2018-11-18 16:09:29,641 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:29,641 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 16:09:29,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 16:09:29,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=269, Invalid=1291, Unknown=0, NotChecked=0, Total=1560 [2018-11-18 16:09:29,641 INFO L87 Difference]: Start difference. First operand 597 states and 602 transitions. Second operand 29 states. [2018-11-18 16:09:30,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:30,426 INFO L93 Difference]: Finished difference Result 779 states and 790 transitions. [2018-11-18 16:09:30,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-18 16:09:30,427 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 514 [2018-11-18 16:09:30,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:30,429 INFO L225 Difference]: With dead ends: 779 [2018-11-18 16:09:30,429 INFO L226 Difference]: Without dead ends: 779 [2018-11-18 16:09:30,430 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1059 GetRequests, 1006 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 651 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=569, Invalid=2401, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 16:09:30,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states. [2018-11-18 16:09:30,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 752. [2018-11-18 16:09:30,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 752 states. [2018-11-18 16:09:30,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 752 states to 752 states and 762 transitions. [2018-11-18 16:09:30,439 INFO L78 Accepts]: Start accepts. Automaton has 752 states and 762 transitions. Word has length 514 [2018-11-18 16:09:30,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:30,440 INFO L480 AbstractCegarLoop]: Abstraction has 752 states and 762 transitions. [2018-11-18 16:09:30,440 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 16:09:30,440 INFO L276 IsEmpty]: Start isEmpty. Operand 752 states and 762 transitions. [2018-11-18 16:09:30,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 588 [2018-11-18 16:09:30,447 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:30,447 INFO L375 BasicCegarLoop]: trace histogram [85, 75, 74, 74, 74, 74, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:30,447 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:30,447 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:30,447 INFO L82 PathProgramCache]: Analyzing trace with hash -1182172111, now seen corresponding path program 19 times [2018-11-18 16:09:30,447 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:30,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,448 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:30,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:30,448 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:30,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:30,935 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 7058 proven. 1492 refuted. 0 times theorem prover too weak. 10003 trivial. 0 not checked. [2018-11-18 16:09:30,936 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:30,936 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:30,936 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:30,936 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:30,936 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:30,936 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:30,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:30,946 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:31,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:31,050 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:31,993 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 10388 proven. 234 refuted. 0 times theorem prover too weak. 7931 trivial. 0 not checked. [2018-11-18 16:09:31,994 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:32,555 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 7583 proven. 817 refuted. 0 times theorem prover too weak. 10153 trivial. 0 not checked. [2018-11-18 16:09:32,570 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:32,571 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 22, 22] total 59 [2018-11-18 16:09:32,571 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:32,571 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 16:09:32,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 16:09:32,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=2882, Unknown=0, NotChecked=0, Total=3422 [2018-11-18 16:09:32,572 INFO L87 Difference]: Start difference. First operand 752 states and 762 transitions. Second operand 49 states. [2018-11-18 16:09:33,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:33,618 INFO L93 Difference]: Finished difference Result 616 states and 619 transitions. [2018-11-18 16:09:33,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 16:09:33,619 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 587 [2018-11-18 16:09:33,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:33,621 INFO L225 Difference]: With dead ends: 616 [2018-11-18 16:09:33,621 INFO L226 Difference]: Without dead ends: 607 [2018-11-18 16:09:33,621 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1243 GetRequests, 1135 SyntacticMatches, 11 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3485 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1570, Invalid=8132, Unknown=0, NotChecked=0, Total=9702 [2018-11-18 16:09:33,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-11-18 16:09:33,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 603. [2018-11-18 16:09:33,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 603 states. [2018-11-18 16:09:33,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603 states to 603 states and 606 transitions. [2018-11-18 16:09:33,627 INFO L78 Accepts]: Start accepts. Automaton has 603 states and 606 transitions. Word has length 587 [2018-11-18 16:09:33,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:33,628 INFO L480 AbstractCegarLoop]: Abstraction has 603 states and 606 transitions. [2018-11-18 16:09:33,628 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 16:09:33,628 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 606 transitions. [2018-11-18 16:09:33,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 594 [2018-11-18 16:09:33,635 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:33,635 INFO L375 BasicCegarLoop]: trace histogram [86, 76, 75, 75, 75, 75, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:33,635 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:33,636 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:33,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1816761367, now seen corresponding path program 20 times [2018-11-18 16:09:33,636 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:33,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:33,637 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:33,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:33,637 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:33,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:34,400 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7932 proven. 1026 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 16:09:34,401 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:34,401 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:34,401 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:34,401 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:34,401 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:34,401 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:34,409 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:34,409 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:34,542 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-18 16:09:34,542 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:34,546 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:34,885 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7643 proven. 1015 refuted. 0 times theorem prover too weak. 10362 trivial. 0 not checked. [2018-11-18 16:09:34,886 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:35,844 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7591 proven. 1067 refuted. 0 times theorem prover too weak. 10362 trivial. 0 not checked. [2018-11-18 16:09:35,860 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:35,860 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 20, 20] total 63 [2018-11-18 16:09:35,860 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:35,861 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-11-18 16:09:35,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-11-18 16:09:35,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=738, Invalid=3168, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 16:09:35,861 INFO L87 Difference]: Start difference. First operand 603 states and 606 transitions. Second operand 44 states. [2018-11-18 16:09:36,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:36,697 INFO L93 Difference]: Finished difference Result 695 states and 700 transitions. [2018-11-18 16:09:36,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-18 16:09:36,698 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 593 [2018-11-18 16:09:36,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:36,699 INFO L225 Difference]: With dead ends: 695 [2018-11-18 16:09:36,699 INFO L226 Difference]: Without dead ends: 695 [2018-11-18 16:09:36,700 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1249 GetRequests, 1153 SyntacticMatches, 1 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2592 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2327, Invalid=6985, Unknown=0, NotChecked=0, Total=9312 [2018-11-18 16:09:36,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states. [2018-11-18 16:09:36,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 688. [2018-11-18 16:09:36,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 688 states. [2018-11-18 16:09:36,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 693 transitions. [2018-11-18 16:09:36,710 INFO L78 Accepts]: Start accepts. Automaton has 688 states and 693 transitions. Word has length 593 [2018-11-18 16:09:36,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:36,711 INFO L480 AbstractCegarLoop]: Abstraction has 688 states and 693 transitions. [2018-11-18 16:09:36,711 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-11-18 16:09:36,711 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 693 transitions. [2018-11-18 16:09:36,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 600 [2018-11-18 16:09:36,714 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:36,714 INFO L375 BasicCegarLoop]: trace histogram [87, 77, 76, 76, 76, 76, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:36,715 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:36,715 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:36,721 INFO L82 PathProgramCache]: Analyzing trace with hash 1117954801, now seen corresponding path program 21 times [2018-11-18 16:09:36,721 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:36,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:36,722 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:36,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:36,722 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:36,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:37,088 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4787 proven. 356 refuted. 0 times theorem prover too weak. 14350 trivial. 0 not checked. [2018-11-18 16:09:37,089 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:37,089 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:37,089 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:37,089 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:37,089 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:37,089 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:37,097 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:37,098 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:37,281 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:37,281 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:37,288 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:37,487 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4725 proven. 363 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 16:09:37,487 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:37,794 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4725 proven. 363 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 16:09:37,810 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:37,810 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13, 13] total 41 [2018-11-18 16:09:37,810 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:37,811 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 16:09:37,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 16:09:37,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=1416, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 16:09:37,811 INFO L87 Difference]: Start difference. First operand 688 states and 693 transitions. Second operand 30 states. [2018-11-18 16:09:38,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:38,977 INFO L93 Difference]: Finished difference Result 882 states and 893 transitions. [2018-11-18 16:09:38,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-18 16:09:38,977 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 599 [2018-11-18 16:09:38,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:38,978 INFO L225 Difference]: With dead ends: 882 [2018-11-18 16:09:38,979 INFO L226 Difference]: Without dead ends: 882 [2018-11-18 16:09:38,979 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1230 GetRequests, 1174 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 745 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=632, Invalid=2674, Unknown=0, NotChecked=0, Total=3306 [2018-11-18 16:09:38,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 882 states. [2018-11-18 16:09:38,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 882 to 855. [2018-11-18 16:09:38,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 855 states. [2018-11-18 16:09:38,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 855 states and 865 transitions. [2018-11-18 16:09:38,985 INFO L78 Accepts]: Start accepts. Automaton has 855 states and 865 transitions. Word has length 599 [2018-11-18 16:09:38,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:38,986 INFO L480 AbstractCegarLoop]: Abstraction has 855 states and 865 transitions. [2018-11-18 16:09:38,986 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 16:09:38,986 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 865 transitions. [2018-11-18 16:09:38,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 679 [2018-11-18 16:09:38,990 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:38,990 INFO L375 BasicCegarLoop]: trace histogram [99, 88, 87, 87, 87, 87, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:38,990 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:38,991 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:38,991 INFO L82 PathProgramCache]: Analyzing trace with hash -160692354, now seen corresponding path program 22 times [2018-11-18 16:09:38,991 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:38,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:38,998 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:38,998 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:38,998 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:39,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:39,836 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 9258 proven. 1805 refuted. 0 times theorem prover too weak. 14339 trivial. 0 not checked. [2018-11-18 16:09:39,836 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:39,836 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:39,836 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:39,836 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:39,836 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:39,836 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:39,842 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:39,842 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:39,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:39,944 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:40,377 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 13686 proven. 290 refuted. 0 times theorem prover too weak. 11426 trivial. 0 not checked. [2018-11-18 16:09:40,377 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:40,978 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 9906 proven. 997 refuted. 0 times theorem prover too weak. 14499 trivial. 0 not checked. [2018-11-18 16:09:40,993 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:40,994 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 24, 24] total 64 [2018-11-18 16:09:40,994 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:40,994 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-18 16:09:40,994 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-18 16:09:40,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=636, Invalid=3396, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 16:09:40,994 INFO L87 Difference]: Start difference. First operand 855 states and 865 transitions. Second operand 53 states. [2018-11-18 16:09:41,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:41,974 INFO L93 Difference]: Finished difference Result 707 states and 710 transitions. [2018-11-18 16:09:41,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-11-18 16:09:41,975 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 678 [2018-11-18 16:09:41,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:41,976 INFO L225 Difference]: With dead ends: 707 [2018-11-18 16:09:41,976 INFO L226 Difference]: Without dead ends: 698 [2018-11-18 16:09:41,977 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1431 GetRequests, 1313 SyntacticMatches, 12 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4220 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1860, Invalid=9696, Unknown=0, NotChecked=0, Total=11556 [2018-11-18 16:09:41,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 698 states. [2018-11-18 16:09:41,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 698 to 694. [2018-11-18 16:09:41,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2018-11-18 16:09:41,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 697 transitions. [2018-11-18 16:09:41,982 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 697 transitions. Word has length 678 [2018-11-18 16:09:41,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:41,982 INFO L480 AbstractCegarLoop]: Abstraction has 694 states and 697 transitions. [2018-11-18 16:09:41,982 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-18 16:09:41,982 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 697 transitions. [2018-11-18 16:09:41,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 685 [2018-11-18 16:09:41,986 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:41,987 INFO L375 BasicCegarLoop]: trace histogram [100, 89, 88, 88, 88, 88, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:41,987 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:41,987 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:41,987 INFO L82 PathProgramCache]: Analyzing trace with hash 1163543926, now seen corresponding path program 23 times [2018-11-18 16:09:41,987 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:41,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:41,988 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:41,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:41,988 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:42,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:42,683 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 10317 proven. 1227 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 16:09:42,683 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:42,683 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:42,684 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:42,684 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:42,684 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:42,684 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:42,689 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:42,689 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:42,853 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-18 16:09:42,853 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:42,858 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:43,215 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 9966 proven. 1215 refuted. 0 times theorem prover too weak. 14768 trivial. 0 not checked. [2018-11-18 16:09:43,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:43,855 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 9909 proven. 1272 refuted. 0 times theorem prover too weak. 14768 trivial. 0 not checked. [2018-11-18 16:09:43,871 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:43,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 21, 21] total 67 [2018-11-18 16:09:43,872 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:43,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-11-18 16:09:43,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-11-18 16:09:43,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=853, Invalid=3569, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 16:09:43,873 INFO L87 Difference]: Start difference. First operand 694 states and 697 transitions. Second operand 47 states. [2018-11-18 16:09:44,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:44,761 INFO L93 Difference]: Finished difference Result 792 states and 797 transitions. [2018-11-18 16:09:44,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-11-18 16:09:44,762 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 684 [2018-11-18 16:09:44,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:44,764 INFO L225 Difference]: With dead ends: 792 [2018-11-18 16:09:44,764 INFO L226 Difference]: Without dead ends: 792 [2018-11-18 16:09:44,765 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1436 GetRequests, 1333 SyntacticMatches, 1 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3004 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2704, Invalid=8008, Unknown=0, NotChecked=0, Total=10712 [2018-11-18 16:09:44,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states. [2018-11-18 16:09:44,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 785. [2018-11-18 16:09:44,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 785 states. [2018-11-18 16:09:44,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 785 states to 785 states and 790 transitions. [2018-11-18 16:09:44,773 INFO L78 Accepts]: Start accepts. Automaton has 785 states and 790 transitions. Word has length 684 [2018-11-18 16:09:44,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:44,773 INFO L480 AbstractCegarLoop]: Abstraction has 785 states and 790 transitions. [2018-11-18 16:09:44,773 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-11-18 16:09:44,773 INFO L276 IsEmpty]: Start isEmpty. Operand 785 states and 790 transitions. [2018-11-18 16:09:44,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 691 [2018-11-18 16:09:44,777 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:44,778 INFO L375 BasicCegarLoop]: trace histogram [101, 90, 89, 89, 89, 89, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:44,778 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:44,778 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:44,778 INFO L82 PathProgramCache]: Analyzing trace with hash -2123062594, now seen corresponding path program 24 times [2018-11-18 16:09:44,778 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:44,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:44,779 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:44,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:44,779 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:44,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:45,118 INFO L134 CoverageAnalysis]: Checked inductivity of 26502 backedges. 6300 proven. 430 refuted. 0 times theorem prover too weak. 19772 trivial. 0 not checked. [2018-11-18 16:09:45,118 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:45,118 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:45,118 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:45,118 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:45,118 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:45,118 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:45,124 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:45,124 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:45,271 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:45,271 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:45,278 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:45,557 INFO L134 CoverageAnalysis]: Checked inductivity of 26502 backedges. 6061 proven. 432 refuted. 0 times theorem prover too weak. 20009 trivial. 0 not checked. [2018-11-18 16:09:45,557 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:46,017 INFO L134 CoverageAnalysis]: Checked inductivity of 26502 backedges. 6061 proven. 432 refuted. 0 times theorem prover too weak. 20009 trivial. 0 not checked. [2018-11-18 16:09:46,033 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:46,033 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 14, 14] total 47 [2018-11-18 16:09:46,033 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:46,034 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-18 16:09:46,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-18 16:09:46,034 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1891, Unknown=0, NotChecked=0, Total=2256 [2018-11-18 16:09:46,035 INFO L87 Difference]: Start difference. First operand 785 states and 790 transitions. Second operand 35 states. [2018-11-18 16:09:46,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:46,878 INFO L93 Difference]: Finished difference Result 991 states and 1002 transitions. [2018-11-18 16:09:46,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-11-18 16:09:46,879 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 690 [2018-11-18 16:09:46,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:46,882 INFO L225 Difference]: With dead ends: 991 [2018-11-18 16:09:46,882 INFO L226 Difference]: Without dead ends: 991 [2018-11-18 16:09:46,882 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1417 GetRequests, 1354 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 929 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=762, Invalid=3398, Unknown=0, NotChecked=0, Total=4160 [2018-11-18 16:09:46,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states. [2018-11-18 16:09:46,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 964. [2018-11-18 16:09:46,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 964 states. [2018-11-18 16:09:46,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 964 states to 964 states and 974 transitions. [2018-11-18 16:09:46,893 INFO L78 Accepts]: Start accepts. Automaton has 964 states and 974 transitions. Word has length 690 [2018-11-18 16:09:46,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:46,894 INFO L480 AbstractCegarLoop]: Abstraction has 964 states and 974 transitions. [2018-11-18 16:09:46,894 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-18 16:09:46,894 INFO L276 IsEmpty]: Start isEmpty. Operand 964 states and 974 transitions. [2018-11-18 16:09:46,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2018-11-18 16:09:46,899 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:46,899 INFO L375 BasicCegarLoop]: trace histogram [114, 102, 101, 101, 101, 101, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:46,900 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:46,900 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:46,900 INFO L82 PathProgramCache]: Analyzing trace with hash 1214238153, now seen corresponding path program 25 times [2018-11-18 16:09:46,900 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:46,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:46,901 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:46,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:46,901 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:46,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:47,788 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 11873 proven. 2148 refuted. 0 times theorem prover too weak. 19936 trivial. 0 not checked. [2018-11-18 16:09:47,789 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:47,789 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:47,789 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:47,789 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:47,789 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:47,789 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:47,796 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:47,796 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:47,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:47,913 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:48,499 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 17610 proven. 352 refuted. 0 times theorem prover too weak. 15995 trivial. 0 not checked. [2018-11-18 16:09:48,499 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:49,338 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 12657 proven. 1195 refuted. 0 times theorem prover too weak. 20105 trivial. 0 not checked. [2018-11-18 16:09:49,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:49,354 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 26, 26] total 69 [2018-11-18 16:09:49,354 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:49,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-18 16:09:49,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-18 16:09:49,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=740, Invalid=3952, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 16:09:49,355 INFO L87 Difference]: Start difference. First operand 964 states and 974 transitions. Second operand 57 states. [2018-11-18 16:09:50,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:50,718 INFO L93 Difference]: Finished difference Result 804 states and 807 transitions. [2018-11-18 16:09:50,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-11-18 16:09:50,718 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 775 [2018-11-18 16:09:50,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:50,720 INFO L225 Difference]: With dead ends: 804 [2018-11-18 16:09:50,720 INFO L226 Difference]: Without dead ends: 795 [2018-11-18 16:09:50,720 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1631 GetRequests, 1503 SyntacticMatches, 13 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5025 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2175, Invalid=11397, Unknown=0, NotChecked=0, Total=13572 [2018-11-18 16:09:50,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 795 states. [2018-11-18 16:09:50,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 795 to 791. [2018-11-18 16:09:50,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 791 states. [2018-11-18 16:09:50,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 791 states to 791 states and 794 transitions. [2018-11-18 16:09:50,725 INFO L78 Accepts]: Start accepts. Automaton has 791 states and 794 transitions. Word has length 775 [2018-11-18 16:09:50,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:50,725 INFO L480 AbstractCegarLoop]: Abstraction has 791 states and 794 transitions. [2018-11-18 16:09:50,725 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-18 16:09:50,725 INFO L276 IsEmpty]: Start isEmpty. Operand 791 states and 794 transitions. [2018-11-18 16:09:50,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2018-11-18 16:09:50,728 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:50,728 INFO L375 BasicCegarLoop]: trace histogram [115, 103, 102, 102, 102, 102, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:50,728 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:50,728 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:50,729 INFO L82 PathProgramCache]: Analyzing trace with hash -520903807, now seen corresponding path program 26 times [2018-11-18 16:09:50,729 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:50,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:50,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:50,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:50,729 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:50,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:51,395 INFO L134 CoverageAnalysis]: Checked inductivity of 34590 backedges. 13135 proven. 1446 refuted. 0 times theorem prover too weak. 20009 trivial. 0 not checked. [2018-11-18 16:09:51,396 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:51,396 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:51,396 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:51,396 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:51,396 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:51,396 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:51,407 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:09:51,407 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:09:51,590 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-11-18 16:09:51,590 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:51,595 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:52,003 INFO L134 CoverageAnalysis]: Checked inductivity of 34590 backedges. 7545 proven. 507 refuted. 0 times theorem prover too weak. 26538 trivial. 0 not checked. [2018-11-18 16:09:52,003 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:52,505 INFO L134 CoverageAnalysis]: Checked inductivity of 34590 backedges. 7545 proven. 507 refuted. 0 times theorem prover too weak. 26538 trivial. 0 not checked. [2018-11-18 16:09:52,521 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:52,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 16, 16] total 64 [2018-11-18 16:09:52,521 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:52,522 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 16:09:52,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 16:09:52,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=682, Invalid=3350, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 16:09:52,522 INFO L87 Difference]: Start difference. First operand 791 states and 794 transitions. Second operand 49 states. [2018-11-18 16:09:53,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:53,602 INFO L93 Difference]: Finished difference Result 904 states and 910 transitions. [2018-11-18 16:09:53,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-11-18 16:09:53,603 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 781 [2018-11-18 16:09:53,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:53,605 INFO L225 Difference]: With dead ends: 904 [2018-11-18 16:09:53,605 INFO L226 Difference]: Without dead ends: 904 [2018-11-18 16:09:53,606 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1636 GetRequests, 1533 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2274 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2735, Invalid=8185, Unknown=0, NotChecked=0, Total=10920 [2018-11-18 16:09:53,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 904 states. [2018-11-18 16:09:53,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 904 to 894. [2018-11-18 16:09:53,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 894 states. [2018-11-18 16:09:53,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 894 states to 894 states and 900 transitions. [2018-11-18 16:09:53,614 INFO L78 Accepts]: Start accepts. Automaton has 894 states and 900 transitions. Word has length 781 [2018-11-18 16:09:53,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:53,614 INFO L480 AbstractCegarLoop]: Abstraction has 894 states and 900 transitions. [2018-11-18 16:09:53,614 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 16:09:53,614 INFO L276 IsEmpty]: Start isEmpty. Operand 894 states and 900 transitions. [2018-11-18 16:09:53,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 794 [2018-11-18 16:09:53,619 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:53,619 INFO L375 BasicCegarLoop]: trace histogram [117, 105, 104, 104, 104, 104, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:53,619 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:53,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:53,620 INFO L82 PathProgramCache]: Analyzing trace with hash -472685503, now seen corresponding path program 27 times [2018-11-18 16:09:53,620 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:53,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:53,620 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:53,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:53,621 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:53,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:54,122 INFO L134 CoverageAnalysis]: Checked inductivity of 35874 backedges. 8749 proven. 539 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-11-18 16:09:54,123 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:54,123 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:54,123 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:54,123 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:54,123 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:54,123 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:54,132 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:09:54,132 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:09:54,239 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:09:54,239 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:09:54,247 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:54,832 INFO L134 CoverageAnalysis]: Checked inductivity of 35874 backedges. 8624 proven. 2005 refuted. 0 times theorem prover too weak. 25245 trivial. 0 not checked. [2018-11-18 16:09:54,832 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:56,277 INFO L134 CoverageAnalysis]: Checked inductivity of 35874 backedges. 8624 proven. 2005 refuted. 0 times theorem prover too weak. 25245 trivial. 0 not checked. [2018-11-18 16:09:56,292 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:56,293 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 35, 35] total 55 [2018-11-18 16:09:56,293 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:56,294 INFO L459 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-11-18 16:09:56,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-11-18 16:09:56,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=559, Invalid=2411, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 16:09:56,294 INFO L87 Difference]: Start difference. First operand 894 states and 900 transitions. Second operand 52 states. [2018-11-18 16:09:57,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:09:57,289 INFO L93 Difference]: Finished difference Result 1096 states and 1106 transitions. [2018-11-18 16:09:57,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-11-18 16:09:57,290 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 793 [2018-11-18 16:09:57,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:09:57,292 INFO L225 Difference]: With dead ends: 1096 [2018-11-18 16:09:57,292 INFO L226 Difference]: Without dead ends: 1096 [2018-11-18 16:09:57,293 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1646 GetRequests, 1533 SyntacticMatches, 31 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2281 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1458, Invalid=5514, Unknown=0, NotChecked=0, Total=6972 [2018-11-18 16:09:57,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1096 states. [2018-11-18 16:09:57,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1096 to 1085. [2018-11-18 16:09:57,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1085 states. [2018-11-18 16:09:57,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1085 states to 1085 states and 1095 transitions. [2018-11-18 16:09:57,303 INFO L78 Accepts]: Start accepts. Automaton has 1085 states and 1095 transitions. Word has length 793 [2018-11-18 16:09:57,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:09:57,304 INFO L480 AbstractCegarLoop]: Abstraction has 1085 states and 1095 transitions. [2018-11-18 16:09:57,304 INFO L481 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-11-18 16:09:57,304 INFO L276 IsEmpty]: Start isEmpty. Operand 1085 states and 1095 transitions. [2018-11-18 16:09:57,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 879 [2018-11-18 16:09:57,309 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:09:57,309 INFO L375 BasicCegarLoop]: trace histogram [130, 117, 116, 116, 116, 116, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:09:57,309 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:09:57,310 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:09:57,310 INFO L82 PathProgramCache]: Analyzing trace with hash -1449420586, now seen corresponding path program 28 times [2018-11-18 16:09:57,310 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:09:57,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:57,310 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:09:57,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:09:57,311 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:09:57,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:57,899 INFO L134 CoverageAnalysis]: Checked inductivity of 44476 backedges. 14939 proven. 2521 refuted. 0 times theorem prover too weak. 27016 trivial. 0 not checked. [2018-11-18 16:09:57,899 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:57,899 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:09:57,900 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:09:57,900 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:09:57,900 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:09:57,900 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:09:57,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:09:57,909 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:09:58,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:09:58,054 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:09:58,716 INFO L134 CoverageAnalysis]: Checked inductivity of 44476 backedges. 22214 proven. 420 refuted. 0 times theorem prover too weak. 21842 trivial. 0 not checked. [2018-11-18 16:09:58,716 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:09:59,532 INFO L134 CoverageAnalysis]: Checked inductivity of 44476 backedges. 15872 proven. 1411 refuted. 0 times theorem prover too weak. 27193 trivial. 0 not checked. [2018-11-18 16:09:59,547 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:09:59,548 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 28, 28] total 74 [2018-11-18 16:09:59,548 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:09:59,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-11-18 16:09:59,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-11-18 16:09:59,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=852, Invalid=4550, Unknown=0, NotChecked=0, Total=5402 [2018-11-18 16:09:59,549 INFO L87 Difference]: Start difference. First operand 1085 states and 1095 transitions. Second operand 61 states. [2018-11-18 16:10:00,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:00,914 INFO L93 Difference]: Finished difference Result 907 states and 910 transitions. [2018-11-18 16:10:00,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 16:10:00,915 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 878 [2018-11-18 16:10:00,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:00,917 INFO L225 Difference]: With dead ends: 907 [2018-11-18 16:10:00,917 INFO L226 Difference]: Without dead ends: 898 [2018-11-18 16:10:00,918 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1843 GetRequests, 1705 SyntacticMatches, 14 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5900 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2515, Invalid=13235, Unknown=0, NotChecked=0, Total=15750 [2018-11-18 16:10:00,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 898 states. [2018-11-18 16:10:00,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 898 to 894. [2018-11-18 16:10:00,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 894 states. [2018-11-18 16:10:00,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 894 states to 894 states and 897 transitions. [2018-11-18 16:10:00,924 INFO L78 Accepts]: Start accepts. Automaton has 894 states and 897 transitions. Word has length 878 [2018-11-18 16:10:00,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:00,924 INFO L480 AbstractCegarLoop]: Abstraction has 894 states and 897 transitions. [2018-11-18 16:10:00,924 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-11-18 16:10:00,924 INFO L276 IsEmpty]: Start isEmpty. Operand 894 states and 897 transitions. [2018-11-18 16:10:00,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 885 [2018-11-18 16:10:00,928 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:00,928 INFO L375 BasicCegarLoop]: trace histogram [131, 118, 117, 117, 117, 117, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:00,929 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:00,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:00,929 INFO L82 PathProgramCache]: Analyzing trace with hash 289664206, now seen corresponding path program 29 times [2018-11-18 16:10:00,929 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:00,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:00,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:00,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:00,930 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:00,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:01,586 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 16422 proven. 1683 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-18 16:10:01,586 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:01,586 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:01,586 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:01,587 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:01,587 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:01,587 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:01,593 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:01,593 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:01,781 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-11-18 16:10:01,781 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:01,788 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:02,294 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 15929 proven. 1669 refuted. 0 times theorem prover too weak. 27603 trivial. 0 not checked. [2018-11-18 16:10:02,294 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:03,331 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 15862 proven. 1736 refuted. 0 times theorem prover too weak. 27603 trivial. 0 not checked. [2018-11-18 16:10:03,357 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:03,357 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 23, 23] total 75 [2018-11-18 16:10:03,357 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:03,358 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-18 16:10:03,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-18 16:10:03,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1110, Invalid=4440, Unknown=0, NotChecked=0, Total=5550 [2018-11-18 16:10:03,359 INFO L87 Difference]: Start difference. First operand 894 states and 897 transitions. Second operand 53 states. [2018-11-18 16:10:04,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:04,780 INFO L93 Difference]: Finished difference Result 1004 states and 1009 transitions. [2018-11-18 16:10:04,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 16:10:04,780 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 884 [2018-11-18 16:10:04,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:04,783 INFO L225 Difference]: With dead ends: 1004 [2018-11-18 16:10:04,783 INFO L226 Difference]: Without dead ends: 1004 [2018-11-18 16:10:04,784 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1846 GetRequests, 1729 SyntacticMatches, 1 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3918 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3545, Invalid=10261, Unknown=0, NotChecked=0, Total=13806 [2018-11-18 16:10:04,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1004 states. [2018-11-18 16:10:04,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1004 to 997. [2018-11-18 16:10:04,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 997 states. [2018-11-18 16:10:04,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 997 states to 997 states and 1002 transitions. [2018-11-18 16:10:04,791 INFO L78 Accepts]: Start accepts. Automaton has 997 states and 1002 transitions. Word has length 884 [2018-11-18 16:10:04,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:04,792 INFO L480 AbstractCegarLoop]: Abstraction has 997 states and 1002 transitions. [2018-11-18 16:10:04,792 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-18 16:10:04,792 INFO L276 IsEmpty]: Start isEmpty. Operand 997 states and 1002 transitions. [2018-11-18 16:10:04,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 891 [2018-11-18 16:10:04,796 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:04,797 INFO L375 BasicCegarLoop]: trace histogram [132, 119, 118, 118, 118, 118, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:04,797 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:04,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:04,797 INFO L82 PathProgramCache]: Analyzing trace with hash 321712150, now seen corresponding path program 30 times [2018-11-18 16:10:04,797 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:04,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:04,798 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:04,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:04,798 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:04,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:05,223 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9593 proven. 599 refuted. 0 times theorem prover too weak. 35740 trivial. 0 not checked. [2018-11-18 16:10:05,223 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:05,223 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:05,223 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:05,223 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:05,223 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:05,223 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:05,234 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:05,234 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:05,432 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:05,432 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:05,442 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:05,799 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9438 proven. 588 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 16:10:05,799 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:06,273 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9438 proven. 588 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 16:10:06,290 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:06,290 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16, 16] total 51 [2018-11-18 16:10:06,290 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:06,291 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 16:10:06,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 16:10:06,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=2201, Unknown=0, NotChecked=0, Total=2652 [2018-11-18 16:10:06,292 INFO L87 Difference]: Start difference. First operand 997 states and 1002 transitions. Second operand 37 states. [2018-11-18 16:10:07,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:07,351 INFO L93 Difference]: Finished difference Result 1227 states and 1238 transitions. [2018-11-18 16:10:07,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 16:10:07,352 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 890 [2018-11-18 16:10:07,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:07,354 INFO L225 Difference]: With dead ends: 1227 [2018-11-18 16:10:07,354 INFO L226 Difference]: Without dead ends: 1227 [2018-11-18 16:10:07,355 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1819 GetRequests, 1750 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1161 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=911, Invalid=4059, Unknown=0, NotChecked=0, Total=4970 [2018-11-18 16:10:07,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1227 states. [2018-11-18 16:10:07,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1227 to 1200. [2018-11-18 16:10:07,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1200 states. [2018-11-18 16:10:07,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1210 transitions. [2018-11-18 16:10:07,362 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1210 transitions. Word has length 890 [2018-11-18 16:10:07,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:07,363 INFO L480 AbstractCegarLoop]: Abstraction has 1200 states and 1210 transitions. [2018-11-18 16:10:07,363 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 16:10:07,363 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1210 transitions. [2018-11-18 16:10:07,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 988 [2018-11-18 16:10:07,368 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:07,368 INFO L375 BasicCegarLoop]: trace histogram [147, 133, 132, 132, 132, 132, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:07,369 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:07,369 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:07,369 INFO L82 PathProgramCache]: Analyzing trace with hash -1912049439, now seen corresponding path program 31 times [2018-11-18 16:10:07,369 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:07,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:07,370 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:07,370 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:07,370 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:07,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:08,087 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 18492 proven. 2924 refuted. 0 times theorem prover too weak. 35819 trivial. 0 not checked. [2018-11-18 16:10:08,087 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:08,087 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:08,087 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:08,087 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:08,087 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:08,087 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:08,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:08,093 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:08,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:08,254 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:09,001 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 27552 proven. 494 refuted. 0 times theorem prover too weak. 29189 trivial. 0 not checked. [2018-11-18 16:10:09,001 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:11,044 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 19587 proven. 1645 refuted. 0 times theorem prover too weak. 36003 trivial. 0 not checked. [2018-11-18 16:10:11,060 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:11,060 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 30, 30] total 79 [2018-11-18 16:10:11,061 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:11,061 INFO L459 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-11-18 16:10:11,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-11-18 16:10:11,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=972, Invalid=5190, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:10:11,062 INFO L87 Difference]: Start difference. First operand 1200 states and 1210 transitions. Second operand 65 states. [2018-11-18 16:10:12,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:12,597 INFO L93 Difference]: Finished difference Result 1016 states and 1019 transitions. [2018-11-18 16:10:12,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-11-18 16:10:12,598 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 987 [2018-11-18 16:10:12,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:12,601 INFO L225 Difference]: With dead ends: 1016 [2018-11-18 16:10:12,601 INFO L226 Difference]: Without dead ends: 1007 [2018-11-18 16:10:12,602 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2067 GetRequests, 1919 SyntacticMatches, 15 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6845 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=2880, Invalid=15210, Unknown=0, NotChecked=0, Total=18090 [2018-11-18 16:10:12,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states. [2018-11-18 16:10:12,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1003. [2018-11-18 16:10:12,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1003 states. [2018-11-18 16:10:12,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1003 states to 1003 states and 1006 transitions. [2018-11-18 16:10:12,610 INFO L78 Accepts]: Start accepts. Automaton has 1003 states and 1006 transitions. Word has length 987 [2018-11-18 16:10:12,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:12,610 INFO L480 AbstractCegarLoop]: Abstraction has 1003 states and 1006 transitions. [2018-11-18 16:10:12,610 INFO L481 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-11-18 16:10:12,610 INFO L276 IsEmpty]: Start isEmpty. Operand 1003 states and 1006 transitions. [2018-11-18 16:10:12,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 994 [2018-11-18 16:10:12,617 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:12,617 INFO L375 BasicCegarLoop]: trace histogram [148, 134, 133, 133, 133, 133, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:12,618 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:12,618 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:12,618 INFO L82 PathProgramCache]: Analyzing trace with hash 1266945177, now seen corresponding path program 32 times [2018-11-18 16:10:12,618 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:12,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:12,619 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:12,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:12,619 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:12,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:13,365 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 20214 proven. 1938 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 16:10:13,365 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:13,365 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:13,365 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:13,365 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:13,365 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:13,365 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:13,371 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:13,372 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:13,639 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-11-18 16:10:13,639 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:13,646 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:14,173 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 11422 proven. 675 refuted. 0 times theorem prover too weak. 45961 trivial. 0 not checked. [2018-11-18 16:10:14,173 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:14,920 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 11422 proven. 675 refuted. 0 times theorem prover too weak. 45961 trivial. 0 not checked. [2018-11-18 16:10:14,944 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:14,945 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 18, 18] total 72 [2018-11-18 16:10:14,945 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:14,946 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-11-18 16:10:14,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-11-18 16:10:14,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=872, Invalid=4240, Unknown=0, NotChecked=0, Total=5112 [2018-11-18 16:10:14,946 INFO L87 Difference]: Start difference. First operand 1003 states and 1006 transitions. Second operand 55 states. [2018-11-18 16:10:16,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:16,211 INFO L93 Difference]: Finished difference Result 1128 states and 1134 transitions. [2018-11-18 16:10:16,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 16:10:16,212 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 993 [2018-11-18 16:10:16,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:16,214 INFO L225 Difference]: With dead ends: 1128 [2018-11-18 16:10:16,214 INFO L226 Difference]: Without dead ends: 1128 [2018-11-18 16:10:16,215 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2070 GetRequests, 1953 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2969 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3537, Invalid=10505, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 16:10:16,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1128 states. [2018-11-18 16:10:16,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1128 to 1118. [2018-11-18 16:10:16,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1118 states. [2018-11-18 16:10:16,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1124 transitions. [2018-11-18 16:10:16,223 INFO L78 Accepts]: Start accepts. Automaton has 1118 states and 1124 transitions. Word has length 993 [2018-11-18 16:10:16,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:16,224 INFO L480 AbstractCegarLoop]: Abstraction has 1118 states and 1124 transitions. [2018-11-18 16:10:16,224 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-11-18 16:10:16,224 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1124 transitions. [2018-11-18 16:10:16,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1006 [2018-11-18 16:10:16,229 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:16,229 INFO L375 BasicCegarLoop]: trace histogram [150, 136, 135, 135, 135, 135, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:16,230 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:16,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:16,230 INFO L82 PathProgramCache]: Analyzing trace with hash 1477341529, now seen corresponding path program 33 times [2018-11-18 16:10:16,230 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:16,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:16,231 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:16,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:16,231 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:16,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:16,947 INFO L134 CoverageAnalysis]: Checked inductivity of 59722 backedges. 12992 proven. 726 refuted. 0 times theorem prover too weak. 46004 trivial. 0 not checked. [2018-11-18 16:10:16,947 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:16,947 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:16,947 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:16,947 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:16,947 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:16,948 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:16,959 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:16,959 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:17,118 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:17,118 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:17,128 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:17,865 INFO L134 CoverageAnalysis]: Checked inductivity of 59722 backedges. 12851 proven. 2632 refuted. 0 times theorem prover too weak. 44239 trivial. 0 not checked. [2018-11-18 16:10:17,865 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:18,860 INFO L134 CoverageAnalysis]: Checked inductivity of 59722 backedges. 12851 proven. 2632 refuted. 0 times theorem prover too weak. 44239 trivial. 0 not checked. [2018-11-18 16:10:18,885 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:18,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 39, 39] total 61 [2018-11-18 16:10:18,885 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:18,886 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-18 16:10:18,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-18 16:10:18,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=697, Invalid=2963, Unknown=0, NotChecked=0, Total=3660 [2018-11-18 16:10:18,886 INFO L87 Difference]: Start difference. First operand 1118 states and 1124 transitions. Second operand 58 states. [2018-11-18 16:10:19,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:19,956 INFO L93 Difference]: Finished difference Result 1344 states and 1354 transitions. [2018-11-18 16:10:19,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 16:10:19,957 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 1005 [2018-11-18 16:10:19,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:19,960 INFO L225 Difference]: With dead ends: 1344 [2018-11-18 16:10:19,960 INFO L226 Difference]: Without dead ends: 1344 [2018-11-18 16:10:19,960 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2078 GetRequests, 1951 SyntacticMatches, 35 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2865 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1846, Invalid=6896, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 16:10:19,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1344 states. [2018-11-18 16:10:19,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1344 to 1333. [2018-11-18 16:10:19,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1333 states. [2018-11-18 16:10:19,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1333 states to 1333 states and 1343 transitions. [2018-11-18 16:10:19,971 INFO L78 Accepts]: Start accepts. Automaton has 1333 states and 1343 transitions. Word has length 1005 [2018-11-18 16:10:19,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:19,971 INFO L480 AbstractCegarLoop]: Abstraction has 1333 states and 1343 transitions. [2018-11-18 16:10:19,972 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-18 16:10:19,972 INFO L276 IsEmpty]: Start isEmpty. Operand 1333 states and 1343 transitions. [2018-11-18 16:10:19,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1103 [2018-11-18 16:10:19,978 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:19,979 INFO L375 BasicCegarLoop]: trace histogram [165, 150, 149, 149, 149, 149, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:19,979 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:19,979 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:19,979 INFO L82 PathProgramCache]: Analyzing trace with hash -452376402, now seen corresponding path program 34 times [2018-11-18 16:10:19,979 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:19,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:19,980 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:19,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:19,980 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:20,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:20,816 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 22568 proven. 3357 refuted. 0 times theorem prover too weak. 46603 trivial. 0 not checked. [2018-11-18 16:10:20,816 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:20,816 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:20,816 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:20,816 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:20,816 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:20,816 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:20,824 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:20,824 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:20,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:20,991 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:21,894 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 33678 proven. 574 refuted. 0 times theorem prover too weak. 38276 trivial. 0 not checked. [2018-11-18 16:10:21,895 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:22,077 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification that was a NOOP. DAG size: 52 [2018-11-18 16:10:23,160 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 23838 proven. 1897 refuted. 0 times theorem prover too weak. 46793 trivial. 0 not checked. [2018-11-18 16:10:23,176 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:23,176 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 32, 32] total 84 [2018-11-18 16:10:23,177 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:23,177 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-18 16:10:23,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-18 16:10:23,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1100, Invalid=5872, Unknown=0, NotChecked=0, Total=6972 [2018-11-18 16:10:23,178 INFO L87 Difference]: Start difference. First operand 1333 states and 1343 transitions. Second operand 69 states. [2018-11-18 16:10:24,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:24,908 INFO L93 Difference]: Finished difference Result 1131 states and 1134 transitions. [2018-11-18 16:10:24,909 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 16:10:24,909 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1102 [2018-11-18 16:10:24,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:24,911 INFO L225 Difference]: With dead ends: 1131 [2018-11-18 16:10:24,912 INFO L226 Difference]: Without dead ends: 1122 [2018-11-18 16:10:24,913 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2303 GetRequests, 2145 SyntacticMatches, 16 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7860 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=3270, Invalid=17322, Unknown=0, NotChecked=0, Total=20592 [2018-11-18 16:10:24,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1122 states. [2018-11-18 16:10:24,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1122 to 1118. [2018-11-18 16:10:24,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1118 states. [2018-11-18 16:10:24,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1121 transitions. [2018-11-18 16:10:24,921 INFO L78 Accepts]: Start accepts. Automaton has 1118 states and 1121 transitions. Word has length 1102 [2018-11-18 16:10:24,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:24,922 INFO L480 AbstractCegarLoop]: Abstraction has 1118 states and 1121 transitions. [2018-11-18 16:10:24,922 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-18 16:10:24,922 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1121 transitions. [2018-11-18 16:10:24,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1109 [2018-11-18 16:10:24,930 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:24,931 INFO L375 BasicCegarLoop]: trace histogram [166, 151, 150, 150, 150, 150, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:24,931 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:24,931 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:24,931 INFO L82 PathProgramCache]: Analyzing trace with hash 505336486, now seen corresponding path program 35 times [2018-11-18 16:10:24,931 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:24,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:24,932 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:24,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:24,932 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:25,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:25,824 INFO L134 CoverageAnalysis]: Checked inductivity of 73455 backedges. 24547 proven. 2211 refuted. 0 times theorem prover too weak. 46697 trivial. 0 not checked. [2018-11-18 16:10:25,825 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:25,825 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:25,825 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:25,825 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:25,825 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:25,825 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:25,835 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:25,835 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:26,108 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-11-18 16:10:26,108 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:26,115 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:26,785 INFO L134 CoverageAnalysis]: Checked inductivity of 73455 backedges. 13776 proven. 768 refuted. 0 times theorem prover too weak. 58911 trivial. 0 not checked. [2018-11-18 16:10:26,785 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:27,577 INFO L134 CoverageAnalysis]: Checked inductivity of 73455 backedges. 13776 proven. 768 refuted. 0 times theorem prover too weak. 58911 trivial. 0 not checked. [2018-11-18 16:10:27,592 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:27,593 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 19, 19] total 75 [2018-11-18 16:10:27,593 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:27,593 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-18 16:10:27,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-18 16:10:27,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=940, Invalid=4610, Unknown=0, NotChecked=0, Total=5550 [2018-11-18 16:10:27,594 INFO L87 Difference]: Start difference. First operand 1118 states and 1121 transitions. Second operand 58 states. [2018-11-18 16:10:29,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:29,239 INFO L93 Difference]: Finished difference Result 1249 states and 1255 transitions. [2018-11-18 16:10:29,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-11-18 16:10:29,239 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 1108 [2018-11-18 16:10:29,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:29,242 INFO L225 Difference]: With dead ends: 1249 [2018-11-18 16:10:29,242 INFO L226 Difference]: Without dead ends: 1249 [2018-11-18 16:10:29,243 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2305 GetRequests, 2181 SyntacticMatches, 1 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3364 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3891, Invalid=11609, Unknown=0, NotChecked=0, Total=15500 [2018-11-18 16:10:29,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1249 states. [2018-11-18 16:10:29,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1249 to 1239. [2018-11-18 16:10:29,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1239 states. [2018-11-18 16:10:29,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1239 states to 1239 states and 1245 transitions. [2018-11-18 16:10:29,251 INFO L78 Accepts]: Start accepts. Automaton has 1239 states and 1245 transitions. Word has length 1108 [2018-11-18 16:10:29,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:29,251 INFO L480 AbstractCegarLoop]: Abstraction has 1239 states and 1245 transitions. [2018-11-18 16:10:29,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-18 16:10:29,251 INFO L276 IsEmpty]: Start isEmpty. Operand 1239 states and 1245 transitions. [2018-11-18 16:10:29,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1121 [2018-11-18 16:10:29,258 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:29,258 INFO L375 BasicCegarLoop]: trace histogram [168, 153, 152, 152, 152, 152, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:29,258 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:29,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:29,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1852755942, now seen corresponding path program 36 times [2018-11-18 16:10:29,259 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:29,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:29,259 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:29,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:29,259 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:29,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:30,052 INFO L134 CoverageAnalysis]: Checked inductivity of 75327 backedges. 15547 proven. 830 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-11-18 16:10:30,052 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:30,052 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:30,053 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:30,053 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:30,053 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:30,053 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:30,059 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:30,059 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:30,219 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:30,219 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:30,228 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:31,605 INFO L134 CoverageAnalysis]: Checked inductivity of 75327 backedges. 15398 proven. 2977 refuted. 0 times theorem prover too weak. 56952 trivial. 0 not checked. [2018-11-18 16:10:31,605 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:32,416 INFO L134 CoverageAnalysis]: Checked inductivity of 75327 backedges. 15398 proven. 2977 refuted. 0 times theorem prover too weak. 56952 trivial. 0 not checked. [2018-11-18 16:10:32,431 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:32,432 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 41, 41] total 64 [2018-11-18 16:10:32,432 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:32,432 INFO L459 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-11-18 16:10:32,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-11-18 16:10:32,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=772, Invalid=3260, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 16:10:32,433 INFO L87 Difference]: Start difference. First operand 1239 states and 1245 transitions. Second operand 61 states. [2018-11-18 16:10:33,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:33,707 INFO L93 Difference]: Finished difference Result 1477 states and 1487 transitions. [2018-11-18 16:10:33,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-11-18 16:10:33,708 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 1120 [2018-11-18 16:10:33,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:33,710 INFO L225 Difference]: With dead ends: 1477 [2018-11-18 16:10:33,710 INFO L226 Difference]: Without dead ends: 1477 [2018-11-18 16:10:33,711 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2312 GetRequests, 2178 SyntacticMatches, 37 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3181 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2058, Invalid=7644, Unknown=0, NotChecked=0, Total=9702 [2018-11-18 16:10:33,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1477 states. [2018-11-18 16:10:33,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1477 to 1466. [2018-11-18 16:10:33,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1466 states. [2018-11-18 16:10:33,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1466 states to 1466 states and 1476 transitions. [2018-11-18 16:10:33,720 INFO L78 Accepts]: Start accepts. Automaton has 1466 states and 1476 transitions. Word has length 1120 [2018-11-18 16:10:33,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:33,721 INFO L480 AbstractCegarLoop]: Abstraction has 1466 states and 1476 transitions. [2018-11-18 16:10:33,721 INFO L481 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-11-18 16:10:33,721 INFO L276 IsEmpty]: Start isEmpty. Operand 1466 states and 1476 transitions. [2018-11-18 16:10:33,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1224 [2018-11-18 16:10:33,730 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:33,730 INFO L375 BasicCegarLoop]: trace histogram [184, 168, 167, 167, 167, 167, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:33,731 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:33,731 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:33,731 INFO L82 PathProgramCache]: Analyzing trace with hash -166910599, now seen corresponding path program 37 times [2018-11-18 16:10:33,731 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:33,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:33,731 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:33,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:33,731 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:33,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:34,767 INFO L134 CoverageAnalysis]: Checked inductivity of 90667 backedges. 27203 proven. 3820 refuted. 0 times theorem prover too weak. 59644 trivial. 0 not checked. [2018-11-18 16:10:34,767 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:34,768 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:34,768 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:34,768 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:34,768 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:34,768 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:34,773 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:34,774 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:34,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:34,970 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:36,006 INFO L134 CoverageAnalysis]: Checked inductivity of 90667 backedges. 40646 proven. 660 refuted. 0 times theorem prover too weak. 49361 trivial. 0 not checked. [2018-11-18 16:10:36,006 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:37,327 INFO L134 CoverageAnalysis]: Checked inductivity of 90667 backedges. 28661 proven. 2167 refuted. 0 times theorem prover too weak. 59839 trivial. 0 not checked. [2018-11-18 16:10:37,343 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:37,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 34, 34] total 89 [2018-11-18 16:10:37,344 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:37,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 16:10:37,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 16:10:37,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1236, Invalid=6596, Unknown=0, NotChecked=0, Total=7832 [2018-11-18 16:10:37,345 INFO L87 Difference]: Start difference. First operand 1466 states and 1476 transitions. Second operand 73 states. [2018-11-18 16:10:39,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:39,203 INFO L93 Difference]: Finished difference Result 1252 states and 1255 transitions. [2018-11-18 16:10:39,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-11-18 16:10:39,204 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1223 [2018-11-18 16:10:39,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:39,207 INFO L225 Difference]: With dead ends: 1252 [2018-11-18 16:10:39,207 INFO L226 Difference]: Without dead ends: 1243 [2018-11-18 16:10:39,208 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2551 GetRequests, 2383 SyntacticMatches, 17 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8945 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=3685, Invalid=19571, Unknown=0, NotChecked=0, Total=23256 [2018-11-18 16:10:39,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1243 states. [2018-11-18 16:10:39,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1243 to 1239. [2018-11-18 16:10:39,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1239 states. [2018-11-18 16:10:39,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1239 states to 1239 states and 1242 transitions. [2018-11-18 16:10:39,216 INFO L78 Accepts]: Start accepts. Automaton has 1239 states and 1242 transitions. Word has length 1223 [2018-11-18 16:10:39,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:39,216 INFO L480 AbstractCegarLoop]: Abstraction has 1239 states and 1242 transitions. [2018-11-18 16:10:39,216 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 16:10:39,216 INFO L276 IsEmpty]: Start isEmpty. Operand 1239 states and 1242 transitions. [2018-11-18 16:10:39,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1230 [2018-11-18 16:10:39,226 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:39,226 INFO L375 BasicCegarLoop]: trace histogram [185, 169, 168, 168, 168, 168, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:39,227 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:39,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:39,227 INFO L82 PathProgramCache]: Analyzing trace with hash -2103351503, now seen corresponding path program 38 times [2018-11-18 16:10:39,227 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:39,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:39,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:39,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:39,228 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:39,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:40,267 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 29457 proven. 2502 refuted. 0 times theorem prover too weak. 59745 trivial. 0 not checked. [2018-11-18 16:10:40,267 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:40,267 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:40,267 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:40,267 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:40,267 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:40,267 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:40,278 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:40,278 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:40,553 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-11-18 16:10:40,553 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:40,565 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:41,393 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 28706 proven. 2485 refuted. 0 times theorem prover too weak. 60513 trivial. 0 not checked. [2018-11-18 16:10:41,393 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:42,694 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 28624 proven. 2567 refuted. 0 times theorem prover too weak. 60513 trivial. 0 not checked. [2018-11-18 16:10:42,719 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:42,720 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 26, 26] total 87 [2018-11-18 16:10:42,720 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:42,721 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-18 16:10:42,721 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-18 16:10:42,722 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1561, Invalid=5921, Unknown=0, NotChecked=0, Total=7482 [2018-11-18 16:10:42,722 INFO L87 Difference]: Start difference. First operand 1239 states and 1242 transitions. Second operand 62 states. [2018-11-18 16:10:44,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:44,103 INFO L93 Difference]: Finished difference Result 1367 states and 1372 transitions. [2018-11-18 16:10:44,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-18 16:10:44,104 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1229 [2018-11-18 16:10:44,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:44,107 INFO L225 Difference]: With dead ends: 1367 [2018-11-18 16:10:44,107 INFO L226 Difference]: Without dead ends: 1367 [2018-11-18 16:10:44,108 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2551 GetRequests, 2413 SyntacticMatches, 1 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5529 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=5021, Invalid=14161, Unknown=0, NotChecked=0, Total=19182 [2018-11-18 16:10:44,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1367 states. [2018-11-18 16:10:44,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1367 to 1360. [2018-11-18 16:10:44,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1360 states. [2018-11-18 16:10:44,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1360 states to 1360 states and 1365 transitions. [2018-11-18 16:10:44,116 INFO L78 Accepts]: Start accepts. Automaton has 1360 states and 1365 transitions. Word has length 1229 [2018-11-18 16:10:44,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:44,117 INFO L480 AbstractCegarLoop]: Abstraction has 1360 states and 1365 transitions. [2018-11-18 16:10:44,117 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-18 16:10:44,117 INFO L276 IsEmpty]: Start isEmpty. Operand 1360 states and 1365 transitions. [2018-11-18 16:10:44,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1236 [2018-11-18 16:10:44,124 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:44,125 INFO L375 BasicCegarLoop]: trace histogram [186, 170, 169, 169, 169, 169, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:44,125 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:44,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:44,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1495359431, now seen corresponding path program 39 times [2018-11-18 16:10:44,125 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:44,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:44,126 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:44,126 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:44,126 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:44,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:44,781 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16634 proven. 905 refuted. 0 times theorem prover too weak. 75208 trivial. 0 not checked. [2018-11-18 16:10:44,782 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:44,782 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:44,782 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:44,782 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:44,782 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:44,782 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:44,791 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:10:44,791 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:10:45,799 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:10:45,799 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:45,814 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:46,451 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-18 16:10:46,451 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:47,250 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-18 16:10:47,268 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:47,269 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19, 19] total 59 [2018-11-18 16:10:47,269 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:47,269 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-11-18 16:10:47,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-11-18 16:10:47,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=606, Invalid=2934, Unknown=0, NotChecked=0, Total=3540 [2018-11-18 16:10:47,270 INFO L87 Difference]: Start difference. First operand 1360 states and 1365 transitions. Second operand 42 states. [2018-11-18 16:10:48,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:48,747 INFO L93 Difference]: Finished difference Result 1626 states and 1637 transitions. [2018-11-18 16:10:48,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-18 16:10:48,747 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1235 [2018-11-18 16:10:48,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:48,751 INFO L225 Difference]: With dead ends: 1626 [2018-11-18 16:10:48,751 INFO L226 Difference]: Without dead ends: 1626 [2018-11-18 16:10:48,751 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2514 GetRequests, 2434 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1603 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1176, Invalid=5466, Unknown=0, NotChecked=0, Total=6642 [2018-11-18 16:10:48,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states. [2018-11-18 16:10:48,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1599. [2018-11-18 16:10:48,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2018-11-18 16:10:48,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 1609 transitions. [2018-11-18 16:10:48,765 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 1609 transitions. Word has length 1235 [2018-11-18 16:10:48,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:48,765 INFO L480 AbstractCegarLoop]: Abstraction has 1599 states and 1609 transitions. [2018-11-18 16:10:48,765 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-11-18 16:10:48,766 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 1609 transitions. [2018-11-18 16:10:48,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1351 [2018-11-18 16:10:48,777 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:48,778 INFO L375 BasicCegarLoop]: trace histogram [204, 187, 186, 186, 186, 186, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:48,778 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:48,778 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:48,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1968183046, now seen corresponding path program 40 times [2018-11-18 16:10:48,778 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:48,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:48,779 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:48,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:48,779 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:48,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:50,048 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 32433 proven. 4313 refuted. 0 times theorem prover too weak. 75236 trivial. 0 not checked. [2018-11-18 16:10:50,049 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:50,049 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:50,049 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:50,049 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:50,049 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:50,049 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:50,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:50,055 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:10:50,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:50,274 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:51,485 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 48510 proven. 752 refuted. 0 times theorem prover too weak. 62720 trivial. 0 not checked. [2018-11-18 16:10:51,485 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:53,003 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 34092 proven. 2455 refuted. 0 times theorem prover too weak. 75435 trivial. 0 not checked. [2018-11-18 16:10:53,019 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:53,020 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 36, 36] total 94 [2018-11-18 16:10:53,020 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:53,021 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-11-18 16:10:53,021 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-11-18 16:10:53,021 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1380, Invalid=7362, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 16:10:53,021 INFO L87 Difference]: Start difference. First operand 1599 states and 1609 transitions. Second operand 77 states. [2018-11-18 16:10:54,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:54,790 INFO L93 Difference]: Finished difference Result 1379 states and 1382 transitions. [2018-11-18 16:10:54,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-11-18 16:10:54,791 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1350 [2018-11-18 16:10:54,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:54,794 INFO L225 Difference]: With dead ends: 1379 [2018-11-18 16:10:54,795 INFO L226 Difference]: Without dead ends: 1370 [2018-11-18 16:10:54,796 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2811 GetRequests, 2633 SyntacticMatches, 18 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10100 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=4125, Invalid=21957, Unknown=0, NotChecked=0, Total=26082 [2018-11-18 16:10:54,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1370 states. [2018-11-18 16:10:54,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1370 to 1366. [2018-11-18 16:10:54,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1366 states. [2018-11-18 16:10:54,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 1369 transitions. [2018-11-18 16:10:54,809 INFO L78 Accepts]: Start accepts. Automaton has 1366 states and 1369 transitions. Word has length 1350 [2018-11-18 16:10:54,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:54,810 INFO L480 AbstractCegarLoop]: Abstraction has 1366 states and 1369 transitions. [2018-11-18 16:10:54,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-11-18 16:10:54,810 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 1369 transitions. [2018-11-18 16:10:54,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1357 [2018-11-18 16:10:54,827 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:54,828 INFO L375 BasicCegarLoop]: trace histogram [205, 188, 187, 187, 187, 187, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:54,828 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:54,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:54,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1169819906, now seen corresponding path program 41 times [2018-11-18 16:10:54,829 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:54,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:54,829 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:10:54,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:54,829 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:10:54,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:10:56,007 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 34980 proven. 2811 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-18 16:10:56,007 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:56,008 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:10:56,008 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:10:56,008 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:10:56,008 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:10:56,008 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:10:56,017 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:10:56,017 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:10:56,365 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-11-18 16:10:56,365 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:10:56,375 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:10:57,272 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 19405 proven. 972 refuted. 0 times theorem prover too weak. 92758 trivial. 0 not checked. [2018-11-18 16:10:57,273 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:10:58,267 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 19405 proven. 972 refuted. 0 times theorem prover too weak. 92758 trivial. 0 not checked. [2018-11-18 16:10:58,283 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:10:58,284 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 21, 21] total 79 [2018-11-18 16:10:58,284 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:10:58,284 INFO L459 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-11-18 16:10:58,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-11-18 16:10:58,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1012, Invalid=5150, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:10:58,285 INFO L87 Difference]: Start difference. First operand 1366 states and 1369 transitions. Second operand 64 states. [2018-11-18 16:10:59,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:10:59,969 INFO L93 Difference]: Finished difference Result 1509 states and 1515 transitions. [2018-11-18 16:10:59,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-18 16:10:59,971 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1356 [2018-11-18 16:10:59,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:10:59,974 INFO L225 Difference]: With dead ends: 1509 [2018-11-18 16:10:59,974 INFO L226 Difference]: Without dead ends: 1509 [2018-11-18 16:10:59,975 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2811 GetRequests, 2673 SyntacticMatches, 5 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4245 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=4465, Invalid=13625, Unknown=0, NotChecked=0, Total=18090 [2018-11-18 16:10:59,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states. [2018-11-18 16:10:59,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1499. [2018-11-18 16:10:59,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1499 states. [2018-11-18 16:10:59,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 1505 transitions. [2018-11-18 16:10:59,984 INFO L78 Accepts]: Start accepts. Automaton has 1499 states and 1505 transitions. Word has length 1356 [2018-11-18 16:10:59,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:10:59,984 INFO L480 AbstractCegarLoop]: Abstraction has 1499 states and 1505 transitions. [2018-11-18 16:10:59,984 INFO L481 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-11-18 16:10:59,984 INFO L276 IsEmpty]: Start isEmpty. Operand 1499 states and 1505 transitions. [2018-11-18 16:10:59,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1369 [2018-11-18 16:10:59,992 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:10:59,992 INFO L375 BasicCegarLoop]: trace histogram [207, 190, 189, 189, 189, 189, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:10:59,992 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:10:59,992 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:10:59,992 INFO L82 PathProgramCache]: Analyzing trace with hash 1575991358, now seen corresponding path program 42 times [2018-11-18 16:10:59,992 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:10:59,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:59,993 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:10:59,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:10:59,993 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:00,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:01,035 INFO L134 CoverageAnalysis]: Checked inductivity of 115459 backedges. 21614 proven. 1059 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-11-18 16:11:01,035 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:01,035 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:01,036 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:01,036 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:01,036 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:01,036 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:01,046 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:01,047 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:01,238 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:01,238 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:01,251 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:02,536 INFO L134 CoverageAnalysis]: Checked inductivity of 115459 backedges. 21449 proven. 3730 refuted. 0 times theorem prover too weak. 90280 trivial. 0 not checked. [2018-11-18 16:11:02,537 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:03,582 INFO L134 CoverageAnalysis]: Checked inductivity of 115459 backedges. 21449 proven. 3730 refuted. 0 times theorem prover too weak. 90280 trivial. 0 not checked. [2018-11-18 16:11:03,607 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:03,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 45, 45] total 70 [2018-11-18 16:11:03,608 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:03,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 16:11:03,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 16:11:03,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=934, Invalid=3896, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 16:11:03,609 INFO L87 Difference]: Start difference. First operand 1499 states and 1505 transitions. Second operand 67 states. [2018-11-18 16:11:04,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:04,923 INFO L93 Difference]: Finished difference Result 1761 states and 1771 transitions. [2018-11-18 16:11:04,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-18 16:11:04,924 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1368 [2018-11-18 16:11:04,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:04,928 INFO L225 Difference]: With dead ends: 1761 [2018-11-18 16:11:04,928 INFO L226 Difference]: Without dead ends: 1761 [2018-11-18 16:11:04,929 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2816 GetRequests, 2668 SyntacticMatches, 41 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3861 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2518, Invalid=9254, Unknown=0, NotChecked=0, Total=11772 [2018-11-18 16:11:04,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1761 states. [2018-11-18 16:11:04,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1761 to 1750. [2018-11-18 16:11:04,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1750 states. [2018-11-18 16:11:04,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1750 states to 1750 states and 1760 transitions. [2018-11-18 16:11:04,944 INFO L78 Accepts]: Start accepts. Automaton has 1750 states and 1760 transitions. Word has length 1368 [2018-11-18 16:11:04,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:04,945 INFO L480 AbstractCegarLoop]: Abstraction has 1750 states and 1760 transitions. [2018-11-18 16:11:04,945 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 16:11:04,945 INFO L276 IsEmpty]: Start isEmpty. Operand 1750 states and 1760 transitions. [2018-11-18 16:11:04,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1484 [2018-11-18 16:11:04,959 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:04,959 INFO L375 BasicCegarLoop]: trace histogram [225, 207, 206, 206, 206, 206, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:04,960 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:04,960 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:04,960 INFO L82 PathProgramCache]: Analyzing trace with hash -551408751, now seen corresponding path program 43 times [2018-11-18 16:11:04,960 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:04,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:04,961 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:04,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:04,961 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:05,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:06,404 INFO L134 CoverageAnalysis]: Checked inductivity of 136821 backedges. 38294 proven. 4836 refuted. 0 times theorem prover too weak. 93691 trivial. 0 not checked. [2018-11-18 16:11:06,404 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:06,404 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:06,405 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:06,405 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:06,405 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:06,405 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:06,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:06,411 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:06,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:06,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:08,046 INFO L134 CoverageAnalysis]: Checked inductivity of 136821 backedges. 57324 proven. 850 refuted. 0 times theorem prover too weak. 78647 trivial. 0 not checked. [2018-11-18 16:11:08,046 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:09,729 INFO L134 CoverageAnalysis]: Checked inductivity of 136821 backedges. 40167 proven. 2761 refuted. 0 times theorem prover too weak. 93893 trivial. 0 not checked. [2018-11-18 16:11:09,745 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:09,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 38, 38] total 99 [2018-11-18 16:11:09,746 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:09,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-11-18 16:11:09,748 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-11-18 16:11:09,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1532, Invalid=8170, Unknown=0, NotChecked=0, Total=9702 [2018-11-18 16:11:09,748 INFO L87 Difference]: Start difference. First operand 1750 states and 1760 transitions. Second operand 81 states. [2018-11-18 16:11:11,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:11,832 INFO L93 Difference]: Finished difference Result 1512 states and 1515 transitions. [2018-11-18 16:11:11,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-18 16:11:11,833 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1483 [2018-11-18 16:11:11,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:11,836 INFO L225 Difference]: With dead ends: 1512 [2018-11-18 16:11:11,836 INFO L226 Difference]: Without dead ends: 1503 [2018-11-18 16:11:11,838 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3083 GetRequests, 2895 SyntacticMatches, 19 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11325 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=4590, Invalid=24480, Unknown=0, NotChecked=0, Total=29070 [2018-11-18 16:11:11,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1503 states. [2018-11-18 16:11:11,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1503 to 1499. [2018-11-18 16:11:11,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1499 states. [2018-11-18 16:11:11,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 1502 transitions. [2018-11-18 16:11:11,845 INFO L78 Accepts]: Start accepts. Automaton has 1499 states and 1502 transitions. Word has length 1483 [2018-11-18 16:11:11,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:11,846 INFO L480 AbstractCegarLoop]: Abstraction has 1499 states and 1502 transitions. [2018-11-18 16:11:11,846 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-11-18 16:11:11,846 INFO L276 IsEmpty]: Start isEmpty. Operand 1499 states and 1502 transitions. [2018-11-18 16:11:11,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1490 [2018-11-18 16:11:11,856 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:11,856 INFO L375 BasicCegarLoop]: trace histogram [226, 208, 207, 207, 207, 207, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:11,856 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:11,857 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:11,857 INFO L82 PathProgramCache]: Analyzing trace with hash -1093668023, now seen corresponding path program 44 times [2018-11-18 16:11:11,857 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:11,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:11,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:11,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:11,858 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:11,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:13,235 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 41152 proven. 3138 refuted. 0 times theorem prover too weak. 93806 trivial. 0 not checked. [2018-11-18 16:11:13,235 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:13,235 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:13,236 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:13,236 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:13,236 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:13,236 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:13,245 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:13,245 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:13,632 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-11-18 16:11:13,632 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:13,645 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:14,631 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 22716 proven. 1083 refuted. 0 times theorem prover too weak. 114297 trivial. 0 not checked. [2018-11-18 16:11:14,631 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:15,828 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 22716 proven. 1083 refuted. 0 times theorem prover too weak. 114297 trivial. 0 not checked. [2018-11-18 16:11:15,844 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:15,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 22, 22] total 81 [2018-11-18 16:11:15,845 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:15,846 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 16:11:15,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 16:11:15,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1051, Invalid=5429, Unknown=0, NotChecked=0, Total=6480 [2018-11-18 16:11:15,846 INFO L87 Difference]: Start difference. First operand 1499 states and 1502 transitions. Second operand 67 states. [2018-11-18 16:11:17,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:17,665 INFO L93 Difference]: Finished difference Result 1648 states and 1654 transitions. [2018-11-18 16:11:17,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-18 16:11:17,665 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1489 [2018-11-18 16:11:17,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:17,669 INFO L225 Difference]: With dead ends: 1648 [2018-11-18 16:11:17,669 INFO L226 Difference]: Without dead ends: 1648 [2018-11-18 16:11:17,670 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3082 GetRequests, 2937 SyntacticMatches, 7 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4720 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=4767, Invalid=14693, Unknown=0, NotChecked=0, Total=19460 [2018-11-18 16:11:17,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1648 states. [2018-11-18 16:11:17,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1648 to 1638. [2018-11-18 16:11:17,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1638 states. [2018-11-18 16:11:17,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1638 states to 1638 states and 1644 transitions. [2018-11-18 16:11:17,681 INFO L78 Accepts]: Start accepts. Automaton has 1638 states and 1644 transitions. Word has length 1489 [2018-11-18 16:11:17,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:17,682 INFO L480 AbstractCegarLoop]: Abstraction has 1638 states and 1644 transitions. [2018-11-18 16:11:17,682 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 16:11:17,682 INFO L276 IsEmpty]: Start isEmpty. Operand 1638 states and 1644 transitions. [2018-11-18 16:11:17,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1502 [2018-11-18 16:11:17,696 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:17,696 INFO L375 BasicCegarLoop]: trace histogram [228, 210, 209, 209, 209, 209, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:17,697 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:17,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:17,697 INFO L82 PathProgramCache]: Analyzing trace with hash -384770039, now seen corresponding path program 45 times [2018-11-18 16:11:17,697 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:17,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:17,698 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:17,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:17,698 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:17,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:18,929 INFO L134 CoverageAnalysis]: Checked inductivity of 140664 backedges. 25162 proven. 1184 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-11-18 16:11:18,929 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:18,929 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:18,929 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:18,929 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:18,929 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:18,929 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:18,940 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:18,941 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:19,142 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:19,142 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:19,157 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:20,499 INFO L134 CoverageAnalysis]: Checked inductivity of 140664 backedges. 24989 proven. 4138 refuted. 0 times theorem prover too weak. 111537 trivial. 0 not checked. [2018-11-18 16:11:20,499 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:21,706 INFO L134 CoverageAnalysis]: Checked inductivity of 140664 backedges. 24989 proven. 4138 refuted. 0 times theorem prover too weak. 111537 trivial. 0 not checked. [2018-11-18 16:11:21,731 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:21,732 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 47, 47] total 73 [2018-11-18 16:11:21,732 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:21,733 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-18 16:11:21,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-18 16:11:21,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1021, Invalid=4235, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 16:11:21,734 INFO L87 Difference]: Start difference. First operand 1638 states and 1644 transitions. Second operand 70 states. [2018-11-18 16:11:23,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:23,413 INFO L93 Difference]: Finished difference Result 1912 states and 1922 transitions. [2018-11-18 16:11:23,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-18 16:11:23,415 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1501 [2018-11-18 16:11:23,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:23,418 INFO L225 Difference]: With dead ends: 1912 [2018-11-18 16:11:23,418 INFO L226 Difference]: Without dead ends: 1912 [2018-11-18 16:11:23,419 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3086 GetRequests, 2931 SyntacticMatches, 43 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4225 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2766, Invalid=10116, Unknown=0, NotChecked=0, Total=12882 [2018-11-18 16:11:23,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1912 states. [2018-11-18 16:11:23,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1912 to 1901. [2018-11-18 16:11:23,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1901 states. [2018-11-18 16:11:23,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1901 states to 1901 states and 1911 transitions. [2018-11-18 16:11:23,433 INFO L78 Accepts]: Start accepts. Automaton has 1901 states and 1911 transitions. Word has length 1501 [2018-11-18 16:11:23,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:23,434 INFO L480 AbstractCegarLoop]: Abstraction has 1901 states and 1911 transitions. [2018-11-18 16:11:23,434 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-18 16:11:23,434 INFO L276 IsEmpty]: Start isEmpty. Operand 1901 states and 1911 transitions. [2018-11-18 16:11:23,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1623 [2018-11-18 16:11:23,455 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:23,455 INFO L375 BasicCegarLoop]: trace histogram [247, 228, 227, 227, 227, 227, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:23,455 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:23,455 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:23,456 INFO L82 PathProgramCache]: Analyzing trace with hash -2138012706, now seen corresponding path program 46 times [2018-11-18 16:11:23,456 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:23,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:23,456 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:23,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:23,457 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:23,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:25,163 INFO L134 CoverageAnalysis]: Checked inductivity of 165550 backedges. 44822 proven. 5389 refuted. 0 times theorem prover too weak. 115339 trivial. 0 not checked. [2018-11-18 16:11:25,163 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:25,163 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:25,163 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:25,163 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:25,163 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:25,163 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:25,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:25,169 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:25,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:25,441 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:27,040 INFO L134 CoverageAnalysis]: Checked inductivity of 165550 backedges. 67142 proven. 954 refuted. 0 times theorem prover too weak. 97454 trivial. 0 not checked. [2018-11-18 16:11:27,040 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:28,903 INFO L134 CoverageAnalysis]: Checked inductivity of 165550 backedges. 46922 proven. 3085 refuted. 0 times theorem prover too weak. 115543 trivial. 0 not checked. [2018-11-18 16:11:28,929 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:28,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 40, 40] total 104 [2018-11-18 16:11:28,930 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:28,930 INFO L459 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-11-18 16:11:28,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-11-18 16:11:28,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1692, Invalid=9020, Unknown=0, NotChecked=0, Total=10712 [2018-11-18 16:11:28,931 INFO L87 Difference]: Start difference. First operand 1901 states and 1911 transitions. Second operand 85 states. [2018-11-18 16:11:31,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:31,216 INFO L93 Difference]: Finished difference Result 1651 states and 1654 transitions. [2018-11-18 16:11:31,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-11-18 16:11:31,217 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1622 [2018-11-18 16:11:31,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:31,219 INFO L225 Difference]: With dead ends: 1651 [2018-11-18 16:11:31,219 INFO L226 Difference]: Without dead ends: 1642 [2018-11-18 16:11:31,221 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3367 GetRequests, 3169 SyntacticMatches, 20 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12620 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=5080, Invalid=27140, Unknown=0, NotChecked=0, Total=32220 [2018-11-18 16:11:31,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1642 states. [2018-11-18 16:11:31,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1642 to 1638. [2018-11-18 16:11:31,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1638 states. [2018-11-18 16:11:31,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1638 states to 1638 states and 1641 transitions. [2018-11-18 16:11:31,233 INFO L78 Accepts]: Start accepts. Automaton has 1638 states and 1641 transitions. Word has length 1622 [2018-11-18 16:11:31,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:31,234 INFO L480 AbstractCegarLoop]: Abstraction has 1638 states and 1641 transitions. [2018-11-18 16:11:31,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-11-18 16:11:31,234 INFO L276 IsEmpty]: Start isEmpty. Operand 1638 states and 1641 transitions. [2018-11-18 16:11:31,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1629 [2018-11-18 16:11:31,257 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:31,257 INFO L375 BasicCegarLoop]: trace histogram [248, 229, 228, 228, 228, 228, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:31,257 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:31,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:31,258 INFO L82 PathProgramCache]: Analyzing trace with hash -1283860010, now seen corresponding path program 47 times [2018-11-18 16:11:31,258 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:31,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:31,258 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:31,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:31,259 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:31,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:33,076 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 48009 proven. 3483 refuted. 0 times theorem prover too weak. 115461 trivial. 0 not checked. [2018-11-18 16:11:33,076 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:33,076 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:33,076 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:33,076 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:33,076 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:33,076 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:33,082 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:33,082 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:33,509 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-11-18 16:11:33,509 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:33,522 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:34,623 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 26382 proven. 1200 refuted. 0 times theorem prover too weak. 139371 trivial. 0 not checked. [2018-11-18 16:11:34,623 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:35,927 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 26382 proven. 1200 refuted. 0 times theorem prover too weak. 139371 trivial. 0 not checked. [2018-11-18 16:11:35,952 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:35,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 23, 23] total 83 [2018-11-18 16:11:35,953 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:35,954 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-18 16:11:35,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-18 16:11:35,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1092, Invalid=5714, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 16:11:35,955 INFO L87 Difference]: Start difference. First operand 1638 states and 1641 transitions. Second operand 70 states. [2018-11-18 16:11:38,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:38,003 INFO L93 Difference]: Finished difference Result 1793 states and 1799 transitions. [2018-11-18 16:11:38,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 16:11:38,004 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1628 [2018-11-18 16:11:38,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:38,008 INFO L225 Difference]: With dead ends: 1793 [2018-11-18 16:11:38,008 INFO L226 Difference]: Without dead ends: 1793 [2018-11-18 16:11:38,009 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3365 GetRequests, 3213 SyntacticMatches, 9 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5218 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=5079, Invalid=15801, Unknown=0, NotChecked=0, Total=20880 [2018-11-18 16:11:38,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1793 states. [2018-11-18 16:11:38,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1793 to 1783. [2018-11-18 16:11:38,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1783 states. [2018-11-18 16:11:38,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1783 states to 1783 states and 1789 transitions. [2018-11-18 16:11:38,024 INFO L78 Accepts]: Start accepts. Automaton has 1783 states and 1789 transitions. Word has length 1628 [2018-11-18 16:11:38,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:38,025 INFO L480 AbstractCegarLoop]: Abstraction has 1783 states and 1789 transitions. [2018-11-18 16:11:38,025 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-18 16:11:38,025 INFO L276 IsEmpty]: Start isEmpty. Operand 1783 states and 1789 transitions. [2018-11-18 16:11:38,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1641 [2018-11-18 16:11:38,048 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:38,049 INFO L375 BasicCegarLoop]: trace histogram [250, 231, 230, 230, 230, 230, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:38,051 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:38,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:38,052 INFO L82 PathProgramCache]: Analyzing trace with hash -456679658, now seen corresponding path program 48 times [2018-11-18 16:11:38,052 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:38,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:38,052 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:38,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:38,052 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:38,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:39,612 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 29077 proven. 1316 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-18 16:11:39,612 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:39,613 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:39,613 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:39,613 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:39,613 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:39,613 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:39,623 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:11:39,623 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:11:39,835 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:11:39,835 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:39,847 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:41,366 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 28896 proven. 4567 refuted. 0 times theorem prover too weak. 136314 trivial. 0 not checked. [2018-11-18 16:11:41,366 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:42,732 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 28896 proven. 4567 refuted. 0 times theorem prover too weak. 136314 trivial. 0 not checked. [2018-11-18 16:11:42,748 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:42,749 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 49, 49] total 76 [2018-11-18 16:11:42,749 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:42,749 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 16:11:42,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 16:11:42,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1112, Invalid=4588, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 16:11:42,750 INFO L87 Difference]: Start difference. First operand 1783 states and 1789 transitions. Second operand 73 states. [2018-11-18 16:11:44,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:44,398 INFO L93 Difference]: Finished difference Result 2069 states and 2079 transitions. [2018-11-18 16:11:44,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 16:11:44,399 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1640 [2018-11-18 16:11:44,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:44,402 INFO L225 Difference]: With dead ends: 2069 [2018-11-18 16:11:44,402 INFO L226 Difference]: Without dead ends: 2069 [2018-11-18 16:11:44,404 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3368 GetRequests, 3206 SyntacticMatches, 45 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4605 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3026, Invalid=11016, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 16:11:44,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2069 states. [2018-11-18 16:11:44,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2069 to 2058. [2018-11-18 16:11:44,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2058 states. [2018-11-18 16:11:44,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2058 states to 2058 states and 2068 transitions. [2018-11-18 16:11:44,419 INFO L78 Accepts]: Start accepts. Automaton has 2058 states and 2068 transitions. Word has length 1640 [2018-11-18 16:11:44,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:44,420 INFO L480 AbstractCegarLoop]: Abstraction has 2058 states and 2068 transitions. [2018-11-18 16:11:44,420 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 16:11:44,421 INFO L276 IsEmpty]: Start isEmpty. Operand 2058 states and 2068 transitions. [2018-11-18 16:11:44,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1768 [2018-11-18 16:11:44,439 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:44,440 INFO L375 BasicCegarLoop]: trace histogram [270, 250, 249, 249, 249, 249, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:44,440 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:44,440 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:44,441 INFO L82 PathProgramCache]: Analyzing trace with hash -496614615, now seen corresponding path program 49 times [2018-11-18 16:11:44,441 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:44,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:44,441 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:44,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:44,441 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:44,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:46,366 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 52053 proven. 5972 refuted. 0 times theorem prover too weak. 140528 trivial. 0 not checked. [2018-11-18 16:11:46,366 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:46,366 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:46,366 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:46,366 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:46,366 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:46,366 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:46,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:46,372 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:11:46,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:46,652 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:48,428 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 78018 proven. 1064 refuted. 0 times theorem prover too weak. 119471 trivial. 0 not checked. [2018-11-18 16:11:48,428 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:50,529 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 54393 proven. 3427 refuted. 0 times theorem prover too weak. 140733 trivial. 0 not checked. [2018-11-18 16:11:50,559 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:50,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 42, 42] total 109 [2018-11-18 16:11:50,560 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:50,561 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-11-18 16:11:50,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-11-18 16:11:50,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1860, Invalid=9912, Unknown=0, NotChecked=0, Total=11772 [2018-11-18 16:11:50,562 INFO L87 Difference]: Start difference. First operand 2058 states and 2068 transitions. Second operand 89 states. [2018-11-18 16:11:52,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:52,739 INFO L93 Difference]: Finished difference Result 1796 states and 1799 transitions. [2018-11-18 16:11:52,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2018-11-18 16:11:52,741 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 1767 [2018-11-18 16:11:52,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:52,744 INFO L225 Difference]: With dead ends: 1796 [2018-11-18 16:11:52,744 INFO L226 Difference]: Without dead ends: 1787 [2018-11-18 16:11:52,746 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3663 GetRequests, 3455 SyntacticMatches, 21 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13985 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=5595, Invalid=29937, Unknown=0, NotChecked=0, Total=35532 [2018-11-18 16:11:52,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1787 states. [2018-11-18 16:11:52,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1787 to 1783. [2018-11-18 16:11:52,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1783 states. [2018-11-18 16:11:52,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1783 states to 1783 states and 1786 transitions. [2018-11-18 16:11:52,755 INFO L78 Accepts]: Start accepts. Automaton has 1783 states and 1786 transitions. Word has length 1767 [2018-11-18 16:11:52,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:52,756 INFO L480 AbstractCegarLoop]: Abstraction has 1783 states and 1786 transitions. [2018-11-18 16:11:52,756 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-11-18 16:11:52,756 INFO L276 IsEmpty]: Start isEmpty. Operand 1783 states and 1786 transitions. [2018-11-18 16:11:52,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1774 [2018-11-18 16:11:52,769 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:52,769 INFO L375 BasicCegarLoop]: trace histogram [271, 251, 250, 250, 250, 250, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:52,770 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:52,770 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:52,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1726058271, now seen corresponding path program 50 times [2018-11-18 16:11:52,770 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:52,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:52,770 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:11:52,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:52,770 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:52,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:11:54,479 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 55587 proven. 3846 refuted. 0 times theorem prover too weak. 140657 trivial. 0 not checked. [2018-11-18 16:11:54,480 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:54,480 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:11:54,480 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:11:54,480 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:11:54,480 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:11:54,480 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:11:54,490 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:11:54,490 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:11:54,931 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-11-18 16:11:54,932 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:11:54,942 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:11:56,300 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 30421 proven. 1323 refuted. 0 times theorem prover too weak. 168346 trivial. 0 not checked. [2018-11-18 16:11:56,300 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:11:57,712 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 30421 proven. 1323 refuted. 0 times theorem prover too weak. 168346 trivial. 0 not checked. [2018-11-18 16:11:57,728 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:11:57,729 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 24, 24] total 85 [2018-11-18 16:11:57,729 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:11:57,730 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 16:11:57,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 16:11:57,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1135, Invalid=6005, Unknown=0, NotChecked=0, Total=7140 [2018-11-18 16:11:57,731 INFO L87 Difference]: Start difference. First operand 1783 states and 1786 transitions. Second operand 73 states. [2018-11-18 16:11:59,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:11:59,818 INFO L93 Difference]: Finished difference Result 1944 states and 1950 transitions. [2018-11-18 16:11:59,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-11-18 16:11:59,819 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1773 [2018-11-18 16:11:59,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:11:59,823 INFO L225 Difference]: With dead ends: 1944 [2018-11-18 16:11:59,823 INFO L226 Difference]: Without dead ends: 1944 [2018-11-18 16:11:59,824 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3660 GetRequests, 3501 SyntacticMatches, 11 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5739 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=5401, Invalid=16949, Unknown=0, NotChecked=0, Total=22350 [2018-11-18 16:11:59,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1944 states. [2018-11-18 16:11:59,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1944 to 1934. [2018-11-18 16:11:59,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1934 states. [2018-11-18 16:11:59,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1934 states to 1934 states and 1940 transitions. [2018-11-18 16:11:59,834 INFO L78 Accepts]: Start accepts. Automaton has 1934 states and 1940 transitions. Word has length 1773 [2018-11-18 16:11:59,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:11:59,836 INFO L480 AbstractCegarLoop]: Abstraction has 1934 states and 1940 transitions. [2018-11-18 16:11:59,836 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 16:11:59,836 INFO L276 IsEmpty]: Start isEmpty. Operand 1934 states and 1940 transitions. [2018-11-18 16:11:59,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1786 [2018-11-18 16:11:59,850 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:11:59,850 INFO L375 BasicCegarLoop]: trace histogram [273, 253, 252, 252, 252, 252, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:11:59,850 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:11:59,851 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:11:59,851 INFO L82 PathProgramCache]: Analyzing trace with hash 1995129249, now seen corresponding path program 51 times [2018-11-18 16:11:59,851 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:11:59,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:59,852 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:11:59,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:11:59,852 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:11:59,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:01,423 INFO L134 CoverageAnalysis]: Checked inductivity of 203182 backedges. 33377 proven. 1455 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-11-18 16:12:01,423 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:01,423 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:01,423 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:01,423 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:01,424 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:01,424 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:01,432 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:12:01,432 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:12:01,680 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:12:01,680 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:01,693 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:03,383 INFO L134 CoverageAnalysis]: Checked inductivity of 203182 backedges. 33188 proven. 5017 refuted. 0 times theorem prover too weak. 164977 trivial. 0 not checked. [2018-11-18 16:12:03,383 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:04,898 INFO L134 CoverageAnalysis]: Checked inductivity of 203182 backedges. 33188 proven. 5017 refuted. 0 times theorem prover too weak. 164977 trivial. 0 not checked. [2018-11-18 16:12:04,914 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:04,915 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 51, 51] total 79 [2018-11-18 16:12:04,915 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:04,915 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-11-18 16:12:04,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-11-18 16:12:04,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1207, Invalid=4955, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 16:12:04,916 INFO L87 Difference]: Start difference. First operand 1934 states and 1940 transitions. Second operand 76 states. [2018-11-18 16:12:06,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:06,359 INFO L93 Difference]: Finished difference Result 2232 states and 2242 transitions. [2018-11-18 16:12:06,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-11-18 16:12:06,360 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1785 [2018-11-18 16:12:06,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:06,363 INFO L225 Difference]: With dead ends: 2232 [2018-11-18 16:12:06,364 INFO L226 Difference]: Without dead ends: 2232 [2018-11-18 16:12:06,365 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3662 GetRequests, 3493 SyntacticMatches, 47 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5001 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=3298, Invalid=11954, Unknown=0, NotChecked=0, Total=15252 [2018-11-18 16:12:06,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2232 states. [2018-11-18 16:12:06,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2232 to 2221. [2018-11-18 16:12:06,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2221 states. [2018-11-18 16:12:06,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2221 states to 2221 states and 2231 transitions. [2018-11-18 16:12:06,375 INFO L78 Accepts]: Start accepts. Automaton has 2221 states and 2231 transitions. Word has length 1785 [2018-11-18 16:12:06,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:06,375 INFO L480 AbstractCegarLoop]: Abstraction has 2221 states and 2231 transitions. [2018-11-18 16:12:06,375 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-11-18 16:12:06,375 INFO L276 IsEmpty]: Start isEmpty. Operand 2221 states and 2231 transitions. [2018-11-18 16:12:06,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1919 [2018-11-18 16:12:06,389 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:06,389 INFO L375 BasicCegarLoop]: trace histogram [294, 273, 272, 272, 272, 272, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:06,389 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:06,389 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:06,390 INFO L82 PathProgramCache]: Analyzing trace with hash -1443852490, now seen corresponding path program 52 times [2018-11-18 16:12:06,390 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:06,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:06,390 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:06,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:06,390 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:06,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:08,287 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 60023 proven. 6585 refuted. 0 times theorem prover too weak. 169624 trivial. 0 not checked. [2018-11-18 16:12:08,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:08,287 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:08,287 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:08,287 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:08,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:08,287 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:08,294 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:08,294 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:12:08,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:08,686 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:10,719 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 90006 proven. 1180 refuted. 0 times theorem prover too weak. 145046 trivial. 0 not checked. [2018-11-18 16:12:10,719 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:13,121 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 62616 proven. 3787 refuted. 0 times theorem prover too weak. 169829 trivial. 0 not checked. [2018-11-18 16:12:13,146 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:13,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 44, 44] total 114 [2018-11-18 16:12:13,147 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:13,148 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-18 16:12:13,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-18 16:12:13,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2036, Invalid=10846, Unknown=0, NotChecked=0, Total=12882 [2018-11-18 16:12:13,149 INFO L87 Difference]: Start difference. First operand 2221 states and 2231 transitions. Second operand 93 states. [2018-11-18 16:12:15,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:15,695 INFO L93 Difference]: Finished difference Result 1947 states and 1950 transitions. [2018-11-18 16:12:15,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-11-18 16:12:15,696 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1918 [2018-11-18 16:12:15,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:15,699 INFO L225 Difference]: With dead ends: 1947 [2018-11-18 16:12:15,699 INFO L226 Difference]: Without dead ends: 1938 [2018-11-18 16:12:15,702 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3971 GetRequests, 3753 SyntacticMatches, 22 SemanticMatches, 196 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15420 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=6135, Invalid=32871, Unknown=0, NotChecked=0, Total=39006 [2018-11-18 16:12:15,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1938 states. [2018-11-18 16:12:15,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1938 to 1934. [2018-11-18 16:12:15,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1934 states. [2018-11-18 16:12:15,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1934 states to 1934 states and 1937 transitions. [2018-11-18 16:12:15,711 INFO L78 Accepts]: Start accepts. Automaton has 1934 states and 1937 transitions. Word has length 1918 [2018-11-18 16:12:15,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:15,712 INFO L480 AbstractCegarLoop]: Abstraction has 1934 states and 1937 transitions. [2018-11-18 16:12:15,712 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-18 16:12:15,712 INFO L276 IsEmpty]: Start isEmpty. Operand 1934 states and 1937 transitions. [2018-11-18 16:12:15,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1925 [2018-11-18 16:12:15,726 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:15,727 INFO L375 BasicCegarLoop]: trace histogram [295, 274, 273, 273, 273, 273, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:15,727 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:15,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:15,727 INFO L82 PathProgramCache]: Analyzing trace with hash -631211218, now seen corresponding path program 53 times [2018-11-18 16:12:15,727 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:15,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:15,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:15,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:15,728 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:15,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:17,724 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 63922 proven. 4227 refuted. 0 times theorem prover too weak. 169760 trivial. 0 not checked. [2018-11-18 16:12:17,724 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:17,724 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:17,724 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:17,724 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:17,724 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:17,724 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:17,730 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:12:17,731 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:12:18,356 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-11-18 16:12:18,356 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:18,368 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:19,954 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 62621 proven. 4205 refuted. 0 times theorem prover too weak. 171083 trivial. 0 not checked. [2018-11-18 16:12:19,954 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:22,155 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 62514 proven. 4312 refuted. 0 times theorem prover too weak. 171083 trivial. 0 not checked. [2018-11-18 16:12:22,172 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:22,172 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 31, 31] total 107 [2018-11-18 16:12:22,172 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:22,173 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-11-18 16:12:22,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-11-18 16:12:22,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2366, Invalid=8976, Unknown=0, NotChecked=0, Total=11342 [2018-11-18 16:12:22,174 INFO L87 Difference]: Start difference. First operand 1934 states and 1937 transitions. Second operand 77 states. [2018-11-18 16:12:23,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:23,894 INFO L93 Difference]: Finished difference Result 2092 states and 2097 transitions. [2018-11-18 16:12:23,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-18 16:12:23,895 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1924 [2018-11-18 16:12:23,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:23,898 INFO L225 Difference]: With dead ends: 2092 [2018-11-18 16:12:23,899 INFO L226 Difference]: Without dead ends: 2092 [2018-11-18 16:12:23,901 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3966 GetRequests, 3793 SyntacticMatches, 1 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9049 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=7871, Invalid=22231, Unknown=0, NotChecked=0, Total=30102 [2018-11-18 16:12:23,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2092 states. [2018-11-18 16:12:23,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2092 to 2085. [2018-11-18 16:12:23,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2085 states. [2018-11-18 16:12:23,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2085 states to 2085 states and 2090 transitions. [2018-11-18 16:12:23,916 INFO L78 Accepts]: Start accepts. Automaton has 2085 states and 2090 transitions. Word has length 1924 [2018-11-18 16:12:23,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:23,917 INFO L480 AbstractCegarLoop]: Abstraction has 2085 states and 2090 transitions. [2018-11-18 16:12:23,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-11-18 16:12:23,917 INFO L276 IsEmpty]: Start isEmpty. Operand 2085 states and 2090 transitions. [2018-11-18 16:12:23,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1931 [2018-11-18 16:12:23,936 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:23,936 INFO L375 BasicCegarLoop]: trace histogram [296, 275, 274, 274, 274, 274, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:23,936 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:23,936 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:23,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1894558090, now seen corresponding path program 54 times [2018-11-18 16:12:23,936 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:23,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:23,937 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:23,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:23,937 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:24,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:25,346 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 35237 proven. 1555 refuted. 0 times theorem prover too weak. 202800 trivial. 0 not checked. [2018-11-18 16:12:25,347 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:25,347 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:25,347 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:25,347 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:25,347 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:25,347 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:25,352 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:12:25,353 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:12:26,729 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:12:26,730 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:26,749 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:28,047 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-18 16:12:28,047 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:29,611 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-18 16:12:29,632 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:29,633 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 24, 24] total 75 [2018-11-18 16:12:29,633 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:29,633 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-18 16:12:29,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-18 16:12:29,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=855, Invalid=4845, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 16:12:29,634 INFO L87 Difference]: Start difference. First operand 2085 states and 2090 transitions. Second operand 53 states. [2018-11-18 16:12:31,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:31,948 INFO L93 Difference]: Finished difference Result 2411 states and 2422 transitions. [2018-11-18 16:12:31,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-18 16:12:31,950 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 1930 [2018-11-18 16:12:31,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:31,953 INFO L225 Difference]: With dead ends: 2411 [2018-11-18 16:12:31,953 INFO L226 Difference]: Without dead ends: 2411 [2018-11-18 16:12:31,954 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3915 GetRequests, 3814 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2548 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1602, Invalid=8904, Unknown=0, NotChecked=0, Total=10506 [2018-11-18 16:12:31,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2411 states. [2018-11-18 16:12:31,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2411 to 2384. [2018-11-18 16:12:31,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2384 states. [2018-11-18 16:12:31,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2384 states to 2384 states and 2394 transitions. [2018-11-18 16:12:31,967 INFO L78 Accepts]: Start accepts. Automaton has 2384 states and 2394 transitions. Word has length 1930 [2018-11-18 16:12:31,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:31,968 INFO L480 AbstractCegarLoop]: Abstraction has 2384 states and 2394 transitions. [2018-11-18 16:12:31,968 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-18 16:12:31,968 INFO L276 IsEmpty]: Start isEmpty. Operand 2384 states and 2394 transitions. [2018-11-18 16:12:31,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2076 [2018-11-18 16:12:31,983 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:31,983 INFO L375 BasicCegarLoop]: trace histogram [319, 297, 296, 296, 296, 296, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:31,984 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:31,984 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:31,984 INFO L82 PathProgramCache]: Analyzing trace with hash -1524454335, now seen corresponding path program 55 times [2018-11-18 16:12:31,984 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:31,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:31,984 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:31,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:31,984 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:32,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:34,157 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 68768 proven. 7228 refuted. 0 times theorem prover too weak. 203011 trivial. 0 not checked. [2018-11-18 16:12:34,157 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:34,157 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:34,157 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:34,158 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:34,158 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:34,158 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:34,164 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:34,164 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:12:34,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:34,490 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:36,771 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 103160 proven. 1302 refuted. 0 times theorem prover too weak. 174545 trivial. 0 not checked. [2018-11-18 16:12:36,771 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:39,486 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 71627 proven. 4165 refuted. 0 times theorem prover too weak. 203215 trivial. 0 not checked. [2018-11-18 16:12:39,512 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:39,513 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 46, 46] total 119 [2018-11-18 16:12:39,513 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:39,514 INFO L459 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-11-18 16:12:39,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-11-18 16:12:39,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2220, Invalid=11822, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 16:12:39,515 INFO L87 Difference]: Start difference. First operand 2384 states and 2394 transitions. Second operand 97 states. [2018-11-18 16:12:42,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:42,320 INFO L93 Difference]: Finished difference Result 2104 states and 2107 transitions. [2018-11-18 16:12:42,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 116 states. [2018-11-18 16:12:42,320 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2075 [2018-11-18 16:12:42,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:42,323 INFO L225 Difference]: With dead ends: 2104 [2018-11-18 16:12:42,324 INFO L226 Difference]: Without dead ends: 2095 [2018-11-18 16:12:42,326 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4291 GetRequests, 4063 SyntacticMatches, 23 SemanticMatches, 205 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16925 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=6700, Invalid=35942, Unknown=0, NotChecked=0, Total=42642 [2018-11-18 16:12:42,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2095 states. [2018-11-18 16:12:42,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2095 to 2091. [2018-11-18 16:12:42,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2091 states. [2018-11-18 16:12:42,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2091 states to 2091 states and 2094 transitions. [2018-11-18 16:12:42,336 INFO L78 Accepts]: Start accepts. Automaton has 2091 states and 2094 transitions. Word has length 2075 [2018-11-18 16:12:42,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:42,337 INFO L480 AbstractCegarLoop]: Abstraction has 2091 states and 2094 transitions. [2018-11-18 16:12:42,337 INFO L481 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-11-18 16:12:42,337 INFO L276 IsEmpty]: Start isEmpty. Operand 2091 states and 2094 transitions. [2018-11-18 16:12:42,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2082 [2018-11-18 16:12:42,354 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:42,354 INFO L375 BasicCegarLoop]: trace histogram [320, 298, 297, 297, 297, 297, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:42,355 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:42,355 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:42,355 INFO L82 PathProgramCache]: Analyzing trace with hash -1931075591, now seen corresponding path program 56 times [2018-11-18 16:12:42,355 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:42,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:42,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:12:42,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:42,356 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:42,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:44,514 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 73050 proven. 4626 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-18 16:12:44,514 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:44,515 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:44,515 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:44,515 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:44,515 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:44,515 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:44,528 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:12:44,528 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:12:45,153 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-11-18 16:12:45,153 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:45,166 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:46,995 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 71621 proven. 4603 refuted. 0 times theorem prover too weak. 204606 trivial. 0 not checked. [2018-11-18 16:12:46,995 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:49,470 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 71509 proven. 4715 refuted. 0 times theorem prover too weak. 204606 trivial. 0 not checked. [2018-11-18 16:12:49,487 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:49,487 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 32, 32] total 111 [2018-11-18 16:12:49,487 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:49,488 INFO L459 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-11-18 16:12:49,488 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-11-18 16:12:49,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2530, Invalid=9680, Unknown=0, NotChecked=0, Total=12210 [2018-11-18 16:12:49,488 INFO L87 Difference]: Start difference. First operand 2091 states and 2094 transitions. Second operand 80 states. [2018-11-18 16:12:51,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:51,283 INFO L93 Difference]: Finished difference Result 2255 states and 2260 transitions. [2018-11-18 16:12:51,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-11-18 16:12:51,284 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2081 [2018-11-18 16:12:51,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:51,287 INFO L225 Difference]: With dead ends: 2255 [2018-11-18 16:12:51,287 INFO L226 Difference]: Without dead ends: 2255 [2018-11-18 16:12:51,289 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4285 GetRequests, 4105 SyntacticMatches, 1 SemanticMatches, 179 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9867 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=8492, Invalid=24088, Unknown=0, NotChecked=0, Total=32580 [2018-11-18 16:12:51,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2255 states. [2018-11-18 16:12:51,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2255 to 2248. [2018-11-18 16:12:51,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2248 states. [2018-11-18 16:12:51,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2248 states to 2248 states and 2253 transitions. [2018-11-18 16:12:51,304 INFO L78 Accepts]: Start accepts. Automaton has 2248 states and 2253 transitions. Word has length 2081 [2018-11-18 16:12:51,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:51,306 INFO L480 AbstractCegarLoop]: Abstraction has 2248 states and 2253 transitions. [2018-11-18 16:12:51,306 INFO L481 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-11-18 16:12:51,306 INFO L276 IsEmpty]: Start isEmpty. Operand 2248 states and 2253 transitions. [2018-11-18 16:12:51,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2088 [2018-11-18 16:12:51,322 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:51,323 INFO L375 BasicCegarLoop]: trace histogram [321, 299, 298, 298, 298, 298, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:51,323 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:51,323 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:51,323 INFO L82 PathProgramCache]: Analyzing trace with hash -165397759, now seen corresponding path program 57 times [2018-11-18 16:12:51,323 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:51,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:51,324 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:51,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:51,324 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:51,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:12:52,958 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39965 proven. 1706 refuted. 0 times theorem prover too weak. 240988 trivial. 0 not checked. [2018-11-18 16:12:52,958 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:52,958 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:12:52,958 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:12:52,958 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:12:52,958 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:12:52,958 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:12:52,964 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:12:52,964 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:12:53,667 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:12:53,667 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:12:53,692 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:12:55,153 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-18 16:12:55,154 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:12:56,940 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-18 16:12:56,961 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:12:56,961 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 25, 25] total 77 [2018-11-18 16:12:56,961 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:12:56,962 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-18 16:12:56,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-18 16:12:56,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=897, Invalid=5109, Unknown=0, NotChecked=0, Total=6006 [2018-11-18 16:12:56,963 INFO L87 Difference]: Start difference. First operand 2248 states and 2253 transitions. Second operand 54 states. [2018-11-18 16:12:59,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:12:59,406 INFO L93 Difference]: Finished difference Result 2586 states and 2597 transitions. [2018-11-18 16:12:59,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-11-18 16:12:59,407 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 2087 [2018-11-18 16:12:59,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:12:59,410 INFO L225 Difference]: With dead ends: 2586 [2018-11-18 16:12:59,410 INFO L226 Difference]: Without dead ends: 2586 [2018-11-18 16:12:59,411 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4230 GetRequests, 4126 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2686 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1647, Invalid=9483, Unknown=0, NotChecked=0, Total=11130 [2018-11-18 16:12:59,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2586 states. [2018-11-18 16:12:59,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2586 to 2559. [2018-11-18 16:12:59,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2559 states. [2018-11-18 16:12:59,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2559 states to 2559 states and 2569 transitions. [2018-11-18 16:12:59,422 INFO L78 Accepts]: Start accepts. Automaton has 2559 states and 2569 transitions. Word has length 2087 [2018-11-18 16:12:59,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:12:59,423 INFO L480 AbstractCegarLoop]: Abstraction has 2559 states and 2569 transitions. [2018-11-18 16:12:59,423 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-18 16:12:59,423 INFO L276 IsEmpty]: Start isEmpty. Operand 2559 states and 2569 transitions. [2018-11-18 16:12:59,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2239 [2018-11-18 16:12:59,441 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:12:59,442 INFO L375 BasicCegarLoop]: trace histogram [345, 322, 321, 321, 321, 321, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:12:59,442 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:12:59,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:12:59,442 INFO L82 PathProgramCache]: Analyzing trace with hash 2057025806, now seen corresponding path program 58 times [2018-11-18 16:12:59,442 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:12:59,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:59,443 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:12:59,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:12:59,443 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:12:59,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:01,925 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 78324 proven. 7901 refuted. 0 times theorem prover too weak. 241091 trivial. 0 not checked. [2018-11-18 16:13:01,925 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:01,925 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:01,926 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:01,926 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:01,926 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:01,926 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:01,931 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:01,932 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:13:02,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:02,290 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:04,859 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 117534 proven. 1430 refuted. 0 times theorem prover too weak. 208352 trivial. 0 not checked. [2018-11-18 16:13:04,859 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:07,844 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 81462 proven. 4561 refuted. 0 times theorem prover too weak. 241293 trivial. 0 not checked. [2018-11-18 16:13:07,870 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:07,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 48, 48] total 124 [2018-11-18 16:13:07,871 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:07,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-18 16:13:07,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-18 16:13:07,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2412, Invalid=12840, Unknown=0, NotChecked=0, Total=15252 [2018-11-18 16:13:07,873 INFO L87 Difference]: Start difference. First operand 2559 states and 2569 transitions. Second operand 101 states. [2018-11-18 16:13:11,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:11,452 INFO L93 Difference]: Finished difference Result 2267 states and 2270 transitions. [2018-11-18 16:13:11,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-11-18 16:13:11,452 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2238 [2018-11-18 16:13:11,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:11,455 INFO L225 Difference]: With dead ends: 2267 [2018-11-18 16:13:11,455 INFO L226 Difference]: Without dead ends: 2258 [2018-11-18 16:13:11,457 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4623 GetRequests, 4385 SyntacticMatches, 24 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18500 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=7290, Invalid=39150, Unknown=0, NotChecked=0, Total=46440 [2018-11-18 16:13:11,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2258 states. [2018-11-18 16:13:11,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2258 to 2254. [2018-11-18 16:13:11,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2254 states. [2018-11-18 16:13:11,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2254 states to 2254 states and 2257 transitions. [2018-11-18 16:13:11,466 INFO L78 Accepts]: Start accepts. Automaton has 2254 states and 2257 transitions. Word has length 2238 [2018-11-18 16:13:11,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:11,467 INFO L480 AbstractCegarLoop]: Abstraction has 2254 states and 2257 transitions. [2018-11-18 16:13:11,467 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-18 16:13:11,467 INFO L276 IsEmpty]: Start isEmpty. Operand 2254 states and 2257 transitions. [2018-11-18 16:13:11,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2245 [2018-11-18 16:13:11,484 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:11,484 INFO L375 BasicCegarLoop]: trace histogram [346, 323, 322, 322, 322, 322, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:11,484 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:13:11,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:11,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1417323770, now seen corresponding path program 59 times [2018-11-18 16:13:11,485 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:11,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:11,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:11,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:11,485 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:11,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:13,963 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 83007 proven. 5043 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-18 16:13:13,963 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:13,963 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:13,963 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:13,963 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:13,963 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:13,963 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:13,971 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:13:13,971 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:13:14,974 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-11-18 16:13:14,974 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:14,990 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:17,035 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 81444 proven. 5019 refuted. 0 times theorem prover too weak. 242828 trivial. 0 not checked. [2018-11-18 16:13:17,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:19,751 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 81327 proven. 5136 refuted. 0 times theorem prover too weak. 242828 trivial. 0 not checked. [2018-11-18 16:13:19,778 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:19,779 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 33, 33] total 115 [2018-11-18 16:13:19,779 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:19,780 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-18 16:13:19,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-18 16:13:19,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2695, Invalid=10415, Unknown=0, NotChecked=0, Total=13110 [2018-11-18 16:13:19,781 INFO L87 Difference]: Start difference. First operand 2254 states and 2257 transitions. Second operand 83 states. [2018-11-18 16:13:21,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:21,769 INFO L93 Difference]: Finished difference Result 2424 states and 2429 transitions. [2018-11-18 16:13:21,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 16:13:21,770 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2244 [2018-11-18 16:13:21,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:21,774 INFO L225 Difference]: With dead ends: 2424 [2018-11-18 16:13:21,774 INFO L226 Difference]: Without dead ends: 2424 [2018-11-18 16:13:21,776 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4616 GetRequests, 4429 SyntacticMatches, 1 SemanticMatches, 186 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10723 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=9130, Invalid=26026, Unknown=0, NotChecked=0, Total=35156 [2018-11-18 16:13:21,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2424 states. [2018-11-18 16:13:21,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2424 to 2417. [2018-11-18 16:13:21,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2417 states. [2018-11-18 16:13:21,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2417 states to 2417 states and 2422 transitions. [2018-11-18 16:13:21,789 INFO L78 Accepts]: Start accepts. Automaton has 2417 states and 2422 transitions. Word has length 2244 [2018-11-18 16:13:21,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:21,790 INFO L480 AbstractCegarLoop]: Abstraction has 2417 states and 2422 transitions. [2018-11-18 16:13:21,790 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-18 16:13:21,790 INFO L276 IsEmpty]: Start isEmpty. Operand 2417 states and 2422 transitions. [2018-11-18 16:13:21,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2251 [2018-11-18 16:13:21,808 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:21,809 INFO L375 BasicCegarLoop]: trace histogram [347, 324, 323, 323, 323, 323, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:21,809 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:13:21,809 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:21,810 INFO L82 PathProgramCache]: Analyzing trace with hash -1667335090, now seen corresponding path program 60 times [2018-11-18 16:13:21,810 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:21,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:21,810 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:21,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:21,810 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:21,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:23,811 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 46062 proven. 1864 refuted. 0 times theorem prover too weak. 283346 trivial. 0 not checked. [2018-11-18 16:13:23,811 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:23,811 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:23,811 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:23,812 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:23,812 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:23,812 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:23,818 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:13:23,818 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:13:26,698 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:13:26,698 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:26,723 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:28,461 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 45103 proven. 1728 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 16:13:28,461 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:30,642 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 45103 proven. 1728 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 16:13:30,664 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:30,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 26, 26] total 87 [2018-11-18 16:13:30,666 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:30,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-18 16:13:30,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-18 16:13:30,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=991, Invalid=6665, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 16:13:30,667 INFO L87 Difference]: Start difference. First operand 2417 states and 2422 transitions. Second operand 63 states. [2018-11-18 16:13:33,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:33,039 INFO L93 Difference]: Finished difference Result 2767 states and 2778 transitions. [2018-11-18 16:13:33,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 16:13:33,040 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 2250 [2018-11-18 16:13:33,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:33,044 INFO L225 Difference]: With dead ends: 2767 [2018-11-18 16:13:33,044 INFO L226 Difference]: Without dead ends: 2767 [2018-11-18 16:13:33,045 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4565 GetRequests, 4450 SyntacticMatches, 0 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3304 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1911, Invalid=11661, Unknown=0, NotChecked=0, Total=13572 [2018-11-18 16:13:33,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2767 states. [2018-11-18 16:13:33,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2767 to 2740. [2018-11-18 16:13:33,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2740 states. [2018-11-18 16:13:33,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2740 states to 2740 states and 2750 transitions. [2018-11-18 16:13:33,058 INFO L78 Accepts]: Start accepts. Automaton has 2740 states and 2750 transitions. Word has length 2250 [2018-11-18 16:13:33,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:33,059 INFO L480 AbstractCegarLoop]: Abstraction has 2740 states and 2750 transitions. [2018-11-18 16:13:33,059 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-18 16:13:33,059 INFO L276 IsEmpty]: Start isEmpty. Operand 2740 states and 2750 transitions. [2018-11-18 16:13:33,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2408 [2018-11-18 16:13:33,080 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:33,081 INFO L375 BasicCegarLoop]: trace histogram [372, 348, 347, 347, 347, 347, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:33,081 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:13:33,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:33,081 INFO L82 PathProgramCache]: Analyzing trace with hash 1963665113, now seen corresponding path program 61 times [2018-11-18 16:13:33,082 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:33,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:33,082 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:33,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:33,082 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:33,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:35,862 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 88727 proven. 8604 refuted. 0 times theorem prover too weak. 284284 trivial. 0 not checked. [2018-11-18 16:13:35,862 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:35,862 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:35,862 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:35,862 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:35,862 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:35,863 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:35,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:35,868 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:13:36,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:36,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:39,170 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 133182 proven. 1564 refuted. 0 times theorem prover too weak. 246869 trivial. 0 not checked. [2018-11-18 16:13:39,170 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:42,485 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 92157 proven. 4975 refuted. 0 times theorem prover too weak. 284483 trivial. 0 not checked. [2018-11-18 16:13:42,512 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:42,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 50, 50] total 129 [2018-11-18 16:13:42,512 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:42,513 INFO L459 AbstractCegarLoop]: Interpolant automaton has 105 states [2018-11-18 16:13:42,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 105 interpolants. [2018-11-18 16:13:42,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2612, Invalid=13900, Unknown=0, NotChecked=0, Total=16512 [2018-11-18 16:13:42,514 INFO L87 Difference]: Start difference. First operand 2740 states and 2750 transitions. Second operand 105 states. [2018-11-18 16:13:45,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:45,847 INFO L93 Difference]: Finished difference Result 2436 states and 2439 transitions. [2018-11-18 16:13:45,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2018-11-18 16:13:45,849 INFO L78 Accepts]: Start accepts. Automaton has 105 states. Word has length 2407 [2018-11-18 16:13:45,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:45,851 INFO L225 Difference]: With dead ends: 2436 [2018-11-18 16:13:45,851 INFO L226 Difference]: Without dead ends: 2427 [2018-11-18 16:13:45,853 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4967 GetRequests, 4719 SyntacticMatches, 25 SemanticMatches, 223 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20145 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=7905, Invalid=42495, Unknown=0, NotChecked=0, Total=50400 [2018-11-18 16:13:45,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2427 states. [2018-11-18 16:13:45,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2427 to 2423. [2018-11-18 16:13:45,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2423 states. [2018-11-18 16:13:45,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2423 states to 2423 states and 2426 transitions. [2018-11-18 16:13:45,864 INFO L78 Accepts]: Start accepts. Automaton has 2423 states and 2426 transitions. Word has length 2407 [2018-11-18 16:13:45,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:45,865 INFO L480 AbstractCegarLoop]: Abstraction has 2423 states and 2426 transitions. [2018-11-18 16:13:45,865 INFO L481 AbstractCegarLoop]: Interpolant automaton has 105 states. [2018-11-18 16:13:45,865 INFO L276 IsEmpty]: Start isEmpty. Operand 2423 states and 2426 transitions. [2018-11-18 16:13:45,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2414 [2018-11-18 16:13:45,887 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:45,887 INFO L375 BasicCegarLoop]: trace histogram [373, 349, 348, 348, 348, 348, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:45,887 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:13:45,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:45,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1678426257, now seen corresponding path program 62 times [2018-11-18 16:13:45,888 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:45,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:45,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:13:45,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:45,889 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:46,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:48,696 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 93829 proven. 5478 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 16:13:48,696 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:48,696 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:48,696 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:48,696 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:48,696 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:48,696 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:48,705 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:13:48,705 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:13:49,826 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-11-18 16:13:49,826 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:13:49,844 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:13:52,223 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 92126 proven. 5453 refuted. 0 times theorem prover too weak. 286169 trivial. 0 not checked. [2018-11-18 16:13:52,224 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:13:55,230 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 92004 proven. 5575 refuted. 0 times theorem prover too weak. 286169 trivial. 0 not checked. [2018-11-18 16:13:55,247 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:13:55,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 34, 34] total 119 [2018-11-18 16:13:55,248 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:13:55,248 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-11-18 16:13:55,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-11-18 16:13:55,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2861, Invalid=11181, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 16:13:55,249 INFO L87 Difference]: Start difference. First operand 2423 states and 2426 transitions. Second operand 86 states. [2018-11-18 16:13:57,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:13:57,676 INFO L93 Difference]: Finished difference Result 2599 states and 2604 transitions. [2018-11-18 16:13:57,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-18 16:13:57,678 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 2413 [2018-11-18 16:13:57,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:13:57,681 INFO L225 Difference]: With dead ends: 2599 [2018-11-18 16:13:57,681 INFO L226 Difference]: Without dead ends: 2599 [2018-11-18 16:13:57,683 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4959 GetRequests, 4765 SyntacticMatches, 1 SemanticMatches, 193 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11617 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=9785, Invalid=28045, Unknown=0, NotChecked=0, Total=37830 [2018-11-18 16:13:57,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2599 states. [2018-11-18 16:13:57,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2599 to 2592. [2018-11-18 16:13:57,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2592 states. [2018-11-18 16:13:57,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2592 states to 2592 states and 2597 transitions. [2018-11-18 16:13:57,699 INFO L78 Accepts]: Start accepts. Automaton has 2592 states and 2597 transitions. Word has length 2413 [2018-11-18 16:13:57,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:13:57,700 INFO L480 AbstractCegarLoop]: Abstraction has 2592 states and 2597 transitions. [2018-11-18 16:13:57,700 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-11-18 16:13:57,700 INFO L276 IsEmpty]: Start isEmpty. Operand 2592 states and 2597 transitions. [2018-11-18 16:13:57,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2420 [2018-11-18 16:13:57,741 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:13:57,741 INFO L375 BasicCegarLoop]: trace histogram [374, 350, 349, 349, 349, 349, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:13:57,742 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:13:57,742 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:13:57,742 INFO L82 PathProgramCache]: Analyzing trace with hash -171601511, now seen corresponding path program 63 times [2018-11-18 16:13:57,742 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:13:57,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:57,743 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:13:57,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:13:57,743 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:13:57,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:13:59,912 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50966 proven. 2029 refuted. 0 times theorem prover too weak. 332892 trivial. 0 not checked. [2018-11-18 16:13:59,912 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:59,912 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:13:59,912 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:13:59,912 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:13:59,912 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:13:59,912 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:13:59,918 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:13:59,919 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:14:00,713 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:14:00,713 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:14:00,740 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:02,652 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50820 proven. 1875 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 16:14:02,652 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:04,938 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50820 proven. 1875 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 16:14:04,971 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:04,972 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 27, 27] total 83 [2018-11-18 16:14:04,972 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:04,972 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-18 16:14:04,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-18 16:14:04,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=986, Invalid=5986, Unknown=0, NotChecked=0, Total=6972 [2018-11-18 16:14:04,973 INFO L87 Difference]: Start difference. First operand 2592 states and 2597 transitions. Second operand 58 states. [2018-11-18 16:14:07,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:07,568 INFO L93 Difference]: Finished difference Result 2954 states and 2965 transitions. [2018-11-18 16:14:07,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-18 16:14:07,570 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 2419 [2018-11-18 16:14:07,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:07,574 INFO L225 Difference]: With dead ends: 2954 [2018-11-18 16:14:07,574 INFO L226 Difference]: Without dead ends: 2954 [2018-11-18 16:14:07,575 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4898 GetRequests, 4786 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3087 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1780, Invalid=11102, Unknown=0, NotChecked=0, Total=12882 [2018-11-18 16:14:07,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2954 states. [2018-11-18 16:14:07,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2954 to 2927. [2018-11-18 16:14:07,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2927 states. [2018-11-18 16:14:07,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2927 states to 2927 states and 2937 transitions. [2018-11-18 16:14:07,590 INFO L78 Accepts]: Start accepts. Automaton has 2927 states and 2937 transitions. Word has length 2419 [2018-11-18 16:14:07,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:07,592 INFO L480 AbstractCegarLoop]: Abstraction has 2927 states and 2937 transitions. [2018-11-18 16:14:07,592 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-18 16:14:07,592 INFO L276 IsEmpty]: Start isEmpty. Operand 2927 states and 2937 transitions. [2018-11-18 16:14:07,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2583 [2018-11-18 16:14:07,616 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:07,616 INFO L375 BasicCegarLoop]: trace histogram [400, 375, 374, 374, 374, 374, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:07,616 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:14:07,617 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:07,617 INFO L82 PathProgramCache]: Analyzing trace with hash 272826726, now seen corresponding path program 64 times [2018-11-18 16:14:07,617 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:07,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:07,617 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:14:07,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:07,618 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:07,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:10,753 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 100013 proven. 9337 refuted. 0 times theorem prover too weak. 333028 trivial. 0 not checked. [2018-11-18 16:14:10,753 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:10,753 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:10,753 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:10,753 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:10,753 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:10,753 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:10,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:14:10,759 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:14:11,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:11,184 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:14,398 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 150158 proven. 1704 refuted. 0 times theorem prover too weak. 290516 trivial. 0 not checked. [2018-11-18 16:14:14,399 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:18,074 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 103748 proven. 5407 refuted. 0 times theorem prover too weak. 333223 trivial. 0 not checked. [2018-11-18 16:14:18,101 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:18,102 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 52, 52] total 134 [2018-11-18 16:14:18,102 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:18,103 INFO L459 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-11-18 16:14:18,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-11-18 16:14:18,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2820, Invalid=15002, Unknown=0, NotChecked=0, Total=17822 [2018-11-18 16:14:18,104 INFO L87 Difference]: Start difference. First operand 2927 states and 2937 transitions. Second operand 109 states. [2018-11-18 16:14:21,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:21,748 INFO L93 Difference]: Finished difference Result 2611 states and 2614 transitions. [2018-11-18 16:14:21,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-11-18 16:14:21,748 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2582 [2018-11-18 16:14:21,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:21,752 INFO L225 Difference]: With dead ends: 2611 [2018-11-18 16:14:21,752 INFO L226 Difference]: Without dead ends: 2602 [2018-11-18 16:14:21,755 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5323 GetRequests, 5065 SyntacticMatches, 26 SemanticMatches, 232 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21860 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=8545, Invalid=45977, Unknown=0, NotChecked=0, Total=54522 [2018-11-18 16:14:21,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2602 states. [2018-11-18 16:14:21,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2602 to 2598. [2018-11-18 16:14:21,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2598 states. [2018-11-18 16:14:21,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2598 states to 2598 states and 2601 transitions. [2018-11-18 16:14:21,766 INFO L78 Accepts]: Start accepts. Automaton has 2598 states and 2601 transitions. Word has length 2582 [2018-11-18 16:14:21,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:21,767 INFO L480 AbstractCegarLoop]: Abstraction has 2598 states and 2601 transitions. [2018-11-18 16:14:21,767 INFO L481 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-11-18 16:14:21,767 INFO L276 IsEmpty]: Start isEmpty. Operand 2598 states and 2601 transitions. [2018-11-18 16:14:21,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2589 [2018-11-18 16:14:21,791 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:21,792 INFO L375 BasicCegarLoop]: trace histogram [401, 376, 375, 375, 375, 375, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:21,792 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:14:21,792 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:21,792 INFO L82 PathProgramCache]: Analyzing trace with hash 500791646, now seen corresponding path program 65 times [2018-11-18 16:14:21,792 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:21,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:21,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:14:21,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:21,793 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:21,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:25,005 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 105552 proven. 5931 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 16:14:25,005 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:25,005 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:25,005 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:25,006 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:25,006 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:25,006 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:25,011 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:14:25,012 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:14:26,658 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-11-18 16:14:26,659 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:14:26,673 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:29,030 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 56841 proven. 2028 refuted. 0 times theorem prover too weak. 385806 trivial. 0 not checked. [2018-11-18 16:14:29,030 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:31,542 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 56841 proven. 2028 refuted. 0 times theorem prover too weak. 385806 trivial. 0 not checked. [2018-11-18 16:14:31,560 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:31,561 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 29, 29] total 95 [2018-11-18 16:14:31,561 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:31,562 INFO L459 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-11-18 16:14:31,563 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-11-18 16:14:31,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1380, Invalid=7550, Unknown=0, NotChecked=0, Total=8930 [2018-11-18 16:14:31,563 INFO L87 Difference]: Start difference. First operand 2598 states and 2601 transitions. Second operand 88 states. [2018-11-18 16:14:34,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:34,514 INFO L93 Difference]: Finished difference Result 2789 states and 2795 transitions. [2018-11-18 16:14:34,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 16:14:34,515 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2588 [2018-11-18 16:14:34,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:34,520 INFO L225 Difference]: With dead ends: 2789 [2018-11-18 16:14:34,520 INFO L226 Difference]: Without dead ends: 2789 [2018-11-18 16:14:34,522 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5315 GetRequests, 5121 SyntacticMatches, 21 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8689 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=7161, Invalid=23289, Unknown=0, NotChecked=0, Total=30450 [2018-11-18 16:14:34,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2789 states. [2018-11-18 16:14:34,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2789 to 2779. [2018-11-18 16:14:34,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2779 states. [2018-11-18 16:14:34,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2779 states to 2779 states and 2785 transitions. [2018-11-18 16:14:34,540 INFO L78 Accepts]: Start accepts. Automaton has 2779 states and 2785 transitions. Word has length 2588 [2018-11-18 16:14:34,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:34,542 INFO L480 AbstractCegarLoop]: Abstraction has 2779 states and 2785 transitions. [2018-11-18 16:14:34,542 INFO L481 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-11-18 16:14:34,542 INFO L276 IsEmpty]: Start isEmpty. Operand 2779 states and 2785 transitions. [2018-11-18 16:14:34,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2601 [2018-11-18 16:14:34,580 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:34,580 INFO L375 BasicCegarLoop]: trace histogram [403, 378, 377, 377, 377, 377, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:34,580 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:14:34,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:34,581 INFO L82 PathProgramCache]: Analyzing trace with hash -762262882, now seen corresponding path program 66 times [2018-11-18 16:14:34,581 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:34,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:34,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:14:34,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:34,582 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:34,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:37,684 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61282 proven. 2255 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 16:14:37,684 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:37,685 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:37,685 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:37,685 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:37,685 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:37,685 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:37,691 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:14:37,691 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:14:38,049 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:14:38,049 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:14:38,067 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:41,024 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61053 proven. 7582 refuted. 0 times theorem prover too weak. 380652 trivial. 0 not checked. [2018-11-18 16:14:41,025 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:43,841 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61053 proven. 7582 refuted. 0 times theorem prover too weak. 380652 trivial. 0 not checked. [2018-11-18 16:14:43,858 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:43,860 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 61, 61] total 94 [2018-11-18 16:14:43,860 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:43,860 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-11-18 16:14:43,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-11-18 16:14:43,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1742, Invalid=7000, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 16:14:43,861 INFO L87 Difference]: Start difference. First operand 2779 states and 2785 transitions. Second operand 91 states. [2018-11-18 16:14:46,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:14:46,135 INFO L93 Difference]: Finished difference Result 3137 states and 3147 transitions. [2018-11-18 16:14:46,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 16:14:46,136 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2600 [2018-11-18 16:14:46,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:14:46,141 INFO L225 Difference]: With dead ends: 3137 [2018-11-18 16:14:46,141 INFO L226 Difference]: Without dead ends: 3137 [2018-11-18 16:14:46,142 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5312 GetRequests, 5108 SyntacticMatches, 57 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7221 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=4838, Invalid=17214, Unknown=0, NotChecked=0, Total=22052 [2018-11-18 16:14:46,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3137 states. [2018-11-18 16:14:46,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3137 to 3126. [2018-11-18 16:14:46,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3126 states. [2018-11-18 16:14:46,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3126 states to 3126 states and 3136 transitions. [2018-11-18 16:14:46,157 INFO L78 Accepts]: Start accepts. Automaton has 3126 states and 3136 transitions. Word has length 2600 [2018-11-18 16:14:46,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:14:46,158 INFO L480 AbstractCegarLoop]: Abstraction has 3126 states and 3136 transitions. [2018-11-18 16:14:46,158 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-11-18 16:14:46,158 INFO L276 IsEmpty]: Start isEmpty. Operand 3126 states and 3136 transitions. [2018-11-18 16:14:46,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2764 [2018-11-18 16:14:46,186 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:14:46,186 INFO L375 BasicCegarLoop]: trace histogram [429, 403, 402, 402, 402, 402, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:14:46,186 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:14:46,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:14:46,187 INFO L82 PathProgramCache]: Analyzing trace with hash 1862136561, now seen corresponding path program 67 times [2018-11-18 16:14:46,187 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:14:46,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:46,187 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:14:46,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:14:46,188 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:14:46,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:49,690 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 112218 proven. 10100 refuted. 0 times theorem prover too weak. 387779 trivial. 0 not checked. [2018-11-18 16:14:49,690 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:49,690 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:14:49,690 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:14:49,690 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:14:49,690 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:14:49,690 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:14:49,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:14:49,698 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:14:50,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:14:50,159 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:14:53,744 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 168516 proven. 1850 refuted. 0 times theorem prover too weak. 339731 trivial. 0 not checked. [2018-11-18 16:14:53,745 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:14:57,853 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 116271 proven. 5857 refuted. 0 times theorem prover too weak. 387969 trivial. 0 not checked. [2018-11-18 16:14:57,871 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:14:57,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 54, 54] total 139 [2018-11-18 16:14:57,872 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:14:57,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 113 states [2018-11-18 16:14:57,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2018-11-18 16:14:57,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=16146, Unknown=0, NotChecked=0, Total=19182 [2018-11-18 16:14:57,873 INFO L87 Difference]: Start difference. First operand 3126 states and 3136 transitions. Second operand 113 states. [2018-11-18 16:15:00,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:00,878 INFO L93 Difference]: Finished difference Result 2792 states and 2795 transitions. [2018-11-18 16:15:00,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 136 states. [2018-11-18 16:15:00,880 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 2763 [2018-11-18 16:15:00,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:00,883 INFO L225 Difference]: With dead ends: 2792 [2018-11-18 16:15:00,883 INFO L226 Difference]: Without dead ends: 2783 [2018-11-18 16:15:00,886 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5691 GetRequests, 5423 SyntacticMatches, 27 SemanticMatches, 241 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23645 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=9210, Invalid=49596, Unknown=0, NotChecked=0, Total=58806 [2018-11-18 16:15:00,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2783 states. [2018-11-18 16:15:00,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2783 to 2779. [2018-11-18 16:15:00,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2779 states. [2018-11-18 16:15:00,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2779 states to 2779 states and 2782 transitions. [2018-11-18 16:15:00,897 INFO L78 Accepts]: Start accepts. Automaton has 2779 states and 2782 transitions. Word has length 2763 [2018-11-18 16:15:00,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:00,898 INFO L480 AbstractCegarLoop]: Abstraction has 2779 states and 2782 transitions. [2018-11-18 16:15:00,898 INFO L481 AbstractCegarLoop]: Interpolant automaton has 113 states. [2018-11-18 16:15:00,898 INFO L276 IsEmpty]: Start isEmpty. Operand 2779 states and 2782 transitions. [2018-11-18 16:15:00,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2770 [2018-11-18 16:15:00,923 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:00,924 INFO L375 BasicCegarLoop]: trace histogram [430, 404, 403, 403, 403, 403, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:00,924 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:15:00,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:00,924 INFO L82 PathProgramCache]: Analyzing trace with hash 1304072873, now seen corresponding path program 68 times [2018-11-18 16:15:00,924 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:00,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:00,925 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:00,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:00,925 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:01,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:04,504 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 118212 proven. 6402 refuted. 0 times theorem prover too weak. 387950 trivial. 0 not checked. [2018-11-18 16:15:04,504 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:04,504 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:04,504 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:04,505 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:04,505 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:04,505 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:04,514 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:15:04,514 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:15:05,856 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-11-18 16:15:05,856 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:15:05,876 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:08,811 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 116211 proven. 6375 refuted. 0 times theorem prover too weak. 389978 trivial. 0 not checked. [2018-11-18 16:15:08,811 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:12,501 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 116079 proven. 6507 refuted. 0 times theorem prover too weak. 389978 trivial. 0 not checked. [2018-11-18 16:15:12,519 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:12,520 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 36, 36] total 127 [2018-11-18 16:15:12,520 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:12,521 INFO L459 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-11-18 16:15:12,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-11-18 16:15:12,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3196, Invalid=12806, Unknown=0, NotChecked=0, Total=16002 [2018-11-18 16:15:12,521 INFO L87 Difference]: Start difference. First operand 2779 states and 2782 transitions. Second operand 92 states. [2018-11-18 16:15:15,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:15,111 INFO L93 Difference]: Finished difference Result 2967 states and 2972 transitions. [2018-11-18 16:15:15,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-11-18 16:15:15,113 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2769 [2018-11-18 16:15:15,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:15,117 INFO L225 Difference]: With dead ends: 2967 [2018-11-18 16:15:15,117 INFO L226 Difference]: Without dead ends: 2967 [2018-11-18 16:15:15,118 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5681 GetRequests, 5473 SyntacticMatches, 1 SemanticMatches, 207 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13519 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=11146, Invalid=32326, Unknown=0, NotChecked=0, Total=43472 [2018-11-18 16:15:15,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2967 states. [2018-11-18 16:15:15,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2967 to 2960. [2018-11-18 16:15:15,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2960 states. [2018-11-18 16:15:15,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2960 states to 2960 states and 2965 transitions. [2018-11-18 16:15:15,131 INFO L78 Accepts]: Start accepts. Automaton has 2960 states and 2965 transitions. Word has length 2769 [2018-11-18 16:15:15,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:15,131 INFO L480 AbstractCegarLoop]: Abstraction has 2960 states and 2965 transitions. [2018-11-18 16:15:15,131 INFO L481 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-11-18 16:15:15,132 INFO L276 IsEmpty]: Start isEmpty. Operand 2960 states and 2965 transitions. [2018-11-18 16:15:15,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2776 [2018-11-18 16:15:15,157 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:15,158 INFO L375 BasicCegarLoop]: trace histogram [431, 405, 404, 404, 404, 404, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:15,158 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:15:15,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:15,158 INFO L82 PathProgramCache]: Analyzing trace with hash 974846385, now seen corresponding path program 69 times [2018-11-18 16:15:15,158 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:15,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:15,159 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:15,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:15,159 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:15,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:17,888 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63819 proven. 2380 refuted. 0 times theorem prover too weak. 448838 trivial. 0 not checked. [2018-11-18 16:15:17,888 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:17,888 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:17,888 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:17,888 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:17,889 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:17,889 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:17,894 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:15:17,894 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:15:18,919 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:15:18,919 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:15:18,953 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:21,402 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63661 proven. 2187 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 16:15:21,402 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:24,296 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63661 proven. 2187 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 16:15:24,320 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:24,321 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 29, 29] total 89 [2018-11-18 16:15:24,321 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:24,322 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-18 16:15:24,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-18 16:15:24,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1071, Invalid=6939, Unknown=0, NotChecked=0, Total=8010 [2018-11-18 16:15:24,322 INFO L87 Difference]: Start difference. First operand 2960 states and 2965 transitions. Second operand 62 states. [2018-11-18 16:15:27,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:27,095 INFO L93 Difference]: Finished difference Result 3346 states and 3357 transitions. [2018-11-18 16:15:27,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-11-18 16:15:27,097 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2775 [2018-11-18 16:15:27,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:27,101 INFO L225 Difference]: With dead ends: 3346 [2018-11-18 16:15:27,101 INFO L226 Difference]: Without dead ends: 3346 [2018-11-18 16:15:27,102 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5614 GetRequests, 5494 SyntacticMatches, 0 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3508 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1901, Invalid=12861, Unknown=0, NotChecked=0, Total=14762 [2018-11-18 16:15:27,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3346 states. [2018-11-18 16:15:27,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3346 to 3319. [2018-11-18 16:15:27,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3319 states. [2018-11-18 16:15:27,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3319 states to 3319 states and 3329 transitions. [2018-11-18 16:15:27,122 INFO L78 Accepts]: Start accepts. Automaton has 3319 states and 3329 transitions. Word has length 2775 [2018-11-18 16:15:27,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:27,123 INFO L480 AbstractCegarLoop]: Abstraction has 3319 states and 3329 transitions. [2018-11-18 16:15:27,123 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-18 16:15:27,123 INFO L276 IsEmpty]: Start isEmpty. Operand 3319 states and 3329 transitions. [2018-11-18 16:15:27,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2951 [2018-11-18 16:15:27,155 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:27,155 INFO L375 BasicCegarLoop]: trace histogram [459, 432, 431, 431, 431, 431, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:27,155 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:15:27,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:27,156 INFO L82 PathProgramCache]: Analyzing trace with hash -1860376514, now seen corresponding path program 70 times [2018-11-18 16:15:27,156 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:27,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:27,156 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:27,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:27,156 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:27,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:31,039 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 125378 proven. 10893 refuted. 0 times theorem prover too weak. 449011 trivial. 0 not checked. [2018-11-18 16:15:31,039 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:31,039 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:31,039 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:31,039 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:31,039 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:31,039 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:31,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:31,045 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:15:31,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:31,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:35,466 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 188310 proven. 2002 refuted. 0 times theorem prover too weak. 394970 trivial. 0 not checked. [2018-11-18 16:15:35,466 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:39,970 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 129762 proven. 6325 refuted. 0 times theorem prover too weak. 449195 trivial. 0 not checked. [2018-11-18 16:15:39,998 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:39,999 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 56, 56] total 144 [2018-11-18 16:15:39,999 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:40,000 INFO L459 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-11-18 16:15:40,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-11-18 16:15:40,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3260, Invalid=17332, Unknown=0, NotChecked=0, Total=20592 [2018-11-18 16:15:40,001 INFO L87 Difference]: Start difference. First operand 3319 states and 3329 transitions. Second operand 117 states. [2018-11-18 16:15:43,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:43,860 INFO L93 Difference]: Finished difference Result 2979 states and 2982 transitions. [2018-11-18 16:15:43,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-11-18 16:15:43,862 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2950 [2018-11-18 16:15:43,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:15:43,866 INFO L225 Difference]: With dead ends: 2979 [2018-11-18 16:15:43,866 INFO L226 Difference]: Without dead ends: 2970 [2018-11-18 16:15:43,868 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6071 GetRequests, 5793 SyntacticMatches, 28 SemanticMatches, 250 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25500 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=9900, Invalid=53352, Unknown=0, NotChecked=0, Total=63252 [2018-11-18 16:15:43,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2970 states. [2018-11-18 16:15:43,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2970 to 2966. [2018-11-18 16:15:43,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2966 states. [2018-11-18 16:15:43,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2966 states to 2966 states and 2969 transitions. [2018-11-18 16:15:43,886 INFO L78 Accepts]: Start accepts. Automaton has 2966 states and 2969 transitions. Word has length 2950 [2018-11-18 16:15:43,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:15:43,887 INFO L480 AbstractCegarLoop]: Abstraction has 2966 states and 2969 transitions. [2018-11-18 16:15:43,887 INFO L481 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-11-18 16:15:43,888 INFO L276 IsEmpty]: Start isEmpty. Operand 2966 states and 2969 transitions. [2018-11-18 16:15:43,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2957 [2018-11-18 16:15:43,916 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:15:43,916 INFO L375 BasicCegarLoop]: trace histogram [460, 433, 432, 432, 432, 432, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:43,917 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:15:43,917 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:43,917 INFO L82 PathProgramCache]: Analyzing trace with hash 380851766, now seen corresponding path program 71 times [2018-11-18 16:15:43,917 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:15:43,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:43,917 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:43,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:43,918 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:15:44,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:47,790 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 131845 proven. 6891 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 16:15:47,790 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:47,790 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:15:47,790 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:15:47,790 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:15:47,790 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:15:47,790 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:15:47,800 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:15:47,800 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:15:50,060 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-11-18 16:15:50,061 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:15:50,078 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:15:53,374 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 129686 proven. 6863 refuted. 0 times theorem prover too weak. 451376 trivial. 0 not checked. [2018-11-18 16:15:53,374 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:15:57,451 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 129549 proven. 7000 refuted. 0 times theorem prover too weak. 451376 trivial. 0 not checked. [2018-11-18 16:15:57,479 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:15:57,480 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 37, 37] total 131 [2018-11-18 16:15:57,480 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:15:57,480 INFO L459 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-11-18 16:15:57,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-11-18 16:15:57,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3365, Invalid=13665, Unknown=0, NotChecked=0, Total=17030 [2018-11-18 16:15:57,482 INFO L87 Difference]: Start difference. First operand 2966 states and 2969 transitions. Second operand 95 states. [2018-11-18 16:16:00,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:00,070 INFO L93 Difference]: Finished difference Result 3160 states and 3165 transitions. [2018-11-18 16:16:00,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-11-18 16:16:00,071 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 2956 [2018-11-18 16:16:00,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:00,076 INFO L225 Difference]: With dead ends: 3160 [2018-11-18 16:16:00,076 INFO L226 Difference]: Without dead ends: 3160 [2018-11-18 16:16:00,078 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6060 GetRequests, 5845 SyntacticMatches, 1 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14527 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=11852, Invalid=34588, Unknown=0, NotChecked=0, Total=46440 [2018-11-18 16:16:00,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3160 states. [2018-11-18 16:16:00,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3160 to 3153. [2018-11-18 16:16:00,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3153 states. [2018-11-18 16:16:00,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3153 states to 3153 states and 3158 transitions. [2018-11-18 16:16:00,095 INFO L78 Accepts]: Start accepts. Automaton has 3153 states and 3158 transitions. Word has length 2956 [2018-11-18 16:16:00,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:00,097 INFO L480 AbstractCegarLoop]: Abstraction has 3153 states and 3158 transitions. [2018-11-18 16:16:00,097 INFO L481 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-11-18 16:16:00,097 INFO L276 IsEmpty]: Start isEmpty. Operand 3153 states and 3158 transitions. [2018-11-18 16:16:00,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2963 [2018-11-18 16:16:00,134 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:00,135 INFO L375 BasicCegarLoop]: trace histogram [461, 434, 433, 433, 433, 433, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:00,135 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:16:00,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:00,136 INFO L82 PathProgramCache]: Analyzing trace with hash -1791335554, now seen corresponding path program 72 times [2018-11-18 16:16:00,136 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:00,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,136 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:00,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,137 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:00,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:03,256 INFO L134 CoverageAnalysis]: Checked inductivity of 590574 backedges. 71444 proven. 2566 refuted. 0 times theorem prover too weak. 516564 trivial. 0 not checked. [2018-11-18 16:16:03,257 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:03,257 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:16:03,257 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:16:03,257 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:16:03,257 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:03,257 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:16:03,269 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:16:03,269 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:16:11,692 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:16:11,692 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:16:11,730 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:16:14,494 INFO L134 CoverageAnalysis]: Checked inductivity of 590574 backedges. 70821 proven. 2352 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 16:16:14,494 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:16:17,815 INFO L134 CoverageAnalysis]: Checked inductivity of 590574 backedges. 70821 proven. 2352 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 16:16:17,841 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:16:17,842 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 30, 30] total 95 [2018-11-18 16:16:17,842 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:16:17,842 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 16:16:17,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 16:16:17,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1127, Invalid=7993, Unknown=0, NotChecked=0, Total=9120 [2018-11-18 16:16:17,843 INFO L87 Difference]: Start difference. First operand 3153 states and 3158 transitions. Second operand 67 states. [2018-11-18 16:16:20,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:20,774 INFO L93 Difference]: Finished difference Result 3551 states and 3562 transitions. [2018-11-18 16:16:20,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-11-18 16:16:20,774 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 2962 [2018-11-18 16:16:20,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:20,780 INFO L225 Difference]: With dead ends: 3551 [2018-11-18 16:16:20,780 INFO L226 Difference]: Without dead ends: 3551 [2018-11-18 16:16:20,781 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5993 GetRequests, 5866 SyntacticMatches, 0 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3960 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2053, Invalid=14459, Unknown=0, NotChecked=0, Total=16512 [2018-11-18 16:16:20,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3551 states. [2018-11-18 16:16:20,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3551 to 3524. [2018-11-18 16:16:20,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3524 states. [2018-11-18 16:16:20,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3524 states to 3524 states and 3534 transitions. [2018-11-18 16:16:20,803 INFO L78 Accepts]: Start accepts. Automaton has 3524 states and 3534 transitions. Word has length 2962 [2018-11-18 16:16:20,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:20,804 INFO L480 AbstractCegarLoop]: Abstraction has 3524 states and 3534 transitions. [2018-11-18 16:16:20,804 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 16:16:20,804 INFO L276 IsEmpty]: Start isEmpty. Operand 3524 states and 3534 transitions. [2018-11-18 16:16:20,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3144 [2018-11-18 16:16:20,841 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:20,841 INFO L375 BasicCegarLoop]: trace histogram [490, 462, 461, 461, 461, 461, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:20,841 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:16:20,841 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:20,842 INFO L82 PathProgramCache]: Analyzing trace with hash 1883492489, now seen corresponding path program 73 times [2018-11-18 16:16:20,842 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:20,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:20,842 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:20,843 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:20,843 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:21,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:25,186 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 139529 proven. 11716 refuted. 0 times theorem prover too weak. 517216 trivial. 0 not checked. [2018-11-18 16:16:25,186 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:25,186 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:16:25,187 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:16:25,187 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:16:25,187 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:25,187 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:16:25,194 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:25,194 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:16:25,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:25,704 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:16:30,376 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 209594 proven. 2160 refuted. 0 times theorem prover too weak. 456707 trivial. 0 not checked. [2018-11-18 16:16:30,376 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:16:35,553 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 144257 proven. 6811 refuted. 0 times theorem prover too weak. 517393 trivial. 0 not checked. [2018-11-18 16:16:35,582 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:16:35,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 58, 58] total 149 [2018-11-18 16:16:35,583 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:16:35,584 INFO L459 AbstractCegarLoop]: Interpolant automaton has 121 states [2018-11-18 16:16:35,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 121 interpolants. [2018-11-18 16:16:35,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3492, Invalid=18560, Unknown=0, NotChecked=0, Total=22052 [2018-11-18 16:16:35,585 INFO L87 Difference]: Start difference. First operand 3524 states and 3534 transitions. Second operand 121 states. [2018-11-18 16:16:39,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:39,545 INFO L93 Difference]: Finished difference Result 3172 states and 3175 transitions. [2018-11-18 16:16:39,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2018-11-18 16:16:39,546 INFO L78 Accepts]: Start accepts. Automaton has 121 states. Word has length 3143 [2018-11-18 16:16:39,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:39,551 INFO L225 Difference]: With dead ends: 3172 [2018-11-18 16:16:39,551 INFO L226 Difference]: Without dead ends: 3163 [2018-11-18 16:16:39,554 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6463 GetRequests, 6175 SyntacticMatches, 29 SemanticMatches, 259 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27425 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=10615, Invalid=57245, Unknown=0, NotChecked=0, Total=67860 [2018-11-18 16:16:39,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3163 states. [2018-11-18 16:16:39,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3163 to 3159. [2018-11-18 16:16:39,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3159 states. [2018-11-18 16:16:39,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3159 states to 3159 states and 3162 transitions. [2018-11-18 16:16:39,570 INFO L78 Accepts]: Start accepts. Automaton has 3159 states and 3162 transitions. Word has length 3143 [2018-11-18 16:16:39,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:39,572 INFO L480 AbstractCegarLoop]: Abstraction has 3159 states and 3162 transitions. [2018-11-18 16:16:39,572 INFO L481 AbstractCegarLoop]: Interpolant automaton has 121 states. [2018-11-18 16:16:39,572 INFO L276 IsEmpty]: Start isEmpty. Operand 3159 states and 3162 transitions. [2018-11-18 16:16:39,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3150 [2018-11-18 16:16:39,612 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:39,613 INFO L375 BasicCegarLoop]: trace histogram [491, 463, 462, 462, 462, 462, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:39,613 INFO L423 AbstractCegarLoop]: === Iteration 90 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:16:39,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:39,613 INFO L82 PathProgramCache]: Analyzing trace with hash -542222783, now seen corresponding path program 74 times [2018-11-18 16:16:39,613 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:39,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:39,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:39,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:39,614 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:39,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:43,958 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 146487 proven. 7398 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 16:16:43,958 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:43,958 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:16:43,958 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:16:43,958 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:16:43,959 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:16:43,959 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:16:43,967 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:16:43,967 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:16:46,302 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-11-18 16:16:46,302 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:16:46,325 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:16:49,994 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 144164 proven. 7369 refuted. 0 times theorem prover too weak. 519753 trivial. 0 not checked. [2018-11-18 16:16:49,994 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:16:54,472 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 144022 proven. 7511 refuted. 0 times theorem prover too weak. 519753 trivial. 0 not checked. [2018-11-18 16:16:54,501 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:16:54,502 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 38, 38] total 135 [2018-11-18 16:16:54,502 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:16:54,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-11-18 16:16:54,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-11-18 16:16:54,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3535, Invalid=14555, Unknown=0, NotChecked=0, Total=18090 [2018-11-18 16:16:54,504 INFO L87 Difference]: Start difference. First operand 3159 states and 3162 transitions. Second operand 98 states. [2018-11-18 16:16:57,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:57,086 INFO L93 Difference]: Finished difference Result 3359 states and 3364 transitions. [2018-11-18 16:16:57,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-18 16:16:57,086 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 3149 [2018-11-18 16:16:57,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:16:57,092 INFO L225 Difference]: With dead ends: 3359 [2018-11-18 16:16:57,092 INFO L226 Difference]: Without dead ends: 3359 [2018-11-18 16:16:57,094 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6451 GetRequests, 6229 SyntacticMatches, 1 SemanticMatches, 221 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15573 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=12575, Invalid=36931, Unknown=0, NotChecked=0, Total=49506 [2018-11-18 16:16:57,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3359 states. [2018-11-18 16:16:57,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3359 to 3352. [2018-11-18 16:16:57,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3352 states. [2018-11-18 16:16:57,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3352 states to 3352 states and 3357 transitions. [2018-11-18 16:16:57,110 INFO L78 Accepts]: Start accepts. Automaton has 3352 states and 3357 transitions. Word has length 3149 [2018-11-18 16:16:57,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:16:57,111 INFO L480 AbstractCegarLoop]: Abstraction has 3352 states and 3357 transitions. [2018-11-18 16:16:57,111 INFO L481 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-11-18 16:16:57,112 INFO L276 IsEmpty]: Start isEmpty. Operand 3352 states and 3357 transitions. [2018-11-18 16:16:57,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3156 [2018-11-18 16:16:57,160 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:16:57,160 INFO L375 BasicCegarLoop]: trace histogram [492, 464, 463, 463, 463, 463, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:57,161 INFO L423 AbstractCegarLoop]: === Iteration 91 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:16:57,161 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:57,161 INFO L82 PathProgramCache]: Analyzing trace with hash -1924320439, now seen corresponding path program 75 times [2018-11-18 16:16:57,161 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:16:57,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:57,162 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:57,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:57,162 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:16:57,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:00,623 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78668 proven. 2759 refuted. 0 times theorem prover too weak. 592690 trivial. 0 not checked. [2018-11-18 16:17:00,623 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:00,623 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:00,623 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:00,624 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:00,624 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:00,624 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:00,634 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:17:00,634 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:17:01,925 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:17:01,925 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:17:01,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:17:05,176 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 16:17:05,176 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:17:08,968 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 16:17:08,993 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:17:08,994 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 31, 31] total 95 [2018-11-18 16:17:08,994 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:17:08,994 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-11-18 16:17:08,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-11-18 16:17:08,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1152, Invalid=7968, Unknown=0, NotChecked=0, Total=9120 [2018-11-18 16:17:08,995 INFO L87 Difference]: Start difference. First operand 3352 states and 3357 transitions. Second operand 66 states. [2018-11-18 16:17:12,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:17:12,659 INFO L93 Difference]: Finished difference Result 3762 states and 3773 transitions. [2018-11-18 16:17:12,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-18 16:17:12,660 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 3155 [2018-11-18 16:17:12,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:17:12,664 INFO L225 Difference]: With dead ends: 3762 [2018-11-18 16:17:12,664 INFO L226 Difference]: Without dead ends: 3762 [2018-11-18 16:17:12,665 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6378 GetRequests, 6250 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3949 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=2010, Invalid=14760, Unknown=0, NotChecked=0, Total=16770 [2018-11-18 16:17:12,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3762 states. [2018-11-18 16:17:12,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3762 to 3735. [2018-11-18 16:17:12,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3735 states. [2018-11-18 16:17:12,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3735 states to 3735 states and 3745 transitions. [2018-11-18 16:17:12,684 INFO L78 Accepts]: Start accepts. Automaton has 3735 states and 3745 transitions. Word has length 3155 [2018-11-18 16:17:12,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:17:12,686 INFO L480 AbstractCegarLoop]: Abstraction has 3735 states and 3745 transitions. [2018-11-18 16:17:12,686 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-11-18 16:17:12,686 INFO L276 IsEmpty]: Start isEmpty. Operand 3735 states and 3745 transitions. [2018-11-18 16:17:12,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3343 [2018-11-18 16:17:12,722 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:17:12,722 INFO L375 BasicCegarLoop]: trace histogram [522, 493, 492, 492, 492, 492, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:17:12,722 INFO L423 AbstractCegarLoop]: === Iteration 92 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:17:12,722 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:17:12,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1701146006, now seen corresponding path program 76 times [2018-11-18 16:17:12,723 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:17:12,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:12,723 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:17:12,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:12,723 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:17:12,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:17,563 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 154707 proven. 12569 refuted. 0 times theorem prover too weak. 592904 trivial. 0 not checked. [2018-11-18 16:17:17,563 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:17,563 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:17,563 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:17,564 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:17,564 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:17,564 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:17,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:17:17,570 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:17:18,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:18,098 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:17:23,056 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 232422 proven. 2324 refuted. 0 times theorem prover too weak. 525434 trivial. 0 not checked. [2018-11-18 16:17:23,056 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:17:28,527 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 159792 proven. 7315 refuted. 0 times theorem prover too weak. 593073 trivial. 0 not checked. [2018-11-18 16:17:28,545 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:17:28,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 60, 60] total 154 [2018-11-18 16:17:28,547 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:17:28,548 INFO L459 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-11-18 16:17:28,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-11-18 16:17:28,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3732, Invalid=19830, Unknown=0, NotChecked=0, Total=23562 [2018-11-18 16:17:28,549 INFO L87 Difference]: Start difference. First operand 3735 states and 3745 transitions. Second operand 125 states. [2018-11-18 16:17:32,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:17:32,534 INFO L93 Difference]: Finished difference Result 3371 states and 3374 transitions. [2018-11-18 16:17:32,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-11-18 16:17:32,536 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 3342 [2018-11-18 16:17:32,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:17:32,541 INFO L225 Difference]: With dead ends: 3371 [2018-11-18 16:17:32,541 INFO L226 Difference]: Without dead ends: 3362 [2018-11-18 16:17:32,544 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6867 GetRequests, 6569 SyntacticMatches, 30 SemanticMatches, 268 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29420 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=11355, Invalid=61275, Unknown=0, NotChecked=0, Total=72630 [2018-11-18 16:17:32,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3362 states. [2018-11-18 16:17:32,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3362 to 3358. [2018-11-18 16:17:32,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3358 states. [2018-11-18 16:17:32,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3358 states to 3358 states and 3361 transitions. [2018-11-18 16:17:32,559 INFO L78 Accepts]: Start accepts. Automaton has 3358 states and 3361 transitions. Word has length 3342 [2018-11-18 16:17:32,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:17:32,561 INFO L480 AbstractCegarLoop]: Abstraction has 3358 states and 3361 transitions. [2018-11-18 16:17:32,561 INFO L481 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-11-18 16:17:32,561 INFO L276 IsEmpty]: Start isEmpty. Operand 3358 states and 3361 transitions. [2018-11-18 16:17:32,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3349 [2018-11-18 16:17:32,598 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:17:32,599 INFO L375 BasicCegarLoop]: trace histogram [523, 494, 493, 493, 493, 493, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:17:32,599 INFO L423 AbstractCegarLoop]: === Iteration 93 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:17:32,599 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:17:32,600 INFO L82 PathProgramCache]: Analyzing trace with hash -2091978354, now seen corresponding path program 77 times [2018-11-18 16:17:32,600 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:17:32,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:32,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:17:32,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:32,600 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:17:32,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:37,455 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 162174 proven. 7923 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 16:17:37,455 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:37,455 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:37,455 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:37,455 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:37,455 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:37,455 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:37,466 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:17:37,466 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:17:41,286 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-11-18 16:17:41,286 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:17:41,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:17:45,478 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 159681 proven. 7893 refuted. 0 times theorem prover too weak. 595619 trivial. 0 not checked. [2018-11-18 16:17:45,479 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:17:50,467 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 159534 proven. 8040 refuted. 0 times theorem prover too weak. 595619 trivial. 0 not checked. [2018-11-18 16:17:50,487 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:17:50,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 39, 39] total 139 [2018-11-18 16:17:50,489 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:17:50,489 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-18 16:17:50,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-18 16:17:50,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3706, Invalid=15476, Unknown=0, NotChecked=0, Total=19182 [2018-11-18 16:17:50,491 INFO L87 Difference]: Start difference. First operand 3358 states and 3361 transitions. Second operand 101 states. [2018-11-18 16:17:53,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:17:53,303 INFO L93 Difference]: Finished difference Result 3564 states and 3569 transitions. [2018-11-18 16:17:53,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-18 16:17:53,305 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 3348 [2018-11-18 16:17:53,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:17:53,309 INFO L225 Difference]: With dead ends: 3564 [2018-11-18 16:17:53,309 INFO L226 Difference]: Without dead ends: 3564 [2018-11-18 16:17:53,312 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6854 GetRequests, 6625 SyntacticMatches, 1 SemanticMatches, 228 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16657 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=13315, Invalid=39355, Unknown=0, NotChecked=0, Total=52670 [2018-11-18 16:17:53,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3564 states. [2018-11-18 16:17:53,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3564 to 3557. [2018-11-18 16:17:53,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3557 states. [2018-11-18 16:17:53,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3557 states to 3557 states and 3562 transitions. [2018-11-18 16:17:53,326 INFO L78 Accepts]: Start accepts. Automaton has 3557 states and 3562 transitions. Word has length 3348 [2018-11-18 16:17:53,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:17:53,328 INFO L480 AbstractCegarLoop]: Abstraction has 3557 states and 3562 transitions. [2018-11-18 16:17:53,328 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-18 16:17:53,328 INFO L276 IsEmpty]: Start isEmpty. Operand 3557 states and 3562 transitions. [2018-11-18 16:17:53,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3355 [2018-11-18 16:17:53,366 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:17:53,367 INFO L375 BasicCegarLoop]: trace histogram [524, 495, 494, 494, 494, 494, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:17:53,367 INFO L423 AbstractCegarLoop]: === Iteration 94 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:17:53,367 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:17:53,367 INFO L82 PathProgramCache]: Analyzing trace with hash 519939286, now seen corresponding path program 78 times [2018-11-18 16:17:53,367 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:17:53,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:53,368 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:17:53,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:17:53,368 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:17:53,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:17:57,173 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 87057 proven. 2959 refuted. 0 times theorem prover too weak. 676196 trivial. 0 not checked. [2018-11-18 16:17:57,173 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:57,173 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:17:57,173 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:17:57,173 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:17:57,173 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:17:57,173 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:17:57,180 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:17:57,180 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:18:05,665 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:18:05,665 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:18:05,704 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:18:09,135 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 16:18:09,135 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:18:13,154 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 16:18:13,195 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:18:13,196 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 32, 32] total 99 [2018-11-18 16:18:13,196 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:18:13,197 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-18 16:18:13,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-18 16:18:13,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1195, Invalid=8705, Unknown=0, NotChecked=0, Total=9900 [2018-11-18 16:18:13,198 INFO L87 Difference]: Start difference. First operand 3557 states and 3562 transitions. Second operand 69 states. [2018-11-18 16:18:16,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:18:16,664 INFO L93 Difference]: Finished difference Result 3979 states and 3990 transitions. [2018-11-18 16:18:16,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-18 16:18:16,666 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3354 [2018-11-18 16:18:16,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:18:16,671 INFO L225 Difference]: With dead ends: 3979 [2018-11-18 16:18:16,671 INFO L226 Difference]: Without dead ends: 3979 [2018-11-18 16:18:16,672 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6779 GetRequests, 6646 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4264 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=2094, Invalid=15996, Unknown=0, NotChecked=0, Total=18090 [2018-11-18 16:18:16,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3979 states. [2018-11-18 16:18:16,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3979 to 3952. [2018-11-18 16:18:16,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3952 states. [2018-11-18 16:18:16,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3952 states to 3952 states and 3962 transitions. [2018-11-18 16:18:16,691 INFO L78 Accepts]: Start accepts. Automaton has 3952 states and 3962 transitions. Word has length 3354 [2018-11-18 16:18:16,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:18:16,693 INFO L480 AbstractCegarLoop]: Abstraction has 3952 states and 3962 transitions. [2018-11-18 16:18:16,693 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-18 16:18:16,693 INFO L276 IsEmpty]: Start isEmpty. Operand 3952 states and 3962 transitions. [2018-11-18 16:18:16,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3548 [2018-11-18 16:18:16,735 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:18:16,735 INFO L375 BasicCegarLoop]: trace histogram [555, 525, 524, 524, 524, 524, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:18:16,735 INFO L423 AbstractCegarLoop]: === Iteration 95 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:18:16,735 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:18:16,736 INFO L82 PathProgramCache]: Analyzing trace with hash -1840250975, now seen corresponding path program 79 times [2018-11-18 16:18:16,736 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:18:16,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:16,736 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:18:16,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:16,737 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:18:16,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:22,124 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 170948 proven. 13452 refuted. 0 times theorem prover too weak. 676603 trivial. 0 not checked. [2018-11-18 16:18:22,124 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:22,124 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:18:22,124 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:18:22,125 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:18:22,125 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:22,125 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:18:22,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:18:22,133 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:18:22,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:22,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:18:28,122 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 256848 proven. 2494 refuted. 0 times theorem prover too weak. 601661 trivial. 0 not checked. [2018-11-18 16:18:28,122 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:18:34,117 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 176403 proven. 7837 refuted. 0 times theorem prover too weak. 676763 trivial. 0 not checked. [2018-11-18 16:18:34,135 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:18:34,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 62, 62] total 159 [2018-11-18 16:18:34,137 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:18:34,138 INFO L459 AbstractCegarLoop]: Interpolant automaton has 129 states [2018-11-18 16:18:34,139 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 129 interpolants. [2018-11-18 16:18:34,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3980, Invalid=21142, Unknown=0, NotChecked=0, Total=25122 [2018-11-18 16:18:34,140 INFO L87 Difference]: Start difference. First operand 3952 states and 3962 transitions. Second operand 129 states. [2018-11-18 16:18:37,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:18:37,805 INFO L93 Difference]: Finished difference Result 3576 states and 3579 transitions. [2018-11-18 16:18:37,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 156 states. [2018-11-18 16:18:37,807 INFO L78 Accepts]: Start accepts. Automaton has 129 states. Word has length 3547 [2018-11-18 16:18:37,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:18:37,811 INFO L225 Difference]: With dead ends: 3576 [2018-11-18 16:18:37,811 INFO L226 Difference]: Without dead ends: 3567 [2018-11-18 16:18:37,815 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7283 GetRequests, 6975 SyntacticMatches, 31 SemanticMatches, 277 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31485 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=12120, Invalid=65442, Unknown=0, NotChecked=0, Total=77562 [2018-11-18 16:18:37,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3567 states. [2018-11-18 16:18:37,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3567 to 3563. [2018-11-18 16:18:37,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3563 states. [2018-11-18 16:18:37,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3563 states to 3563 states and 3566 transitions. [2018-11-18 16:18:37,831 INFO L78 Accepts]: Start accepts. Automaton has 3563 states and 3566 transitions. Word has length 3547 [2018-11-18 16:18:37,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:18:37,833 INFO L480 AbstractCegarLoop]: Abstraction has 3563 states and 3566 transitions. [2018-11-18 16:18:37,833 INFO L481 AbstractCegarLoop]: Interpolant automaton has 129 states. [2018-11-18 16:18:37,833 INFO L276 IsEmpty]: Start isEmpty. Operand 3563 states and 3566 transitions. [2018-11-18 16:18:37,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3554 [2018-11-18 16:18:37,875 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:18:37,876 INFO L375 BasicCegarLoop]: trace histogram [556, 526, 525, 525, 525, 525, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:18:37,876 INFO L423 AbstractCegarLoop]: === Iteration 96 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:18:37,876 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:18:37,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1041675431, now seen corresponding path program 80 times [2018-11-18 16:18:37,877 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:18:37,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:37,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:18:37,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:37,877 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:18:38,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:18:43,284 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 178942 proven. 8466 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 16:18:43,284 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:43,284 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:18:43,285 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:18:43,285 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:18:43,285 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:18:43,285 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:18:43,298 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:18:43,298 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:18:46,411 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-11-18 16:18:46,412 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:18:46,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:18:50,975 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 176273 proven. 8435 refuted. 0 times theorem prover too weak. 679502 trivial. 0 not checked. [2018-11-18 16:18:50,975 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:18:56,365 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 176121 proven. 8587 refuted. 0 times theorem prover too weak. 679502 trivial. 0 not checked. [2018-11-18 16:18:56,384 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:18:56,385 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 40, 40] total 141 [2018-11-18 16:18:56,385 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:18:56,386 INFO L459 AbstractCegarLoop]: Interpolant automaton has 104 states [2018-11-18 16:18:56,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2018-11-18 16:18:56,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3837, Invalid=15903, Unknown=0, NotChecked=0, Total=19740 [2018-11-18 16:18:56,387 INFO L87 Difference]: Start difference. First operand 3563 states and 3566 transitions. Second operand 104 states. [2018-11-18 16:18:59,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:18:59,504 INFO L93 Difference]: Finished difference Result 3775 states and 3780 transitions. [2018-11-18 16:18:59,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2018-11-18 16:18:59,507 INFO L78 Accepts]: Start accepts. Automaton has 104 states. Word has length 3553 [2018-11-18 16:18:59,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:18:59,513 INFO L225 Difference]: With dead ends: 3775 [2018-11-18 16:18:59,513 INFO L226 Difference]: Without dead ends: 3775 [2018-11-18 16:18:59,516 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7269 GetRequests, 7033 SyntacticMatches, 3 SemanticMatches, 233 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17492 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=13967, Invalid=41023, Unknown=0, NotChecked=0, Total=54990 [2018-11-18 16:18:59,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3775 states. [2018-11-18 16:18:59,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3775 to 3768. [2018-11-18 16:18:59,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3768 states. [2018-11-18 16:18:59,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 3773 transitions. [2018-11-18 16:18:59,538 INFO L78 Accepts]: Start accepts. Automaton has 3768 states and 3773 transitions. Word has length 3553 [2018-11-18 16:18:59,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:18:59,540 INFO L480 AbstractCegarLoop]: Abstraction has 3768 states and 3773 transitions. [2018-11-18 16:18:59,540 INFO L481 AbstractCegarLoop]: Interpolant automaton has 104 states. [2018-11-18 16:18:59,540 INFO L276 IsEmpty]: Start isEmpty. Operand 3768 states and 3773 transitions. [2018-11-18 16:18:59,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3560 [2018-11-18 16:18:59,604 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:18:59,604 INFO L375 BasicCegarLoop]: trace histogram [557, 527, 526, 526, 526, 526, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:18:59,605 INFO L423 AbstractCegarLoop]: === Iteration 97 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:18:59,605 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:18:59,605 INFO L82 PathProgramCache]: Analyzing trace with hash -1980793247, now seen corresponding path program 81 times [2018-11-18 16:18:59,605 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:18:59,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:59,606 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:18:59,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:18:59,606 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:18:59,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:03,808 INFO L134 CoverageAnalysis]: Checked inductivity of 867423 backedges. 95657 proven. 3166 refuted. 0 times theorem prover too weak. 768600 trivial. 0 not checked. [2018-11-18 16:19:03,808 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:03,808 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:19:03,808 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:19:03,808 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:19:03,809 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:03,809 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:19:03,819 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 16:19:03,819 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-18 16:19:10,926 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 16:19:10,926 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:19:10,972 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:19:14,734 INFO L134 CoverageAnalysis]: Checked inductivity of 867423 backedges. 95475 proven. 2883 refuted. 0 times theorem prover too weak. 769065 trivial. 0 not checked. [2018-11-18 16:19:14,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:19:19,145 INFO L134 CoverageAnalysis]: Checked inductivity of 867423 backedges. 95475 proven. 2883 refuted. 0 times theorem prover too weak. 769065 trivial. 0 not checked. [2018-11-18 16:19:19,186 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:19:19,188 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 33, 33] total 101 [2018-11-18 16:19:19,188 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:19:19,189 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-18 16:19:19,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-18 16:19:19,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1229, Invalid=9073, Unknown=0, NotChecked=0, Total=10302 [2018-11-18 16:19:19,189 INFO L87 Difference]: Start difference. First operand 3768 states and 3773 transitions. Second operand 70 states. [2018-11-18 16:19:22,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:19:22,758 INFO L93 Difference]: Finished difference Result 4202 states and 4213 transitions. [2018-11-18 16:19:22,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2018-11-18 16:19:22,758 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 3559 [2018-11-18 16:19:22,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:19:22,764 INFO L225 Difference]: With dead ends: 4202 [2018-11-18 16:19:22,765 INFO L226 Difference]: Without dead ends: 4202 [2018-11-18 16:19:22,766 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7190 GetRequests, 7054 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4410 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=2107, Invalid=16799, Unknown=0, NotChecked=0, Total=18906 [2018-11-18 16:19:22,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4202 states. [2018-11-18 16:19:22,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4202 to 4175. [2018-11-18 16:19:22,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4175 states. [2018-11-18 16:19:22,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4175 states to 4175 states and 4185 transitions. [2018-11-18 16:19:22,786 INFO L78 Accepts]: Start accepts. Automaton has 4175 states and 4185 transitions. Word has length 3559 [2018-11-18 16:19:22,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:19:22,788 INFO L480 AbstractCegarLoop]: Abstraction has 4175 states and 4185 transitions. [2018-11-18 16:19:22,788 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-18 16:19:22,788 INFO L276 IsEmpty]: Start isEmpty. Operand 4175 states and 4185 transitions. [2018-11-18 16:19:22,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3759 [2018-11-18 16:19:22,835 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:19:22,835 INFO L375 BasicCegarLoop]: trace histogram [589, 558, 557, 557, 557, 557, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:19:22,835 INFO L423 AbstractCegarLoop]: === Iteration 98 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:19:22,836 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:19:22,836 INFO L82 PathProgramCache]: Analyzing trace with hash -1235349138, now seen corresponding path program 82 times [2018-11-18 16:19:22,836 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:19:22,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:22,837 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:19:22,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:22,837 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:19:23,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:28,736 INFO L134 CoverageAnalysis]: Checked inductivity of 971512 backedges. 188288 proven. 14365 refuted. 0 times theorem prover too weak. 768859 trivial. 0 not checked. [2018-11-18 16:19:28,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:28,737 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:19:28,737 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:19:28,737 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:19:28,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:28,737 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:19:28,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:19:28,746 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 16:19:29,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:29,341 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:19:35,238 INFO L134 CoverageAnalysis]: Checked inductivity of 971512 backedges. 282926 proven. 2670 refuted. 0 times theorem prover too weak. 685916 trivial. 0 not checked. [2018-11-18 16:19:35,238 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:19:41,841 INFO L134 CoverageAnalysis]: Checked inductivity of 971512 backedges. 194126 proven. 8377 refuted. 0 times theorem prover too weak. 769009 trivial. 0 not checked. [2018-11-18 16:19:41,859 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:19:41,861 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 64, 64] total 164 [2018-11-18 16:19:41,861 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:19:41,862 INFO L459 AbstractCegarLoop]: Interpolant automaton has 133 states [2018-11-18 16:19:41,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 133 interpolants. [2018-11-18 16:19:41,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4236, Invalid=22496, Unknown=0, NotChecked=0, Total=26732 [2018-11-18 16:19:41,864 INFO L87 Difference]: Start difference. First operand 4175 states and 4185 transitions. Second operand 133 states. [2018-11-18 16:19:46,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:19:46,091 INFO L93 Difference]: Finished difference Result 3787 states and 3790 transitions. [2018-11-18 16:19:46,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-11-18 16:19:46,093 INFO L78 Accepts]: Start accepts. Automaton has 133 states. Word has length 3758 [2018-11-18 16:19:46,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:19:46,098 INFO L225 Difference]: With dead ends: 3787 [2018-11-18 16:19:46,098 INFO L226 Difference]: Without dead ends: 3778 [2018-11-18 16:19:46,101 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7711 GetRequests, 7393 SyntacticMatches, 32 SemanticMatches, 286 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33620 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=12910, Invalid=69746, Unknown=0, NotChecked=0, Total=82656 [2018-11-18 16:19:46,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3778 states. [2018-11-18 16:19:46,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3778 to 3774. [2018-11-18 16:19:46,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3774 states. [2018-11-18 16:19:46,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3774 states to 3774 states and 3777 transitions. [2018-11-18 16:19:46,116 INFO L78 Accepts]: Start accepts. Automaton has 3774 states and 3777 transitions. Word has length 3758 [2018-11-18 16:19:46,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:19:46,117 INFO L480 AbstractCegarLoop]: Abstraction has 3774 states and 3777 transitions. [2018-11-18 16:19:46,117 INFO L481 AbstractCegarLoop]: Interpolant automaton has 133 states. [2018-11-18 16:19:46,118 INFO L276 IsEmpty]: Start isEmpty. Operand 3774 states and 3777 transitions. [2018-11-18 16:19:46,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3765 [2018-11-18 16:19:46,164 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:19:46,165 INFO L375 BasicCegarLoop]: trace histogram [590, 559, 558, 558, 558, 558, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:19:46,165 INFO L423 AbstractCegarLoop]: === Iteration 99 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:19:46,165 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:19:46,165 INFO L82 PathProgramCache]: Analyzing trace with hash -1748120730, now seen corresponding path program 83 times [2018-11-18 16:19:46,165 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:19:46,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:46,166 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:19:46,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:19:46,166 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:19:46,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:19:52,101 INFO L134 CoverageAnalysis]: Checked inductivity of 974919 backedges. 196827 proven. 9027 refuted. 0 times theorem prover too weak. 769065 trivial. 0 not checked. [2018-11-18 16:19:52,101 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:52,102 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 16:19:52,102 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 16:19:52,102 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 16:19:52,102 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 16:19:52,102 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/z3 Starting monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 16:19:52,111 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 16:19:52,111 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 16:19:57,522 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-11-18 16:19:57,522 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 16:19:57,550 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 16:20:02,454 INFO L134 CoverageAnalysis]: Checked inductivity of 974919 backedges. 193976 proven. 8995 refuted. 0 times theorem prover too weak. 771948 trivial. 0 not checked. [2018-11-18 16:20:02,454 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 16:20:08,259 INFO L134 CoverageAnalysis]: Checked inductivity of 974919 backedges. 193819 proven. 9152 refuted. 0 times theorem prover too weak. 771948 trivial. 0 not checked. [2018-11-18 16:20:08,290 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-18 16:20:08,291 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 41, 41] total 142 [2018-11-18 16:20:08,291 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 16:20:08,292 INFO L459 AbstractCegarLoop]: Interpolant automaton has 107 states [2018-11-18 16:20:08,293 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2018-11-18 16:20:08,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3964, Invalid=16058, Unknown=0, NotChecked=0, Total=20022 [2018-11-18 16:20:08,294 INFO L87 Difference]: Start difference. First operand 3774 states and 3777 transitions. Second operand 107 states. [2018-11-18 16:20:12,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:20:12,023 INFO L93 Difference]: Finished difference Result 3992 states and 3997 transitions. [2018-11-18 16:20:12,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-11-18 16:20:12,023 INFO L78 Accepts]: Start accepts. Automaton has 107 states. Word has length 3764 [2018-11-18 16:20:12,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 16:20:12,029 INFO L225 Difference]: With dead ends: 3992 [2018-11-18 16:20:12,030 INFO L226 Difference]: Without dead ends: 3992 [2018-11-18 16:20:12,033 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7696 GetRequests, 7453 SyntacticMatches, 6 SemanticMatches, 237 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18963 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=14033, Invalid=42849, Unknown=0, NotChecked=0, Total=56882 [2018-11-18 16:20:12,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3992 states. [2018-11-18 16:20:12,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3992 to 3985. [2018-11-18 16:20:12,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3985 states. [2018-11-18 16:20:12,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3985 states to 3985 states and 3990 transitions. [2018-11-18 16:20:12,051 INFO L78 Accepts]: Start accepts. Automaton has 3985 states and 3990 transitions. Word has length 3764 [2018-11-18 16:20:12,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 16:20:12,053 INFO L480 AbstractCegarLoop]: Abstraction has 3985 states and 3990 transitions. [2018-11-18 16:20:12,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 107 states. [2018-11-18 16:20:12,053 INFO L276 IsEmpty]: Start isEmpty. Operand 3985 states and 3990 transitions. [2018-11-18 16:20:12,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3771 [2018-11-18 16:20:12,100 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 16:20:12,101 INFO L375 BasicCegarLoop]: trace histogram [591, 560, 559, 559, 559, 559, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:20:12,101 INFO L423 AbstractCegarLoop]: === Iteration 100 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-11-18 16:20:12,101 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:20:12,101 INFO L82 PathProgramCache]: Analyzing trace with hash -288406354, now seen corresponding path program 84 times [2018-11-18 16:20:12,101 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 16:20:12,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:20:12,102 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:20:12,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:20:12,102 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 16:20:12,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:20:13,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:20:14,563 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 16:20:15,053 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 04:20:15 BoogieIcfgContainer [2018-11-18 16:20:15,053 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 16:20:15,053 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 16:20:15,053 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 16:20:15,053 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 16:20:15,054 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:08:52" (3/4) ... [2018-11-18 16:20:15,063 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 16:20:15,442 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_286c1fcb-91eb-4dd1-bddb-0f14c1cd69f6/bin-2019/utaipan/witness.graphml [2018-11-18 16:20:15,443 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 16:20:15,446 INFO L168 Benchmark]: Toolchain (without parser) took 683538.68 ms. Allocated memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: 4.1 GB). Free memory was 959.6 MB in the beginning and 2.0 GB in the end (delta: -1.1 GB). Peak memory consumption was 3.0 GB. Max. memory is 11.5 GB. [2018-11-18 16:20:15,447 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 16:20:15,447 INFO L168 Benchmark]: CACSL2BoogieTranslator took 194.71 ms. Allocated memory is still 1.0 GB. Free memory was 959.6 MB in the beginning and 948.9 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:15,447 INFO L168 Benchmark]: Boogie Procedure Inliner took 17.86 ms. Allocated memory is still 1.0 GB. Free memory was 948.9 MB in the beginning and 946.2 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:15,447 INFO L168 Benchmark]: Boogie Preprocessor took 24.02 ms. Allocated memory is still 1.0 GB. Free memory is still 946.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 16:20:15,447 INFO L168 Benchmark]: RCFGBuilder took 314.82 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.8 MB). Free memory was 946.2 MB in the beginning and 1.1 GB in the end (delta: -190.8 MB). Peak memory consumption was 17.5 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:15,448 INFO L168 Benchmark]: TraceAbstraction took 682591.56 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: -993.0 MB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. [2018-11-18 16:20:15,448 INFO L168 Benchmark]: Witness Printer took 389.46 ms. Allocated memory is still 5.1 GB. Free memory was 2.1 GB in the beginning and 2.0 GB in the end (delta: 83.9 MB). Peak memory consumption was 83.9 MB. Max. memory is 11.5 GB. [2018-11-18 16:20:15,449 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 194.71 ms. Allocated memory is still 1.0 GB. Free memory was 959.6 MB in the beginning and 948.9 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 17.86 ms. Allocated memory is still 1.0 GB. Free memory was 948.9 MB in the beginning and 946.2 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.02 ms. Allocated memory is still 1.0 GB. Free memory is still 946.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 314.82 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.8 MB). Free memory was 946.2 MB in the beginning and 1.1 GB in the end (delta: -190.8 MB). Peak memory consumption was 17.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 682591.56 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: -993.0 MB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. * Witness Printer took 389.46 ms. Allocated memory is still 5.1 GB. Free memory was 2.1 GB in the beginning and 2.0 GB in the end (delta: 83.9 MB). Peak memory consumption was 83.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; [L26] i = 0 VAL [b={159:0}, i=0, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=0, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=160, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=131, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L20] RET return i; VAL [\old(size)=1, \result=2, b={143:0}, b={143:0}, i=2, size=1] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=2, i=0, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=2, i=0, mask={143:0}] [L26] i++ VAL [b={159:0}, i=1, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=1, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=160, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=131, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=133, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L20] RET return i; VAL [\old(size)=2, \result=3, b={143:0}, b={143:0}, i=3, size=2] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=3, i=1, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=3, i=1, mask={143:0}] [L26] i++ VAL [b={159:0}, i=2, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=2, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=160, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=131, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=133, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=135, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L20] RET return i; VAL [\old(size)=3, \result=4, b={143:0}, b={143:0}, i=4, size=3] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=4, i=2, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=4, i=2, mask={143:0}] [L26] i++ VAL [b={159:0}, i=3, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=3, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=160, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=131, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=133, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=135, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=151, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L20] RET return i; VAL [\old(size)=4, \result=5, b={143:0}, b={143:0}, i=5, size=4] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=5, i=3, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=5, i=3, mask={143:0}] [L26] i++ VAL [b={159:0}, i=4, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=4, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=160, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=131, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=133, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=135, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=151, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=137, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L20] RET return i; VAL [\old(size)=5, \result=6, b={143:0}, b={143:0}, i=6, size=5] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=6, i=4, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=6, i=4, mask={143:0}] [L26] i++ VAL [b={159:0}, i=5, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=5, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=160, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=131, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=133, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=135, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=151, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=137, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=136, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L20] RET return i; VAL [\old(size)=6, \result=7, b={143:0}, b={143:0}, i=7, size=6] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=7, i=5, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=7, i=5, mask={143:0}] [L26] i++ VAL [b={159:0}, i=6, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=6, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=160, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=131, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=133, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=135, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=151, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=137, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=136, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=154, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L20] RET return i; VAL [\old(size)=7, \result=8, b={143:0}, b={143:0}, i=8, size=7] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=8, i=6, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=8, i=6, mask={143:0}] [L26] i++ VAL [b={159:0}, i=7, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=7, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=160, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=131, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=133, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=135, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=151, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=137, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=136, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=154, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=132, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L20] RET return i; VAL [\old(size)=8, \result=9, b={143:0}, b={143:0}, i=9, size=8] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=9, i=7, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=9, i=7, mask={143:0}] [L26] i++ VAL [b={159:0}, i=8, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=8, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=160, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=131, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=133, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=135, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=151, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=137, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=136, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=154, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=132, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=138, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L20] RET return i; VAL [\old(size)=9, \result=10, b={143:0}, b={143:0}, i=10, size=9] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=10, i=8, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=10, i=8, mask={143:0}] [L26] i++ VAL [b={159:0}, i=9, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=9, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=160, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=131, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=133, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=135, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=151, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=137, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=136, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=154, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=132, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=138, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L20] RET return i; VAL [\old(size)=10, \result=11, b={143:0}, b={143:0}, i=11, size=10] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=11, i=9, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=11, i=9, mask={143:0}] [L26] i++ VAL [b={159:0}, i=10, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=10, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=160, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=131, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=133, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=135, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=151, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=137, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=136, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=154, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=132, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=138, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=129, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L20] RET return i; VAL [\old(size)=11, \result=12, b={143:0}, b={143:0}, i=12, size=11] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=12, i=10, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=12, i=10, mask={143:0}] [L26] i++ VAL [b={159:0}, i=11, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=11, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=160, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=131, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=133, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=135, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=151, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=137, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=136, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=154, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=132, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=138, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=129, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=144, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L20] RET return i; VAL [\old(size)=12, \result=13, b={143:0}, b={143:0}, i=13, size=12] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=13, i=11, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=13, i=11, mask={143:0}] [L26] i++ VAL [b={159:0}, i=12, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=12, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=160, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=131, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=133, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=135, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=151, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=137, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=136, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=154, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=132, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=138, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=129, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=144, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=134, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L20] RET return i; VAL [\old(size)=13, \result=14, b={143:0}, b={143:0}, i=14, size=13] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=14, i=12, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=14, i=12, mask={143:0}] [L26] i++ VAL [b={159:0}, i=13, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=13, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=160, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=131, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=133, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=135, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=151, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=137, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=136, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=154, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=132, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=138, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=129, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=144, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=134, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=155, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L20] RET return i; VAL [\old(size)=14, \result=15, b={143:0}, b={143:0}, i=15, size=14] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=15, i=13, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=15, i=13, mask={143:0}] [L26] i++ VAL [b={159:0}, i=14, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=14, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=160, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=131, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=133, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=135, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=151, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=137, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=136, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=154, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=132, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=138, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=129, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=144, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=134, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=155, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=142, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L20] RET return i; VAL [\old(size)=15, \result=16, b={143:0}, b={143:0}, i=16, size=15] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=16, i=14, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=16, i=14, mask={143:0}] [L26] i++ VAL [b={159:0}, i=15, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=15, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=160, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=131, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=133, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=135, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=151, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=137, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=136, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=154, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=132, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=138, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=129, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=144, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=134, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=155, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=142, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=148, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L20] RET return i; VAL [\old(size)=16, \result=17, b={143:0}, b={143:0}, i=17, size=16] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=17, i=15, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=17, i=15, mask={143:0}] [L26] i++ VAL [b={159:0}, i=16, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=16, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=160, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=131, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=133, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=135, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=151, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=137, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=136, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=154, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=132, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=138, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=129, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=144, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=134, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=155, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=142, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=148, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=163, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L20] RET return i; VAL [\old(size)=17, \result=18, b={143:0}, b={143:0}, i=18, size=17] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=18, i=16, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=18, i=16, mask={143:0}] [L26] i++ VAL [b={159:0}, i=17, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=17, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=160, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=131, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=133, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=135, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=151, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=137, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=136, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=154, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=132, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=138, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=129, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=144, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=134, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=155, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=142, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=148, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=163, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=146, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L20] RET return i; VAL [\old(size)=18, \result=19, b={143:0}, b={143:0}, i=19, size=18] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=19, i=17, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=19, i=17, mask={143:0}] [L26] i++ VAL [b={159:0}, i=18, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=18, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=160, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=131, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=133, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=135, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=151, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=137, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=136, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=154, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=132, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=138, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=129, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=144, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=134, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=155, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=142, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=148, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=163, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=146, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=140, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L20] RET return i; VAL [\old(size)=19, \result=20, b={143:0}, b={143:0}, i=20, size=19] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=20, i=18, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=20, i=18, mask={143:0}] [L26] i++ VAL [b={159:0}, i=19, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=19, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=160, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=131, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=133, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=135, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=151, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=137, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=136, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=154, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=132, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=138, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=129, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=144, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=134, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=155, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=142, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=148, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=163, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=146, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=140, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=156, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L20] RET return i; VAL [\old(size)=20, \result=21, b={143:0}, b={143:0}, i=21, size=20] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=21, i=19, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=21, i=19, mask={143:0}] [L26] i++ VAL [b={159:0}, i=20, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=20, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=160, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=131, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=133, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=135, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=151, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=137, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=136, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=154, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=132, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=138, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=129, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=144, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=134, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=155, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=142, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=148, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=163, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=146, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=140, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=156, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=139, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L20] RET return i; VAL [\old(size)=21, \result=22, b={143:0}, b={143:0}, i=22, size=21] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=22, i=20, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=22, i=20, mask={143:0}] [L26] i++ VAL [b={159:0}, i=21, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=21, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=160, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=131, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=133, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=135, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=151, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=137, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=136, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=154, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=132, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=138, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=129, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=144, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=134, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=155, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=142, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=148, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=163, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=146, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=140, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=156, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=139, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=157, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L20] RET return i; VAL [\old(size)=22, \result=23, b={143:0}, b={143:0}, i=23, size=22] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=23, i=21, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=23, i=21, mask={143:0}] [L26] i++ VAL [b={159:0}, i=22, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=22, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=160, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=131, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=133, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=135, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=151, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=137, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=136, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=154, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=132, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=138, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=129, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=144, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=134, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=155, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=142, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=148, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=163, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=146, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=140, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=156, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=139, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=157, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=152, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L20] RET return i; VAL [\old(size)=23, \result=24, b={143:0}, b={143:0}, i=24, size=23] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=24, i=22, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=24, i=22, mask={143:0}] [L26] i++ VAL [b={159:0}, i=23, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=23, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=160, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=131, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=133, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=135, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=151, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=137, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=136, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=154, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=132, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=138, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=129, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=144, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=134, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=155, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=142, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=148, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=163, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=146, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=140, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=156, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=139, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=157, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=152, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=162, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L20] RET return i; VAL [\old(size)=24, \result=25, b={143:0}, b={143:0}, i=25, size=24] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=25, i=23, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=25, i=23, mask={143:0}] [L26] i++ VAL [b={159:0}, i=24, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=24, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=160, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=131, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=133, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=135, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=151, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=137, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=136, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=154, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=132, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=138, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=129, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=144, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=134, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=155, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=142, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=148, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=163, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=146, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=140, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=156, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=139, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=157, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=152, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=162, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=164, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L20] RET return i; VAL [\old(size)=25, \result=26, b={143:0}, b={143:0}, i=26, size=25] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=26, i=24, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=26, i=24, mask={143:0}] [L26] i++ VAL [b={159:0}, i=25, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=25, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=160, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=131, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=133, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=135, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=151, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=137, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=136, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=154, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=132, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=138, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=129, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=144, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=134, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=155, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=142, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=148, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=163, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=146, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=140, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=156, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=139, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=157, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=152, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=162, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=164, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=161, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L20] RET return i; VAL [\old(size)=26, \result=27, b={143:0}, b={143:0}, i=27, size=26] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=27, i=25, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=27, i=25, mask={143:0}] [L26] i++ VAL [b={159:0}, i=26, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=26, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=160, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=131, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=133, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=135, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=151, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=137, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=136, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=154, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=132, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=138, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=129, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=144, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=134, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=155, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=142, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=148, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=163, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=146, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=140, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=156, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=139, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=157, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=152, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=162, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=164, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=161, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=141, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L20] RET return i; VAL [\old(size)=27, \result=28, b={143:0}, b={143:0}, i=28, size=27] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=28, i=26, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=28, i=26, mask={143:0}] [L26] i++ VAL [b={159:0}, i=27, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=27, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=160, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=131, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=133, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=135, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=151, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=137, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=136, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=154, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=132, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=138, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=129, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=144, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=134, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=155, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=142, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=148, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=163, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=146, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=140, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=156, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=139, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=157, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=152, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=162, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=164, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=161, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=141, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=130, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L20] RET return i; VAL [\old(size)=28, \result=29, b={143:0}, b={143:0}, i=29, size=28] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=29, i=27, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=29, i=27, mask={143:0}] [L26] i++ VAL [b={159:0}, i=28, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=28, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=160, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=131, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=133, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=135, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=151, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=137, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=136, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=154, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=132, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=138, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=129, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=144, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=134, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=155, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=142, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=148, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=163, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=146, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=140, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=156, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=139, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=157, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=152, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=162, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=164, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=161, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=141, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=130, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=147, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L20] RET return i; VAL [\old(size)=29, \result=30, b={143:0}, b={143:0}, i=30, size=29] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=30, i=28, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=30, i=28, mask={143:0}] [L26] i++ VAL [b={159:0}, i=29, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=29, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=160, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=131, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=133, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=135, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=151, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=137, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=136, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=154, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=132, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=138, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=129, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=144, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=134, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=155, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=142, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=148, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=163, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=146, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=140, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=156, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=139, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=157, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=152, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=162, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=164, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=161, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=141, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=130, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=147, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=153, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L20] RET return i; VAL [\old(size)=30, \result=31, b={143:0}, b={143:0}, i=31, size=30] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=31, i=29, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=31, i=29, mask={143:0}] [L26] i++ VAL [b={159:0}, i=30, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=30, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=160, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=131, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=133, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=135, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=151, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=137, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=136, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=154, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=132, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=138, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=129, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=144, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=134, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=155, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=142, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=148, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=163, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=146, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=140, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=156, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=139, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=157, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=152, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=162, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=164, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=161, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=141, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=130, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=147, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=153, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=145, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L20] RET return i; VAL [\old(size)=31, \result=32, b={143:0}, b={143:0}, i=32, size=31] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=32, i=30, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=32, i=30, mask={143:0}] [L26] i++ VAL [b={159:0}, i=31, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=31, mask={143:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={143:0}, b={143:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=0, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=160, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=1, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=131, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=2, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=133, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=3, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=135, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=4, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=151, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=5, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=137, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=6, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=136, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=7, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=154, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=8, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=132, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=9, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=138, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=10, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=150, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=11, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=129, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=12, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=144, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=13, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=134, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=14, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=155, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=15, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=142, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=16, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=148, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=17, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=163, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=18, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=146, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=19, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=140, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=20, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=156, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=21, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=139, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=22, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=157, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=23, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=152, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=24, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=162, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=25, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=164, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=26, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=161, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=27, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=141, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=28, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=130, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=29, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=147, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=30, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=153, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=31, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=145, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 43 locations, 8 error locations. UNSAFE Result, 682.5s OverallTime, 100 OverallIterations, 591 TraceHistogramMax, 157.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5220 SDtfs, 81040 SDslu, 87779 SDs, 0 SdLazy, 240614 SolverSat, 12746 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 65.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 271439 GetRequests, 259361 SyntacticMatches, 954 SemanticMatches, 11124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 632338 ImplicationChecksByTransitivity, 220.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=4175occurred in iteration=97, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.8s AbstIntTime, 5 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.9s AutomataMinimizationTime, 99 MinimizatonAttempts, 1112 StatesRemovedByMinimization, 95 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 5.0s SsaConstructionTime, 73.8s SatisfiabilityAnalysisTime, 349.3s InterpolantComputationTime, 267840 NumberOfCodeBlocks, 240283 NumberOfCodeBlocksAsserted, 722 NumberOfCheckSat, 395714 ConstructedInterpolants, 54 QuantifiedInterpolants, 1350448944 SizeOfPredicates, 262 NumberOfNonLiveVariables, 237521 ConjunctsInSsa, 2932 ConjunctsInUnsatCore, 279 InterpolantComputations, 9 PerfectInterpolantSequences, 59872305/60555255 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...