./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/loop-acceleration/phases_true-unreach-call2_false-termination.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/loop-acceleration/phases_true-unreach-call2_false-termination.i -s /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4a156731963582ce9a466285688eba3a68b58029 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: TRUE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 10:21:47,003 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 10:21:47,004 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 10:21:47,011 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 10:21:47,011 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 10:21:47,012 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 10:21:47,012 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 10:21:47,014 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 10:21:47,015 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 10:21:47,015 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 10:21:47,016 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 10:21:47,016 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 10:21:47,017 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 10:21:47,018 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 10:21:47,018 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 10:21:47,019 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 10:21:47,019 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 10:21:47,025 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 10:21:47,026 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 10:21:47,027 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 10:21:47,028 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 10:21:47,029 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 10:21:47,030 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 10:21:47,030 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 10:21:47,030 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 10:21:47,031 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 10:21:47,032 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 10:21:47,032 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 10:21:47,033 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 10:21:47,034 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 10:21:47,034 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 10:21:47,034 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 10:21:47,034 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 10:21:47,034 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 10:21:47,035 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 10:21:47,036 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 10:21:47,036 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-18 10:21:47,045 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 10:21:47,046 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 10:21:47,046 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 10:21:47,046 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-18 10:21:47,046 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-18 10:21:47,047 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-18 10:21:47,047 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-18 10:21:47,048 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 10:21:47,048 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 10:21:47,048 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 10:21:47,048 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 10:21:47,048 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 10:21:47,049 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 10:21:47,049 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 10:21:47,050 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-18 10:21:47,050 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4a156731963582ce9a466285688eba3a68b58029 [2018-11-18 10:21:47,072 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 10:21:47,080 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 10:21:47,082 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 10:21:47,083 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 10:21:47,083 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 10:21:47,084 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/../../sv-benchmarks/c/loop-acceleration/phases_true-unreach-call2_false-termination.i [2018-11-18 10:21:47,120 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/data/d3b1a7d68/693d78c6f8ad460080f9d8b3cbc5dff5/FLAG1d2797d61 [2018-11-18 10:21:47,524 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 10:21:47,524 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/sv-benchmarks/c/loop-acceleration/phases_true-unreach-call2_false-termination.i [2018-11-18 10:21:47,529 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/data/d3b1a7d68/693d78c6f8ad460080f9d8b3cbc5dff5/FLAG1d2797d61 [2018-11-18 10:21:47,538 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/data/d3b1a7d68/693d78c6f8ad460080f9d8b3cbc5dff5 [2018-11-18 10:21:47,541 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 10:21:47,542 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 10:21:47,543 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 10:21:47,543 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 10:21:47,545 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 10:21:47,546 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,548 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@88e9939 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47, skipping insertion in model container [2018-11-18 10:21:47,548 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,557 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 10:21:47,574 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 10:21:47,682 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:21:47,684 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 10:21:47,693 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:21:47,702 INFO L195 MainTranslator]: Completed translation [2018-11-18 10:21:47,702 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47 WrapperNode [2018-11-18 10:21:47,702 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 10:21:47,703 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 10:21:47,703 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 10:21:47,703 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 10:21:47,708 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,710 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,714 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 10:21:47,714 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 10:21:47,714 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 10:21:47,714 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 10:21:47,720 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,720 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,721 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,721 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,723 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,726 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,726 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... [2018-11-18 10:21:47,727 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 10:21:47,727 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 10:21:47,727 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 10:21:47,727 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 10:21:47,728 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 10:21:47,802 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 10:21:47,802 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 10:21:47,802 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 10:21:47,802 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 10:21:47,802 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 10:21:47,803 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 10:21:47,803 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-18 10:21:47,803 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-18 10:21:47,898 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 10:21:47,899 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:21:47 BoogieIcfgContainer [2018-11-18 10:21:47,899 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 10:21:47,899 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 10:21:47,899 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 10:21:47,901 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 10:21:47,902 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 10:21:47" (1/3) ... [2018-11-18 10:21:47,902 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@466bf98e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 10:21:47, skipping insertion in model container [2018-11-18 10:21:47,902 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:21:47" (2/3) ... [2018-11-18 10:21:47,902 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@466bf98e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 10:21:47, skipping insertion in model container [2018-11-18 10:21:47,903 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:21:47" (3/3) ... [2018-11-18 10:21:47,904 INFO L112 eAbstractionObserver]: Analyzing ICFG phases_true-unreach-call2_false-termination.i [2018-11-18 10:21:47,910 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 10:21:47,915 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 10:21:47,926 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 10:21:47,947 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 10:21:47,947 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 10:21:47,947 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 10:21:47,947 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 10:21:47,947 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 10:21:47,947 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 10:21:47,947 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 10:21:47,947 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 10:21:47,958 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states. [2018-11-18 10:21:47,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-18 10:21:47,962 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:21:47,962 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:21:47,964 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 10:21:47,967 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:47,967 INFO L82 PathProgramCache]: Analyzing trace with hash -1994259344, now seen corresponding path program 1 times [2018-11-18 10:21:47,968 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 10:21:48,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:48,000 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:48,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:48,000 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 10:21:48,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:48,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:21:48,039 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:21:48,039 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:21:48,039 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 10:21:48,042 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 10:21:48,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 10:21:48,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 10:21:48,052 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 2 states. [2018-11-18 10:21:48,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:21:48,066 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2018-11-18 10:21:48,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 10:21:48,067 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 11 [2018-11-18 10:21:48,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:21:48,072 INFO L225 Difference]: With dead ends: 31 [2018-11-18 10:21:48,073 INFO L226 Difference]: Without dead ends: 14 [2018-11-18 10:21:48,075 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 10:21:48,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-11-18 10:21:48,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-11-18 10:21:48,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-18 10:21:48,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2018-11-18 10:21:48,102 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 15 transitions. Word has length 11 [2018-11-18 10:21:48,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:21:48,103 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 15 transitions. [2018-11-18 10:21:48,103 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 10:21:48,103 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 15 transitions. [2018-11-18 10:21:48,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-18 10:21:48,103 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:21:48,104 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:21:48,104 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 10:21:48,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:48,104 INFO L82 PathProgramCache]: Analyzing trace with hash -2119643788, now seen corresponding path program 1 times [2018-11-18 10:21:48,104 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 10:21:48,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:48,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:48,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:48,105 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 10:21:48,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:48,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:21:48,358 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:21:48,358 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-18 10:21:48,358 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 10:21:48,359 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 10:21:48,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 10:21:48,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-18 10:21:48,360 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. Second operand 7 states. [2018-11-18 10:21:50,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:21:50,411 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2018-11-18 10:21:50,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 10:21:50,412 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 12 [2018-11-18 10:21:50,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:21:50,413 INFO L225 Difference]: With dead ends: 22 [2018-11-18 10:21:50,413 INFO L226 Difference]: Without dead ends: 17 [2018-11-18 10:21:50,414 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-18 10:21:50,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2018-11-18 10:21:50,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 16. [2018-11-18 10:21:50,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-18 10:21:50,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2018-11-18 10:21:50,417 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 17 transitions. Word has length 12 [2018-11-18 10:21:50,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:21:50,417 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 17 transitions. [2018-11-18 10:21:50,417 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 10:21:50,417 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 17 transitions. [2018-11-18 10:21:50,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-18 10:21:50,417 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:21:50,418 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:21:50,418 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 10:21:50,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:50,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1430769513, now seen corresponding path program 1 times [2018-11-18 10:21:50,418 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 10:21:50,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:50,419 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:50,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:50,419 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 10:21:50,424 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-11-18 10:21:50,424 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-11-18 10:21:50,424 INFO L169 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-11-18 10:21:50,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:50,430 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-11-18 10:21:50,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:50,451 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 16 with the following transitions: [2018-11-18 10:21:50,452 INFO L202 CegarAbsIntRunner]: [0], [4], [8], [12], [16], [18], [21], [30], [33], [35], [41], [42], [43], [45] [2018-11-18 10:21:50,476 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 10:21:50,476 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 10:21:50,573 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 10:21:50,574 INFO L272 AbstractInterpreter]: Visited 14 different actions 14 times. Never merged. Never widened. Performed 20 root evaluator evaluations with a maximum evaluation depth of 9. Performed 20 inverse root evaluator evaluations with a maximum inverse evaluation depth of 9. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-11-18 10:21:50,581 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:50,581 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 10:21:50,581 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:21:50,581 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:21:50,587 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:50,588 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 10:21:50,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:50,600 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:21:50,624 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:21:50,625 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 10:21:52,709 WARN L854 $PredicateComparison]: unable to prove that (forall ((main_~y~0 Int)) (let ((.cse0 (mod main_~y~0 4294967296))) (or (< (mod (* c_main_~x~0 c_main_~x~0) 4294967296) .cse0) (<= .cse0 (mod c_main_~x~0 4294967296))))) is different from true [2018-11-18 10:21:52,720 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 2 not checked. [2018-11-18 10:21:52,735 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 10:21:52,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-18 10:21:52,736 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 10:21:52,736 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 10:21:52,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 10:21:52,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=18, Unknown=2, NotChecked=8, Total=42 [2018-11-18 10:21:52,737 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. Second operand 4 states. [2018-11-18 10:21:54,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:21:54,757 INFO L93 Difference]: Finished difference Result 24 states and 26 transitions. [2018-11-18 10:21:54,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 10:21:54,758 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-11-18 10:21:54,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:21:54,758 INFO L225 Difference]: With dead ends: 24 [2018-11-18 10:21:54,758 INFO L226 Difference]: Without dead ends: 19 [2018-11-18 10:21:54,759 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=14, Invalid=18, Unknown=2, NotChecked=8, Total=42 [2018-11-18 10:21:54,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-11-18 10:21:54,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 17. [2018-11-18 10:21:54,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-18 10:21:54,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 19 transitions. [2018-11-18 10:21:54,762 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 19 transitions. Word has length 15 [2018-11-18 10:21:54,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:21:54,762 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 19 transitions. [2018-11-18 10:21:54,762 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 10:21:54,762 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 19 transitions. [2018-11-18 10:21:54,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-18 10:21:54,763 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:21:54,763 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:21:54,763 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 10:21:54,763 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:54,763 INFO L82 PathProgramCache]: Analyzing trace with hash -1089190421, now seen corresponding path program 1 times [2018-11-18 10:21:54,764 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 10:21:54,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:54,764 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:54,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:54,764 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 10:21:54,767 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-11-18 10:21:54,767 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-11-18 10:21:54,767 INFO L169 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-11-18 10:21:54,778 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:54,778 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-11-18 10:21:54,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:54,797 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 16 with the following transitions: [2018-11-18 10:21:54,797 INFO L202 CegarAbsIntRunner]: [0], [4], [8], [12], [16], [18], [23], [30], [33], [35], [41], [42], [43], [45] [2018-11-18 10:21:54,798 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 10:21:54,798 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 10:21:54,863 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 10:21:54,863 INFO L272 AbstractInterpreter]: Visited 14 different actions 38 times. Merged at 4 different actions 12 times. Never widened. Performed 82 root evaluator evaluations with a maximum evaluation depth of 10. Performed 82 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 1 fixpoints after 1 different actions. Largest state had 4 variables. [2018-11-18 10:21:54,874 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:54,874 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 10:21:54,874 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:21:54,874 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:21:54,882 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:54,882 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 10:21:54,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:54,892 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:21:54,968 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:21:54,968 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 10:21:55,031 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:21:55,050 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 10:21:55,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 13 [2018-11-18 10:21:55,050 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 10:21:55,051 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 10:21:55,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 10:21:55,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-18 10:21:55,051 INFO L87 Difference]: Start difference. First operand 17 states and 19 transitions. Second operand 7 states. [2018-11-18 10:21:59,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:21:59,597 INFO L93 Difference]: Finished difference Result 24 states and 26 transitions. [2018-11-18 10:21:59,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 10:21:59,597 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 15 [2018-11-18 10:21:59,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:21:59,598 INFO L225 Difference]: With dead ends: 24 [2018-11-18 10:21:59,598 INFO L226 Difference]: Without dead ends: 19 [2018-11-18 10:21:59,599 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 17 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2018-11-18 10:21:59,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-11-18 10:21:59,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-11-18 10:21:59,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-18 10:21:59,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2018-11-18 10:21:59,602 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 21 transitions. Word has length 15 [2018-11-18 10:21:59,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:21:59,602 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 21 transitions. [2018-11-18 10:21:59,602 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 10:21:59,602 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 21 transitions. [2018-11-18 10:21:59,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-18 10:21:59,602 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:21:59,602 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:21:59,603 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 10:21:59,603 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:59,603 INFO L82 PathProgramCache]: Analyzing trace with hash -759205998, now seen corresponding path program 1 times [2018-11-18 10:21:59,603 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 10:21:59,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:59,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:59,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:21:59,604 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 10:21:59,606 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-11-18 10:21:59,606 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-11-18 10:21:59,606 INFO L169 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-11-18 10:21:59,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:59,614 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-11-18 10:21:59,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:59,632 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 19 with the following transitions: [2018-11-18 10:21:59,632 INFO L202 CegarAbsIntRunner]: [0], [4], [8], [12], [16], [18], [21], [23], [30], [33], [35], [41], [42], [43], [45] [2018-11-18 10:21:59,633 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 10:21:59,633 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 10:21:59,710 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 10:21:59,710 INFO L272 AbstractInterpreter]: Visited 15 different actions 42 times. Merged at 5 different actions 12 times. Never widened. Performed 106 root evaluator evaluations with a maximum evaluation depth of 10. Performed 106 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 2 different actions. Largest state had 4 variables. [2018-11-18 10:21:59,711 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:21:59,712 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 10:21:59,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:21:59,712 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:21:59,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:21:59,728 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 10:21:59,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:21:59,741 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:21:59,802 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:21:59,802 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 10:22:02,046 WARN L832 $PredicateComparison]: unable to prove that (let ((.cse217 (mod c_main_~x~0 4294967296))) (let ((.cse69 (forall ((v_prenex_69 Int)) (let ((.cse224 (mod v_prenex_69 4294967296)) (.cse222 (mod c_main_~x~0 4294967296))) (let ((.cse223 (div .cse224 .cse222)) (.cse225 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse222 (mod (+ .cse223 1) 4294967296)) (<= 0 .cse224) (<= .cse224 .cse225) (< .cse222 (mod (+ .cse223 4294967295) 4294967296)) (<= (mod (div .cse224 .cse225) 4294967296) .cse225) (= (mod .cse224 .cse222) 0)))))) (.cse70 (forall ((v_prenex_69 Int)) (let ((.cse220 (mod v_prenex_69 4294967296)) (.cse218 (mod c_main_~x~0 4294967296))) (let ((.cse219 (div .cse220 .cse218)) (.cse221 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse218 (mod (+ .cse219 1) 4294967296)) (< .cse218 (mod .cse219 4294967296)) (<= 0 .cse220) (<= .cse220 .cse221) (< .cse218 (mod (+ .cse219 4294967295) 4294967296)) (<= (mod (div .cse220 .cse221) 4294967296) .cse221) (= (mod .cse220 .cse218) 0)))))) (.cse0 (< .cse217 0)) (.cse5 (<= 0 .cse217))) (and (or .cse0 (forall ((v_prenex_51 Int)) (let ((.cse3 (mod v_prenex_51 4294967296)) (.cse1 (mod c_main_~x~0 4294967296))) (let ((.cse2 (div .cse3 .cse1)) (.cse4 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse1 (mod (+ .cse2 1) 4294967296)) (< .cse1 (mod .cse2 4294967296)) (<= .cse3 .cse4) (not (= (mod .cse3 .cse1) 0)) (<= (mod (div .cse3 .cse4) 4294967296) .cse4)))))) (or .cse5 (forall ((v_prenex_69 Int)) (let ((.cse8 (mod v_prenex_69 4294967296)) (.cse6 (mod c_main_~x~0 4294967296))) (let ((.cse7 (div .cse8 .cse6)) (.cse9 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse6 (mod .cse7 4294967296)) (<= 0 .cse8) (<= .cse8 .cse9) (< .cse6 (mod (+ .cse7 4294967295) 4294967296)) (<= (mod (div .cse8 .cse9) 4294967296) .cse9) (= (mod .cse8 .cse6) 0)))))) (or (forall ((v_prenex_49 Int)) (let ((.cse12 (mod v_prenex_49 4294967296)) (.cse10 (mod c_main_~x~0 4294967296))) (let ((.cse11 (div .cse12 .cse10)) (.cse13 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse10 (mod (+ .cse11 4294967295) 4294967296)) (< .cse10 (mod .cse11 4294967296)) (<= .cse12 .cse13) (< .cse10 (mod (+ .cse11 1) 4294967296)) (<= (mod (div .cse12 .cse13) 4294967296) .cse13))))) .cse0) (or (forall ((v_prenex_71 Int)) (let ((.cse16 (mod (+ c_main_~x~0 1) 4294967296)) (.cse15 (mod v_prenex_71 4294967296))) (or (let ((.cse14 (mod c_main_~x~0 4294967296))) (< .cse14 (mod (div .cse15 .cse14) 4294967296))) (<= .cse15 .cse16) (<= (mod (div .cse15 .cse16) 4294967296) .cse16) (< .cse15 0)))) .cse5) (or (forall ((v_prenex_65 Int)) (let ((.cse19 (mod v_prenex_65 4294967296)) (.cse17 (mod c_main_~x~0 4294967296))) (let ((.cse20 (mod (+ c_main_~x~0 1) 4294967296)) (.cse18 (div .cse19 .cse17))) (or (< .cse17 (mod .cse18 4294967296)) (<= .cse19 .cse20) (<= (mod (div .cse19 .cse20) 4294967296) .cse20) (< .cse17 (mod (+ .cse18 1) 4294967296)) (< .cse19 0) (< .cse17 (mod (+ .cse18 4294967295) 4294967296)))))) .cse0) (or (forall ((v_prenex_90 Int)) (let ((.cse23 (mod v_prenex_90 4294967296)) (.cse21 (mod c_main_~x~0 4294967296))) (let ((.cse22 (div .cse23 .cse21)) (.cse24 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse21 (mod (+ .cse22 1) 4294967296)) (< .cse21 (mod .cse22 4294967296)) (<= .cse23 .cse24) (< .cse21 (mod (+ .cse22 4294967295) 4294967296)) (<= (mod (div .cse23 .cse24) 4294967296) .cse24) (< .cse23 0))))) .cse5) (or (forall ((v_prenex_69 Int)) (let ((.cse27 (mod v_prenex_69 4294967296)) (.cse25 (mod c_main_~x~0 4294967296))) (let ((.cse26 (div .cse27 .cse25)) (.cse28 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse25 (mod (+ .cse26 1) 4294967296)) (< .cse25 (mod .cse26 4294967296)) (<= 0 .cse27) (<= .cse27 .cse28) (<= (mod (div .cse27 .cse28) 4294967296) .cse28) (= (mod .cse27 .cse25) 0))))) .cse0) (or (forall ((v_prenex_61 Int)) (let ((.cse31 (mod v_prenex_61 4294967296)) (.cse29 (mod c_main_~x~0 4294967296))) (let ((.cse32 (mod (+ c_main_~x~0 1) 4294967296)) (.cse30 (div .cse31 .cse29))) (or (< .cse29 (mod (+ .cse30 1) 4294967296)) (<= .cse31 .cse32) (<= (mod (div .cse31 .cse32) 4294967296) .cse32) (< .cse29 (mod .cse30 4294967296)))))) .cse0) (or (forall ((v_prenex_30 Int)) (let ((.cse35 (mod v_prenex_30 4294967296)) (.cse33 (mod c_main_~x~0 4294967296))) (let ((.cse36 (mod (+ c_main_~x~0 1) 4294967296)) (.cse34 (div .cse35 .cse33))) (or (< .cse33 (mod (+ .cse34 1) 4294967296)) (<= (mod (div .cse35 .cse36) 4294967296) .cse36) (<= .cse35 .cse36) (< .cse33 (mod (+ .cse34 4294967295) 4294967296)) (< .cse33 (mod .cse34 4294967296)))))) .cse0) (or .cse0 (forall ((v_prenex_23 Int)) (let ((.cse37 (mod v_prenex_23 4294967296)) (.cse38 (mod c_main_~x~0 4294967296))) (let ((.cse39 (mod (+ c_main_~x~0 1) 4294967296)) (.cse40 (div .cse37 .cse38))) (or (not (= (mod .cse37 .cse38) 0)) (<= .cse37 .cse39) (< .cse38 (mod (+ .cse40 4294967295) 4294967296)) (< .cse38 (mod .cse40 4294967296)) (<= (mod (div .cse37 .cse39) 4294967296) .cse39) (< .cse38 (mod (+ .cse40 1) 4294967296))))))) (or (forall ((v_prenex_7 Int)) (let ((.cse41 (mod v_prenex_7 4294967296)) (.cse43 (mod c_main_~x~0 4294967296))) (let ((.cse42 (mod (+ c_main_~x~0 1) 4294967296)) (.cse44 (div .cse41 .cse43))) (or (<= .cse41 .cse42) (<= (mod (div .cse41 .cse42) 4294967296) .cse42) (< .cse43 (mod .cse44 4294967296)) (< .cse43 (mod (+ .cse44 4294967295) 4294967296)) (not (= (mod .cse41 .cse43) 0)) (< .cse43 (mod (+ .cse44 1) 4294967296)))))) .cse0) (forall ((v_prenex_80 Int)) (let ((.cse45 (mod v_prenex_80 4294967296)) (.cse46 (mod c_main_~x~0 4294967296))) (let ((.cse48 (mod (+ c_main_~x~0 1) 4294967296)) (.cse47 (div .cse45 .cse46))) (or (not (= (mod .cse45 .cse46) 0)) (< .cse46 (mod (+ .cse47 1) 4294967296)) (<= (mod (div .cse45 .cse48) 4294967296) .cse48) (< .cse46 (mod .cse47 4294967296)) (<= .cse45 .cse48) (< .cse46 (mod (+ .cse47 4294967295) 4294967296)))))) (or (forall ((v_prenex_103 Int)) (let ((.cse51 (mod v_prenex_103 4294967296)) (.cse49 (mod c_main_~x~0 4294967296))) (let ((.cse50 (div .cse51 .cse49)) (.cse52 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse49 (mod .cse50 4294967296)) (< .cse51 0) (<= .cse51 .cse52) (< .cse49 (mod (+ .cse50 1) 4294967296)) (<= (mod (div .cse51 .cse52) 4294967296) .cse52))))) .cse0) (or (forall ((v_prenex_66 Int)) (let ((.cse55 (mod v_prenex_66 4294967296)) (.cse53 (mod c_main_~x~0 4294967296))) (let ((.cse54 (div .cse55 .cse53)) (.cse56 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse53 (mod .cse54 4294967296)) (< .cse53 (mod (+ .cse54 1) 4294967296)) (<= .cse55 .cse56) (< .cse55 0) (<= (mod (div .cse55 .cse56) 4294967296) .cse56))))) .cse0) (or .cse0 (forall ((v_prenex_99 Int)) (let ((.cse57 (mod v_prenex_99 4294967296)) (.cse59 (mod c_main_~x~0 4294967296))) (let ((.cse60 (div .cse57 .cse59)) (.cse58 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse57 .cse58) (= (mod .cse57 .cse59) 0) (<= 0 .cse57) (< .cse59 (mod .cse60 4294967296)) (< .cse59 (mod (+ .cse60 1) 4294967296)) (<= (mod (div .cse57 .cse58) 4294967296) .cse58)))))) (or (forall ((v_prenex_47 Int)) (let ((.cse63 (mod v_prenex_47 4294967296)) (.cse61 (mod c_main_~x~0 4294967296))) (let ((.cse62 (div .cse63 .cse61)) (.cse64 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse61 (mod .cse62 4294967296)) (= (mod .cse63 .cse61) 0) (<= 0 .cse63) (< .cse61 (mod (+ .cse62 1) 4294967296)) (<= .cse63 .cse64) (<= (mod (div .cse63 .cse64) 4294967296) .cse64))))) .cse0) (forall ((v_prenex_99 Int)) (let ((.cse65 (mod v_prenex_99 4294967296)) (.cse67 (mod c_main_~x~0 4294967296))) (let ((.cse68 (div .cse65 .cse67)) (.cse66 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse65 .cse66) (= (mod .cse65 .cse67) 0) (< .cse67 (mod (+ .cse68 4294967295) 4294967296)) (<= 0 .cse65) (< .cse67 (mod .cse68 4294967296)) (< .cse67 (mod (+ .cse68 1) 4294967296)) (<= (mod (div .cse65 .cse66) 4294967296) .cse66))))) .cse69 (or .cse0 .cse70) (or .cse5 (forall ((v_prenex_81 Int)) (let ((.cse71 (mod c_main_~x~0 4294967296)) (.cse72 (mod v_prenex_81 4294967296)) (.cse73 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse71 (mod (div .cse72 .cse71) 4294967296)) (not (= (mod .cse72 .cse71) 0)) (<= .cse72 .cse73) (<= (mod (div .cse72 .cse73) 4294967296) .cse73))))) (or (forall ((v_prenex_97 Int)) (let ((.cse74 (mod v_prenex_97 4294967296)) (.cse76 (mod c_main_~x~0 4294967296))) (let ((.cse77 (div .cse74 .cse76)) (.cse75 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse74 .cse75) (< .cse76 (mod .cse77 4294967296)) (< .cse76 (mod (+ .cse77 1) 4294967296)) (< .cse76 (mod (+ .cse77 4294967295) 4294967296)) (<= (mod (div .cse74 .cse75) 4294967296) .cse75))))) .cse5) (forall ((v_prenex_107 Int)) (let ((.cse79 (mod (+ c_main_~x~0 1) 4294967296)) (.cse78 (mod v_prenex_107 4294967296)) (.cse80 (mod c_main_~x~0 4294967296))) (or (<= (mod (div .cse78 .cse79) 4294967296) .cse79) (not (= (mod .cse78 .cse80) 0)) (<= .cse78 .cse79) (< .cse80 (mod (div .cse78 .cse80) 4294967296))))) (forall ((v_prenex_71 Int)) (let ((.cse83 (mod v_prenex_71 4294967296)) (.cse81 (mod c_main_~x~0 4294967296))) (let ((.cse84 (mod (+ c_main_~x~0 1) 4294967296)) (.cse82 (div .cse83 .cse81))) (or (< .cse81 (mod .cse82 4294967296)) (<= .cse83 .cse84) (<= (mod (div .cse83 .cse84) 4294967296) .cse84) (< .cse83 0) (< .cse81 (mod (+ .cse82 1) 4294967296)))))) (or (forall ((v_prenex_47 Int)) (let ((.cse87 (mod v_prenex_47 4294967296)) (.cse85 (mod c_main_~x~0 4294967296))) (let ((.cse86 (div .cse87 .cse85)) (.cse88 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse85 (mod (+ .cse86 4294967295) 4294967296)) (< .cse85 (mod .cse86 4294967296)) (= (mod .cse87 .cse85) 0) (<= 0 .cse87) (< .cse85 (mod (+ .cse86 1) 4294967296)) (<= .cse87 .cse88) (<= (mod (div .cse87 .cse88) 4294967296) .cse88))))) .cse0) (or (forall ((v_prenex_74 Int)) (let ((.cse89 (mod v_prenex_74 4294967296)) (.cse91 (mod c_main_~x~0 4294967296))) (let ((.cse90 (mod (+ c_main_~x~0 1) 4294967296)) (.cse92 (div .cse89 .cse91))) (or (<= (mod (div .cse89 .cse90) 4294967296) .cse90) (< .cse91 (mod (+ .cse92 1) 4294967296)) (<= .cse89 .cse90) (< .cse89 0) (< .cse91 (mod .cse92 4294967296)))))) .cse0) (or (forall ((v_prenex_4 Int)) (let ((.cse95 (mod v_prenex_4 4294967296)) (.cse93 (mod c_main_~x~0 4294967296))) (let ((.cse96 (mod (+ c_main_~x~0 1) 4294967296)) (.cse94 (div .cse95 .cse93))) (or (< .cse93 (mod .cse94 4294967296)) (<= (mod (div .cse95 .cse96) 4294967296) .cse96) (<= .cse95 .cse96) (< .cse93 (mod (+ .cse94 1) 4294967296)) (not (= (mod .cse95 .cse93) 0)))))) .cse0) (or (forall ((v_prenex_69 Int)) (let ((.cse99 (mod (+ c_main_~x~0 1) 4294967296)) (.cse98 (mod v_prenex_69 4294967296)) (.cse97 (mod c_main_~x~0 4294967296))) (or (< .cse97 (mod (+ (div .cse98 .cse97) 1) 4294967296)) (<= 0 .cse98) (<= .cse98 .cse99) (<= (mod (div .cse98 .cse99) 4294967296) .cse99) (= (mod .cse98 .cse97) 0)))) .cse0) (or (forall ((v_prenex_14 Int)) (let ((.cse100 (mod v_prenex_14 4294967296)) (.cse102 (mod c_main_~x~0 4294967296))) (let ((.cse101 (mod (+ c_main_~x~0 1) 4294967296)) (.cse103 (div .cse100 .cse102))) (or (<= (mod (div .cse100 .cse101) 4294967296) .cse101) (< .cse102 (mod (+ .cse103 4294967295) 4294967296)) (< .cse100 0) (< .cse102 (mod .cse103 4294967296)) (<= .cse100 .cse101) (< .cse102 (mod (+ .cse103 1) 4294967296)))))) .cse0) (forall ((v_prenex_108 Int)) (let ((.cse104 (mod v_prenex_108 4294967296)) (.cse106 (mod c_main_~x~0 4294967296))) (let ((.cse107 (div .cse104 .cse106)) (.cse105 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= (mod (div .cse104 .cse105) 4294967296) .cse105) (< .cse106 (mod .cse107 4294967296)) (< .cse106 (mod (+ .cse107 4294967295) 4294967296)) (< .cse106 (mod (+ .cse107 1) 4294967296)) (= (mod .cse104 .cse106) 0) (<= 0 .cse104) (<= .cse104 .cse105))))) (or .cse0 (forall ((v_prenex_21 Int)) (let ((.cse108 (mod v_prenex_21 4294967296)) (.cse110 (mod c_main_~x~0 4294967296))) (let ((.cse109 (mod (+ c_main_~x~0 1) 4294967296)) (.cse111 (div .cse108 .cse110))) (or (<= (mod (div .cse108 .cse109) 4294967296) .cse109) (<= .cse108 .cse109) (not (= (mod .cse108 .cse110) 0)) (< .cse110 (mod (+ .cse111 1) 4294967296)) (< .cse110 (mod .cse111 4294967296))))))) (or .cse0 (forall ((v_prenex_89 Int)) (let ((.cse114 (mod v_prenex_89 4294967296)) (.cse112 (mod c_main_~x~0 4294967296))) (let ((.cse115 (mod (+ c_main_~x~0 1) 4294967296)) (.cse113 (div .cse114 .cse112))) (or (< .cse112 (mod (+ .cse113 1) 4294967296)) (<= (mod (div .cse114 .cse115) 4294967296) .cse115) (< .cse112 (mod .cse113 4294967296)) (<= .cse114 .cse115) (< .cse112 (mod (+ .cse113 4294967295) 4294967296))))))) (or (forall ((v_prenex_102 Int)) (let ((.cse116 (mod v_prenex_102 4294967296)) (.cse118 (mod c_main_~x~0 4294967296))) (let ((.cse117 (mod (+ c_main_~x~0 1) 4294967296)) (.cse119 (div .cse116 .cse118))) (or (<= (mod (div .cse116 .cse117) 4294967296) .cse117) (< .cse118 (mod .cse119 4294967296)) (<= .cse116 .cse117) (< .cse118 (mod (+ .cse119 1) 4294967296)) (not (= (mod .cse116 .cse118) 0)))))) .cse0) (or .cse5 .cse69) (or (forall ((v_prenex_43 Int)) (let ((.cse120 (mod v_prenex_43 4294967296)) (.cse122 (mod c_main_~x~0 4294967296))) (let ((.cse121 (mod (+ c_main_~x~0 1) 4294967296)) (.cse123 (div .cse120 .cse122))) (or (<= (mod (div .cse120 .cse121) 4294967296) .cse121) (< .cse122 (mod .cse123 4294967296)) (<= .cse120 .cse121) (< .cse122 (mod (+ .cse123 1) 4294967296)) (< .cse120 0) (< .cse122 (mod (+ .cse123 4294967295) 4294967296)))))) .cse0) (or (forall ((v_prenex_112 Int)) (let ((.cse124 (mod v_prenex_112 4294967296)) (.cse125 (mod c_main_~x~0 4294967296))) (let ((.cse126 (div .cse124 .cse125)) (.cse127 (mod (+ c_main_~x~0 1) 4294967296))) (or (= (mod .cse124 .cse125) 0) (< .cse125 (mod .cse126 4294967296)) (< .cse125 (mod (+ .cse126 4294967295) 4294967296)) (<= (mod (div .cse124 .cse127) 4294967296) .cse127) (<= .cse124 .cse127) (<= 0 .cse124))))) .cse5) (or (forall ((v_prenex_73 Int)) (let ((.cse128 (mod v_prenex_73 4294967296)) (.cse130 (mod c_main_~x~0 4294967296))) (let ((.cse129 (mod (+ c_main_~x~0 1) 4294967296)) (.cse131 (div .cse128 .cse130))) (or (<= (mod (div .cse128 .cse129) 4294967296) .cse129) (<= .cse128 .cse129) (< .cse130 (mod .cse131 4294967296)) (< .cse130 (mod (+ .cse131 4294967295) 4294967296)))))) .cse5) (forall ((v_prenex_67 Int)) (let ((.cse133 (mod v_prenex_67 4294967296)) (.cse134 (mod (+ c_main_~x~0 1) 4294967296))) (or (let ((.cse132 (mod c_main_~x~0 4294967296))) (< .cse132 (mod (div .cse133 .cse132) 4294967296))) (< .cse133 0) (<= .cse133 .cse134) (<= (mod (div .cse133 .cse134) 4294967296) .cse134)))) (forall ((v_prenex_72 Int)) (let ((.cse135 (mod v_prenex_72 4294967296)) (.cse137 (mod c_main_~x~0 4294967296))) (let ((.cse136 (mod (+ c_main_~x~0 1) 4294967296)) (.cse138 (div .cse135 .cse137))) (or (<= (mod (div .cse135 .cse136) 4294967296) .cse136) (<= .cse135 .cse136) (< .cse137 (mod (+ .cse138 1) 4294967296)) (< .cse137 (mod (+ .cse138 4294967295) 4294967296)) (< .cse137 (mod .cse138 4294967296)))))) (or .cse5 (forall ((v_prenex_95 Int)) (let ((.cse141 (mod v_prenex_95 4294967296)) (.cse139 (mod c_main_~x~0 4294967296))) (let ((.cse142 (mod (+ c_main_~x~0 1) 4294967296)) (.cse140 (div .cse141 .cse139))) (or (< .cse139 (mod .cse140 4294967296)) (<= .cse141 .cse142) (<= (mod (div .cse141 .cse142) 4294967296) .cse142) (< .cse139 (mod (+ .cse140 4294967295) 4294967296))))))) .cse70 (or (forall ((v_prenex_99 Int)) (let ((.cse143 (mod v_prenex_99 4294967296)) (.cse145 (mod c_main_~x~0 4294967296))) (let ((.cse146 (div .cse143 .cse145)) (.cse144 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse143 .cse144) (= (mod .cse143 .cse145) 0) (< .cse145 (mod (+ .cse146 4294967295) 4294967296)) (<= 0 .cse143) (< .cse145 (mod .cse146 4294967296)) (<= (mod (div .cse143 .cse144) 4294967296) .cse144))))) .cse5) (or .cse5 (forall ((v_prenex_70 Int)) (let ((.cse149 (mod v_prenex_70 4294967296)) (.cse147 (mod c_main_~x~0 4294967296))) (let ((.cse150 (mod (+ c_main_~x~0 1) 4294967296)) (.cse148 (div .cse149 .cse147))) (or (< .cse147 (mod .cse148 4294967296)) (<= (mod (div .cse149 .cse150) 4294967296) .cse150) (<= .cse149 .cse150) (< .cse147 (mod (+ .cse148 4294967295) 4294967296)) (< .cse149 0)))))) (or (forall ((v_prenex_53 Int)) (let ((.cse153 (mod v_prenex_53 4294967296)) (.cse151 (mod c_main_~x~0 4294967296))) (let ((.cse152 (div .cse153 .cse151)) (.cse154 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse151 (mod (+ .cse152 1) 4294967296)) (<= (mod (div .cse153 .cse154) 4294967296) .cse154) (< .cse151 (mod .cse152 4294967296)) (<= .cse153 .cse154))))) .cse0) (or .cse0 (forall ((v_prenex_17 Int)) (let ((.cse155 (mod c_main_~x~0 4294967296)) (.cse157 (mod (+ c_main_~x~0 1) 4294967296)) (.cse156 (mod v_prenex_17 4294967296))) (or (< .cse155 (mod (+ (div .cse156 .cse155) 1) 4294967296)) (= (mod .cse156 .cse155) 0) (<= .cse156 .cse157) (<= (mod (div .cse156 .cse157) 4294967296) .cse157) (<= 0 .cse156))))) (forall ((v_prenex_98 Int)) (let ((.cse158 (mod v_prenex_98 4294967296)) (.cse160 (mod c_main_~x~0 4294967296))) (let ((.cse159 (mod (+ c_main_~x~0 1) 4294967296)) (.cse161 (div .cse158 .cse160))) (or (<= .cse158 .cse159) (< .cse160 (mod (+ .cse161 1) 4294967296)) (<= (mod (div .cse158 .cse159) 4294967296) .cse159) (< .cse160 (mod (+ .cse161 4294967295) 4294967296)) (< .cse160 (mod .cse161 4294967296)) (< .cse158 0))))) (or (forall ((v_prenex_111 Int)) (let ((.cse162 (mod v_prenex_111 4294967296)) (.cse163 (mod c_main_~x~0 4294967296))) (let ((.cse164 (mod (+ c_main_~x~0 1) 4294967296)) (.cse165 (div .cse162 .cse163))) (or (not (= (mod .cse162 .cse163) 0)) (<= .cse162 .cse164) (< .cse163 (mod .cse165 4294967296)) (<= (mod (div .cse162 .cse164) 4294967296) .cse164) (< .cse163 (mod (+ .cse165 4294967295) 4294967296)))))) .cse5) (or .cse0 (forall ((v_prenex_100 Int)) (let ((.cse166 (mod v_prenex_100 4294967296)) (.cse168 (mod c_main_~x~0 4294967296))) (let ((.cse169 (div .cse166 .cse168)) (.cse167 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= (mod (div .cse166 .cse167) 4294967296) .cse167) (< .cse168 (mod (+ .cse169 1) 4294967296)) (< .cse168 (mod .cse169 4294967296)) (<= .cse166 .cse167)))))) (or .cse0 (forall ((v_prenex_48 Int)) (let ((.cse172 (mod v_prenex_48 4294967296)) (.cse170 (mod c_main_~x~0 4294967296))) (let ((.cse173 (mod (+ c_main_~x~0 1) 4294967296)) (.cse171 (div .cse172 .cse170))) (or (< .cse170 (mod (+ .cse171 4294967295) 4294967296)) (<= .cse172 .cse173) (<= (mod (div .cse172 .cse173) 4294967296) .cse173) (<= 0 .cse172) (= (mod .cse172 .cse170) 0) (< .cse170 (mod (+ .cse171 1) 4294967296))))))) (or (forall ((v_prenex_44 Int)) (let ((.cse176 (mod v_prenex_44 4294967296)) (.cse174 (mod c_main_~x~0 4294967296))) (let ((.cse175 (div .cse176 .cse174)) (.cse177 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse174 (mod (+ .cse175 1) 4294967296)) (< .cse174 (mod .cse175 4294967296)) (<= (mod (div .cse176 .cse177) 4294967296) .cse177) (<= .cse176 .cse177))))) .cse0) (or (forall ((v_prenex_8 Int)) (let ((.cse180 (mod v_prenex_8 4294967296)) (.cse178 (mod c_main_~x~0 4294967296))) (let ((.cse179 (div .cse180 .cse178)) (.cse181 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse178 (mod .cse179 4294967296)) (< .cse178 (mod (+ .cse179 1) 4294967296)) (<= .cse180 .cse181) (<= (mod (div .cse180 .cse181) 4294967296) .cse181) (< .cse180 0))))) .cse0) (or (forall ((v_prenex_110 Int)) (let ((.cse184 (mod v_prenex_110 4294967296)) (.cse182 (mod c_main_~x~0 4294967296))) (let ((.cse185 (mod (+ c_main_~x~0 1) 4294967296)) (.cse183 (div .cse184 .cse182))) (or (< .cse182 (mod (+ .cse183 1) 4294967296)) (<= .cse184 .cse185) (not (= (mod .cse184 .cse182) 0)) (<= (mod (div .cse184 .cse185) 4294967296) .cse185) (< .cse182 (mod .cse183 4294967296)))))) .cse0) (or (forall ((v_prenex_79 Int)) (let ((.cse188 (mod v_prenex_79 4294967296)) (.cse186 (mod c_main_~x~0 4294967296))) (let ((.cse187 (div .cse188 .cse186)) (.cse189 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse186 (mod .cse187 4294967296)) (= (mod .cse188 .cse186) 0) (<= .cse188 .cse189) (< .cse186 (mod (+ .cse187 1) 4294967296)) (<= 0 .cse188) (<= (mod (div .cse188 .cse189) 4294967296) .cse189))))) .cse0) (or (forall ((v_prenex_83 Int)) (let ((.cse192 (mod v_prenex_83 4294967296)) (.cse190 (mod c_main_~x~0 4294967296))) (let ((.cse193 (mod (+ c_main_~x~0 1) 4294967296)) (.cse191 (div .cse192 .cse190))) (or (< .cse190 (mod .cse191 4294967296)) (not (= (mod .cse192 .cse190) 0)) (<= .cse192 .cse193) (< .cse190 (mod (+ .cse191 4294967295) 4294967296)) (<= (mod (div .cse192 .cse193) 4294967296) .cse193) (< .cse190 (mod (+ .cse191 1) 4294967296)))))) .cse5) (or .cse5 (forall ((v_prenex_93 Int)) (let ((.cse196 (mod v_prenex_93 4294967296)) (.cse194 (mod c_main_~x~0 4294967296))) (let ((.cse195 (div .cse196 .cse194)) (.cse197 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse194 (mod (+ .cse195 4294967295) 4294967296)) (< .cse194 (mod .cse195 4294967296)) (<= (mod (div .cse196 .cse197) 4294967296) .cse197) (<= .cse196 .cse197) (< .cse196 0)))))) (or .cse5 .cse70) (forall ((v_prenex_81 Int)) (let ((.cse200 (mod v_prenex_81 4294967296)) (.cse198 (mod c_main_~x~0 4294967296))) (let ((.cse199 (div .cse200 .cse198)) (.cse201 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse198 (mod .cse199 4294967296)) (not (= (mod .cse200 .cse198) 0)) (<= .cse200 .cse201) (< .cse198 (mod (+ .cse199 1) 4294967296)) (<= (mod (div .cse200 .cse201) 4294967296) .cse201))))) (or .cse5 (forall ((v_prenex_69 Int)) (let ((.cse203 (mod (+ c_main_~x~0 1) 4294967296)) (.cse202 (mod v_prenex_69 4294967296)) (.cse204 (mod c_main_~x~0 4294967296))) (or (<= 0 .cse202) (<= .cse202 .cse203) (< .cse204 (mod (+ (div .cse202 .cse204) 4294967295) 4294967296)) (<= (mod (div .cse202 .cse203) 4294967296) .cse203) (= (mod .cse202 .cse204) 0))))) (or .cse0 (forall ((v_prenex_35 Int)) (let ((.cse207 (mod v_prenex_35 4294967296)) (.cse205 (mod c_main_~x~0 4294967296))) (let ((.cse206 (div .cse207 .cse205)) (.cse208 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse205 (mod .cse206 4294967296)) (< .cse207 0) (< .cse205 (mod (+ .cse206 1) 4294967296)) (<= (mod (div .cse207 .cse208) 4294967296) .cse208) (<= .cse207 .cse208)))))) (or (forall ((v_prenex_56 Int)) (let ((.cse209 (mod v_prenex_56 4294967296)) (.cse210 (mod c_main_~x~0 4294967296))) (let ((.cse211 (div .cse209 .cse210)) (.cse212 (mod (+ c_main_~x~0 1) 4294967296))) (or (not (= (mod .cse209 .cse210) 0)) (< .cse210 (mod .cse211 4294967296)) (< .cse210 (mod (+ .cse211 1) 4294967296)) (< .cse210 (mod (+ .cse211 4294967295) 4294967296)) (<= .cse209 .cse212) (<= (mod (div .cse209 .cse212) 4294967296) .cse212))))) .cse0) (or .cse5 (forall ((v_prenex_82 Int)) (let ((.cse215 (mod v_prenex_82 4294967296)) (.cse213 (mod c_main_~x~0 4294967296))) (let ((.cse214 (div .cse215 .cse213)) (.cse216 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse213 (mod (+ .cse214 4294967295) 4294967296)) (< .cse213 (mod .cse214 4294967296)) (<= .cse215 .cse216) (not (= (mod .cse215 .cse213) 0)) (<= (mod (div .cse215 .cse216) 4294967296) .cse216))))))))) is different from false [2018-11-18 10:22:05,151 WARN L832 $PredicateComparison]: unable to prove that (let ((.cse235 (mod c_main_~x~0 4294967296))) (let ((.cse4 (< .cse235 0)) (.cse9 (<= 0 .cse235))) (and (forall ((v_prenex_121 Int)) (let ((.cse0 (mod v_prenex_121 4294967296)) (.cse2 (mod c_main_~x~0 4294967296))) (let ((.cse3 (div .cse0 .cse2)) (.cse1 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse0 .cse1) (= (mod .cse0 .cse2) 0) (<= 0 .cse0) (< .cse2 (mod .cse3 4294967296)) (< .cse2 (mod (+ .cse3 4294967295) 4294967296)) (< .cse2 (mod (+ .cse3 1) 4294967296)) (<= (mod (div .cse0 .cse1) 4294967296) .cse1))))) (or .cse4 (forall ((v_prenex_51 Int)) (let ((.cse7 (mod v_prenex_51 4294967296)) (.cse5 (mod c_main_~x~0 4294967296))) (let ((.cse6 (div .cse7 .cse5)) (.cse8 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse5 (mod (+ .cse6 1) 4294967296)) (< .cse5 (mod .cse6 4294967296)) (<= .cse7 .cse8) (not (= (mod .cse7 .cse5) 0)) (<= (mod (div .cse7 .cse8) 4294967296) .cse8)))))) (or .cse9 (forall ((v_prenex_69 Int)) (let ((.cse12 (mod v_prenex_69 4294967296)) (.cse10 (mod c_main_~x~0 4294967296))) (let ((.cse11 (div .cse12 .cse10)) (.cse13 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse10 (mod .cse11 4294967296)) (<= 0 .cse12) (<= .cse12 .cse13) (< .cse10 (mod (+ .cse11 4294967295) 4294967296)) (<= (mod (div .cse12 .cse13) 4294967296) .cse13) (= (mod .cse12 .cse10) 0)))))) (forall ((v_prenex_115 Int)) (let ((.cse14 (mod v_prenex_115 4294967296)) (.cse16 (mod c_main_~x~0 4294967296))) (let ((.cse15 (mod (+ c_main_~x~0 1) 4294967296)) (.cse17 (div .cse14 .cse16))) (or (<= (mod (div .cse14 .cse15) 4294967296) .cse15) (<= .cse14 .cse15) (< .cse16 (mod (+ .cse17 1) 4294967296)) (<= 0 .cse14) (= (mod .cse14 .cse16) 0) (< .cse16 (mod (+ .cse17 4294967295) 4294967296)))))) (or (forall ((v_prenex_49 Int)) (let ((.cse20 (mod v_prenex_49 4294967296)) (.cse18 (mod c_main_~x~0 4294967296))) (let ((.cse19 (div .cse20 .cse18)) (.cse21 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse18 (mod (+ .cse19 4294967295) 4294967296)) (< .cse18 (mod .cse19 4294967296)) (<= .cse20 .cse21) (< .cse18 (mod (+ .cse19 1) 4294967296)) (<= (mod (div .cse20 .cse21) 4294967296) .cse21))))) .cse4) (or (forall ((v_prenex_71 Int)) (let ((.cse24 (mod (+ c_main_~x~0 1) 4294967296)) (.cse23 (mod v_prenex_71 4294967296))) (or (let ((.cse22 (mod c_main_~x~0 4294967296))) (< .cse22 (mod (div .cse23 .cse22) 4294967296))) (<= .cse23 .cse24) (<= (mod (div .cse23 .cse24) 4294967296) .cse24) (< .cse23 0)))) .cse9) (or .cse9 (forall ((v_prenex_122 Int)) (let ((.cse27 (mod v_prenex_122 4294967296)) (.cse25 (mod c_main_~x~0 4294967296))) (let ((.cse26 (div .cse27 .cse25)) (.cse28 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse25 (mod (+ .cse26 4294967295) 4294967296)) (< .cse25 (mod .cse26 4294967296)) (<= 0 .cse27) (<= .cse27 .cse28) (= (mod .cse27 .cse25) 0) (<= (mod (div .cse27 .cse28) 4294967296) .cse28)))))) (or (forall ((v_prenex_65 Int)) (let ((.cse31 (mod v_prenex_65 4294967296)) (.cse29 (mod c_main_~x~0 4294967296))) (let ((.cse32 (mod (+ c_main_~x~0 1) 4294967296)) (.cse30 (div .cse31 .cse29))) (or (< .cse29 (mod .cse30 4294967296)) (<= .cse31 .cse32) (<= (mod (div .cse31 .cse32) 4294967296) .cse32) (< .cse29 (mod (+ .cse30 1) 4294967296)) (< .cse31 0) (< .cse29 (mod (+ .cse30 4294967295) 4294967296)))))) .cse4) (or (forall ((v_prenex_90 Int)) (let ((.cse35 (mod v_prenex_90 4294967296)) (.cse33 (mod c_main_~x~0 4294967296))) (let ((.cse34 (div .cse35 .cse33)) (.cse36 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse33 (mod (+ .cse34 1) 4294967296)) (< .cse33 (mod .cse34 4294967296)) (<= .cse35 .cse36) (< .cse33 (mod (+ .cse34 4294967295) 4294967296)) (<= (mod (div .cse35 .cse36) 4294967296) .cse36) (< .cse35 0))))) .cse9) (or (forall ((v_prenex_61 Int)) (let ((.cse39 (mod v_prenex_61 4294967296)) (.cse37 (mod c_main_~x~0 4294967296))) (let ((.cse40 (mod (+ c_main_~x~0 1) 4294967296)) (.cse38 (div .cse39 .cse37))) (or (< .cse37 (mod (+ .cse38 1) 4294967296)) (<= .cse39 .cse40) (<= (mod (div .cse39 .cse40) 4294967296) .cse40) (< .cse37 (mod .cse38 4294967296)))))) .cse4) (or (forall ((v_prenex_30 Int)) (let ((.cse43 (mod v_prenex_30 4294967296)) (.cse41 (mod c_main_~x~0 4294967296))) (let ((.cse44 (mod (+ c_main_~x~0 1) 4294967296)) (.cse42 (div .cse43 .cse41))) (or (< .cse41 (mod (+ .cse42 1) 4294967296)) (<= (mod (div .cse43 .cse44) 4294967296) .cse44) (<= .cse43 .cse44) (< .cse41 (mod (+ .cse42 4294967295) 4294967296)) (< .cse41 (mod .cse42 4294967296)))))) .cse4) (or .cse4 (forall ((v_prenex_23 Int)) (let ((.cse45 (mod v_prenex_23 4294967296)) (.cse46 (mod c_main_~x~0 4294967296))) (let ((.cse47 (mod (+ c_main_~x~0 1) 4294967296)) (.cse48 (div .cse45 .cse46))) (or (not (= (mod .cse45 .cse46) 0)) (<= .cse45 .cse47) (< .cse46 (mod (+ .cse48 4294967295) 4294967296)) (< .cse46 (mod .cse48 4294967296)) (<= (mod (div .cse45 .cse47) 4294967296) .cse47) (< .cse46 (mod (+ .cse48 1) 4294967296))))))) (or (forall ((v_prenex_7 Int)) (let ((.cse49 (mod v_prenex_7 4294967296)) (.cse51 (mod c_main_~x~0 4294967296))) (let ((.cse50 (mod (+ c_main_~x~0 1) 4294967296)) (.cse52 (div .cse49 .cse51))) (or (<= .cse49 .cse50) (<= (mod (div .cse49 .cse50) 4294967296) .cse50) (< .cse51 (mod .cse52 4294967296)) (< .cse51 (mod (+ .cse52 4294967295) 4294967296)) (not (= (mod .cse49 .cse51) 0)) (< .cse51 (mod (+ .cse52 1) 4294967296)))))) .cse4) (forall ((v_prenex_80 Int)) (let ((.cse53 (mod v_prenex_80 4294967296)) (.cse54 (mod c_main_~x~0 4294967296))) (let ((.cse56 (mod (+ c_main_~x~0 1) 4294967296)) (.cse55 (div .cse53 .cse54))) (or (not (= (mod .cse53 .cse54) 0)) (< .cse54 (mod (+ .cse55 1) 4294967296)) (<= (mod (div .cse53 .cse56) 4294967296) .cse56) (< .cse54 (mod .cse55 4294967296)) (<= .cse53 .cse56) (< .cse54 (mod (+ .cse55 4294967295) 4294967296)))))) (or (forall ((v_prenex_103 Int)) (let ((.cse59 (mod v_prenex_103 4294967296)) (.cse57 (mod c_main_~x~0 4294967296))) (let ((.cse58 (div .cse59 .cse57)) (.cse60 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse57 (mod .cse58 4294967296)) (< .cse59 0) (<= .cse59 .cse60) (< .cse57 (mod (+ .cse58 1) 4294967296)) (<= (mod (div .cse59 .cse60) 4294967296) .cse60))))) .cse4) (or (forall ((v_prenex_66 Int)) (let ((.cse63 (mod v_prenex_66 4294967296)) (.cse61 (mod c_main_~x~0 4294967296))) (let ((.cse62 (div .cse63 .cse61)) (.cse64 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse61 (mod .cse62 4294967296)) (< .cse61 (mod (+ .cse62 1) 4294967296)) (<= .cse63 .cse64) (< .cse63 0) (<= (mod (div .cse63 .cse64) 4294967296) .cse64))))) .cse4) (or (forall ((v_prenex_118 Int)) (let ((.cse67 (mod v_prenex_118 4294967296)) (.cse65 (mod c_main_~x~0 4294967296))) (let ((.cse66 (div .cse67 .cse65)) (.cse68 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse65 (mod .cse66 4294967296)) (<= (mod (div .cse67 .cse68) 4294967296) .cse68) (< .cse65 (mod (+ .cse66 1) 4294967296)) (= (mod .cse67 .cse65) 0) (< .cse65 (mod (+ .cse66 4294967295) 4294967296)) (<= 0 .cse67) (<= .cse67 .cse68))))) .cse4) (or .cse4 (forall ((v_prenex_99 Int)) (let ((.cse69 (mod v_prenex_99 4294967296)) (.cse71 (mod c_main_~x~0 4294967296))) (let ((.cse72 (div .cse69 .cse71)) (.cse70 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse69 .cse70) (= (mod .cse69 .cse71) 0) (<= 0 .cse69) (< .cse71 (mod .cse72 4294967296)) (< .cse71 (mod (+ .cse72 1) 4294967296)) (<= (mod (div .cse69 .cse70) 4294967296) .cse70)))))) (or (forall ((v_prenex_47 Int)) (let ((.cse75 (mod v_prenex_47 4294967296)) (.cse73 (mod c_main_~x~0 4294967296))) (let ((.cse74 (div .cse75 .cse73)) (.cse76 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse73 (mod .cse74 4294967296)) (= (mod .cse75 .cse73) 0) (<= 0 .cse75) (< .cse73 (mod (+ .cse74 1) 4294967296)) (<= .cse75 .cse76) (<= (mod (div .cse75 .cse76) 4294967296) .cse76))))) .cse4) (or (forall ((v_prenex_120 Int)) (let ((.cse79 (mod v_prenex_120 4294967296)) (.cse77 (mod c_main_~x~0 4294967296))) (let ((.cse78 (div .cse79 .cse77)) (.cse80 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse77 (mod (+ .cse78 4294967295) 4294967296)) (<= 0 .cse79) (< .cse77 (mod (+ .cse78 1) 4294967296)) (<= .cse79 .cse80) (= (mod .cse79 .cse77) 0) (<= (mod (div .cse79 .cse80) 4294967296) .cse80))))) .cse9) (or .cse4 (forall ((v_prenex_119 Int)) (let ((.cse81 (mod c_main_~x~0 4294967296)) (.cse82 (mod v_prenex_119 4294967296)) (.cse83 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse81 (mod (+ (div .cse82 .cse81) 1) 4294967296)) (= (mod .cse82 .cse81) 0) (<= (mod (div .cse82 .cse83) 4294967296) .cse83) (<= 0 .cse82) (<= .cse82 .cse83))))) (or .cse4 (forall ((v_prenex_113 Int)) (let ((.cse84 (mod v_prenex_113 4294967296)) (.cse86 (mod c_main_~x~0 4294967296))) (let ((.cse85 (mod (+ c_main_~x~0 1) 4294967296)) (.cse87 (div .cse84 .cse86))) (or (<= .cse84 .cse85) (< .cse86 (mod .cse87 4294967296)) (= (mod .cse84 .cse86) 0) (<= 0 .cse84) (<= (mod (div .cse84 .cse85) 4294967296) .cse85) (< .cse86 (mod (+ .cse87 1) 4294967296))))))) (or .cse9 (forall ((v_prenex_81 Int)) (let ((.cse88 (mod c_main_~x~0 4294967296)) (.cse89 (mod v_prenex_81 4294967296)) (.cse90 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse88 (mod (div .cse89 .cse88) 4294967296)) (not (= (mod .cse89 .cse88) 0)) (<= .cse89 .cse90) (<= (mod (div .cse89 .cse90) 4294967296) .cse90))))) (or (forall ((v_prenex_97 Int)) (let ((.cse91 (mod v_prenex_97 4294967296)) (.cse93 (mod c_main_~x~0 4294967296))) (let ((.cse94 (div .cse91 .cse93)) (.cse92 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse91 .cse92) (< .cse93 (mod .cse94 4294967296)) (< .cse93 (mod (+ .cse94 1) 4294967296)) (< .cse93 (mod (+ .cse94 4294967295) 4294967296)) (<= (mod (div .cse91 .cse92) 4294967296) .cse92))))) .cse9) (forall ((v_prenex_107 Int)) (let ((.cse96 (mod (+ c_main_~x~0 1) 4294967296)) (.cse95 (mod v_prenex_107 4294967296)) (.cse97 (mod c_main_~x~0 4294967296))) (or (<= (mod (div .cse95 .cse96) 4294967296) .cse96) (not (= (mod .cse95 .cse97) 0)) (<= .cse95 .cse96) (< .cse97 (mod (div .cse95 .cse97) 4294967296))))) (or (forall ((v_prenex_74 Int)) (let ((.cse98 (mod v_prenex_74 4294967296)) (.cse100 (mod c_main_~x~0 4294967296))) (let ((.cse99 (mod (+ c_main_~x~0 1) 4294967296)) (.cse101 (div .cse98 .cse100))) (or (<= (mod (div .cse98 .cse99) 4294967296) .cse99) (< .cse100 (mod (+ .cse101 1) 4294967296)) (<= .cse98 .cse99) (< .cse98 0) (< .cse100 (mod .cse101 4294967296)))))) .cse4) (or (forall ((v_prenex_4 Int)) (let ((.cse104 (mod v_prenex_4 4294967296)) (.cse102 (mod c_main_~x~0 4294967296))) (let ((.cse105 (mod (+ c_main_~x~0 1) 4294967296)) (.cse103 (div .cse104 .cse102))) (or (< .cse102 (mod .cse103 4294967296)) (<= (mod (div .cse104 .cse105) 4294967296) .cse105) (<= .cse104 .cse105) (< .cse102 (mod (+ .cse103 1) 4294967296)) (not (= (mod .cse104 .cse102) 0)))))) .cse4) (or (forall ((v_prenex_14 Int)) (let ((.cse106 (mod v_prenex_14 4294967296)) (.cse108 (mod c_main_~x~0 4294967296))) (let ((.cse107 (mod (+ c_main_~x~0 1) 4294967296)) (.cse109 (div .cse106 .cse108))) (or (<= (mod (div .cse106 .cse107) 4294967296) .cse107) (< .cse108 (mod (+ .cse109 4294967295) 4294967296)) (< .cse106 0) (< .cse108 (mod .cse109 4294967296)) (<= .cse106 .cse107) (< .cse108 (mod (+ .cse109 1) 4294967296)))))) .cse4) (forall ((v_prenex_108 Int)) (let ((.cse110 (mod v_prenex_108 4294967296)) (.cse112 (mod c_main_~x~0 4294967296))) (let ((.cse113 (div .cse110 .cse112)) (.cse111 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= (mod (div .cse110 .cse111) 4294967296) .cse111) (< .cse112 (mod .cse113 4294967296)) (< .cse112 (mod (+ .cse113 4294967295) 4294967296)) (< .cse112 (mod (+ .cse113 1) 4294967296)) (= (mod .cse110 .cse112) 0) (<= 0 .cse110) (<= .cse110 .cse111))))) (or .cse4 (forall ((v_prenex_21 Int)) (let ((.cse114 (mod v_prenex_21 4294967296)) (.cse116 (mod c_main_~x~0 4294967296))) (let ((.cse115 (mod (+ c_main_~x~0 1) 4294967296)) (.cse117 (div .cse114 .cse116))) (or (<= (mod (div .cse114 .cse115) 4294967296) .cse115) (<= .cse114 .cse115) (not (= (mod .cse114 .cse116) 0)) (< .cse116 (mod (+ .cse117 1) 4294967296)) (< .cse116 (mod .cse117 4294967296))))))) (or .cse4 (forall ((v_prenex_89 Int)) (let ((.cse120 (mod v_prenex_89 4294967296)) (.cse118 (mod c_main_~x~0 4294967296))) (let ((.cse121 (mod (+ c_main_~x~0 1) 4294967296)) (.cse119 (div .cse120 .cse118))) (or (< .cse118 (mod (+ .cse119 1) 4294967296)) (<= (mod (div .cse120 .cse121) 4294967296) .cse121) (< .cse118 (mod .cse119 4294967296)) (<= .cse120 .cse121) (< .cse118 (mod (+ .cse119 4294967295) 4294967296))))))) (or (forall ((v_prenex_102 Int)) (let ((.cse122 (mod v_prenex_102 4294967296)) (.cse124 (mod c_main_~x~0 4294967296))) (let ((.cse123 (mod (+ c_main_~x~0 1) 4294967296)) (.cse125 (div .cse122 .cse124))) (or (<= (mod (div .cse122 .cse123) 4294967296) .cse123) (< .cse124 (mod .cse125 4294967296)) (<= .cse122 .cse123) (< .cse124 (mod (+ .cse125 1) 4294967296)) (not (= (mod .cse122 .cse124) 0)))))) .cse4) (or (forall ((v_prenex_116 Int)) (let ((.cse126 (mod v_prenex_116 4294967296)) (.cse128 (mod c_main_~x~0 4294967296))) (let ((.cse127 (mod (+ c_main_~x~0 1) 4294967296)) (.cse129 (div .cse126 .cse128))) (or (<= (mod (div .cse126 .cse127) 4294967296) .cse127) (< .cse128 (mod (+ .cse129 4294967295) 4294967296)) (<= .cse126 .cse127) (<= 0 .cse126) (= (mod .cse126 .cse128) 0) (< .cse128 (mod .cse129 4294967296)) (< .cse128 (mod (+ .cse129 1) 4294967296)))))) .cse4) (or (forall ((v_prenex_43 Int)) (let ((.cse130 (mod v_prenex_43 4294967296)) (.cse132 (mod c_main_~x~0 4294967296))) (let ((.cse131 (mod (+ c_main_~x~0 1) 4294967296)) (.cse133 (div .cse130 .cse132))) (or (<= (mod (div .cse130 .cse131) 4294967296) .cse131) (< .cse132 (mod .cse133 4294967296)) (<= .cse130 .cse131) (< .cse132 (mod (+ .cse133 1) 4294967296)) (< .cse130 0) (< .cse132 (mod (+ .cse133 4294967295) 4294967296)))))) .cse4) (or (forall ((v_prenex_112 Int)) (let ((.cse134 (mod v_prenex_112 4294967296)) (.cse135 (mod c_main_~x~0 4294967296))) (let ((.cse136 (div .cse134 .cse135)) (.cse137 (mod (+ c_main_~x~0 1) 4294967296))) (or (= (mod .cse134 .cse135) 0) (< .cse135 (mod .cse136 4294967296)) (< .cse135 (mod (+ .cse136 4294967295) 4294967296)) (<= (mod (div .cse134 .cse137) 4294967296) .cse137) (<= .cse134 .cse137) (<= 0 .cse134))))) .cse9) (or (forall ((v_prenex_73 Int)) (let ((.cse138 (mod v_prenex_73 4294967296)) (.cse140 (mod c_main_~x~0 4294967296))) (let ((.cse139 (mod (+ c_main_~x~0 1) 4294967296)) (.cse141 (div .cse138 .cse140))) (or (<= (mod (div .cse138 .cse139) 4294967296) .cse139) (<= .cse138 .cse139) (< .cse140 (mod .cse141 4294967296)) (< .cse140 (mod (+ .cse141 4294967295) 4294967296)))))) .cse9) (forall ((v_prenex_67 Int)) (let ((.cse143 (mod v_prenex_67 4294967296)) (.cse144 (mod (+ c_main_~x~0 1) 4294967296))) (or (let ((.cse142 (mod c_main_~x~0 4294967296))) (< .cse142 (mod (div .cse143 .cse142) 4294967296))) (< .cse143 0) (<= .cse143 .cse144) (<= (mod (div .cse143 .cse144) 4294967296) .cse144)))) (forall ((v_prenex_72 Int)) (let ((.cse145 (mod v_prenex_72 4294967296)) (.cse147 (mod c_main_~x~0 4294967296))) (let ((.cse146 (mod (+ c_main_~x~0 1) 4294967296)) (.cse148 (div .cse145 .cse147))) (or (<= (mod (div .cse145 .cse146) 4294967296) .cse146) (<= .cse145 .cse146) (< .cse147 (mod (+ .cse148 1) 4294967296)) (< .cse147 (mod (+ .cse148 4294967295) 4294967296)) (< .cse147 (mod .cse148 4294967296)))))) (or .cse9 (forall ((v_prenex_95 Int)) (let ((.cse151 (mod v_prenex_95 4294967296)) (.cse149 (mod c_main_~x~0 4294967296))) (let ((.cse152 (mod (+ c_main_~x~0 1) 4294967296)) (.cse150 (div .cse151 .cse149))) (or (< .cse149 (mod .cse150 4294967296)) (<= .cse151 .cse152) (<= (mod (div .cse151 .cse152) 4294967296) .cse152) (< .cse149 (mod (+ .cse150 4294967295) 4294967296))))))) (or .cse9 (forall ((v_prenex_70 Int)) (let ((.cse155 (mod v_prenex_70 4294967296)) (.cse153 (mod c_main_~x~0 4294967296))) (let ((.cse156 (mod (+ c_main_~x~0 1) 4294967296)) (.cse154 (div .cse155 .cse153))) (or (< .cse153 (mod .cse154 4294967296)) (<= (mod (div .cse155 .cse156) 4294967296) .cse156) (<= .cse155 .cse156) (< .cse153 (mod (+ .cse154 4294967295) 4294967296)) (< .cse155 0)))))) (or (forall ((v_prenex_53 Int)) (let ((.cse159 (mod v_prenex_53 4294967296)) (.cse157 (mod c_main_~x~0 4294967296))) (let ((.cse158 (div .cse159 .cse157)) (.cse160 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse157 (mod (+ .cse158 1) 4294967296)) (<= (mod (div .cse159 .cse160) 4294967296) .cse160) (< .cse157 (mod .cse158 4294967296)) (<= .cse159 .cse160))))) .cse4) (or .cse4 (forall ((v_prenex_17 Int)) (let ((.cse161 (mod c_main_~x~0 4294967296)) (.cse163 (mod (+ c_main_~x~0 1) 4294967296)) (.cse162 (mod v_prenex_17 4294967296))) (or (< .cse161 (mod (+ (div .cse162 .cse161) 1) 4294967296)) (= (mod .cse162 .cse161) 0) (<= .cse162 .cse163) (<= (mod (div .cse162 .cse163) 4294967296) .cse163) (<= 0 .cse162))))) (forall ((v_prenex_98 Int)) (let ((.cse164 (mod v_prenex_98 4294967296)) (.cse166 (mod c_main_~x~0 4294967296))) (let ((.cse165 (mod (+ c_main_~x~0 1) 4294967296)) (.cse167 (div .cse164 .cse166))) (or (<= .cse164 .cse165) (< .cse166 (mod (+ .cse167 1) 4294967296)) (<= (mod (div .cse164 .cse165) 4294967296) .cse165) (< .cse166 (mod (+ .cse167 4294967295) 4294967296)) (< .cse166 (mod .cse167 4294967296)) (< .cse164 0))))) (or (forall ((v_prenex_111 Int)) (let ((.cse168 (mod v_prenex_111 4294967296)) (.cse169 (mod c_main_~x~0 4294967296))) (let ((.cse170 (mod (+ c_main_~x~0 1) 4294967296)) (.cse171 (div .cse168 .cse169))) (or (not (= (mod .cse168 .cse169) 0)) (<= .cse168 .cse170) (< .cse169 (mod .cse171 4294967296)) (<= (mod (div .cse168 .cse170) 4294967296) .cse170) (< .cse169 (mod (+ .cse171 4294967295) 4294967296)))))) .cse9) (or .cse4 (forall ((v_prenex_100 Int)) (let ((.cse172 (mod v_prenex_100 4294967296)) (.cse174 (mod c_main_~x~0 4294967296))) (let ((.cse175 (div .cse172 .cse174)) (.cse173 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= (mod (div .cse172 .cse173) 4294967296) .cse173) (< .cse174 (mod (+ .cse175 1) 4294967296)) (< .cse174 (mod .cse175 4294967296)) (<= .cse172 .cse173)))))) (or .cse4 (forall ((v_prenex_48 Int)) (let ((.cse178 (mod v_prenex_48 4294967296)) (.cse176 (mod c_main_~x~0 4294967296))) (let ((.cse179 (mod (+ c_main_~x~0 1) 4294967296)) (.cse177 (div .cse178 .cse176))) (or (< .cse176 (mod (+ .cse177 4294967295) 4294967296)) (<= .cse178 .cse179) (<= (mod (div .cse178 .cse179) 4294967296) .cse179) (<= 0 .cse178) (= (mod .cse178 .cse176) 0) (< .cse176 (mod (+ .cse177 1) 4294967296))))))) (or (forall ((v_prenex_44 Int)) (let ((.cse182 (mod v_prenex_44 4294967296)) (.cse180 (mod c_main_~x~0 4294967296))) (let ((.cse181 (div .cse182 .cse180)) (.cse183 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse180 (mod (+ .cse181 1) 4294967296)) (< .cse180 (mod .cse181 4294967296)) (<= (mod (div .cse182 .cse183) 4294967296) .cse183) (<= .cse182 .cse183))))) .cse4) (or (forall ((v_prenex_8 Int)) (let ((.cse186 (mod v_prenex_8 4294967296)) (.cse184 (mod c_main_~x~0 4294967296))) (let ((.cse185 (div .cse186 .cse184)) (.cse187 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse184 (mod .cse185 4294967296)) (< .cse184 (mod (+ .cse185 1) 4294967296)) (<= .cse186 .cse187) (<= (mod (div .cse186 .cse187) 4294967296) .cse187) (< .cse186 0))))) .cse4) (or (forall ((v_prenex_110 Int)) (let ((.cse190 (mod v_prenex_110 4294967296)) (.cse188 (mod c_main_~x~0 4294967296))) (let ((.cse191 (mod (+ c_main_~x~0 1) 4294967296)) (.cse189 (div .cse190 .cse188))) (or (< .cse188 (mod (+ .cse189 1) 4294967296)) (<= .cse190 .cse191) (not (= (mod .cse190 .cse188) 0)) (<= (mod (div .cse190 .cse191) 4294967296) .cse191) (< .cse188 (mod .cse189 4294967296)))))) .cse4) (or (forall ((v_prenex_79 Int)) (let ((.cse194 (mod v_prenex_79 4294967296)) (.cse192 (mod c_main_~x~0 4294967296))) (let ((.cse193 (div .cse194 .cse192)) (.cse195 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse192 (mod .cse193 4294967296)) (= (mod .cse194 .cse192) 0) (<= .cse194 .cse195) (< .cse192 (mod (+ .cse193 1) 4294967296)) (<= 0 .cse194) (<= (mod (div .cse194 .cse195) 4294967296) .cse195))))) .cse4) (forall ((v_prenex_124 Int)) (let ((.cse198 (mod v_prenex_124 4294967296)) (.cse196 (mod c_main_~x~0 4294967296))) (let ((.cse199 (mod (+ c_main_~x~0 1) 4294967296)) (.cse197 (div .cse198 .cse196))) (or (< .cse196 (mod .cse197 4294967296)) (<= .cse198 .cse199) (<= (mod (div .cse198 .cse199) 4294967296) .cse199) (not (= (mod .cse198 .cse196) 0)) (< .cse196 (mod (+ .cse197 1) 4294967296)))))) (or (forall ((v_prenex_83 Int)) (let ((.cse202 (mod v_prenex_83 4294967296)) (.cse200 (mod c_main_~x~0 4294967296))) (let ((.cse203 (mod (+ c_main_~x~0 1) 4294967296)) (.cse201 (div .cse202 .cse200))) (or (< .cse200 (mod .cse201 4294967296)) (not (= (mod .cse202 .cse200) 0)) (<= .cse202 .cse203) (< .cse200 (mod (+ .cse201 4294967295) 4294967296)) (<= (mod (div .cse202 .cse203) 4294967296) .cse203) (< .cse200 (mod (+ .cse201 1) 4294967296)))))) .cse9) (forall ((v_prenex_117 Int)) (let ((.cse204 (mod v_prenex_117 4294967296)) (.cse206 (mod c_main_~x~0 4294967296))) (let ((.cse205 (mod (+ c_main_~x~0 1) 4294967296)) (.cse207 (div .cse204 .cse206))) (or (<= .cse204 .cse205) (< .cse206 (mod .cse207 4294967296)) (<= (mod (div .cse204 .cse205) 4294967296) .cse205) (< .cse204 0) (< .cse206 (mod (+ .cse207 1) 4294967296)))))) (or .cse9 (forall ((v_prenex_93 Int)) (let ((.cse210 (mod v_prenex_93 4294967296)) (.cse208 (mod c_main_~x~0 4294967296))) (let ((.cse209 (div .cse210 .cse208)) (.cse211 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse208 (mod (+ .cse209 4294967295) 4294967296)) (< .cse208 (mod .cse209 4294967296)) (<= (mod (div .cse210 .cse211) 4294967296) .cse211) (<= .cse210 .cse211) (< .cse210 0)))))) (or (forall ((v_prenex_123 Int)) (let ((.cse214 (mod v_prenex_123 4294967296)) (.cse212 (mod c_main_~x~0 4294967296))) (let ((.cse213 (div .cse214 .cse212)) (.cse215 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse212 (mod .cse213 4294967296)) (= (mod .cse214 .cse212) 0) (<= (mod (div .cse214 .cse215) 4294967296) .cse215) (<= 0 .cse214) (< .cse212 (mod (+ .cse213 1) 4294967296)) (< .cse212 (mod (+ .cse213 4294967295) 4294967296)) (<= .cse214 .cse215))))) .cse9) (or .cse4 (forall ((v_prenex_35 Int)) (let ((.cse218 (mod v_prenex_35 4294967296)) (.cse216 (mod c_main_~x~0 4294967296))) (let ((.cse217 (div .cse218 .cse216)) (.cse219 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse216 (mod .cse217 4294967296)) (< .cse218 0) (< .cse216 (mod (+ .cse217 1) 4294967296)) (<= (mod (div .cse218 .cse219) 4294967296) .cse219) (<= .cse218 .cse219)))))) (forall ((v_prenex_114 Int)) (let ((.cse220 (mod v_prenex_114 4294967296)) (.cse222 (mod c_main_~x~0 4294967296))) (let ((.cse221 (mod (+ c_main_~x~0 1) 4294967296)) (.cse223 (div .cse220 .cse222))) (or (<= .cse220 .cse221) (<= 0 .cse220) (< .cse222 (mod (+ .cse223 4294967295) 4294967296)) (< .cse222 (mod .cse223 4294967296)) (<= (mod (div .cse220 .cse221) 4294967296) .cse221) (= (mod .cse220 .cse222) 0) (< .cse222 (mod (+ .cse223 1) 4294967296)))))) (or (forall ((v_prenex_56 Int)) (let ((.cse224 (mod v_prenex_56 4294967296)) (.cse225 (mod c_main_~x~0 4294967296))) (let ((.cse226 (div .cse224 .cse225)) (.cse227 (mod (+ c_main_~x~0 1) 4294967296))) (or (not (= (mod .cse224 .cse225) 0)) (< .cse225 (mod .cse226 4294967296)) (< .cse225 (mod (+ .cse226 1) 4294967296)) (< .cse225 (mod (+ .cse226 4294967295) 4294967296)) (<= .cse224 .cse227) (<= (mod (div .cse224 .cse227) 4294967296) .cse227))))) .cse4) (or .cse9 (forall ((v_prenex_82 Int)) (let ((.cse230 (mod v_prenex_82 4294967296)) (.cse228 (mod c_main_~x~0 4294967296))) (let ((.cse229 (div .cse230 .cse228)) (.cse231 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse228 (mod (+ .cse229 4294967295) 4294967296)) (< .cse228 (mod .cse229 4294967296)) (<= .cse230 .cse231) (not (= (mod .cse230 .cse228) 0)) (<= (mod (div .cse230 .cse231) 4294967296) .cse231)))))) (or (forall ((v_prenex_125 Int)) (let ((.cse233 (mod c_main_~x~0 4294967296)) (.cse232 (mod v_prenex_125 4294967296)) (.cse234 (mod (+ c_main_~x~0 1) 4294967296))) (or (= (mod .cse232 .cse233) 0) (<= .cse232 .cse234) (< .cse233 (mod (+ (div .cse232 .cse233) 4294967295) 4294967296)) (<= 0 .cse232) (<= (mod (div .cse232 .cse234) 4294967296) .cse234)))) .cse9)))) is different from false [2018-11-18 10:22:05,483 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 3 not checked. [2018-11-18 10:22:05,510 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:22:05,511 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-11-18 10:22:05,511 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-18 10:22:05,511 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-18 10:22:05,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-18 10:22:05,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=20, Unknown=2, NotChecked=18, Total=56 [2018-11-18 10:22:05,512 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. Second operand 8 states. [2018-11-18 10:22:07,672 WARN L854 $PredicateComparison]: unable to prove that (let ((.cse217 (mod c_main_~x~0 4294967296))) (let ((.cse69 (forall ((v_prenex_69 Int)) (let ((.cse224 (mod v_prenex_69 4294967296)) (.cse222 (mod c_main_~x~0 4294967296))) (let ((.cse223 (div .cse224 .cse222)) (.cse225 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse222 (mod (+ .cse223 1) 4294967296)) (<= 0 .cse224) (<= .cse224 .cse225) (< .cse222 (mod (+ .cse223 4294967295) 4294967296)) (<= (mod (div .cse224 .cse225) 4294967296) .cse225) (= (mod .cse224 .cse222) 0)))))) (.cse70 (forall ((v_prenex_69 Int)) (let ((.cse220 (mod v_prenex_69 4294967296)) (.cse218 (mod c_main_~x~0 4294967296))) (let ((.cse219 (div .cse220 .cse218)) (.cse221 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse218 (mod (+ .cse219 1) 4294967296)) (< .cse218 (mod .cse219 4294967296)) (<= 0 .cse220) (<= .cse220 .cse221) (< .cse218 (mod (+ .cse219 4294967295) 4294967296)) (<= (mod (div .cse220 .cse221) 4294967296) .cse221) (= (mod .cse220 .cse218) 0)))))) (.cse0 (< .cse217 0)) (.cse5 (<= 0 .cse217))) (and (or .cse0 (forall ((v_prenex_51 Int)) (let ((.cse3 (mod v_prenex_51 4294967296)) (.cse1 (mod c_main_~x~0 4294967296))) (let ((.cse2 (div .cse3 .cse1)) (.cse4 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse1 (mod (+ .cse2 1) 4294967296)) (< .cse1 (mod .cse2 4294967296)) (<= .cse3 .cse4) (not (= (mod .cse3 .cse1) 0)) (<= (mod (div .cse3 .cse4) 4294967296) .cse4)))))) (or .cse5 (forall ((v_prenex_69 Int)) (let ((.cse8 (mod v_prenex_69 4294967296)) (.cse6 (mod c_main_~x~0 4294967296))) (let ((.cse7 (div .cse8 .cse6)) (.cse9 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse6 (mod .cse7 4294967296)) (<= 0 .cse8) (<= .cse8 .cse9) (< .cse6 (mod (+ .cse7 4294967295) 4294967296)) (<= (mod (div .cse8 .cse9) 4294967296) .cse9) (= (mod .cse8 .cse6) 0)))))) (or (forall ((v_prenex_49 Int)) (let ((.cse12 (mod v_prenex_49 4294967296)) (.cse10 (mod c_main_~x~0 4294967296))) (let ((.cse11 (div .cse12 .cse10)) (.cse13 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse10 (mod (+ .cse11 4294967295) 4294967296)) (< .cse10 (mod .cse11 4294967296)) (<= .cse12 .cse13) (< .cse10 (mod (+ .cse11 1) 4294967296)) (<= (mod (div .cse12 .cse13) 4294967296) .cse13))))) .cse0) (or (forall ((v_prenex_71 Int)) (let ((.cse16 (mod (+ c_main_~x~0 1) 4294967296)) (.cse15 (mod v_prenex_71 4294967296))) (or (let ((.cse14 (mod c_main_~x~0 4294967296))) (< .cse14 (mod (div .cse15 .cse14) 4294967296))) (<= .cse15 .cse16) (<= (mod (div .cse15 .cse16) 4294967296) .cse16) (< .cse15 0)))) .cse5) (or (forall ((v_prenex_65 Int)) (let ((.cse19 (mod v_prenex_65 4294967296)) (.cse17 (mod c_main_~x~0 4294967296))) (let ((.cse20 (mod (+ c_main_~x~0 1) 4294967296)) (.cse18 (div .cse19 .cse17))) (or (< .cse17 (mod .cse18 4294967296)) (<= .cse19 .cse20) (<= (mod (div .cse19 .cse20) 4294967296) .cse20) (< .cse17 (mod (+ .cse18 1) 4294967296)) (< .cse19 0) (< .cse17 (mod (+ .cse18 4294967295) 4294967296)))))) .cse0) (or (forall ((v_prenex_90 Int)) (let ((.cse23 (mod v_prenex_90 4294967296)) (.cse21 (mod c_main_~x~0 4294967296))) (let ((.cse22 (div .cse23 .cse21)) (.cse24 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse21 (mod (+ .cse22 1) 4294967296)) (< .cse21 (mod .cse22 4294967296)) (<= .cse23 .cse24) (< .cse21 (mod (+ .cse22 4294967295) 4294967296)) (<= (mod (div .cse23 .cse24) 4294967296) .cse24) (< .cse23 0))))) .cse5) (or (forall ((v_prenex_69 Int)) (let ((.cse27 (mod v_prenex_69 4294967296)) (.cse25 (mod c_main_~x~0 4294967296))) (let ((.cse26 (div .cse27 .cse25)) (.cse28 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse25 (mod (+ .cse26 1) 4294967296)) (< .cse25 (mod .cse26 4294967296)) (<= 0 .cse27) (<= .cse27 .cse28) (<= (mod (div .cse27 .cse28) 4294967296) .cse28) (= (mod .cse27 .cse25) 0))))) .cse0) (or (forall ((v_prenex_61 Int)) (let ((.cse31 (mod v_prenex_61 4294967296)) (.cse29 (mod c_main_~x~0 4294967296))) (let ((.cse32 (mod (+ c_main_~x~0 1) 4294967296)) (.cse30 (div .cse31 .cse29))) (or (< .cse29 (mod (+ .cse30 1) 4294967296)) (<= .cse31 .cse32) (<= (mod (div .cse31 .cse32) 4294967296) .cse32) (< .cse29 (mod .cse30 4294967296)))))) .cse0) (or (forall ((v_prenex_30 Int)) (let ((.cse35 (mod v_prenex_30 4294967296)) (.cse33 (mod c_main_~x~0 4294967296))) (let ((.cse36 (mod (+ c_main_~x~0 1) 4294967296)) (.cse34 (div .cse35 .cse33))) (or (< .cse33 (mod (+ .cse34 1) 4294967296)) (<= (mod (div .cse35 .cse36) 4294967296) .cse36) (<= .cse35 .cse36) (< .cse33 (mod (+ .cse34 4294967295) 4294967296)) (< .cse33 (mod .cse34 4294967296)))))) .cse0) (or .cse0 (forall ((v_prenex_23 Int)) (let ((.cse37 (mod v_prenex_23 4294967296)) (.cse38 (mod c_main_~x~0 4294967296))) (let ((.cse39 (mod (+ c_main_~x~0 1) 4294967296)) (.cse40 (div .cse37 .cse38))) (or (not (= (mod .cse37 .cse38) 0)) (<= .cse37 .cse39) (< .cse38 (mod (+ .cse40 4294967295) 4294967296)) (< .cse38 (mod .cse40 4294967296)) (<= (mod (div .cse37 .cse39) 4294967296) .cse39) (< .cse38 (mod (+ .cse40 1) 4294967296))))))) (or (forall ((v_prenex_7 Int)) (let ((.cse41 (mod v_prenex_7 4294967296)) (.cse43 (mod c_main_~x~0 4294967296))) (let ((.cse42 (mod (+ c_main_~x~0 1) 4294967296)) (.cse44 (div .cse41 .cse43))) (or (<= .cse41 .cse42) (<= (mod (div .cse41 .cse42) 4294967296) .cse42) (< .cse43 (mod .cse44 4294967296)) (< .cse43 (mod (+ .cse44 4294967295) 4294967296)) (not (= (mod .cse41 .cse43) 0)) (< .cse43 (mod (+ .cse44 1) 4294967296)))))) .cse0) (forall ((v_prenex_80 Int)) (let ((.cse45 (mod v_prenex_80 4294967296)) (.cse46 (mod c_main_~x~0 4294967296))) (let ((.cse48 (mod (+ c_main_~x~0 1) 4294967296)) (.cse47 (div .cse45 .cse46))) (or (not (= (mod .cse45 .cse46) 0)) (< .cse46 (mod (+ .cse47 1) 4294967296)) (<= (mod (div .cse45 .cse48) 4294967296) .cse48) (< .cse46 (mod .cse47 4294967296)) (<= .cse45 .cse48) (< .cse46 (mod (+ .cse47 4294967295) 4294967296)))))) (or (forall ((v_prenex_103 Int)) (let ((.cse51 (mod v_prenex_103 4294967296)) (.cse49 (mod c_main_~x~0 4294967296))) (let ((.cse50 (div .cse51 .cse49)) (.cse52 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse49 (mod .cse50 4294967296)) (< .cse51 0) (<= .cse51 .cse52) (< .cse49 (mod (+ .cse50 1) 4294967296)) (<= (mod (div .cse51 .cse52) 4294967296) .cse52))))) .cse0) (or (forall ((v_prenex_66 Int)) (let ((.cse55 (mod v_prenex_66 4294967296)) (.cse53 (mod c_main_~x~0 4294967296))) (let ((.cse54 (div .cse55 .cse53)) (.cse56 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse53 (mod .cse54 4294967296)) (< .cse53 (mod (+ .cse54 1) 4294967296)) (<= .cse55 .cse56) (< .cse55 0) (<= (mod (div .cse55 .cse56) 4294967296) .cse56))))) .cse0) (or .cse0 (forall ((v_prenex_99 Int)) (let ((.cse57 (mod v_prenex_99 4294967296)) (.cse59 (mod c_main_~x~0 4294967296))) (let ((.cse60 (div .cse57 .cse59)) (.cse58 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse57 .cse58) (= (mod .cse57 .cse59) 0) (<= 0 .cse57) (< .cse59 (mod .cse60 4294967296)) (< .cse59 (mod (+ .cse60 1) 4294967296)) (<= (mod (div .cse57 .cse58) 4294967296) .cse58)))))) (or (forall ((v_prenex_47 Int)) (let ((.cse63 (mod v_prenex_47 4294967296)) (.cse61 (mod c_main_~x~0 4294967296))) (let ((.cse62 (div .cse63 .cse61)) (.cse64 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse61 (mod .cse62 4294967296)) (= (mod .cse63 .cse61) 0) (<= 0 .cse63) (< .cse61 (mod (+ .cse62 1) 4294967296)) (<= .cse63 .cse64) (<= (mod (div .cse63 .cse64) 4294967296) .cse64))))) .cse0) (= c_main_~x~0 1) (forall ((v_prenex_99 Int)) (let ((.cse65 (mod v_prenex_99 4294967296)) (.cse67 (mod c_main_~x~0 4294967296))) (let ((.cse68 (div .cse65 .cse67)) (.cse66 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse65 .cse66) (= (mod .cse65 .cse67) 0) (< .cse67 (mod (+ .cse68 4294967295) 4294967296)) (<= 0 .cse65) (< .cse67 (mod .cse68 4294967296)) (< .cse67 (mod (+ .cse68 1) 4294967296)) (<= (mod (div .cse65 .cse66) 4294967296) .cse66))))) .cse69 (or .cse0 .cse70) (or .cse5 (forall ((v_prenex_81 Int)) (let ((.cse71 (mod c_main_~x~0 4294967296)) (.cse72 (mod v_prenex_81 4294967296)) (.cse73 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse71 (mod (div .cse72 .cse71) 4294967296)) (not (= (mod .cse72 .cse71) 0)) (<= .cse72 .cse73) (<= (mod (div .cse72 .cse73) 4294967296) .cse73))))) (or (forall ((v_prenex_97 Int)) (let ((.cse74 (mod v_prenex_97 4294967296)) (.cse76 (mod c_main_~x~0 4294967296))) (let ((.cse77 (div .cse74 .cse76)) (.cse75 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse74 .cse75) (< .cse76 (mod .cse77 4294967296)) (< .cse76 (mod (+ .cse77 1) 4294967296)) (< .cse76 (mod (+ .cse77 4294967295) 4294967296)) (<= (mod (div .cse74 .cse75) 4294967296) .cse75))))) .cse5) (forall ((v_prenex_107 Int)) (let ((.cse79 (mod (+ c_main_~x~0 1) 4294967296)) (.cse78 (mod v_prenex_107 4294967296)) (.cse80 (mod c_main_~x~0 4294967296))) (or (<= (mod (div .cse78 .cse79) 4294967296) .cse79) (not (= (mod .cse78 .cse80) 0)) (<= .cse78 .cse79) (< .cse80 (mod (div .cse78 .cse80) 4294967296))))) (forall ((v_prenex_71 Int)) (let ((.cse83 (mod v_prenex_71 4294967296)) (.cse81 (mod c_main_~x~0 4294967296))) (let ((.cse84 (mod (+ c_main_~x~0 1) 4294967296)) (.cse82 (div .cse83 .cse81))) (or (< .cse81 (mod .cse82 4294967296)) (<= .cse83 .cse84) (<= (mod (div .cse83 .cse84) 4294967296) .cse84) (< .cse83 0) (< .cse81 (mod (+ .cse82 1) 4294967296)))))) (or (forall ((v_prenex_47 Int)) (let ((.cse87 (mod v_prenex_47 4294967296)) (.cse85 (mod c_main_~x~0 4294967296))) (let ((.cse86 (div .cse87 .cse85)) (.cse88 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse85 (mod (+ .cse86 4294967295) 4294967296)) (< .cse85 (mod .cse86 4294967296)) (= (mod .cse87 .cse85) 0) (<= 0 .cse87) (< .cse85 (mod (+ .cse86 1) 4294967296)) (<= .cse87 .cse88) (<= (mod (div .cse87 .cse88) 4294967296) .cse88))))) .cse0) (or (forall ((v_prenex_74 Int)) (let ((.cse89 (mod v_prenex_74 4294967296)) (.cse91 (mod c_main_~x~0 4294967296))) (let ((.cse90 (mod (+ c_main_~x~0 1) 4294967296)) (.cse92 (div .cse89 .cse91))) (or (<= (mod (div .cse89 .cse90) 4294967296) .cse90) (< .cse91 (mod (+ .cse92 1) 4294967296)) (<= .cse89 .cse90) (< .cse89 0) (< .cse91 (mod .cse92 4294967296)))))) .cse0) (or (forall ((v_prenex_4 Int)) (let ((.cse95 (mod v_prenex_4 4294967296)) (.cse93 (mod c_main_~x~0 4294967296))) (let ((.cse96 (mod (+ c_main_~x~0 1) 4294967296)) (.cse94 (div .cse95 .cse93))) (or (< .cse93 (mod .cse94 4294967296)) (<= (mod (div .cse95 .cse96) 4294967296) .cse96) (<= .cse95 .cse96) (< .cse93 (mod (+ .cse94 1) 4294967296)) (not (= (mod .cse95 .cse93) 0)))))) .cse0) (or (forall ((v_prenex_69 Int)) (let ((.cse99 (mod (+ c_main_~x~0 1) 4294967296)) (.cse98 (mod v_prenex_69 4294967296)) (.cse97 (mod c_main_~x~0 4294967296))) (or (< .cse97 (mod (+ (div .cse98 .cse97) 1) 4294967296)) (<= 0 .cse98) (<= .cse98 .cse99) (<= (mod (div .cse98 .cse99) 4294967296) .cse99) (= (mod .cse98 .cse97) 0)))) .cse0) (or (forall ((v_prenex_14 Int)) (let ((.cse100 (mod v_prenex_14 4294967296)) (.cse102 (mod c_main_~x~0 4294967296))) (let ((.cse101 (mod (+ c_main_~x~0 1) 4294967296)) (.cse103 (div .cse100 .cse102))) (or (<= (mod (div .cse100 .cse101) 4294967296) .cse101) (< .cse102 (mod (+ .cse103 4294967295) 4294967296)) (< .cse100 0) (< .cse102 (mod .cse103 4294967296)) (<= .cse100 .cse101) (< .cse102 (mod (+ .cse103 1) 4294967296)))))) .cse0) (forall ((v_prenex_108 Int)) (let ((.cse104 (mod v_prenex_108 4294967296)) (.cse106 (mod c_main_~x~0 4294967296))) (let ((.cse107 (div .cse104 .cse106)) (.cse105 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= (mod (div .cse104 .cse105) 4294967296) .cse105) (< .cse106 (mod .cse107 4294967296)) (< .cse106 (mod (+ .cse107 4294967295) 4294967296)) (< .cse106 (mod (+ .cse107 1) 4294967296)) (= (mod .cse104 .cse106) 0) (<= 0 .cse104) (<= .cse104 .cse105))))) (or .cse0 (forall ((v_prenex_21 Int)) (let ((.cse108 (mod v_prenex_21 4294967296)) (.cse110 (mod c_main_~x~0 4294967296))) (let ((.cse109 (mod (+ c_main_~x~0 1) 4294967296)) (.cse111 (div .cse108 .cse110))) (or (<= (mod (div .cse108 .cse109) 4294967296) .cse109) (<= .cse108 .cse109) (not (= (mod .cse108 .cse110) 0)) (< .cse110 (mod (+ .cse111 1) 4294967296)) (< .cse110 (mod .cse111 4294967296))))))) (or .cse0 (forall ((v_prenex_89 Int)) (let ((.cse114 (mod v_prenex_89 4294967296)) (.cse112 (mod c_main_~x~0 4294967296))) (let ((.cse115 (mod (+ c_main_~x~0 1) 4294967296)) (.cse113 (div .cse114 .cse112))) (or (< .cse112 (mod (+ .cse113 1) 4294967296)) (<= (mod (div .cse114 .cse115) 4294967296) .cse115) (< .cse112 (mod .cse113 4294967296)) (<= .cse114 .cse115) (< .cse112 (mod (+ .cse113 4294967295) 4294967296))))))) (or (forall ((v_prenex_102 Int)) (let ((.cse116 (mod v_prenex_102 4294967296)) (.cse118 (mod c_main_~x~0 4294967296))) (let ((.cse117 (mod (+ c_main_~x~0 1) 4294967296)) (.cse119 (div .cse116 .cse118))) (or (<= (mod (div .cse116 .cse117) 4294967296) .cse117) (< .cse118 (mod .cse119 4294967296)) (<= .cse116 .cse117) (< .cse118 (mod (+ .cse119 1) 4294967296)) (not (= (mod .cse116 .cse118) 0)))))) .cse0) (or .cse5 .cse69) (or (forall ((v_prenex_43 Int)) (let ((.cse120 (mod v_prenex_43 4294967296)) (.cse122 (mod c_main_~x~0 4294967296))) (let ((.cse121 (mod (+ c_main_~x~0 1) 4294967296)) (.cse123 (div .cse120 .cse122))) (or (<= (mod (div .cse120 .cse121) 4294967296) .cse121) (< .cse122 (mod .cse123 4294967296)) (<= .cse120 .cse121) (< .cse122 (mod (+ .cse123 1) 4294967296)) (< .cse120 0) (< .cse122 (mod (+ .cse123 4294967295) 4294967296)))))) .cse0) (or (forall ((v_prenex_112 Int)) (let ((.cse124 (mod v_prenex_112 4294967296)) (.cse125 (mod c_main_~x~0 4294967296))) (let ((.cse126 (div .cse124 .cse125)) (.cse127 (mod (+ c_main_~x~0 1) 4294967296))) (or (= (mod .cse124 .cse125) 0) (< .cse125 (mod .cse126 4294967296)) (< .cse125 (mod (+ .cse126 4294967295) 4294967296)) (<= (mod (div .cse124 .cse127) 4294967296) .cse127) (<= .cse124 .cse127) (<= 0 .cse124))))) .cse5) (or (forall ((v_prenex_73 Int)) (let ((.cse128 (mod v_prenex_73 4294967296)) (.cse130 (mod c_main_~x~0 4294967296))) (let ((.cse129 (mod (+ c_main_~x~0 1) 4294967296)) (.cse131 (div .cse128 .cse130))) (or (<= (mod (div .cse128 .cse129) 4294967296) .cse129) (<= .cse128 .cse129) (< .cse130 (mod .cse131 4294967296)) (< .cse130 (mod (+ .cse131 4294967295) 4294967296)))))) .cse5) (forall ((v_prenex_67 Int)) (let ((.cse133 (mod v_prenex_67 4294967296)) (.cse134 (mod (+ c_main_~x~0 1) 4294967296))) (or (let ((.cse132 (mod c_main_~x~0 4294967296))) (< .cse132 (mod (div .cse133 .cse132) 4294967296))) (< .cse133 0) (<= .cse133 .cse134) (<= (mod (div .cse133 .cse134) 4294967296) .cse134)))) (forall ((v_prenex_72 Int)) (let ((.cse135 (mod v_prenex_72 4294967296)) (.cse137 (mod c_main_~x~0 4294967296))) (let ((.cse136 (mod (+ c_main_~x~0 1) 4294967296)) (.cse138 (div .cse135 .cse137))) (or (<= (mod (div .cse135 .cse136) 4294967296) .cse136) (<= .cse135 .cse136) (< .cse137 (mod (+ .cse138 1) 4294967296)) (< .cse137 (mod (+ .cse138 4294967295) 4294967296)) (< .cse137 (mod .cse138 4294967296)))))) (or .cse5 (forall ((v_prenex_95 Int)) (let ((.cse141 (mod v_prenex_95 4294967296)) (.cse139 (mod c_main_~x~0 4294967296))) (let ((.cse142 (mod (+ c_main_~x~0 1) 4294967296)) (.cse140 (div .cse141 .cse139))) (or (< .cse139 (mod .cse140 4294967296)) (<= .cse141 .cse142) (<= (mod (div .cse141 .cse142) 4294967296) .cse142) (< .cse139 (mod (+ .cse140 4294967295) 4294967296))))))) .cse70 (or (forall ((v_prenex_99 Int)) (let ((.cse143 (mod v_prenex_99 4294967296)) (.cse145 (mod c_main_~x~0 4294967296))) (let ((.cse146 (div .cse143 .cse145)) (.cse144 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= .cse143 .cse144) (= (mod .cse143 .cse145) 0) (< .cse145 (mod (+ .cse146 4294967295) 4294967296)) (<= 0 .cse143) (< .cse145 (mod .cse146 4294967296)) (<= (mod (div .cse143 .cse144) 4294967296) .cse144))))) .cse5) (or .cse5 (forall ((v_prenex_70 Int)) (let ((.cse149 (mod v_prenex_70 4294967296)) (.cse147 (mod c_main_~x~0 4294967296))) (let ((.cse150 (mod (+ c_main_~x~0 1) 4294967296)) (.cse148 (div .cse149 .cse147))) (or (< .cse147 (mod .cse148 4294967296)) (<= (mod (div .cse149 .cse150) 4294967296) .cse150) (<= .cse149 .cse150) (< .cse147 (mod (+ .cse148 4294967295) 4294967296)) (< .cse149 0)))))) (or (forall ((v_prenex_53 Int)) (let ((.cse153 (mod v_prenex_53 4294967296)) (.cse151 (mod c_main_~x~0 4294967296))) (let ((.cse152 (div .cse153 .cse151)) (.cse154 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse151 (mod (+ .cse152 1) 4294967296)) (<= (mod (div .cse153 .cse154) 4294967296) .cse154) (< .cse151 (mod .cse152 4294967296)) (<= .cse153 .cse154))))) .cse0) (or .cse0 (forall ((v_prenex_17 Int)) (let ((.cse155 (mod c_main_~x~0 4294967296)) (.cse157 (mod (+ c_main_~x~0 1) 4294967296)) (.cse156 (mod v_prenex_17 4294967296))) (or (< .cse155 (mod (+ (div .cse156 .cse155) 1) 4294967296)) (= (mod .cse156 .cse155) 0) (<= .cse156 .cse157) (<= (mod (div .cse156 .cse157) 4294967296) .cse157) (<= 0 .cse156))))) (forall ((v_prenex_98 Int)) (let ((.cse158 (mod v_prenex_98 4294967296)) (.cse160 (mod c_main_~x~0 4294967296))) (let ((.cse159 (mod (+ c_main_~x~0 1) 4294967296)) (.cse161 (div .cse158 .cse160))) (or (<= .cse158 .cse159) (< .cse160 (mod (+ .cse161 1) 4294967296)) (<= (mod (div .cse158 .cse159) 4294967296) .cse159) (< .cse160 (mod (+ .cse161 4294967295) 4294967296)) (< .cse160 (mod .cse161 4294967296)) (< .cse158 0))))) (or (forall ((v_prenex_111 Int)) (let ((.cse162 (mod v_prenex_111 4294967296)) (.cse163 (mod c_main_~x~0 4294967296))) (let ((.cse164 (mod (+ c_main_~x~0 1) 4294967296)) (.cse165 (div .cse162 .cse163))) (or (not (= (mod .cse162 .cse163) 0)) (<= .cse162 .cse164) (< .cse163 (mod .cse165 4294967296)) (<= (mod (div .cse162 .cse164) 4294967296) .cse164) (< .cse163 (mod (+ .cse165 4294967295) 4294967296)))))) .cse5) (or .cse0 (forall ((v_prenex_100 Int)) (let ((.cse166 (mod v_prenex_100 4294967296)) (.cse168 (mod c_main_~x~0 4294967296))) (let ((.cse169 (div .cse166 .cse168)) (.cse167 (mod (+ c_main_~x~0 1) 4294967296))) (or (<= (mod (div .cse166 .cse167) 4294967296) .cse167) (< .cse168 (mod (+ .cse169 1) 4294967296)) (< .cse168 (mod .cse169 4294967296)) (<= .cse166 .cse167)))))) (or .cse0 (forall ((v_prenex_48 Int)) (let ((.cse172 (mod v_prenex_48 4294967296)) (.cse170 (mod c_main_~x~0 4294967296))) (let ((.cse173 (mod (+ c_main_~x~0 1) 4294967296)) (.cse171 (div .cse172 .cse170))) (or (< .cse170 (mod (+ .cse171 4294967295) 4294967296)) (<= .cse172 .cse173) (<= (mod (div .cse172 .cse173) 4294967296) .cse173) (<= 0 .cse172) (= (mod .cse172 .cse170) 0) (< .cse170 (mod (+ .cse171 1) 4294967296))))))) (or (forall ((v_prenex_44 Int)) (let ((.cse176 (mod v_prenex_44 4294967296)) (.cse174 (mod c_main_~x~0 4294967296))) (let ((.cse175 (div .cse176 .cse174)) (.cse177 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse174 (mod (+ .cse175 1) 4294967296)) (< .cse174 (mod .cse175 4294967296)) (<= (mod (div .cse176 .cse177) 4294967296) .cse177) (<= .cse176 .cse177))))) .cse0) (or (forall ((v_prenex_8 Int)) (let ((.cse180 (mod v_prenex_8 4294967296)) (.cse178 (mod c_main_~x~0 4294967296))) (let ((.cse179 (div .cse180 .cse178)) (.cse181 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse178 (mod .cse179 4294967296)) (< .cse178 (mod (+ .cse179 1) 4294967296)) (<= .cse180 .cse181) (<= (mod (div .cse180 .cse181) 4294967296) .cse181) (< .cse180 0))))) .cse0) (or (forall ((v_prenex_110 Int)) (let ((.cse184 (mod v_prenex_110 4294967296)) (.cse182 (mod c_main_~x~0 4294967296))) (let ((.cse185 (mod (+ c_main_~x~0 1) 4294967296)) (.cse183 (div .cse184 .cse182))) (or (< .cse182 (mod (+ .cse183 1) 4294967296)) (<= .cse184 .cse185) (not (= (mod .cse184 .cse182) 0)) (<= (mod (div .cse184 .cse185) 4294967296) .cse185) (< .cse182 (mod .cse183 4294967296)))))) .cse0) (or (forall ((v_prenex_79 Int)) (let ((.cse188 (mod v_prenex_79 4294967296)) (.cse186 (mod c_main_~x~0 4294967296))) (let ((.cse187 (div .cse188 .cse186)) (.cse189 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse186 (mod .cse187 4294967296)) (= (mod .cse188 .cse186) 0) (<= .cse188 .cse189) (< .cse186 (mod (+ .cse187 1) 4294967296)) (<= 0 .cse188) (<= (mod (div .cse188 .cse189) 4294967296) .cse189))))) .cse0) (or (forall ((v_prenex_83 Int)) (let ((.cse192 (mod v_prenex_83 4294967296)) (.cse190 (mod c_main_~x~0 4294967296))) (let ((.cse193 (mod (+ c_main_~x~0 1) 4294967296)) (.cse191 (div .cse192 .cse190))) (or (< .cse190 (mod .cse191 4294967296)) (not (= (mod .cse192 .cse190) 0)) (<= .cse192 .cse193) (< .cse190 (mod (+ .cse191 4294967295) 4294967296)) (<= (mod (div .cse192 .cse193) 4294967296) .cse193) (< .cse190 (mod (+ .cse191 1) 4294967296)))))) .cse5) (or .cse5 (forall ((v_prenex_93 Int)) (let ((.cse196 (mod v_prenex_93 4294967296)) (.cse194 (mod c_main_~x~0 4294967296))) (let ((.cse195 (div .cse196 .cse194)) (.cse197 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse194 (mod (+ .cse195 4294967295) 4294967296)) (< .cse194 (mod .cse195 4294967296)) (<= (mod (div .cse196 .cse197) 4294967296) .cse197) (<= .cse196 .cse197) (< .cse196 0)))))) (or .cse5 .cse70) (forall ((v_prenex_81 Int)) (let ((.cse200 (mod v_prenex_81 4294967296)) (.cse198 (mod c_main_~x~0 4294967296))) (let ((.cse199 (div .cse200 .cse198)) (.cse201 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse198 (mod .cse199 4294967296)) (not (= (mod .cse200 .cse198) 0)) (<= .cse200 .cse201) (< .cse198 (mod (+ .cse199 1) 4294967296)) (<= (mod (div .cse200 .cse201) 4294967296) .cse201))))) (or .cse5 (forall ((v_prenex_69 Int)) (let ((.cse203 (mod (+ c_main_~x~0 1) 4294967296)) (.cse202 (mod v_prenex_69 4294967296)) (.cse204 (mod c_main_~x~0 4294967296))) (or (<= 0 .cse202) (<= .cse202 .cse203) (< .cse204 (mod (+ (div .cse202 .cse204) 4294967295) 4294967296)) (<= (mod (div .cse202 .cse203) 4294967296) .cse203) (= (mod .cse202 .cse204) 0))))) (or .cse0 (forall ((v_prenex_35 Int)) (let ((.cse207 (mod v_prenex_35 4294967296)) (.cse205 (mod c_main_~x~0 4294967296))) (let ((.cse206 (div .cse207 .cse205)) (.cse208 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse205 (mod .cse206 4294967296)) (< .cse207 0) (< .cse205 (mod (+ .cse206 1) 4294967296)) (<= (mod (div .cse207 .cse208) 4294967296) .cse208) (<= .cse207 .cse208)))))) (or (forall ((v_prenex_56 Int)) (let ((.cse209 (mod v_prenex_56 4294967296)) (.cse210 (mod c_main_~x~0 4294967296))) (let ((.cse211 (div .cse209 .cse210)) (.cse212 (mod (+ c_main_~x~0 1) 4294967296))) (or (not (= (mod .cse209 .cse210) 0)) (< .cse210 (mod .cse211 4294967296)) (< .cse210 (mod (+ .cse211 1) 4294967296)) (< .cse210 (mod (+ .cse211 4294967295) 4294967296)) (<= .cse209 .cse212) (<= (mod (div .cse209 .cse212) 4294967296) .cse212))))) .cse0) (or .cse5 (forall ((v_prenex_82 Int)) (let ((.cse215 (mod v_prenex_82 4294967296)) (.cse213 (mod c_main_~x~0 4294967296))) (let ((.cse214 (div .cse215 .cse213)) (.cse216 (mod (+ c_main_~x~0 1) 4294967296))) (or (< .cse213 (mod (+ .cse214 4294967295) 4294967296)) (< .cse213 (mod .cse214 4294967296)) (<= .cse215 .cse216) (not (= (mod .cse215 .cse213) 0)) (<= (mod (div .cse215 .cse216) 4294967296) .cse216))))))))) is different from true [2018-11-18 10:22:11,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:22:11,737 INFO L93 Difference]: Finished difference Result 34 states and 38 transitions. [2018-11-18 10:22:11,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:22:11,738 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 18 [2018-11-18 10:22:11,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:22:11,738 INFO L225 Difference]: With dead ends: 34 [2018-11-18 10:22:11,738 INFO L226 Difference]: Without dead ends: 22 [2018-11-18 10:22:11,738 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 28 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=18, Invalid=21, Unknown=3, NotChecked=30, Total=72 [2018-11-18 10:22:11,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-11-18 10:22:11,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-11-18 10:22:11,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-11-18 10:22:11,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 24 transitions. [2018-11-18 10:22:11,741 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 24 transitions. Word has length 18 [2018-11-18 10:22:11,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:22:11,742 INFO L480 AbstractCegarLoop]: Abstraction has 22 states and 24 transitions. [2018-11-18 10:22:11,742 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-18 10:22:11,742 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 24 transitions. [2018-11-18 10:22:11,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-18 10:22:11,742 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:22:11,742 INFO L375 BasicCegarLoop]: trace histogram [4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:22:11,743 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 10:22:11,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:22:11,743 INFO L82 PathProgramCache]: Analyzing trace with hash -1179621945, now seen corresponding path program 2 times [2018-11-18 10:22:11,743 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 10:22:11,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:22:11,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:22:11,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:22:11,744 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 10:22:11,747 ERROR L235 seRefinementStrategy]: Caught known exception: Unsupported non-linear arithmetic [2018-11-18 10:22:11,747 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-11-18 10:22:11,747 INFO L169 anRefinementStrategy]: Switched to traceCheck mode Z3_NO_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-11-18 10:22:11,754 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:22:11,754 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_NO_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: null) [2018-11-18 10:22:11,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:22:11,772 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-18 10:22:11,772 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-18 10:22:11,772 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:22:11,772 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:22:11,778 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:22:11,778 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-18 10:22:26,082 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-11-18 10:22:26,082 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:22:26,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:22:26,107 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-18 10:22:26,107 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 10:22:26,268 WARN L854 $PredicateComparison]: unable to prove that (let ((.cse10 (mod c_main_~x~0 4294967296))) (let ((.cse4 (forall ((v_prenex_127 Int)) (let ((.cse14 (mod v_prenex_127 4294967296)) (.cse15 (mod c_main_~x~0 4294967296))) (or (<= (mod (div .cse14 .cse15) 4294967296) .cse15) (let ((.cse16 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse16 (mod (div .cse14 .cse16) 4294967296))) (not (= (mod .cse14 .cse15) 0)))))) (.cse3 (<= 0 .cse10)) (.cse9 (forall ((v_prenex_128 Int)) (let ((.cse12 (mod v_prenex_128 4294967296))) (or (let ((.cse11 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse11 (mod (div .cse12 .cse11) 4294967296))) (let ((.cse13 (mod c_main_~x~0 4294967296))) (<= (mod (div .cse12 .cse13) 4294967296) .cse13)) (< .cse12 0))))) (.cse5 (< .cse10 0))) (and (or (forall ((main_~y~0 Int)) (let ((.cse0 (mod main_~y~0 4294967296)) (.cse2 (mod c_main_~x~0 4294967296))) (or (<= 0 .cse0) (let ((.cse1 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse1 (mod (div .cse0 .cse1) 4294967296))) (= (mod .cse0 .cse2) 0) (<= (mod (+ (div .cse0 .cse2) 4294967295) 4294967296) .cse2)))) .cse3) (or .cse4 .cse5) (or .cse5 (forall ((v_prenex_126 Int)) (let ((.cse7 (mod v_prenex_126 4294967296)) (.cse8 (mod c_main_~x~0 4294967296))) (or (let ((.cse6 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse6 (mod (div .cse7 .cse6) 4294967296))) (= (mod .cse7 .cse8) 0) (<= 0 .cse7) (<= (mod (+ (div .cse7 .cse8) 1) 4294967296) .cse8))))) (or .cse9 .cse3) (or .cse4 .cse3) (or .cse9 .cse5)))) is different from true [2018-11-18 10:22:26,298 WARN L854 $PredicateComparison]: unable to prove that (let ((.cse20 (mod c_main_~x~0 4294967296))) (let ((.cse3 (<= 0 .cse20)) (.cse7 (< .cse20 0))) (and (or (forall ((main_~y~0 Int)) (let ((.cse0 (mod main_~y~0 4294967296)) (.cse2 (mod c_main_~x~0 4294967296))) (or (<= 0 .cse0) (let ((.cse1 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse1 (mod (div .cse0 .cse1) 4294967296))) (= (mod .cse0 .cse2) 0) (<= (mod (+ (div .cse0 .cse2) 4294967295) 4294967296) .cse2)))) .cse3) (or (forall ((v_prenex_127 Int)) (let ((.cse4 (mod v_prenex_127 4294967296)) (.cse5 (mod c_main_~x~0 4294967296))) (or (<= (mod (div .cse4 .cse5) 4294967296) .cse5) (let ((.cse6 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse6 (mod (div .cse4 .cse6) 4294967296))) (not (= (mod .cse4 .cse5) 0))))) .cse7) (or .cse7 (forall ((v_prenex_126 Int)) (let ((.cse9 (mod v_prenex_126 4294967296)) (.cse10 (mod c_main_~x~0 4294967296))) (or (let ((.cse8 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse8 (mod (div .cse9 .cse8) 4294967296))) (= (mod .cse9 .cse10) 0) (<= 0 .cse9) (<= (mod (+ (div .cse9 .cse10) 1) 4294967296) .cse10))))) (or (forall ((v_prenex_128 Int)) (let ((.cse12 (mod v_prenex_128 4294967296))) (or (let ((.cse11 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse11 (mod (div .cse12 .cse11) 4294967296))) (let ((.cse13 (mod c_main_~x~0 4294967296))) (<= (mod (div .cse12 .cse13) 4294967296) .cse13)) (< .cse12 0)))) .cse3) (or (forall ((v_prenex_129 Int)) (let ((.cse14 (mod v_prenex_129 4294967296)) (.cse15 (mod c_main_~x~0 4294967296))) (or (<= (mod (div .cse14 .cse15) 4294967296) .cse15) (let ((.cse16 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse16 (mod (div .cse14 .cse16) 4294967296))) (not (= (mod .cse14 .cse15) 0))))) .cse3) (or .cse7 (forall ((v_prenex_130 Int)) (let ((.cse17 (mod v_prenex_130 4294967296))) (or (< .cse17 0) (let ((.cse18 (mod c_main_~x~0 4294967296))) (<= (mod (div .cse17 .cse18) 4294967296) .cse18)) (let ((.cse19 (mod (* c_main_~x~0 c_main_~x~0) 4294967296))) (< .cse19 (mod (div .cse17 .cse19) 4294967296)))))))))) is different from true [2018-11-18 10:22:26,313 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 3 not checked. [2018-11-18 10:22:26,330 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 10:22:26,330 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-18 10:22:26,330 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 10:22:26,330 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 10:22:26,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 10:22:26,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=13, Unknown=2, NotChecked=14, Total=42 [2018-11-18 10:22:26,331 INFO L87 Difference]: Start difference. First operand 22 states and 24 transitions. Second operand 4 states. [2018-11-18 10:22:26,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:22:26,340 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2018-11-18 10:22:26,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 10:22:26,340 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2018-11-18 10:22:26,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:22:26,340 INFO L225 Difference]: With dead ends: 22 [2018-11-18 10:22:26,340 INFO L226 Difference]: Without dead ends: 0 [2018-11-18 10:22:26,341 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=13, Invalid=13, Unknown=2, NotChecked=14, Total=42 [2018-11-18 10:22:26,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-11-18 10:22:26,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-11-18 10:22:26,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-11-18 10:22:26,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-11-18 10:22:26,341 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 21 [2018-11-18 10:22:26,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:22:26,342 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-11-18 10:22:26,342 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 10:22:26,342 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-11-18 10:22:26,342 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-18 10:22:26,345 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-11-18 10:22:26,387 INFO L428 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-11-18 10:22:26,387 INFO L425 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-11-18 10:22:26,387 INFO L425 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-11-18 10:22:26,387 INFO L428 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-11-18 10:22:26,387 INFO L428 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-11-18 10:22:26,387 INFO L425 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-11-18 10:22:26,387 INFO L428 ceAbstractionStarter]: At program point mainENTRY(lines 10 22) the Hoare annotation is: true [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point mainEXIT(lines 10 22) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point L15(lines 15 19) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point L13(line 13) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point L14-1(lines 14 20) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L421 ceAbstractionStarter]: At program point L15-2(lines 14 20) the Hoare annotation is: (and (= main_~x~0 1) (<= (+ (* 4294967296 (div main_~y~0 4294967296)) main_~x~0) (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))))) [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point mainFINAL(lines 10 22) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L421 ceAbstractionStarter]: At program point L14-3(lines 14 20) the Hoare annotation is: (= (mod main_~y~0 4294967296) (mod main_~x~0 4294967296)) [2018-11-18 10:22:26,388 INFO L428 ceAbstractionStarter]: At program point __VERIFIER_assertENTRY(lines 4 9) the Hoare annotation is: true [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point __VERIFIER_assertEXIT(lines 4 9) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point L6(line 6) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point L5(lines 5 7) no Hoare annotation was computed. [2018-11-18 10:22:26,388 INFO L425 ceAbstractionStarter]: For program point L5-2(lines 4 9) no Hoare annotation was computed. [2018-11-18 10:22:26,389 INFO L425 ceAbstractionStarter]: For program point __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION(line 6) no Hoare annotation was computed. [2018-11-18 10:22:26,398 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 10:22:26 BoogieIcfgContainer [2018-11-18 10:22:26,399 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 10:22:26,399 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 10:22:26,399 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 10:22:26,399 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 10:22:26,399 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:21:47" (3/4) ... [2018-11-18 10:22:26,401 INFO L144 WitnessPrinter]: Generating witness for correct program [2018-11-18 10:22:26,405 INFO L333 RCFGBacktranslator]: Ignoring RootEdge to procedure ULTIMATE.init [2018-11-18 10:22:26,405 INFO L333 RCFGBacktranslator]: Ignoring RootEdge to procedure main [2018-11-18 10:22:26,405 INFO L333 RCFGBacktranslator]: Ignoring RootEdge to procedure __VERIFIER_assert [2018-11-18 10:22:26,407 INFO L846 BoogieBacktranslator]: Reduced CFG by removing 9 nodes and edges [2018-11-18 10:22:26,407 INFO L846 BoogieBacktranslator]: Reduced CFG by removing 3 nodes and edges [2018-11-18 10:22:26,407 INFO L846 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2018-11-18 10:22:26,433 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_67e7f99e-b64a-4e2f-88b6-9b96e8ac5453/bin-2019/utaipan/witness.graphml [2018-11-18 10:22:26,433 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 10:22:26,434 INFO L168 Benchmark]: Toolchain (without parser) took 38892.18 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 216.0 MB). Free memory was 960.2 MB in the beginning and 1.1 GB in the end (delta: -144.2 MB). Peak memory consumption was 71.8 MB. Max. memory is 11.5 GB. [2018-11-18 10:22:26,434 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:22:26,435 INFO L168 Benchmark]: CACSL2BoogieTranslator took 159.80 ms. Allocated memory is still 1.0 GB. Free memory was 960.2 MB in the beginning and 948.4 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 11.5 GB. [2018-11-18 10:22:26,435 INFO L168 Benchmark]: Boogie Procedure Inliner took 11.51 ms. Allocated memory is still 1.0 GB. Free memory is still 948.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:22:26,435 INFO L168 Benchmark]: Boogie Preprocessor took 12.82 ms. Allocated memory is still 1.0 GB. Free memory was 948.4 MB in the beginning and 945.7 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 10:22:26,436 INFO L168 Benchmark]: RCFGBuilder took 171.66 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 945.7 MB in the beginning and 1.1 GB in the end (delta: -198.2 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. [2018-11-18 10:22:26,436 INFO L168 Benchmark]: TraceAbstraction took 38499.27 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 56.6 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.5 MB). Peak memory consumption was 96.1 MB. Max. memory is 11.5 GB. [2018-11-18 10:22:26,436 INFO L168 Benchmark]: Witness Printer took 34.07 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:22:26,438 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 159.80 ms. Allocated memory is still 1.0 GB. Free memory was 960.2 MB in the beginning and 948.4 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 11.51 ms. Allocated memory is still 1.0 GB. Free memory is still 948.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 12.82 ms. Allocated memory is still 1.0 GB. Free memory was 948.4 MB in the beginning and 945.7 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 171.66 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 945.7 MB in the beginning and 1.1 GB in the end (delta: -198.2 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 38499.27 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 56.6 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.5 MB). Peak memory consumption was 96.1 MB. Max. memory is 11.5 GB. * Witness Printer took 34.07 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 6]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 14]: Loop Invariant Derived loop invariant: x == 1 && 4294967296 * (y / 4294967296) + x <= y + 4294967296 * (x / 4294967296) - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 20 locations, 1 error locations. SAFE Result, 38.4s OverallTime, 6 OverallIterations, 4 TraceHistogramMax, 14.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 79 SDtfs, 11 SDslu, 146 SDs, 0 SdLazy, 91 SolverSat, 5 SolverUnsat, 6 SolverUnknown, 0 SolverNotchecked, 12.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 148 GetRequests, 108 SyntacticMatches, 4 SemanticMatches, 36 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 10.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=22occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.2s AbstIntTime, 3 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 6 MinimizatonAttempts, 3 StatesRemovedByMinimization, 2 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 7 LocationsWithAnnotation, 12 PreInvPairs, 17 NumberOfFragments, 31 HoareAnnotationTreeSize, 12 FomulaSimplifications, 55 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 7 FomulaSimplificationsInter, 86 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 14.3s SatisfiabilityAnalysisTime, 8.4s InterpolantComputationTime, 161 NumberOfCodeBlocks, 161 NumberOfCodeBlocksAsserted, 13 NumberOfCheckSat, 151 ConstructedInterpolants, 11 QuantifiedInterpolants, 329812 SizeOfPredicates, 7 NumberOfNonLiveVariables, 139 ConjunctsInSsa, 31 ConjunctsInUnsatCore, 10 InterpolantComputations, 5 PerfectInterpolantSequences, 40/52 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Received shutdown request...