./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:13:22,047 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:13:22,048 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:13:22,055 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:13:22,055 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:13:22,056 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:13:22,056 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:13:22,057 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:13:22,058 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:13:22,059 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:13:22,060 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:13:22,060 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:13:22,061 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:13:22,061 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:13:22,062 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:13:22,062 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:13:22,063 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:13:22,064 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:13:22,065 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:13:22,066 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:13:22,066 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:13:22,067 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:13:22,068 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:13:22,068 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:13:22,068 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:13:22,069 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:13:22,069 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:13:22,070 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:13:22,070 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:13:22,071 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:13:22,071 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:13:22,072 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:13:22,072 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:13:22,072 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:13:22,073 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:13:22,073 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:13:22,073 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-18 15:13:22,084 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:13:22,084 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:13:22,085 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 15:13:22,085 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-18 15:13:22,085 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-18 15:13:22,085 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-18 15:13:22,085 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-18 15:13:22,085 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-18 15:13:22,085 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-18 15:13:22,086 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-18 15:13:22,086 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-18 15:13:22,086 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-18 15:13:22,086 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-18 15:13:22,086 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:13:22,086 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:13:22,087 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 15:13:22,088 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:13:22,088 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:13:22,088 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 15:13:22,089 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 15:13:22,089 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-18 15:13:22,089 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 15:13:22,089 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 15:13:22,089 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-18 15:13:22,089 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2018-11-18 15:13:22,111 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:13:22,120 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:13:22,123 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:13:22,124 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:13:22,124 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:13:22,125 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 15:13:22,165 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/data/5ecb33d39/b478597270f541b7abfe47a5ed8b21b6/FLAG65aaa36a2 [2018-11-18 15:13:22,572 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:13:22,573 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 15:13:22,580 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/data/5ecb33d39/b478597270f541b7abfe47a5ed8b21b6/FLAG65aaa36a2 [2018-11-18 15:13:22,591 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/data/5ecb33d39/b478597270f541b7abfe47a5ed8b21b6 [2018-11-18 15:13:22,593 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:13:22,593 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 15:13:22,594 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:13:22,594 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:13:22,597 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:13:22,598 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,600 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5ff47436 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22, skipping insertion in model container [2018-11-18 15:13:22,600 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,608 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:13:22,634 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:13:22,765 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:13:22,768 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:13:22,790 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:13:22,800 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:13:22,800 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22 WrapperNode [2018-11-18 15:13:22,800 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:13:22,800 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 15:13:22,801 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 15:13:22,801 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 15:13:22,805 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,809 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,814 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 15:13:22,814 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:13:22,814 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:13:22,814 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:13:22,856 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,856 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,857 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,857 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,862 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,868 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,870 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... [2018-11-18 15:13:22,872 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:13:22,873 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:13:22,873 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:13:22,873 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:13:22,874 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:13:22,907 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-18 15:13:22,907 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-18 15:13:22,907 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-18 15:13:22,908 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-18 15:13:22,908 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-18 15:13:22,909 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-18 15:13:22,909 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:13:22,910 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-18 15:13:22,910 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-18 15:13:23,290 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:13:23,291 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:13:23 BoogieIcfgContainer [2018-11-18 15:13:23,291 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:13:23,291 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 15:13:23,291 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 15:13:23,294 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 15:13:23,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 03:13:22" (1/3) ... [2018-11-18 15:13:23,294 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2bca4668 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:13:23, skipping insertion in model container [2018-11-18 15:13:23,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:13:22" (2/3) ... [2018-11-18 15:13:23,295 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2bca4668 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:13:23, skipping insertion in model container [2018-11-18 15:13:23,295 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:13:23" (3/3) ... [2018-11-18 15:13:23,296 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 15:13:23,302 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 15:13:23,306 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 15:13:23,315 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 15:13:23,336 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 15:13:23,336 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 15:13:23,336 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 15:13:23,336 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:13:23,337 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:13:23,337 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 15:13:23,337 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:13:23,337 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 15:13:23,352 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states. [2018-11-18 15:13:23,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:23,360 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:23,360 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:23,362 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:23,365 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:23,366 INFO L82 PathProgramCache]: Analyzing trace with hash -1125728260, now seen corresponding path program 1 times [2018-11-18 15:13:23,367 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:23,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:23,396 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:23,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:23,396 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:23,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:23,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:23,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:23,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:23,575 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:23,582 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:23,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:23,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:23,596 INFO L87 Difference]: Start difference. First operand 175 states. Second operand 5 states. [2018-11-18 15:13:24,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:24,023 INFO L93 Difference]: Finished difference Result 362 states and 521 transitions. [2018-11-18 15:13:24,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:24,024 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 15:13:24,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:24,034 INFO L225 Difference]: With dead ends: 362 [2018-11-18 15:13:24,034 INFO L226 Difference]: Without dead ends: 195 [2018-11-18 15:13:24,037 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:24,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-11-18 15:13:24,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 166. [2018-11-18 15:13:24,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 15:13:24,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 218 transitions. [2018-11-18 15:13:24,085 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 218 transitions. Word has length 92 [2018-11-18 15:13:24,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:24,086 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 218 transitions. [2018-11-18 15:13:24,086 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:24,086 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 218 transitions. [2018-11-18 15:13:24,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:24,089 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:24,089 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:24,090 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:24,090 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:24,090 INFO L82 PathProgramCache]: Analyzing trace with hash -1618354434, now seen corresponding path program 1 times [2018-11-18 15:13:24,090 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:24,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:24,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:24,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:24,091 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:24,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:24,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:24,166 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:24,166 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:24,167 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:24,168 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:24,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:24,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:24,169 INFO L87 Difference]: Start difference. First operand 166 states and 218 transitions. Second operand 5 states. [2018-11-18 15:13:24,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:24,421 INFO L93 Difference]: Finished difference Result 339 states and 459 transitions. [2018-11-18 15:13:24,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:24,421 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 15:13:24,422 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:24,423 INFO L225 Difference]: With dead ends: 339 [2018-11-18 15:13:24,423 INFO L226 Difference]: Without dead ends: 193 [2018-11-18 15:13:24,424 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:24,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-11-18 15:13:24,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 166. [2018-11-18 15:13:24,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 15:13:24,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 217 transitions. [2018-11-18 15:13:24,442 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 217 transitions. Word has length 92 [2018-11-18 15:13:24,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:24,442 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 217 transitions. [2018-11-18 15:13:24,442 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:24,442 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 217 transitions. [2018-11-18 15:13:24,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:24,444 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:24,444 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:24,444 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:24,444 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:24,444 INFO L82 PathProgramCache]: Analyzing trace with hash -664414276, now seen corresponding path program 1 times [2018-11-18 15:13:24,444 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:24,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:24,445 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:24,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:24,445 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:24,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:24,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:24,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:24,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:24,529 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:24,529 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:24,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:24,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:24,529 INFO L87 Difference]: Start difference. First operand 166 states and 217 transitions. Second operand 5 states. [2018-11-18 15:13:24,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:24,729 INFO L93 Difference]: Finished difference Result 358 states and 487 transitions. [2018-11-18 15:13:24,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:24,730 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 15:13:24,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:24,731 INFO L225 Difference]: With dead ends: 358 [2018-11-18 15:13:24,731 INFO L226 Difference]: Without dead ends: 212 [2018-11-18 15:13:24,732 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:24,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-11-18 15:13:24,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 166. [2018-11-18 15:13:24,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 15:13:24,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 216 transitions. [2018-11-18 15:13:24,747 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 216 transitions. Word has length 92 [2018-11-18 15:13:24,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:24,747 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 216 transitions. [2018-11-18 15:13:24,747 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:24,747 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 216 transitions. [2018-11-18 15:13:24,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:24,748 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:24,748 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:24,751 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:24,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:24,751 INFO L82 PathProgramCache]: Analyzing trace with hash -1880568002, now seen corresponding path program 1 times [2018-11-18 15:13:24,751 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:24,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:24,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:24,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:24,752 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:24,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:24,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:24,799 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:24,799 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:24,799 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:24,800 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:24,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:24,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:24,800 INFO L87 Difference]: Start difference. First operand 166 states and 216 transitions. Second operand 5 states. [2018-11-18 15:13:25,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:25,012 INFO L93 Difference]: Finished difference Result 356 states and 481 transitions. [2018-11-18 15:13:25,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:25,013 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 15:13:25,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:25,015 INFO L225 Difference]: With dead ends: 356 [2018-11-18 15:13:25,015 INFO L226 Difference]: Without dead ends: 210 [2018-11-18 15:13:25,016 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:25,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-11-18 15:13:25,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 166. [2018-11-18 15:13:25,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 15:13:25,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 215 transitions. [2018-11-18 15:13:25,032 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 215 transitions. Word has length 92 [2018-11-18 15:13:25,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:25,033 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 215 transitions. [2018-11-18 15:13:25,033 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:25,033 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 215 transitions. [2018-11-18 15:13:25,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:25,034 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:25,034 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:25,034 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:25,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:25,034 INFO L82 PathProgramCache]: Analyzing trace with hash 1682431868, now seen corresponding path program 1 times [2018-11-18 15:13:25,034 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:25,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,035 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:25,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,035 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:25,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:25,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:25,083 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:25,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:13:25,083 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:25,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:13:25,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:13:25,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:25,084 INFO L87 Difference]: Start difference. First operand 166 states and 215 transitions. Second operand 6 states. [2018-11-18 15:13:25,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:25,107 INFO L93 Difference]: Finished difference Result 324 states and 433 transitions. [2018-11-18 15:13:25,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:13:25,107 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 92 [2018-11-18 15:13:25,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:25,109 INFO L225 Difference]: With dead ends: 324 [2018-11-18 15:13:25,109 INFO L226 Difference]: Without dead ends: 179 [2018-11-18 15:13:25,109 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:25,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-11-18 15:13:25,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 171. [2018-11-18 15:13:25,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-11-18 15:13:25,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 220 transitions. [2018-11-18 15:13:25,124 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 220 transitions. Word has length 92 [2018-11-18 15:13:25,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:25,124 INFO L480 AbstractCegarLoop]: Abstraction has 171 states and 220 transitions. [2018-11-18 15:13:25,125 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:13:25,125 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 220 transitions. [2018-11-18 15:13:25,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:25,125 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:25,126 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:25,126 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:25,126 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:25,126 INFO L82 PathProgramCache]: Analyzing trace with hash 2126332542, now seen corresponding path program 1 times [2018-11-18 15:13:25,126 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:25,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,127 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:25,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,127 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:25,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:25,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:25,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:25,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:13:25,186 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:25,187 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:13:25,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:13:25,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:25,187 INFO L87 Difference]: Start difference. First operand 171 states and 220 transitions. Second operand 6 states. [2018-11-18 15:13:25,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:25,209 INFO L93 Difference]: Finished difference Result 331 states and 438 transitions. [2018-11-18 15:13:25,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:13:25,210 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 92 [2018-11-18 15:13:25,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:25,212 INFO L225 Difference]: With dead ends: 331 [2018-11-18 15:13:25,212 INFO L226 Difference]: Without dead ends: 181 [2018-11-18 15:13:25,212 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:25,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-11-18 15:13:25,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 176. [2018-11-18 15:13:25,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-18 15:13:25,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 225 transitions. [2018-11-18 15:13:25,224 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 225 transitions. Word has length 92 [2018-11-18 15:13:25,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:25,224 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 225 transitions. [2018-11-18 15:13:25,224 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:13:25,224 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 225 transitions. [2018-11-18 15:13:25,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 15:13:25,225 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:25,225 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:25,225 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:25,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:25,226 INFO L82 PathProgramCache]: Analyzing trace with hash 76944700, now seen corresponding path program 1 times [2018-11-18 15:13:25,226 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:25,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,226 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:25,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,227 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:25,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:25,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:13:25,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:25,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:13:25,274 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:25,275 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:13:25,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:13:25,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:13:25,275 INFO L87 Difference]: Start difference. First operand 176 states and 225 transitions. Second operand 4 states. [2018-11-18 15:13:25,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:25,392 INFO L93 Difference]: Finished difference Result 476 states and 631 transitions. [2018-11-18 15:13:25,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:13:25,393 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 92 [2018-11-18 15:13:25,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:25,394 INFO L225 Difference]: With dead ends: 476 [2018-11-18 15:13:25,394 INFO L226 Difference]: Without dead ends: 321 [2018-11-18 15:13:25,395 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:13:25,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-11-18 15:13:25,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 321. [2018-11-18 15:13:25,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 321 states. [2018-11-18 15:13:25,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 408 transitions. [2018-11-18 15:13:25,412 INFO L78 Accepts]: Start accepts. Automaton has 321 states and 408 transitions. Word has length 92 [2018-11-18 15:13:25,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:25,413 INFO L480 AbstractCegarLoop]: Abstraction has 321 states and 408 transitions. [2018-11-18 15:13:25,413 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:13:25,413 INFO L276 IsEmpty]: Start isEmpty. Operand 321 states and 408 transitions. [2018-11-18 15:13:25,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:25,414 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:25,414 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:25,414 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:25,414 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:25,414 INFO L82 PathProgramCache]: Analyzing trace with hash 491226630, now seen corresponding path program 1 times [2018-11-18 15:13:25,414 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:25,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:25,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,415 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:25,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:25,459 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:25,460 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:25,460 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:13:25,460 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:25,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:13:25,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:13:25,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:25,461 INFO L87 Difference]: Start difference. First operand 321 states and 408 transitions. Second operand 6 states. [2018-11-18 15:13:25,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:25,490 INFO L93 Difference]: Finished difference Result 628 states and 817 transitions. [2018-11-18 15:13:25,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:13:25,491 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 113 [2018-11-18 15:13:25,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:25,493 INFO L225 Difference]: With dead ends: 628 [2018-11-18 15:13:25,493 INFO L226 Difference]: Without dead ends: 328 [2018-11-18 15:13:25,494 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:25,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states. [2018-11-18 15:13:25,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 326. [2018-11-18 15:13:25,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-11-18 15:13:25,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 412 transitions. [2018-11-18 15:13:25,512 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 412 transitions. Word has length 113 [2018-11-18 15:13:25,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:25,513 INFO L480 AbstractCegarLoop]: Abstraction has 326 states and 412 transitions. [2018-11-18 15:13:25,513 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:13:25,513 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 412 transitions. [2018-11-18 15:13:25,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:25,514 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:25,514 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:25,514 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:25,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:25,515 INFO L82 PathProgramCache]: Analyzing trace with hash 531901380, now seen corresponding path program 1 times [2018-11-18 15:13:25,515 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:25,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,515 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:25,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,516 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:25,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:25,575 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:25,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:25,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:25,575 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:25,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:25,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:25,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:25,576 INFO L87 Difference]: Start difference. First operand 326 states and 412 transitions. Second operand 5 states. [2018-11-18 15:13:25,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:25,844 INFO L93 Difference]: Finished difference Result 852 states and 1129 transitions. [2018-11-18 15:13:25,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:13:25,848 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 15:13:25,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:25,851 INFO L225 Difference]: With dead ends: 852 [2018-11-18 15:13:25,852 INFO L226 Difference]: Without dead ends: 547 [2018-11-18 15:13:25,853 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:13:25,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-11-18 15:13:25,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 454. [2018-11-18 15:13:25,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-11-18 15:13:25,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 581 transitions. [2018-11-18 15:13:25,881 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 581 transitions. Word has length 113 [2018-11-18 15:13:25,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:25,881 INFO L480 AbstractCegarLoop]: Abstraction has 454 states and 581 transitions. [2018-11-18 15:13:25,881 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:25,881 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 581 transitions. [2018-11-18 15:13:25,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:25,883 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:25,883 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:25,883 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:25,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:25,883 INFO L82 PathProgramCache]: Analyzing trace with hash 2070241410, now seen corresponding path program 1 times [2018-11-18 15:13:25,883 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:25,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:25,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:25,884 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:25,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:25,943 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:25,943 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:25,943 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:25,943 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:25,943 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:25,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:25,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:25,944 INFO L87 Difference]: Start difference. First operand 454 states and 581 transitions. Second operand 5 states. [2018-11-18 15:13:26,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:26,127 INFO L93 Difference]: Finished difference Result 884 states and 1141 transitions. [2018-11-18 15:13:26,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:26,127 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 15:13:26,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:26,129 INFO L225 Difference]: With dead ends: 884 [2018-11-18 15:13:26,129 INFO L226 Difference]: Without dead ends: 454 [2018-11-18 15:13:26,130 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:26,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states. [2018-11-18 15:13:26,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2018-11-18 15:13:26,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-11-18 15:13:26,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 573 transitions. [2018-11-18 15:13:26,156 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 573 transitions. Word has length 113 [2018-11-18 15:13:26,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:26,157 INFO L480 AbstractCegarLoop]: Abstraction has 454 states and 573 transitions. [2018-11-18 15:13:26,157 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:26,157 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 573 transitions. [2018-11-18 15:13:26,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:26,158 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:26,158 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:26,159 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:26,159 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:26,159 INFO L82 PathProgramCache]: Analyzing trace with hash 41655300, now seen corresponding path program 1 times [2018-11-18 15:13:26,159 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:26,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:26,160 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:26,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:26,160 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:26,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:26,219 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:26,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:26,220 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:26,220 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:26,220 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:26,220 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:26,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:26,220 INFO L87 Difference]: Start difference. First operand 454 states and 573 transitions. Second operand 5 states. [2018-11-18 15:13:26,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:26,409 INFO L93 Difference]: Finished difference Result 884 states and 1125 transitions. [2018-11-18 15:13:26,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:26,409 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 15:13:26,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:26,411 INFO L225 Difference]: With dead ends: 884 [2018-11-18 15:13:26,411 INFO L226 Difference]: Without dead ends: 454 [2018-11-18 15:13:26,412 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:26,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states. [2018-11-18 15:13:26,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2018-11-18 15:13:26,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-11-18 15:13:26,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 565 transitions. [2018-11-18 15:13:26,435 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 565 transitions. Word has length 113 [2018-11-18 15:13:26,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:26,435 INFO L480 AbstractCegarLoop]: Abstraction has 454 states and 565 transitions. [2018-11-18 15:13:26,436 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:26,436 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 565 transitions. [2018-11-18 15:13:26,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:26,437 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:26,437 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:26,437 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:26,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:26,438 INFO L82 PathProgramCache]: Analyzing trace with hash -439424958, now seen corresponding path program 1 times [2018-11-18 15:13:26,438 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:26,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:26,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:26,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:26,439 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:26,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:26,493 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:26,493 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:26,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:26,493 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:26,494 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:26,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:26,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:26,494 INFO L87 Difference]: Start difference. First operand 454 states and 565 transitions. Second operand 5 states. [2018-11-18 15:13:26,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:26,751 INFO L93 Difference]: Finished difference Result 1072 states and 1431 transitions. [2018-11-18 15:13:26,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:13:26,751 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 15:13:26,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:26,754 INFO L225 Difference]: With dead ends: 1072 [2018-11-18 15:13:26,754 INFO L226 Difference]: Without dead ends: 640 [2018-11-18 15:13:26,755 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:26,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-11-18 15:13:26,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 520. [2018-11-18 15:13:26,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-11-18 15:13:26,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 629 transitions. [2018-11-18 15:13:26,781 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 629 transitions. Word has length 113 [2018-11-18 15:13:26,781 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:26,781 INFO L480 AbstractCegarLoop]: Abstraction has 520 states and 629 transitions. [2018-11-18 15:13:26,781 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:26,781 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 629 transitions. [2018-11-18 15:13:26,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:26,783 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:26,783 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:26,783 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:26,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:26,783 INFO L82 PathProgramCache]: Analyzing trace with hash -454943676, now seen corresponding path program 1 times [2018-11-18 15:13:26,783 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:26,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:26,784 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:26,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:26,784 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:26,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:26,829 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:26,829 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:26,830 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:26,830 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:26,830 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:26,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:26,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:26,830 INFO L87 Difference]: Start difference. First operand 520 states and 629 transitions. Second operand 5 states. [2018-11-18 15:13:27,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:27,089 INFO L93 Difference]: Finished difference Result 1156 states and 1480 transitions. [2018-11-18 15:13:27,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:13:27,090 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 15:13:27,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:27,092 INFO L225 Difference]: With dead ends: 1156 [2018-11-18 15:13:27,092 INFO L226 Difference]: Without dead ends: 660 [2018-11-18 15:13:27,093 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:27,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states. [2018-11-18 15:13:27,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 571. [2018-11-18 15:13:27,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 571 states. [2018-11-18 15:13:27,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 571 states to 571 states and 671 transitions. [2018-11-18 15:13:27,120 INFO L78 Accepts]: Start accepts. Automaton has 571 states and 671 transitions. Word has length 113 [2018-11-18 15:13:27,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:27,121 INFO L480 AbstractCegarLoop]: Abstraction has 571 states and 671 transitions. [2018-11-18 15:13:27,121 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:27,121 INFO L276 IsEmpty]: Start isEmpty. Operand 571 states and 671 transitions. [2018-11-18 15:13:27,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-18 15:13:27,122 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:27,122 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:27,122 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:27,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:27,123 INFO L82 PathProgramCache]: Analyzing trace with hash 455886741, now seen corresponding path program 1 times [2018-11-18 15:13:27,123 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:27,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:27,123 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:27,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:27,123 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:27,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:27,169 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 15:13:27,169 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:27,169 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:13:27,169 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:27,170 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:27,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:27,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:13:27,170 INFO L87 Difference]: Start difference. First operand 571 states and 671 transitions. Second operand 5 states. [2018-11-18 15:13:27,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:27,375 INFO L93 Difference]: Finished difference Result 1123 states and 1327 transitions. [2018-11-18 15:13:27,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:13:27,375 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 114 [2018-11-18 15:13:27,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:27,377 INFO L225 Difference]: With dead ends: 1123 [2018-11-18 15:13:27,377 INFO L226 Difference]: Without dead ends: 573 [2018-11-18 15:13:27,378 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:27,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 573 states. [2018-11-18 15:13:27,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 573 to 539. [2018-11-18 15:13:27,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 539 states. [2018-11-18 15:13:27,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 539 states and 624 transitions. [2018-11-18 15:13:27,404 INFO L78 Accepts]: Start accepts. Automaton has 539 states and 624 transitions. Word has length 114 [2018-11-18 15:13:27,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:27,404 INFO L480 AbstractCegarLoop]: Abstraction has 539 states and 624 transitions. [2018-11-18 15:13:27,404 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:13:27,404 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 624 transitions. [2018-11-18 15:13:27,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:13:27,405 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:27,405 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:27,406 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:27,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:27,406 INFO L82 PathProgramCache]: Analyzing trace with hash 1484218370, now seen corresponding path program 1 times [2018-11-18 15:13:27,406 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:27,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:27,407 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:27,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:27,407 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:27,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:27,435 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 15:13:27,436 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:27,436 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:27,437 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 114 with the following transitions: [2018-11-18 15:13:27,438 INFO L202 CegarAbsIntRunner]: [30], [32], [37], [40], [45], [48], [53], [55], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [225], [226], [238], [242], [248], [251], [254], [269], [282], [286], [289], [301], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [450], [451], [452], [453], [454], [455], [458], [460], [461], [462], [468], [469], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:27,463 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:27,463 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:27,613 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:13:27,614 INFO L272 AbstractInterpreter]: Visited 84 different actions 84 times. Never merged. Never widened. Performed 519 root evaluator evaluations with a maximum evaluation depth of 3. Performed 519 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 34 variables. [2018-11-18 15:13:27,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:27,632 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:13:27,776 INFO L227 lantSequenceWeakener]: Weakened 93 states. On average, predicates are now at 70.47% of their original sizes. [2018-11-18 15:13:27,776 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:13:28,055 INFO L415 sIntCurrentIteration]: We unified 112 AI predicates to 112 [2018-11-18 15:13:28,055 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:13:28,056 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:28,056 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [3] total 31 [2018-11-18 15:13:28,056 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:28,056 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 15:13:28,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 15:13:28,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=701, Unknown=0, NotChecked=0, Total=870 [2018-11-18 15:13:28,057 INFO L87 Difference]: Start difference. First operand 539 states and 624 transitions. Second operand 30 states. [2018-11-18 15:13:31,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:31,283 INFO L93 Difference]: Finished difference Result 1149 states and 1342 transitions. [2018-11-18 15:13:31,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-18 15:13:31,283 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 113 [2018-11-18 15:13:31,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:31,286 INFO L225 Difference]: With dead ends: 1149 [2018-11-18 15:13:31,286 INFO L226 Difference]: Without dead ends: 625 [2018-11-18 15:13:31,288 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 132 GetRequests, 84 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 572 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=526, Invalid=1924, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 15:13:31,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 625 states. [2018-11-18 15:13:31,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 625 to 612. [2018-11-18 15:13:31,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 612 states. [2018-11-18 15:13:31,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 612 states to 612 states and 698 transitions. [2018-11-18 15:13:31,336 INFO L78 Accepts]: Start accepts. Automaton has 612 states and 698 transitions. Word has length 113 [2018-11-18 15:13:31,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:31,337 INFO L480 AbstractCegarLoop]: Abstraction has 612 states and 698 transitions. [2018-11-18 15:13:31,337 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 15:13:31,337 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 698 transitions. [2018-11-18 15:13:31,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-18 15:13:31,338 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:31,338 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:31,339 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:31,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:31,339 INFO L82 PathProgramCache]: Analyzing trace with hash -1054771583, now seen corresponding path program 1 times [2018-11-18 15:13:31,339 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:31,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:31,340 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:31,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:31,340 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:31,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:31,379 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-18 15:13:31,379 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:31,379 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:31,379 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 116 with the following transitions: [2018-11-18 15:13:31,380 INFO L202 CegarAbsIntRunner]: [30], [32], [37], [40], [45], [48], [53], [55], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [225], [226], [238], [242], [248], [251], [254], [260], [266], [269], [273], [279], [282], [286], [289], [301], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [450], [451], [452], [453], [454], [455], [458], [460], [461], [462], [468], [469], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:31,382 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:31,382 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:31,450 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:13:31,450 INFO L272 AbstractInterpreter]: Visited 99 different actions 116 times. Merged at 10 different actions 10 times. Never widened. Performed 784 root evaluator evaluations with a maximum evaluation depth of 3. Performed 784 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 36 variables. [2018-11-18 15:13:31,460 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:31,461 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:13:31,614 INFO L227 lantSequenceWeakener]: Weakened 110 states. On average, predicates are now at 73.68% of their original sizes. [2018-11-18 15:13:31,614 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:13:32,276 INFO L415 sIntCurrentIteration]: We unified 114 AI predicates to 114 [2018-11-18 15:13:32,277 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:13:32,277 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:32,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [37] imperfect sequences [3] total 38 [2018-11-18 15:13:32,277 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:32,277 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 15:13:32,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 15:13:32,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=1001, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 15:13:32,278 INFO L87 Difference]: Start difference. First operand 612 states and 698 transitions. Second operand 37 states. [2018-11-18 15:13:38,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:38,974 INFO L93 Difference]: Finished difference Result 2413 states and 2941 transitions. [2018-11-18 15:13:38,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-18 15:13:38,974 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 115 [2018-11-18 15:13:38,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:38,978 INFO L225 Difference]: With dead ends: 2413 [2018-11-18 15:13:38,978 INFO L226 Difference]: Without dead ends: 1572 [2018-11-18 15:13:38,981 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 148 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1485 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1043, Invalid=3927, Unknown=0, NotChecked=0, Total=4970 [2018-11-18 15:13:38,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1572 states. [2018-11-18 15:13:39,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1572 to 1533. [2018-11-18 15:13:39,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1533 states. [2018-11-18 15:13:39,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1533 states to 1533 states and 1783 transitions. [2018-11-18 15:13:39,063 INFO L78 Accepts]: Start accepts. Automaton has 1533 states and 1783 transitions. Word has length 115 [2018-11-18 15:13:39,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:39,063 INFO L480 AbstractCegarLoop]: Abstraction has 1533 states and 1783 transitions. [2018-11-18 15:13:39,063 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 15:13:39,063 INFO L276 IsEmpty]: Start isEmpty. Operand 1533 states and 1783 transitions. [2018-11-18 15:13:39,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-11-18 15:13:39,065 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:39,066 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:39,066 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:39,066 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:39,066 INFO L82 PathProgramCache]: Analyzing trace with hash 330171772, now seen corresponding path program 1 times [2018-11-18 15:13:39,066 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:39,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:39,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:39,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:39,067 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:39,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:39,126 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-18 15:13:39,126 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:39,126 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:39,126 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 162 with the following transitions: [2018-11-18 15:13:39,126 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [225], [226], [238], [242], [248], [251], [254], [260], [266], [273], [276], [279], [286], [289], [301], [304], [307], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [468], [469], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:39,129 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:39,129 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:39,158 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:13:39,159 INFO L272 AbstractInterpreter]: Visited 102 different actions 120 times. Merged at 11 different actions 11 times. Never widened. Performed 935 root evaluator evaluations with a maximum evaluation depth of 3. Performed 935 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 36 variables. [2018-11-18 15:13:39,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:39,160 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:13:39,225 INFO L227 lantSequenceWeakener]: Weakened 114 states. On average, predicates are now at 70.47% of their original sizes. [2018-11-18 15:13:39,225 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:13:39,588 INFO L415 sIntCurrentIteration]: We unified 160 AI predicates to 160 [2018-11-18 15:13:39,588 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:13:39,588 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:39,588 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [41] imperfect sequences [6] total 45 [2018-11-18 15:13:39,588 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:39,589 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 15:13:39,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 15:13:39,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=1240, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 15:13:39,590 INFO L87 Difference]: Start difference. First operand 1533 states and 1783 transitions. Second operand 41 states. [2018-11-18 15:13:42,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:42,443 INFO L93 Difference]: Finished difference Result 3092 states and 3615 transitions. [2018-11-18 15:13:42,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 15:13:42,444 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 161 [2018-11-18 15:13:42,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:42,448 INFO L225 Difference]: With dead ends: 3092 [2018-11-18 15:13:42,448 INFO L226 Difference]: Without dead ends: 1652 [2018-11-18 15:13:42,451 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 191 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1572 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1178, Invalid=3934, Unknown=0, NotChecked=0, Total=5112 [2018-11-18 15:13:42,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1652 states. [2018-11-18 15:13:42,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1652 to 1634. [2018-11-18 15:13:42,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1634 states. [2018-11-18 15:13:42,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1634 states to 1634 states and 1888 transitions. [2018-11-18 15:13:42,539 INFO L78 Accepts]: Start accepts. Automaton has 1634 states and 1888 transitions. Word has length 161 [2018-11-18 15:13:42,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:42,539 INFO L480 AbstractCegarLoop]: Abstraction has 1634 states and 1888 transitions. [2018-11-18 15:13:42,539 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 15:13:42,539 INFO L276 IsEmpty]: Start isEmpty. Operand 1634 states and 1888 transitions. [2018-11-18 15:13:42,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2018-11-18 15:13:42,541 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:42,542 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:42,542 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:42,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:42,542 INFO L82 PathProgramCache]: Analyzing trace with hash 437080369, now seen corresponding path program 1 times [2018-11-18 15:13:42,542 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:42,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:42,543 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:42,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:42,543 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:42,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:42,584 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 10 proven. 9 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-11-18 15:13:42,584 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:42,584 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:42,584 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 168 with the following transitions: [2018-11-18 15:13:42,585 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [225], [226], [238], [242], [248], [251], [254], [260], [266], [269], [273], [276], [286], [289], [301], [304], [307], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [468], [469], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:42,587 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:42,587 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:42,613 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:13:42,613 INFO L272 AbstractInterpreter]: Visited 108 different actions 122 times. Merged at 8 different actions 8 times. Never widened. Performed 798 root evaluator evaluations with a maximum evaluation depth of 3. Performed 798 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 36 variables. [2018-11-18 15:13:42,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:42,615 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:13:42,675 INFO L227 lantSequenceWeakener]: Weakened 125 states. On average, predicates are now at 71.96% of their original sizes. [2018-11-18 15:13:42,675 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:13:43,094 INFO L415 sIntCurrentIteration]: We unified 166 AI predicates to 166 [2018-11-18 15:13:43,094 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:13:43,094 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:43,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [44] imperfect sequences [4] total 46 [2018-11-18 15:13:43,095 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:43,095 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-11-18 15:13:43,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-11-18 15:13:43,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=387, Invalid=1505, Unknown=0, NotChecked=0, Total=1892 [2018-11-18 15:13:43,096 INFO L87 Difference]: Start difference. First operand 1634 states and 1888 transitions. Second operand 44 states. [2018-11-18 15:13:47,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:47,263 INFO L93 Difference]: Finished difference Result 3323 states and 3893 transitions. [2018-11-18 15:13:47,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-18 15:13:47,263 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 167 [2018-11-18 15:13:47,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:47,270 INFO L225 Difference]: With dead ends: 3323 [2018-11-18 15:13:47,270 INFO L226 Difference]: Without dead ends: 1874 [2018-11-18 15:13:47,274 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 196 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1566 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1060, Invalid=4342, Unknown=0, NotChecked=0, Total=5402 [2018-11-18 15:13:47,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1874 states. [2018-11-18 15:13:47,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1874 to 1838. [2018-11-18 15:13:47,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1838 states. [2018-11-18 15:13:47,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1838 states to 1838 states and 2112 transitions. [2018-11-18 15:13:47,448 INFO L78 Accepts]: Start accepts. Automaton has 1838 states and 2112 transitions. Word has length 167 [2018-11-18 15:13:47,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:47,448 INFO L480 AbstractCegarLoop]: Abstraction has 1838 states and 2112 transitions. [2018-11-18 15:13:47,448 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-11-18 15:13:47,448 INFO L276 IsEmpty]: Start isEmpty. Operand 1838 states and 2112 transitions. [2018-11-18 15:13:47,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-11-18 15:13:47,452 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:47,452 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:47,452 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:47,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:47,452 INFO L82 PathProgramCache]: Analyzing trace with hash 2125489486, now seen corresponding path program 1 times [2018-11-18 15:13:47,452 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:47,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:47,453 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:47,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:47,453 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:47,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:47,519 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 16 proven. 12 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-11-18 15:13:47,519 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:47,519 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:47,520 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 183 with the following transitions: [2018-11-18 15:13:47,520 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [225], [226], [238], [242], [248], [251], [254], [260], [266], [269], [273], [276], [279], [286], [289], [295], [301], [304], [307], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [468], [469], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:47,524 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:47,524 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:47,619 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:13:47,620 INFO L272 AbstractInterpreter]: Visited 117 different actions 255 times. Merged at 15 different actions 39 times. Never widened. Performed 2263 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2263 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 7 fixpoints after 4 different actions. Largest state had 36 variables. [2018-11-18 15:13:47,628 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:47,629 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:13:47,630 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:47,630 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:13:47,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:47,662 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:13:47,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:47,732 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:13:47,765 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 68 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 15:13:47,765 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:13:47,861 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2018-11-18 15:13:47,877 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:13:47,878 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 3] total 6 [2018-11-18 15:13:47,878 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:47,878 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:13:47,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:13:47,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:47,879 INFO L87 Difference]: Start difference. First operand 1838 states and 2112 transitions. Second operand 3 states. [2018-11-18 15:13:48,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:48,034 INFO L93 Difference]: Finished difference Result 3704 states and 4352 transitions. [2018-11-18 15:13:48,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:13:48,035 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 182 [2018-11-18 15:13:48,035 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:48,040 INFO L225 Difference]: With dead ends: 3704 [2018-11-18 15:13:48,040 INFO L226 Difference]: Without dead ends: 2264 [2018-11-18 15:13:48,043 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 369 GetRequests, 364 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:13:48,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2264 states. [2018-11-18 15:13:48,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2264 to 2254. [2018-11-18 15:13:48,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2254 states. [2018-11-18 15:13:48,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2254 states to 2254 states and 2603 transitions. [2018-11-18 15:13:48,193 INFO L78 Accepts]: Start accepts. Automaton has 2254 states and 2603 transitions. Word has length 182 [2018-11-18 15:13:48,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:48,193 INFO L480 AbstractCegarLoop]: Abstraction has 2254 states and 2603 transitions. [2018-11-18 15:13:48,193 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:13:48,193 INFO L276 IsEmpty]: Start isEmpty. Operand 2254 states and 2603 transitions. [2018-11-18 15:13:48,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2018-11-18 15:13:48,196 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:48,196 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:48,197 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:48,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:48,197 INFO L82 PathProgramCache]: Analyzing trace with hash -472478042, now seen corresponding path program 1 times [2018-11-18 15:13:48,197 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:48,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:48,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:48,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:48,198 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:48,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:48,254 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-11-18 15:13:48,255 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:13:48,255 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:13:48,255 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:48,255 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:13:48,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:13:48,255 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:13:48,256 INFO L87 Difference]: Start difference. First operand 2254 states and 2603 transitions. Second operand 4 states. [2018-11-18 15:13:48,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:48,525 INFO L93 Difference]: Finished difference Result 5012 states and 5893 transitions. [2018-11-18 15:13:48,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:13:48,525 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 205 [2018-11-18 15:13:48,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:48,536 INFO L225 Difference]: With dead ends: 5012 [2018-11-18 15:13:48,537 INFO L226 Difference]: Without dead ends: 3156 [2018-11-18 15:13:48,542 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:13:48,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3156 states. [2018-11-18 15:13:48,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3156 to 3061. [2018-11-18 15:13:48,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3061 states. [2018-11-18 15:13:48,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3061 states to 3061 states and 3478 transitions. [2018-11-18 15:13:48,807 INFO L78 Accepts]: Start accepts. Automaton has 3061 states and 3478 transitions. Word has length 205 [2018-11-18 15:13:48,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:48,808 INFO L480 AbstractCegarLoop]: Abstraction has 3061 states and 3478 transitions. [2018-11-18 15:13:48,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:13:48,808 INFO L276 IsEmpty]: Start isEmpty. Operand 3061 states and 3478 transitions. [2018-11-18 15:13:48,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-11-18 15:13:48,810 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:48,811 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:48,811 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:48,811 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:48,811 INFO L82 PathProgramCache]: Analyzing trace with hash 508726010, now seen corresponding path program 1 times [2018-11-18 15:13:48,811 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:48,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:48,812 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:48,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:48,812 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:48,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:48,897 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 82 trivial. 0 not checked. [2018-11-18 15:13:48,897 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:48,897 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:48,897 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 207 with the following transitions: [2018-11-18 15:13:48,898 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [91], [94], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [181], [192], [198], [200], [202], [206], [212], [214], [222], [225], [226], [238], [242], [248], [251], [254], [260], [263], [269], [273], [276], [279], [286], [289], [301], [304], [307], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [464], [465], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:48,899 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:48,899 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:48,952 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:13:48,952 INFO L272 AbstractInterpreter]: Visited 121 different actions 174 times. Merged at 13 different actions 13 times. Never widened. Performed 1159 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1159 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 3 fixpoints after 3 different actions. Largest state had 36 variables. [2018-11-18 15:13:48,954 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:48,954 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:13:49,049 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 74.24% of their original sizes. [2018-11-18 15:13:49,050 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:13:49,683 INFO L415 sIntCurrentIteration]: We unified 205 AI predicates to 205 [2018-11-18 15:13:49,683 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:13:49,684 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:49,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [57] imperfect sequences [6] total 61 [2018-11-18 15:13:49,684 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:49,684 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-18 15:13:49,685 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-18 15:13:49,685 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=423, Invalid=2769, Unknown=0, NotChecked=0, Total=3192 [2018-11-18 15:13:49,685 INFO L87 Difference]: Start difference. First operand 3061 states and 3478 transitions. Second operand 57 states. [2018-11-18 15:13:57,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:57,884 INFO L93 Difference]: Finished difference Result 6024 states and 6916 transitions. [2018-11-18 15:13:57,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-18 15:13:57,884 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 206 [2018-11-18 15:13:57,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:57,892 INFO L225 Difference]: With dead ends: 6024 [2018-11-18 15:13:57,892 INFO L226 Difference]: Without dead ends: 3361 [2018-11-18 15:13:57,897 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 271 GetRequests, 150 SyntacticMatches, 0 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5032 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1620, Invalid=13386, Unknown=0, NotChecked=0, Total=15006 [2018-11-18 15:13:57,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3361 states. [2018-11-18 15:13:58,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3361 to 3327. [2018-11-18 15:13:58,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3327 states. [2018-11-18 15:13:58,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3327 states to 3327 states and 3781 transitions. [2018-11-18 15:13:58,067 INFO L78 Accepts]: Start accepts. Automaton has 3327 states and 3781 transitions. Word has length 206 [2018-11-18 15:13:58,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:58,068 INFO L480 AbstractCegarLoop]: Abstraction has 3327 states and 3781 transitions. [2018-11-18 15:13:58,068 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-18 15:13:58,068 INFO L276 IsEmpty]: Start isEmpty. Operand 3327 states and 3781 transitions. [2018-11-18 15:13:58,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2018-11-18 15:13:58,071 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:58,071 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:58,071 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:58,071 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:58,071 INFO L82 PathProgramCache]: Analyzing trace with hash 1071398701, now seen corresponding path program 1 times [2018-11-18 15:13:58,072 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:58,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:58,072 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:58,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:58,072 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:58,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:58,137 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-11-18 15:13:58,137 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:58,137 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:58,137 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 208 with the following transitions: [2018-11-18 15:13:58,137 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [181], [192], [198], [200], [202], [206], [212], [214], [222], [225], [226], [238], [242], [248], [251], [254], [260], [263], [266], [273], [276], [279], [286], [289], [301], [304], [307], [309], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [464], [465], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:58,139 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:58,139 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:58,214 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:13:58,215 INFO L272 AbstractInterpreter]: Visited 124 different actions 332 times. Merged at 31 different actions 58 times. Never widened. Performed 3114 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3114 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 6 fixpoints after 3 different actions. Largest state had 36 variables. [2018-11-18 15:13:58,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:58,216 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:13:58,217 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:58,217 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:13:58,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:58,225 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:13:58,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:58,289 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:13:58,316 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 68 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-11-18 15:13:58,316 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:13:58,421 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2018-11-18 15:13:58,436 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:58,436 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 8 [2018-11-18 15:13:58,437 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:58,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:13:58,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:13:58,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:13:58,437 INFO L87 Difference]: Start difference. First operand 3327 states and 3781 transitions. Second operand 3 states. [2018-11-18 15:13:58,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:58,644 INFO L93 Difference]: Finished difference Result 5555 states and 6436 transitions. [2018-11-18 15:13:58,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:13:58,644 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 207 [2018-11-18 15:13:58,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:58,649 INFO L225 Difference]: With dead ends: 5555 [2018-11-18 15:13:58,649 INFO L226 Difference]: Without dead ends: 1764 [2018-11-18 15:13:58,656 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 420 GetRequests, 414 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:13:58,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1764 states. [2018-11-18 15:13:58,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1764 to 1711. [2018-11-18 15:13:58,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1711 states. [2018-11-18 15:13:58,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1711 states to 1711 states and 1886 transitions. [2018-11-18 15:13:58,795 INFO L78 Accepts]: Start accepts. Automaton has 1711 states and 1886 transitions. Word has length 207 [2018-11-18 15:13:58,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:58,795 INFO L480 AbstractCegarLoop]: Abstraction has 1711 states and 1886 transitions. [2018-11-18 15:13:58,795 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:13:58,795 INFO L276 IsEmpty]: Start isEmpty. Operand 1711 states and 1886 transitions. [2018-11-18 15:13:58,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2018-11-18 15:13:58,797 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:58,797 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:58,797 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:58,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:58,798 INFO L82 PathProgramCache]: Analyzing trace with hash 517428426, now seen corresponding path program 1 times [2018-11-18 15:13:58,798 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:58,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:58,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:58,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:58,799 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:58,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:58,852 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-11-18 15:13:58,853 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:58,853 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:58,853 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 209 with the following transitions: [2018-11-18 15:13:58,853 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [181], [192], [198], [200], [202], [206], [212], [214], [222], [225], [226], [238], [242], [248], [251], [254], [260], [263], [266], [273], [276], [279], [286], [289], [301], [304], [307], [309], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [399], [404], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [464], [465], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:58,854 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:58,854 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:58,935 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:13:58,935 INFO L272 AbstractInterpreter]: Visited 125 different actions 357 times. Merged at 31 different actions 68 times. Never widened. Performed 3469 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3469 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 6 fixpoints after 3 different actions. Largest state had 36 variables. [2018-11-18 15:13:58,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:58,940 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:13:58,940 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:58,941 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:13:58,947 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:58,947 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:13:58,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:59,002 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:13:59,032 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 66 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-18 15:13:59,032 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:13:59,107 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 82 trivial. 0 not checked. [2018-11-18 15:13:59,123 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:13:59,123 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2018-11-18 15:13:59,123 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:59,124 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:13:59,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:13:59,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:59,124 INFO L87 Difference]: Start difference. First operand 1711 states and 1886 transitions. Second operand 3 states. [2018-11-18 15:13:59,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:13:59,226 INFO L93 Difference]: Finished difference Result 3262 states and 3681 transitions. [2018-11-18 15:13:59,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:13:59,226 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 208 [2018-11-18 15:13:59,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:13:59,230 INFO L225 Difference]: With dead ends: 3262 [2018-11-18 15:13:59,231 INFO L226 Difference]: Without dead ends: 1926 [2018-11-18 15:13:59,233 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 422 GetRequests, 413 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:13:59,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1926 states. [2018-11-18 15:13:59,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1926 to 1920. [2018-11-18 15:13:59,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2018-11-18 15:13:59,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 2109 transitions. [2018-11-18 15:13:59,342 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 2109 transitions. Word has length 208 [2018-11-18 15:13:59,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:13:59,342 INFO L480 AbstractCegarLoop]: Abstraction has 1920 states and 2109 transitions. [2018-11-18 15:13:59,342 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:13:59,343 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 2109 transitions. [2018-11-18 15:13:59,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 210 [2018-11-18 15:13:59,344 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:13:59,344 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:13:59,345 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:13:59,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:59,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1395456767, now seen corresponding path program 1 times [2018-11-18 15:13:59,345 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:13:59,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:59,346 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:59,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:13:59,346 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:13:59,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:59,400 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-11-18 15:13:59,400 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:59,400 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:13:59,401 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 210 with the following transitions: [2018-11-18 15:13:59,401 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [30], [32], [37], [40], [45], [48], [51], [53], [55], [57], [60], [62], [65], [71], [77], [79], [85], [86], [89], [103], [104], [109], [115], [121], [127], [133], [135], [136], [139], [144], [146], [148], [150], [151], [154], [160], [166], [170], [171], [176], [181], [192], [198], [200], [202], [206], [212], [214], [222], [225], [226], [238], [242], [248], [251], [254], [260], [263], [266], [273], [276], [279], [286], [289], [301], [304], [307], [309], [311], [313], [315], [316], [321], [327], [333], [339], [345], [347], [348], [357], [363], [365], [395], [396], [399], [404], [406], [408], [410], [411], [446], [447], [448], [449], [450], [451], [452], [453], [454], [455], [456], [457], [458], [460], [461], [462], [464], [465], [468], [469], [470], [471], [472], [473], [474], [475], [476], [477], [478], [479], [480], [481], [482], [483], [484], [485], [486], [506], [507], [508] [2018-11-18 15:13:59,402 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:13:59,402 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:13:59,481 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:13:59,481 INFO L272 AbstractInterpreter]: Visited 126 different actions 361 times. Merged at 31 different actions 68 times. Never widened. Performed 3475 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3475 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 6 fixpoints after 3 different actions. Largest state had 36 variables. [2018-11-18 15:13:59,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:13:59,485 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:13:59,485 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:13:59,485 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:13:59,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:13:59,492 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:13:59,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:13:59,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:13:59,684 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 4 proven. 62 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-11-18 15:13:59,684 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:13:59,877 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 106 trivial. 0 not checked. [2018-11-18 15:13:59,903 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:13:59,903 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-11-18 15:13:59,903 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:13:59,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:13:59,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:13:59,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:13:59,904 INFO L87 Difference]: Start difference. First operand 1920 states and 2109 transitions. Second operand 5 states. [2018-11-18 15:14:00,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:14:00,483 INFO L93 Difference]: Finished difference Result 2691 states and 2971 transitions. [2018-11-18 15:14:00,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:14:00,483 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 209 [2018-11-18 15:14:00,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:14:00,487 INFO L225 Difference]: With dead ends: 2691 [2018-11-18 15:14:00,487 INFO L226 Difference]: Without dead ends: 1824 [2018-11-18 15:14:00,489 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 423 GetRequests, 411 SyntacticMatches, 5 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:14:00,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1824 states. [2018-11-18 15:14:00,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1824 to 1821. [2018-11-18 15:14:00,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1821 states. [2018-11-18 15:14:00,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1821 states to 1821 states and 2013 transitions. [2018-11-18 15:14:00,624 INFO L78 Accepts]: Start accepts. Automaton has 1821 states and 2013 transitions. Word has length 209 [2018-11-18 15:14:00,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:14:00,624 INFO L480 AbstractCegarLoop]: Abstraction has 1821 states and 2013 transitions. [2018-11-18 15:14:00,624 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:14:00,624 INFO L276 IsEmpty]: Start isEmpty. Operand 1821 states and 2013 transitions. [2018-11-18 15:14:00,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2018-11-18 15:14:00,625 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:14:00,626 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:14:00,626 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:14:00,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:14:00,626 INFO L82 PathProgramCache]: Analyzing trace with hash 381492844, now seen corresponding path program 1 times [2018-11-18 15:14:00,626 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:14:00,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:14:00,627 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:14:00,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:14:00,627 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:14:00,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:14:00,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:14:00,705 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 15:14:00,787 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 03:14:00 BoogieIcfgContainer [2018-11-18 15:14:00,787 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 15:14:00,788 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:14:00,788 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:14:00,788 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:14:00,788 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:13:23" (3/4) ... [2018-11-18 15:14:00,790 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 15:14:00,883 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_a05f93de-ad0a-4007-89f7-61aee91574c8/bin-2019/utaipan/witness.graphml [2018-11-18 15:14:00,883 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:14:00,884 INFO L168 Benchmark]: Toolchain (without parser) took 38290.69 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.2 GB). Free memory was 959.2 MB in the beginning and 2.0 GB in the end (delta: -1.0 GB). Peak memory consumption was 127.3 MB. Max. memory is 11.5 GB. [2018-11-18 15:14:00,884 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:14:00,885 INFO L168 Benchmark]: CACSL2BoogieTranslator took 206.31 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 943.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-18 15:14:00,885 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.54 ms. Allocated memory is still 1.0 GB. Free memory is still 943.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:14:00,885 INFO L168 Benchmark]: Boogie Preprocessor took 58.33 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.3 MB). Free memory was 943.1 MB in the beginning and 1.1 GB in the end (delta: -190.5 MB). Peak memory consumption was 17.3 MB. Max. memory is 11.5 GB. [2018-11-18 15:14:00,885 INFO L168 Benchmark]: RCFGBuilder took 418.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.5 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:14:00,886 INFO L168 Benchmark]: TraceAbstraction took 37496.03 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: -930.9 MB). Peak memory consumption was 98.8 MB. Max. memory is 11.5 GB. [2018-11-18 15:14:00,886 INFO L168 Benchmark]: Witness Printer took 95.26 ms. Allocated memory is still 2.2 GB. Free memory was 2.0 GB in the beginning and 2.0 GB in the end (delta: 25.4 MB). Peak memory consumption was 25.4 MB. Max. memory is 11.5 GB. [2018-11-18 15:14:00,887 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 206.31 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 943.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.54 ms. Allocated memory is still 1.0 GB. Free memory is still 943.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 58.33 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.3 MB). Free memory was 943.1 MB in the beginning and 1.1 GB in the end (delta: -190.5 MB). Peak memory consumption was 17.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 418.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.5 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 37496.03 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: -930.9 MB). Peak memory consumption was 98.8 MB. Max. memory is 11.5 GB. * Witness Printer took 95.26 ms. Allocated memory is still 2.2 GB. Free memory was 2.0 GB in the beginning and 2.0 GB in the end (delta: 25.4 MB). Peak memory consumption was 25.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; VAL [\old(E_1)=16, \old(E_2)=5, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=11, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=15, \old(t1_pc)=8, \old(t1_st)=4, \old(T2_E)=14, \old(t2_i)=6, \old(t2_pc)=9, \old(t2_st)=10, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] RET t2_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L567] init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L221] COND TRUE t2_i == 1 [L222] RET t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L329] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L334] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE, RET !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L401] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L409] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE, RET !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L514] activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L362] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L367] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE, RET !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L252] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L91] t1_pc = 1 [L92] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L291] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L126] t2_pc = 1 [L127] RET t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L305] transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L252] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L264] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE, RET !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1, tmp___1=0] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L58] m_pc = 1 [L59] RET m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] RET t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=0, tmp___0=0, tmp___1=1] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L91] t1_pc = 1 [L92] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L291] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 175 locations, 1 error locations. UNSAFE Result, 37.4s OverallTime, 25 OverallIterations, 3 TraceHistogramMax, 29.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 6144 SDtfs, 9913 SDslu, 20344 SDs, 0 SdLazy, 10117 SolverSat, 3057 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 7.3s Time, PredicateUnifierStatistics: 10 DeclaredPredicates, 2711 GetRequests, 2208 SyntacticMatches, 38 SemanticMatches, 465 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10259 ImplicationChecksByTransitivity, 5.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3327occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.7s AbstIntTime, 9 AbstIntIterations, 5 AbstIntStrong, 0.9877347416485258 AbsIntWeakeningRatio, 0.5416116248348745 AbsIntAvgWeakeningVarsNumRemoved, 12.80449141347424 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.6s AutomataMinimizationTime, 24 MinimizatonAttempts, 804 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 4231 NumberOfCodeBlocks, 4231 NumberOfCodeBlocksAsserted, 29 NumberOfCheckSat, 4789 ConstructedInterpolants, 0 QuantifiedInterpolants, 1168902 SizeOfPredicates, 5 NumberOfNonLiveVariables, 3091 ConjunctsInSsa, 18 ConjunctsInUnsatCore, 32 InterpolantComputations, 21 PerfectInterpolantSequences, 1506/1696 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...