./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:38:59,761 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:38:59,762 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:38:59,771 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:38:59,771 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:38:59,772 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:38:59,772 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:38:59,773 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:38:59,774 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:38:59,775 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:38:59,775 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:38:59,775 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:38:59,776 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:38:59,777 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:38:59,778 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:38:59,779 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:38:59,779 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:38:59,780 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:38:59,782 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:38:59,783 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:38:59,784 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:38:59,785 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:38:59,787 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:38:59,787 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:38:59,787 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:38:59,788 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:38:59,789 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:38:59,790 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:38:59,790 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:38:59,791 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:38:59,791 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:38:59,792 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:38:59,792 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:38:59,792 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:38:59,793 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:38:59,793 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:38:59,794 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-18 15:38:59,804 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:38:59,804 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:38:59,805 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 15:38:59,805 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-11-18 15:38:59,806 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-18 15:38:59,806 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-18 15:38:59,807 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-18 15:38:59,807 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:38:59,807 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:38:59,807 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:38:59,808 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:38:59,809 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 15:38:59,810 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:38:59,811 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:38:59,811 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 15:38:59,811 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 15:38:59,811 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:38:59,811 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:38:59,811 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 15:38:59,811 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 15:38:59,812 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-18 15:38:59,812 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 15:38:59,812 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 15:38:59,812 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-18 15:38:59,812 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-11-18 15:38:59,835 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:38:59,844 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:38:59,847 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:38:59,848 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:38:59,848 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:38:59,849 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-18 15:38:59,894 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/data/a45b744d0/56c10776ea6545f1ba771527e05291ec/FLAGa09f09c01 [2018-11-18 15:39:00,335 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:39:00,335 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-18 15:39:00,344 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/data/a45b744d0/56c10776ea6545f1ba771527e05291ec/FLAGa09f09c01 [2018-11-18 15:39:00,355 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/data/a45b744d0/56c10776ea6545f1ba771527e05291ec [2018-11-18 15:39:00,358 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:39:00,359 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 15:39:00,360 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:39:00,360 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:39:00,363 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:39:00,363 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,365 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1dead91d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00, skipping insertion in model container [2018-11-18 15:39:00,366 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,373 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:39:00,401 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:39:00,559 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:39:00,564 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:39:00,591 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:39:00,602 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:39:00,602 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00 WrapperNode [2018-11-18 15:39:00,602 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:39:00,603 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 15:39:00,603 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 15:39:00,603 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 15:39:00,608 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,651 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,656 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 15:39:00,657 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:39:00,657 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:39:00,657 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:39:00,663 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,663 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,665 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,665 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,672 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,682 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,684 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... [2018-11-18 15:39:00,687 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:39:00,687 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:39:00,687 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:39:00,687 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:39:00,688 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:39:00,723 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-18 15:39:00,723 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-11-18 15:39:00,724 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-18 15:39:00,724 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-11-18 15:39:00,724 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 15:39:00,724 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-18 15:39:00,724 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-18 15:39:00,724 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-18 15:39:00,724 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-18 15:39:00,725 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-18 15:39:00,725 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-18 15:39:00,725 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-18 15:39:00,725 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-18 15:39:00,725 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-18 15:39:00,725 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-18 15:39:00,725 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-18 15:39:00,725 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-11-18 15:39:00,725 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-11-18 15:39:00,726 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-18 15:39:00,726 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-18 15:39:00,726 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-18 15:39:00,726 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-18 15:39:00,726 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-18 15:39:00,726 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-18 15:39:00,726 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-18 15:39:00,727 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-18 15:39:00,727 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-18 15:39:00,727 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-18 15:39:00,727 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-18 15:39:00,727 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-18 15:39:00,727 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-18 15:39:00,727 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-18 15:39:00,727 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-18 15:39:00,727 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-18 15:39:00,727 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 15:39:00,728 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 15:39:00,728 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-18 15:39:00,728 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-18 15:39:00,728 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-11-18 15:39:00,728 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-11-18 15:39:00,728 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-18 15:39:00,728 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-18 15:39:00,728 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-18 15:39:00,728 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-18 15:39:00,729 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:39:00,729 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:39:00,729 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-18 15:39:00,729 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-18 15:39:01,218 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:39:01,218 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:39:01 BoogieIcfgContainer [2018-11-18 15:39:01,218 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:39:01,219 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 15:39:01,219 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 15:39:01,222 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 15:39:01,222 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 03:39:00" (1/3) ... [2018-11-18 15:39:01,222 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@40e6ff6d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:39:01, skipping insertion in model container [2018-11-18 15:39:01,223 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:39:00" (2/3) ... [2018-11-18 15:39:01,223 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@40e6ff6d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:39:01, skipping insertion in model container [2018-11-18 15:39:01,223 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:39:01" (3/3) ... [2018-11-18 15:39:01,225 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-18 15:39:01,233 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 15:39:01,239 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 15:39:01,249 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 15:39:01,270 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 15:39:01,270 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 15:39:01,270 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 15:39:01,271 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:39:01,271 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:39:01,271 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 15:39:01,271 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:39:01,271 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 15:39:01,289 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states. [2018-11-18 15:39:01,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:01,297 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:01,297 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:01,299 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:01,302 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:01,302 INFO L82 PathProgramCache]: Analyzing trace with hash -184296924, now seen corresponding path program 1 times [2018-11-18 15:39:01,303 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:01,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:01,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:01,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:01,333 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:01,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:01,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:01,504 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:01,505 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:39:01,505 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:01,509 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:39:01,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:39:01,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:01,523 INFO L87 Difference]: Start difference. First operand 237 states. Second operand 4 states. [2018-11-18 15:39:01,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:01,715 INFO L93 Difference]: Finished difference Result 456 states and 664 transitions. [2018-11-18 15:39:01,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:39:01,717 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 122 [2018-11-18 15:39:01,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:01,725 INFO L225 Difference]: With dead ends: 456 [2018-11-18 15:39:01,725 INFO L226 Difference]: Without dead ends: 228 [2018-11-18 15:39:01,728 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:01,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-11-18 15:39:01,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 228. [2018-11-18 15:39:01,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:01,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 312 transitions. [2018-11-18 15:39:01,773 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 312 transitions. Word has length 122 [2018-11-18 15:39:01,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:01,775 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 312 transitions. [2018-11-18 15:39:01,775 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:39:01,775 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 312 transitions. [2018-11-18 15:39:01,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:01,778 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:01,778 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:01,778 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:01,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:01,779 INFO L82 PathProgramCache]: Analyzing trace with hash -302738398, now seen corresponding path program 1 times [2018-11-18 15:39:01,779 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:01,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:01,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:01,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:01,780 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:01,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:01,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:01,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:01,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:01,921 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:01,922 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:01,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:01,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:01,923 INFO L87 Difference]: Start difference. First operand 228 states and 312 transitions. Second operand 5 states. [2018-11-18 15:39:02,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:02,333 INFO L93 Difference]: Finished difference Result 471 states and 663 transitions. [2018-11-18 15:39:02,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:02,334 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:02,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:02,336 INFO L225 Difference]: With dead ends: 471 [2018-11-18 15:39:02,336 INFO L226 Difference]: Without dead ends: 265 [2018-11-18 15:39:02,338 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:02,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-11-18 15:39:02,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 228. [2018-11-18 15:39:02,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:02,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 311 transitions. [2018-11-18 15:39:02,361 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 311 transitions. Word has length 122 [2018-11-18 15:39:02,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:02,361 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 311 transitions. [2018-11-18 15:39:02,361 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:02,361 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 311 transitions. [2018-11-18 15:39:02,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:02,364 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:02,364 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:02,364 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:02,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:02,365 INFO L82 PathProgramCache]: Analyzing trace with hash 2085825632, now seen corresponding path program 1 times [2018-11-18 15:39:02,365 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:02,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:02,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:02,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:02,366 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:02,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:02,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:02,464 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:02,464 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:02,464 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:02,464 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:02,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:02,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:02,465 INFO L87 Difference]: Start difference. First operand 228 states and 311 transitions. Second operand 5 states. [2018-11-18 15:39:02,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:02,802 INFO L93 Difference]: Finished difference Result 471 states and 662 transitions. [2018-11-18 15:39:02,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:02,802 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:02,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:02,804 INFO L225 Difference]: With dead ends: 471 [2018-11-18 15:39:02,804 INFO L226 Difference]: Without dead ends: 265 [2018-11-18 15:39:02,805 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:02,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-11-18 15:39:02,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 228. [2018-11-18 15:39:02,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:02,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 310 transitions. [2018-11-18 15:39:02,827 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 310 transitions. Word has length 122 [2018-11-18 15:39:02,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:02,827 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 310 transitions. [2018-11-18 15:39:02,827 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:02,827 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 310 transitions. [2018-11-18 15:39:02,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:02,828 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:02,829 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:02,830 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:02,830 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:02,830 INFO L82 PathProgramCache]: Analyzing trace with hash -608070558, now seen corresponding path program 1 times [2018-11-18 15:39:02,831 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:02,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:02,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:02,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:02,831 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:02,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:02,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:02,909 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:02,909 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:02,909 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:02,910 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:02,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:02,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:02,910 INFO L87 Difference]: Start difference. First operand 228 states and 310 transitions. Second operand 5 states. [2018-11-18 15:39:03,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:03,229 INFO L93 Difference]: Finished difference Result 469 states and 656 transitions. [2018-11-18 15:39:03,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:03,230 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:03,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:03,231 INFO L225 Difference]: With dead ends: 469 [2018-11-18 15:39:03,232 INFO L226 Difference]: Without dead ends: 263 [2018-11-18 15:39:03,232 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:03,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states. [2018-11-18 15:39:03,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 228. [2018-11-18 15:39:03,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:03,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 309 transitions. [2018-11-18 15:39:03,255 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 309 transitions. Word has length 122 [2018-11-18 15:39:03,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:03,255 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 309 transitions. [2018-11-18 15:39:03,255 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:03,255 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 309 transitions. [2018-11-18 15:39:03,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:03,256 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:03,257 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:03,257 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:03,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:03,258 INFO L82 PathProgramCache]: Analyzing trace with hash -1664801760, now seen corresponding path program 1 times [2018-11-18 15:39:03,258 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:03,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:03,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:03,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:03,259 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:03,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:03,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:03,315 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:03,315 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:03,315 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:03,316 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:03,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:03,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:03,316 INFO L87 Difference]: Start difference. First operand 228 states and 309 transitions. Second operand 5 states. [2018-11-18 15:39:03,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:03,661 INFO L93 Difference]: Finished difference Result 467 states and 650 transitions. [2018-11-18 15:39:03,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:03,662 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:03,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:03,664 INFO L225 Difference]: With dead ends: 467 [2018-11-18 15:39:03,664 INFO L226 Difference]: Without dead ends: 261 [2018-11-18 15:39:03,665 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:03,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-11-18 15:39:03,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 228. [2018-11-18 15:39:03,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:03,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 308 transitions. [2018-11-18 15:39:03,682 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 308 transitions. Word has length 122 [2018-11-18 15:39:03,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:03,682 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 308 transitions. [2018-11-18 15:39:03,682 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:03,683 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 308 transitions. [2018-11-18 15:39:03,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:03,684 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:03,684 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:03,684 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:03,684 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:03,684 INFO L82 PathProgramCache]: Analyzing trace with hash -313416542, now seen corresponding path program 1 times [2018-11-18 15:39:03,685 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:03,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:03,685 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:03,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:03,686 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:03,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:03,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:03,745 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:03,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:03,745 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:03,746 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:03,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:03,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:03,746 INFO L87 Difference]: Start difference. First operand 228 states and 308 transitions. Second operand 5 states. [2018-11-18 15:39:04,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:04,064 INFO L93 Difference]: Finished difference Result 465 states and 644 transitions. [2018-11-18 15:39:04,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:04,065 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:04,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:04,066 INFO L225 Difference]: With dead ends: 465 [2018-11-18 15:39:04,067 INFO L226 Difference]: Without dead ends: 259 [2018-11-18 15:39:04,067 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:04,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2018-11-18 15:39:04,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 228. [2018-11-18 15:39:04,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:04,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 307 transitions. [2018-11-18 15:39:04,083 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 307 transitions. Word has length 122 [2018-11-18 15:39:04,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:04,084 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 307 transitions. [2018-11-18 15:39:04,084 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:04,084 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 307 transitions. [2018-11-18 15:39:04,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:04,085 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:04,085 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:04,085 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:04,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:04,086 INFO L82 PathProgramCache]: Analyzing trace with hash -1932391456, now seen corresponding path program 1 times [2018-11-18 15:39:04,086 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:04,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:04,086 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:04,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:04,087 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:04,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:04,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:04,135 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:04,135 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:04,135 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:04,135 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:04,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:04,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:04,136 INFO L87 Difference]: Start difference. First operand 228 states and 307 transitions. Second operand 5 states. [2018-11-18 15:39:04,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:04,409 INFO L93 Difference]: Finished difference Result 490 states and 684 transitions. [2018-11-18 15:39:04,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:04,410 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:04,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:04,411 INFO L225 Difference]: With dead ends: 490 [2018-11-18 15:39:04,411 INFO L226 Difference]: Without dead ends: 284 [2018-11-18 15:39:04,412 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:04,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2018-11-18 15:39:04,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 228. [2018-11-18 15:39:04,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:04,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 306 transitions. [2018-11-18 15:39:04,432 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 306 transitions. Word has length 122 [2018-11-18 15:39:04,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:04,432 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 306 transitions. [2018-11-18 15:39:04,432 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:04,432 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 306 transitions. [2018-11-18 15:39:04,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:04,433 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:04,433 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:04,434 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:04,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:04,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1479066850, now seen corresponding path program 1 times [2018-11-18 15:39:04,434 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:04,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:04,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:04,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:04,435 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:04,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:04,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:04,481 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:04,481 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:04,481 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:04,482 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:04,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:04,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:04,482 INFO L87 Difference]: Start difference. First operand 228 states and 306 transitions. Second operand 5 states. [2018-11-18 15:39:04,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:04,790 INFO L93 Difference]: Finished difference Result 486 states and 674 transitions. [2018-11-18 15:39:04,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:04,790 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:04,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:04,792 INFO L225 Difference]: With dead ends: 486 [2018-11-18 15:39:04,792 INFO L226 Difference]: Without dead ends: 280 [2018-11-18 15:39:04,793 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:04,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2018-11-18 15:39:04,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 228. [2018-11-18 15:39:04,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:04,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 305 transitions. [2018-11-18 15:39:04,811 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 305 transitions. Word has length 122 [2018-11-18 15:39:04,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:04,811 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 305 transitions. [2018-11-18 15:39:04,811 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:04,811 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 305 transitions. [2018-11-18 15:39:04,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:04,812 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:04,812 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:04,812 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:04,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:04,813 INFO L82 PathProgramCache]: Analyzing trace with hash -461515164, now seen corresponding path program 1 times [2018-11-18 15:39:04,813 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:04,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:04,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:04,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:04,814 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:04,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:04,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:04,868 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:04,868 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:04,868 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:04,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:04,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:04,869 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:04,870 INFO L87 Difference]: Start difference. First operand 228 states and 305 transitions. Second operand 5 states. [2018-11-18 15:39:05,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:05,161 INFO L93 Difference]: Finished difference Result 484 states and 668 transitions. [2018-11-18 15:39:05,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:05,162 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:05,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:05,163 INFO L225 Difference]: With dead ends: 484 [2018-11-18 15:39:05,163 INFO L226 Difference]: Without dead ends: 278 [2018-11-18 15:39:05,164 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:05,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-11-18 15:39:05,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 228. [2018-11-18 15:39:05,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 15:39:05,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 304 transitions. [2018-11-18 15:39:05,183 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 304 transitions. Word has length 122 [2018-11-18 15:39:05,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:05,183 INFO L480 AbstractCegarLoop]: Abstraction has 228 states and 304 transitions. [2018-11-18 15:39:05,184 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:05,184 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 304 transitions. [2018-11-18 15:39:05,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:05,185 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:05,185 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:05,185 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:05,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:05,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1415548066, now seen corresponding path program 1 times [2018-11-18 15:39:05,186 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:05,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:05,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,187 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:05,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:05,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:05,255 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:05,255 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:39:05,255 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:05,256 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:39:05,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:39:05,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:05,256 INFO L87 Difference]: Start difference. First operand 228 states and 304 transitions. Second operand 4 states. [2018-11-18 15:39:05,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:05,449 INFO L93 Difference]: Finished difference Result 629 states and 868 transitions. [2018-11-18 15:39:05,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:39:05,450 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 122 [2018-11-18 15:39:05,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:05,452 INFO L225 Difference]: With dead ends: 629 [2018-11-18 15:39:05,452 INFO L226 Difference]: Without dead ends: 424 [2018-11-18 15:39:05,453 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:05,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states. [2018-11-18 15:39:05,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 418. [2018-11-18 15:39:05,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2018-11-18 15:39:05,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 558 transitions. [2018-11-18 15:39:05,489 INFO L78 Accepts]: Start accepts. Automaton has 418 states and 558 transitions. Word has length 122 [2018-11-18 15:39:05,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:05,489 INFO L480 AbstractCegarLoop]: Abstraction has 418 states and 558 transitions. [2018-11-18 15:39:05,489 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:39:05,489 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 558 transitions. [2018-11-18 15:39:05,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:05,490 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:05,491 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:05,491 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:05,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:05,491 INFO L82 PathProgramCache]: Analyzing trace with hash 15400355, now seen corresponding path program 1 times [2018-11-18 15:39:05,491 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:05,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:05,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,492 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:05,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:05,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:05,542 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:05,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:39:05,542 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:05,542 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:39:05,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:39:05,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:05,543 INFO L87 Difference]: Start difference. First operand 418 states and 558 transitions. Second operand 6 states. [2018-11-18 15:39:05,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:05,596 INFO L93 Difference]: Finished difference Result 832 states and 1140 transitions. [2018-11-18 15:39:05,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:05,597 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2018-11-18 15:39:05,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:05,599 INFO L225 Difference]: With dead ends: 832 [2018-11-18 15:39:05,599 INFO L226 Difference]: Without dead ends: 437 [2018-11-18 15:39:05,600 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:05,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states. [2018-11-18 15:39:05,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 423. [2018-11-18 15:39:05,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 423 states. [2018-11-18 15:39:05,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423 states to 423 states and 562 transitions. [2018-11-18 15:39:05,635 INFO L78 Accepts]: Start accepts. Automaton has 423 states and 562 transitions. Word has length 122 [2018-11-18 15:39:05,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:05,635 INFO L480 AbstractCegarLoop]: Abstraction has 423 states and 562 transitions. [2018-11-18 15:39:05,635 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:39:05,635 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 562 transitions. [2018-11-18 15:39:05,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:05,636 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:05,637 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:05,637 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:05,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:05,637 INFO L82 PathProgramCache]: Analyzing trace with hash 42465957, now seen corresponding path program 1 times [2018-11-18 15:39:05,637 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:05,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,638 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:05,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,638 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:05,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:05,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:05,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:05,702 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:39:05,702 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:05,703 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:39:05,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:39:05,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:05,703 INFO L87 Difference]: Start difference. First operand 423 states and 562 transitions. Second operand 6 states. [2018-11-18 15:39:05,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:05,754 INFO L93 Difference]: Finished difference Result 855 states and 1169 transitions. [2018-11-18 15:39:05,755 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:05,755 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2018-11-18 15:39:05,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:05,757 INFO L225 Difference]: With dead ends: 855 [2018-11-18 15:39:05,757 INFO L226 Difference]: Without dead ends: 455 [2018-11-18 15:39:05,759 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:05,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 455 states. [2018-11-18 15:39:05,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 455 to 433. [2018-11-18 15:39:05,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 433 states. [2018-11-18 15:39:05,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 572 transitions. [2018-11-18 15:39:05,794 INFO L78 Accepts]: Start accepts. Automaton has 433 states and 572 transitions. Word has length 122 [2018-11-18 15:39:05,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:05,794 INFO L480 AbstractCegarLoop]: Abstraction has 433 states and 572 transitions. [2018-11-18 15:39:05,794 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:39:05,794 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 572 transitions. [2018-11-18 15:39:05,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:05,795 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:05,795 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:05,796 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:05,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:05,796 INFO L82 PathProgramCache]: Analyzing trace with hash 996406115, now seen corresponding path program 1 times [2018-11-18 15:39:05,796 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:05,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,797 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:05,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,797 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:05,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:05,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:05,841 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:05,841 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:39:05,842 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:05,842 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:39:05,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:39:05,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:05,842 INFO L87 Difference]: Start difference. First operand 433 states and 572 transitions. Second operand 6 states. [2018-11-18 15:39:05,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:05,896 INFO L93 Difference]: Finished difference Result 869 states and 1179 transitions. [2018-11-18 15:39:05,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:05,896 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2018-11-18 15:39:05,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:05,899 INFO L225 Difference]: With dead ends: 869 [2018-11-18 15:39:05,899 INFO L226 Difference]: Without dead ends: 459 [2018-11-18 15:39:05,900 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:05,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459 states. [2018-11-18 15:39:05,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459 to 443. [2018-11-18 15:39:05,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 443 states. [2018-11-18 15:39:05,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 582 transitions. [2018-11-18 15:39:05,936 INFO L78 Accepts]: Start accepts. Automaton has 443 states and 582 transitions. Word has length 122 [2018-11-18 15:39:05,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:05,937 INFO L480 AbstractCegarLoop]: Abstraction has 443 states and 582 transitions. [2018-11-18 15:39:05,937 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:39:05,937 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 582 transitions. [2018-11-18 15:39:05,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:05,938 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:05,938 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:05,938 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:05,938 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:05,938 INFO L82 PathProgramCache]: Analyzing trace with hash 1557105893, now seen corresponding path program 1 times [2018-11-18 15:39:05,939 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:05,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:05,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:05,939 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:05,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:05,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:05,980 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:05,980 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:39:05,981 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:05,981 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:39:05,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:39:05,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:05,983 INFO L87 Difference]: Start difference. First operand 443 states and 582 transitions. Second operand 4 states. [2018-11-18 15:39:06,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:06,274 INFO L93 Difference]: Finished difference Result 1270 states and 1722 transitions. [2018-11-18 15:39:06,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:39:06,275 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 122 [2018-11-18 15:39:06,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:06,277 INFO L225 Difference]: With dead ends: 1270 [2018-11-18 15:39:06,278 INFO L226 Difference]: Without dead ends: 850 [2018-11-18 15:39:06,279 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:06,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states. [2018-11-18 15:39:06,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 841. [2018-11-18 15:39:06,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 841 states. [2018-11-18 15:39:06,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 841 states to 841 states and 1103 transitions. [2018-11-18 15:39:06,320 INFO L78 Accepts]: Start accepts. Automaton has 841 states and 1103 transitions. Word has length 122 [2018-11-18 15:39:06,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:06,321 INFO L480 AbstractCegarLoop]: Abstraction has 841 states and 1103 transitions. [2018-11-18 15:39:06,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:39:06,321 INFO L276 IsEmpty]: Start isEmpty. Operand 841 states and 1103 transitions. [2018-11-18 15:39:06,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:06,322 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:06,322 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:06,322 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:06,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:06,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1564856452, now seen corresponding path program 1 times [2018-11-18 15:39:06,322 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:06,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:06,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:06,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:06,323 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:06,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:06,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:06,365 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:06,366 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:39:06,366 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:06,366 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:39:06,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:39:06,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:06,366 INFO L87 Difference]: Start difference. First operand 841 states and 1103 transitions. Second operand 6 states. [2018-11-18 15:39:06,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:06,440 INFO L93 Difference]: Finished difference Result 1679 states and 2252 transitions. [2018-11-18 15:39:06,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:06,441 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2018-11-18 15:39:06,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:06,443 INFO L225 Difference]: With dead ends: 1679 [2018-11-18 15:39:06,443 INFO L226 Difference]: Without dead ends: 861 [2018-11-18 15:39:06,445 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:06,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 861 states. [2018-11-18 15:39:06,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 861 to 851. [2018-11-18 15:39:06,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 851 states. [2018-11-18 15:39:06,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 851 states to 851 states and 1111 transitions. [2018-11-18 15:39:06,487 INFO L78 Accepts]: Start accepts. Automaton has 851 states and 1111 transitions. Word has length 122 [2018-11-18 15:39:06,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:06,487 INFO L480 AbstractCegarLoop]: Abstraction has 851 states and 1111 transitions. [2018-11-18 15:39:06,487 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:39:06,488 INFO L276 IsEmpty]: Start isEmpty. Operand 851 states and 1111 transitions. [2018-11-18 15:39:06,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:06,489 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:06,489 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:06,489 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:06,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:06,489 INFO L82 PathProgramCache]: Analyzing trace with hash 1083776194, now seen corresponding path program 1 times [2018-11-18 15:39:06,489 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:06,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:06,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:06,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:06,490 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:06,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:06,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:06,539 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:06,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:39:06,539 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:06,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:39:06,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:39:06,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:06,539 INFO L87 Difference]: Start difference. First operand 851 states and 1111 transitions. Second operand 6 states. [2018-11-18 15:39:06,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:06,602 INFO L93 Difference]: Finished difference Result 1707 states and 2279 transitions. [2018-11-18 15:39:06,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:06,603 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2018-11-18 15:39:06,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:06,605 INFO L225 Difference]: With dead ends: 1707 [2018-11-18 15:39:06,605 INFO L226 Difference]: Without dead ends: 879 [2018-11-18 15:39:06,607 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:06,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 879 states. [2018-11-18 15:39:06,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 879 to 871. [2018-11-18 15:39:06,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 871 states. [2018-11-18 15:39:06,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1131 transitions. [2018-11-18 15:39:06,648 INFO L78 Accepts]: Start accepts. Automaton has 871 states and 1131 transitions. Word has length 122 [2018-11-18 15:39:06,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:06,648 INFO L480 AbstractCegarLoop]: Abstraction has 871 states and 1131 transitions. [2018-11-18 15:39:06,648 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:39:06,648 INFO L276 IsEmpty]: Start isEmpty. Operand 871 states and 1131 transitions. [2018-11-18 15:39:06,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:06,649 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:06,649 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:06,649 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:06,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:06,650 INFO L82 PathProgramCache]: Analyzing trace with hash 1507422916, now seen corresponding path program 1 times [2018-11-18 15:39:06,650 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:06,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:06,650 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:06,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:06,650 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:06,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:06,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:06,710 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:06,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:06,710 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:06,710 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:06,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:06,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:06,710 INFO L87 Difference]: Start difference. First operand 871 states and 1131 transitions. Second operand 5 states. [2018-11-18 15:39:07,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:07,115 INFO L93 Difference]: Finished difference Result 2096 states and 2768 transitions. [2018-11-18 15:39:07,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:39:07,115 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:07,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:07,119 INFO L225 Difference]: With dead ends: 2096 [2018-11-18 15:39:07,119 INFO L226 Difference]: Without dead ends: 1249 [2018-11-18 15:39:07,121 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:39:07,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1249 states. [2018-11-18 15:39:07,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1249 to 1161. [2018-11-18 15:39:07,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1161 states. [2018-11-18 15:39:07,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1161 states to 1161 states and 1475 transitions. [2018-11-18 15:39:07,175 INFO L78 Accepts]: Start accepts. Automaton has 1161 states and 1475 transitions. Word has length 122 [2018-11-18 15:39:07,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:07,176 INFO L480 AbstractCegarLoop]: Abstraction has 1161 states and 1475 transitions. [2018-11-18 15:39:07,176 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:07,176 INFO L276 IsEmpty]: Start isEmpty. Operand 1161 states and 1475 transitions. [2018-11-18 15:39:07,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:07,177 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:07,177 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:07,177 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:07,177 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:07,178 INFO L82 PathProgramCache]: Analyzing trace with hash -2128012858, now seen corresponding path program 1 times [2018-11-18 15:39:07,178 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:07,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:07,178 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:07,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:07,178 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:07,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:07,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:07,237 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:07,238 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:07,238 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:07,238 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:07,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:07,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:07,238 INFO L87 Difference]: Start difference. First operand 1161 states and 1475 transitions. Second operand 5 states. [2018-11-18 15:39:07,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:07,567 INFO L93 Difference]: Finished difference Result 2298 states and 2931 transitions. [2018-11-18 15:39:07,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:07,568 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:07,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:07,571 INFO L225 Difference]: With dead ends: 2298 [2018-11-18 15:39:07,571 INFO L226 Difference]: Without dead ends: 1161 [2018-11-18 15:39:07,573 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:07,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1161 states. [2018-11-18 15:39:07,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1161 to 1161. [2018-11-18 15:39:07,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1161 states. [2018-11-18 15:39:07,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1161 states to 1161 states and 1465 transitions. [2018-11-18 15:39:07,624 INFO L78 Accepts]: Start accepts. Automaton has 1161 states and 1465 transitions. Word has length 122 [2018-11-18 15:39:07,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:07,624 INFO L480 AbstractCegarLoop]: Abstraction has 1161 states and 1465 transitions. [2018-11-18 15:39:07,624 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:07,625 INFO L276 IsEmpty]: Start isEmpty. Operand 1161 states and 1465 transitions. [2018-11-18 15:39:07,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:07,626 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:07,626 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:07,626 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:07,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:07,626 INFO L82 PathProgramCache]: Analyzing trace with hash 1772587652, now seen corresponding path program 1 times [2018-11-18 15:39:07,626 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:07,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:07,627 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:07,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:07,627 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:07,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:07,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:07,690 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:07,690 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:07,690 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:07,690 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:07,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:07,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:07,691 INFO L87 Difference]: Start difference. First operand 1161 states and 1465 transitions. Second operand 5 states. [2018-11-18 15:39:07,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:07,964 INFO L93 Difference]: Finished difference Result 2298 states and 2911 transitions. [2018-11-18 15:39:07,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:07,965 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:07,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:07,968 INFO L225 Difference]: With dead ends: 2298 [2018-11-18 15:39:07,968 INFO L226 Difference]: Without dead ends: 1161 [2018-11-18 15:39:07,970 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:07,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1161 states. [2018-11-18 15:39:08,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1161 to 1161. [2018-11-18 15:39:08,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1161 states. [2018-11-18 15:39:08,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1161 states to 1161 states and 1455 transitions. [2018-11-18 15:39:08,020 INFO L78 Accepts]: Start accepts. Automaton has 1161 states and 1455 transitions. Word has length 122 [2018-11-18 15:39:08,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:08,020 INFO L480 AbstractCegarLoop]: Abstraction has 1161 states and 1455 transitions. [2018-11-18 15:39:08,020 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:08,020 INFO L276 IsEmpty]: Start isEmpty. Operand 1161 states and 1455 transitions. [2018-11-18 15:39:08,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:08,021 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:08,021 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:08,021 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:08,022 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:08,022 INFO L82 PathProgramCache]: Analyzing trace with hash -471395646, now seen corresponding path program 1 times [2018-11-18 15:39:08,022 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:08,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:08,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:08,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:08,022 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:08,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:08,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:08,074 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:08,075 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:08,075 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:08,075 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:08,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:08,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:08,075 INFO L87 Difference]: Start difference. First operand 1161 states and 1455 transitions. Second operand 5 states. [2018-11-18 15:39:08,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:08,343 INFO L93 Difference]: Finished difference Result 2298 states and 2891 transitions. [2018-11-18 15:39:08,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:08,344 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:08,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:08,347 INFO L225 Difference]: With dead ends: 2298 [2018-11-18 15:39:08,347 INFO L226 Difference]: Without dead ends: 1161 [2018-11-18 15:39:08,349 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:08,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1161 states. [2018-11-18 15:39:08,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1161 to 1161. [2018-11-18 15:39:08,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1161 states. [2018-11-18 15:39:08,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1161 states to 1161 states and 1445 transitions. [2018-11-18 15:39:08,399 INFO L78 Accepts]: Start accepts. Automaton has 1161 states and 1445 transitions. Word has length 122 [2018-11-18 15:39:08,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:08,399 INFO L480 AbstractCegarLoop]: Abstraction has 1161 states and 1445 transitions. [2018-11-18 15:39:08,399 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:08,399 INFO L276 IsEmpty]: Start isEmpty. Operand 1161 states and 1445 transitions. [2018-11-18 15:39:08,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:08,400 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:08,400 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:08,400 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:08,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:08,401 INFO L82 PathProgramCache]: Analyzing trace with hash -543782204, now seen corresponding path program 1 times [2018-11-18 15:39:08,401 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:08,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:08,401 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:08,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:08,402 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:08,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:08,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:08,459 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:08,459 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:08,459 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:08,460 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:08,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:08,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:08,460 INFO L87 Difference]: Start difference. First operand 1161 states and 1445 transitions. Second operand 5 states. [2018-11-18 15:39:08,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:08,976 INFO L93 Difference]: Finished difference Result 2551 states and 3242 transitions. [2018-11-18 15:39:08,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:08,977 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:08,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:08,981 INFO L225 Difference]: With dead ends: 2551 [2018-11-18 15:39:08,981 INFO L226 Difference]: Without dead ends: 1413 [2018-11-18 15:39:08,984 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:08,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1413 states. [2018-11-18 15:39:09,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1413 to 1319. [2018-11-18 15:39:09,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1319 states. [2018-11-18 15:39:09,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1319 states to 1319 states and 1631 transitions. [2018-11-18 15:39:09,042 INFO L78 Accepts]: Start accepts. Automaton has 1319 states and 1631 transitions. Word has length 122 [2018-11-18 15:39:09,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:09,042 INFO L480 AbstractCegarLoop]: Abstraction has 1319 states and 1631 transitions. [2018-11-18 15:39:09,042 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:09,042 INFO L276 IsEmpty]: Start isEmpty. Operand 1319 states and 1631 transitions. [2018-11-18 15:39:09,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:09,043 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:09,043 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:09,044 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:09,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:09,044 INFO L82 PathProgramCache]: Analyzing trace with hash -269022590, now seen corresponding path program 1 times [2018-11-18 15:39:09,044 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:09,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:09,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:09,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:09,045 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:09,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:09,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:09,106 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:09,106 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:09,106 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:09,106 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:09,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:09,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:09,107 INFO L87 Difference]: Start difference. First operand 1319 states and 1631 transitions. Second operand 5 states. [2018-11-18 15:39:09,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:09,522 INFO L93 Difference]: Finished difference Result 3264 states and 4262 transitions. [2018-11-18 15:39:09,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:39:09,524 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:09,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:09,529 INFO L225 Difference]: With dead ends: 3264 [2018-11-18 15:39:09,529 INFO L226 Difference]: Without dead ends: 1968 [2018-11-18 15:39:09,532 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:39:09,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1968 states. [2018-11-18 15:39:09,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1968 to 1609. [2018-11-18 15:39:09,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1609 states. [2018-11-18 15:39:09,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1609 states to 1609 states and 1964 transitions. [2018-11-18 15:39:09,610 INFO L78 Accepts]: Start accepts. Automaton has 1609 states and 1964 transitions. Word has length 122 [2018-11-18 15:39:09,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:09,610 INFO L480 AbstractCegarLoop]: Abstraction has 1609 states and 1964 transitions. [2018-11-18 15:39:09,610 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:09,610 INFO L276 IsEmpty]: Start isEmpty. Operand 1609 states and 1964 transitions. [2018-11-18 15:39:09,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:09,611 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:09,611 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:09,611 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:09,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:09,612 INFO L82 PathProgramCache]: Analyzing trace with hash 432577284, now seen corresponding path program 1 times [2018-11-18 15:39:09,612 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:09,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:09,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:09,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:09,612 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:09,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:09,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:09,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:09,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:09,673 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:09,673 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:09,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:09,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:09,674 INFO L87 Difference]: Start difference. First operand 1609 states and 1964 transitions. Second operand 5 states. [2018-11-18 15:39:10,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:10,160 INFO L93 Difference]: Finished difference Result 3633 states and 4654 transitions. [2018-11-18 15:39:10,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:10,161 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:10,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:10,166 INFO L225 Difference]: With dead ends: 3633 [2018-11-18 15:39:10,166 INFO L226 Difference]: Without dead ends: 2050 [2018-11-18 15:39:10,169 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:10,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2050 states. [2018-11-18 15:39:10,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2050 to 1808. [2018-11-18 15:39:10,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1808 states. [2018-11-18 15:39:10,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1808 states to 1808 states and 2159 transitions. [2018-11-18 15:39:10,258 INFO L78 Accepts]: Start accepts. Automaton has 1808 states and 2159 transitions. Word has length 122 [2018-11-18 15:39:10,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:10,258 INFO L480 AbstractCegarLoop]: Abstraction has 1808 states and 2159 transitions. [2018-11-18 15:39:10,258 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:10,258 INFO L276 IsEmpty]: Start isEmpty. Operand 1808 states and 2159 transitions. [2018-11-18 15:39:10,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-18 15:39:10,259 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:10,259 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:10,260 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:10,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:10,260 INFO L82 PathProgramCache]: Analyzing trace with hash 800861034, now seen corresponding path program 1 times [2018-11-18 15:39:10,260 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:10,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:10,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:10,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:10,261 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:10,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:10,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:10,318 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:10,318 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:10,318 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:10,319 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:10,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:10,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:10,319 INFO L87 Difference]: Start difference. First operand 1808 states and 2159 transitions. Second operand 5 states. [2018-11-18 15:39:10,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:10,689 INFO L93 Difference]: Finished difference Result 3753 states and 4604 transitions. [2018-11-18 15:39:10,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:39:10,690 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 123 [2018-11-18 15:39:10,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:10,695 INFO L225 Difference]: With dead ends: 3753 [2018-11-18 15:39:10,695 INFO L226 Difference]: Without dead ends: 1968 [2018-11-18 15:39:10,698 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:39:10,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1968 states. [2018-11-18 15:39:10,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1968 to 1738. [2018-11-18 15:39:10,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1738 states. [2018-11-18 15:39:10,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1738 states to 1738 states and 2056 transitions. [2018-11-18 15:39:10,787 INFO L78 Accepts]: Start accepts. Automaton has 1738 states and 2056 transitions. Word has length 123 [2018-11-18 15:39:10,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:10,787 INFO L480 AbstractCegarLoop]: Abstraction has 1738 states and 2056 transitions. [2018-11-18 15:39:10,787 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:10,787 INFO L276 IsEmpty]: Start isEmpty. Operand 1738 states and 2056 transitions. [2018-11-18 15:39:10,788 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:10,788 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:10,789 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:10,789 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:10,789 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:10,789 INFO L82 PathProgramCache]: Analyzing trace with hash 455209538, now seen corresponding path program 1 times [2018-11-18 15:39:10,789 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:10,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:10,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:10,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:10,790 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:10,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:10,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:10,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:10,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:39:10,843 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:10,843 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:39:10,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:39:10,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:39:10,844 INFO L87 Difference]: Start difference. First operand 1738 states and 2056 transitions. Second operand 5 states. [2018-11-18 15:39:11,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:11,260 INFO L93 Difference]: Finished difference Result 3607 states and 4432 transitions. [2018-11-18 15:39:11,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:39:11,261 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 122 [2018-11-18 15:39:11,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:11,265 INFO L225 Difference]: With dead ends: 3607 [2018-11-18 15:39:11,266 INFO L226 Difference]: Without dead ends: 1892 [2018-11-18 15:39:11,268 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:39:11,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1892 states. [2018-11-18 15:39:11,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1892 to 1777. [2018-11-18 15:39:11,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1777 states. [2018-11-18 15:39:11,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1777 states to 1777 states and 2059 transitions. [2018-11-18 15:39:11,358 INFO L78 Accepts]: Start accepts. Automaton has 1777 states and 2059 transitions. Word has length 122 [2018-11-18 15:39:11,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:11,359 INFO L480 AbstractCegarLoop]: Abstraction has 1777 states and 2059 transitions. [2018-11-18 15:39:11,359 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:39:11,359 INFO L276 IsEmpty]: Start isEmpty. Operand 1777 states and 2059 transitions. [2018-11-18 15:39:11,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-11-18 15:39:11,360 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:11,360 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:11,360 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:11,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:11,360 INFO L82 PathProgramCache]: Analyzing trace with hash 1841412932, now seen corresponding path program 1 times [2018-11-18 15:39:11,360 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:11,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:11,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:11,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:11,361 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:11,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:11,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:11,388 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:11,388 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:39:11,389 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:11,389 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:39:11,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:39:11,389 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:39:11,389 INFO L87 Difference]: Start difference. First operand 1777 states and 2059 transitions. Second operand 3 states. [2018-11-18 15:39:11,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:11,567 INFO L93 Difference]: Finished difference Result 5107 states and 5972 transitions. [2018-11-18 15:39:11,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:39:11,568 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 122 [2018-11-18 15:39:11,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:11,578 INFO L225 Difference]: With dead ends: 5107 [2018-11-18 15:39:11,578 INFO L226 Difference]: Without dead ends: 3354 [2018-11-18 15:39:11,582 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:39:11,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3354 states. [2018-11-18 15:39:11,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3354 to 3349. [2018-11-18 15:39:11,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3349 states. [2018-11-18 15:39:11,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3349 states to 3349 states and 3895 transitions. [2018-11-18 15:39:11,857 INFO L78 Accepts]: Start accepts. Automaton has 3349 states and 3895 transitions. Word has length 122 [2018-11-18 15:39:11,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:11,857 INFO L480 AbstractCegarLoop]: Abstraction has 3349 states and 3895 transitions. [2018-11-18 15:39:11,857 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:39:11,857 INFO L276 IsEmpty]: Start isEmpty. Operand 3349 states and 3895 transitions. [2018-11-18 15:39:11,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-18 15:39:11,859 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:11,859 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:11,859 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:11,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:11,859 INFO L82 PathProgramCache]: Analyzing trace with hash -528058497, now seen corresponding path program 1 times [2018-11-18 15:39:11,859 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:11,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:11,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:11,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:11,860 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:11,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:11,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:39:11,908 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:11,909 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:39:11,909 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:11,911 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:39:11,911 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:39:11,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:39:11,911 INFO L87 Difference]: Start difference. First operand 3349 states and 3895 transitions. Second operand 3 states. [2018-11-18 15:39:12,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:12,310 INFO L93 Difference]: Finished difference Result 9858 states and 11927 transitions. [2018-11-18 15:39:12,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:39:12,310 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 123 [2018-11-18 15:39:12,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:12,326 INFO L225 Difference]: With dead ends: 9858 [2018-11-18 15:39:12,326 INFO L226 Difference]: Without dead ends: 6540 [2018-11-18 15:39:12,332 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:39:12,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6540 states. [2018-11-18 15:39:12,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6540 to 6540. [2018-11-18 15:39:12,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6540 states. [2018-11-18 15:39:12,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6540 states to 6540 states and 7788 transitions. [2018-11-18 15:39:12,658 INFO L78 Accepts]: Start accepts. Automaton has 6540 states and 7788 transitions. Word has length 123 [2018-11-18 15:39:12,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:12,658 INFO L480 AbstractCegarLoop]: Abstraction has 6540 states and 7788 transitions. [2018-11-18 15:39:12,658 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:39:12,658 INFO L276 IsEmpty]: Start isEmpty. Operand 6540 states and 7788 transitions. [2018-11-18 15:39:12,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-11-18 15:39:12,660 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:12,660 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:12,660 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:12,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:12,661 INFO L82 PathProgramCache]: Analyzing trace with hash 1194904598, now seen corresponding path program 1 times [2018-11-18 15:39:12,661 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:12,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:12,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:12,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:12,661 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:12,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:12,694 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-18 15:39:12,695 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:12,695 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:39:12,695 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:12,695 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:39:12,695 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:39:12,695 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:39:12,696 INFO L87 Difference]: Start difference. First operand 6540 states and 7788 transitions. Second operand 3 states. [2018-11-18 15:39:13,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:13,366 INFO L93 Difference]: Finished difference Result 17941 states and 21618 transitions. [2018-11-18 15:39:13,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:39:13,367 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 147 [2018-11-18 15:39:13,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:13,385 INFO L225 Difference]: With dead ends: 17941 [2018-11-18 15:39:13,385 INFO L226 Difference]: Without dead ends: 8249 [2018-11-18 15:39:13,400 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:39:13,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8249 states. [2018-11-18 15:39:13,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8249 to 8249. [2018-11-18 15:39:13,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8249 states. [2018-11-18 15:39:13,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8249 states to 8249 states and 9693 transitions. [2018-11-18 15:39:13,865 INFO L78 Accepts]: Start accepts. Automaton has 8249 states and 9693 transitions. Word has length 147 [2018-11-18 15:39:13,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:13,865 INFO L480 AbstractCegarLoop]: Abstraction has 8249 states and 9693 transitions. [2018-11-18 15:39:13,865 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:39:13,866 INFO L276 IsEmpty]: Start isEmpty. Operand 8249 states and 9693 transitions. [2018-11-18 15:39:13,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 220 [2018-11-18 15:39:13,872 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:13,872 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:13,872 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:13,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:13,872 INFO L82 PathProgramCache]: Analyzing trace with hash 136582976, now seen corresponding path program 1 times [2018-11-18 15:39:13,872 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:13,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:13,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:13,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:13,873 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:13,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:13,917 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-11-18 15:39:13,917 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:39:13,917 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:39:13,917 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:13,918 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:39:13,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:39:13,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:13,918 INFO L87 Difference]: Start difference. First operand 8249 states and 9693 transitions. Second operand 4 states. [2018-11-18 15:39:14,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:14,334 INFO L93 Difference]: Finished difference Result 14787 states and 17318 transitions. [2018-11-18 15:39:14,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:39:14,334 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 219 [2018-11-18 15:39:14,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:14,349 INFO L225 Difference]: With dead ends: 14787 [2018-11-18 15:39:14,349 INFO L226 Difference]: Without dead ends: 6562 [2018-11-18 15:39:14,359 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:39:14,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6562 states. [2018-11-18 15:39:14,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6562 to 6366. [2018-11-18 15:39:14,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6366 states. [2018-11-18 15:39:14,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6366 states to 6366 states and 7450 transitions. [2018-11-18 15:39:14,724 INFO L78 Accepts]: Start accepts. Automaton has 6366 states and 7450 transitions. Word has length 219 [2018-11-18 15:39:14,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:14,724 INFO L480 AbstractCegarLoop]: Abstraction has 6366 states and 7450 transitions. [2018-11-18 15:39:14,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:39:14,724 INFO L276 IsEmpty]: Start isEmpty. Operand 6366 states and 7450 transitions. [2018-11-18 15:39:14,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 220 [2018-11-18 15:39:14,728 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:14,728 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:14,728 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:14,728 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:14,728 INFO L82 PathProgramCache]: Analyzing trace with hash 1411506622, now seen corresponding path program 1 times [2018-11-18 15:39:14,728 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:14,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:14,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:14,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:14,729 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:14,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:14,780 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-11-18 15:39:14,780 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:39:14,780 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:39:14,781 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 220 with the following transitions: [2018-11-18 15:39:14,783 INFO L202 CegarAbsIntRunner]: [32], [34], [37], [43], [49], [51], [53], [55], [59], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [562], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:39:14,811 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:39:14,811 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:39:15,002 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:39:15,003 INFO L272 AbstractInterpreter]: Visited 117 different actions 117 times. Never merged. Never widened. Performed 986 root evaluator evaluations with a maximum evaluation depth of 3. Performed 986 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 58 variables. [2018-11-18 15:39:15,007 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:15,007 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:39:15,200 INFO L227 lantSequenceWeakener]: Weakened 125 states. On average, predicates are now at 65.48% of their original sizes. [2018-11-18 15:39:15,200 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:39:15,922 INFO L415 sIntCurrentIteration]: We unified 218 AI predicates to 218 [2018-11-18 15:39:15,922 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:39:15,923 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:39:15,923 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [47] imperfect sequences [3] total 48 [2018-11-18 15:39:15,923 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:15,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-11-18 15:39:15,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-11-18 15:39:15,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=418, Invalid=1744, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 15:39:15,925 INFO L87 Difference]: Start difference. First operand 6366 states and 7450 transitions. Second operand 47 states. [2018-11-18 15:39:21,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:21,919 INFO L93 Difference]: Finished difference Result 12897 states and 15129 transitions. [2018-11-18 15:39:21,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 15:39:21,920 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 219 [2018-11-18 15:39:21,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:21,935 INFO L225 Difference]: With dead ends: 12897 [2018-11-18 15:39:21,935 INFO L226 Difference]: Without dead ends: 6548 [2018-11-18 15:39:21,944 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 250 GetRequests, 173 SyntacticMatches, 0 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1494 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1212, Invalid=4950, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 15:39:21,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6548 states. [2018-11-18 15:39:22,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6548 to 6528. [2018-11-18 15:39:22,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6528 states. [2018-11-18 15:39:22,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6528 states to 6528 states and 7631 transitions. [2018-11-18 15:39:22,485 INFO L78 Accepts]: Start accepts. Automaton has 6528 states and 7631 transitions. Word has length 219 [2018-11-18 15:39:22,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:22,485 INFO L480 AbstractCegarLoop]: Abstraction has 6528 states and 7631 transitions. [2018-11-18 15:39:22,485 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-11-18 15:39:22,485 INFO L276 IsEmpty]: Start isEmpty. Operand 6528 states and 7631 transitions. [2018-11-18 15:39:22,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-11-18 15:39:22,490 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:22,490 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:22,491 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:22,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:22,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1356681699, now seen corresponding path program 1 times [2018-11-18 15:39:22,491 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:22,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:22,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:22,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:22,492 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:22,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:22,561 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 16 proven. 6 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-18 15:39:22,562 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:39:22,562 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:39:22,562 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-11-18 15:39:22,564 INFO L202 CegarAbsIntRunner]: [32], [34], [37], [43], [49], [51], [53], [55], [59], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [559], [562], [566], [572], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:39:22,567 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:39:22,567 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:39:22,663 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:39:22,663 INFO L272 AbstractInterpreter]: Visited 142 different actions 161 times. Merged at 12 different actions 12 times. Never widened. Performed 1438 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1438 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-11-18 15:39:22,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:22,668 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:39:22,880 INFO L227 lantSequenceWeakener]: Weakened 160 states. On average, predicates are now at 69.88% of their original sizes. [2018-11-18 15:39:22,881 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:39:23,873 INFO L415 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-11-18 15:39:23,873 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:39:23,874 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:39:23,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [59] imperfect sequences [4] total 61 [2018-11-18 15:39:23,874 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:23,874 INFO L459 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-11-18 15:39:23,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-11-18 15:39:23,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=733, Invalid=2689, Unknown=0, NotChecked=0, Total=3422 [2018-11-18 15:39:23,876 INFO L87 Difference]: Start difference. First operand 6528 states and 7631 transitions. Second operand 59 states. [2018-11-18 15:39:37,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:37,044 INFO L93 Difference]: Finished difference Result 14517 states and 17081 transitions. [2018-11-18 15:39:37,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-11-18 15:39:37,044 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 221 [2018-11-18 15:39:37,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:37,061 INFO L225 Difference]: With dead ends: 14517 [2018-11-18 15:39:37,061 INFO L226 Difference]: Without dead ends: 8175 [2018-11-18 15:39:37,071 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 259 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2722 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1891, Invalid=7615, Unknown=0, NotChecked=0, Total=9506 [2018-11-18 15:39:37,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8175 states. [2018-11-18 15:39:37,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8175 to 8133. [2018-11-18 15:39:37,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8133 states. [2018-11-18 15:39:37,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8133 states to 8133 states and 9465 transitions. [2018-11-18 15:39:37,545 INFO L78 Accepts]: Start accepts. Automaton has 8133 states and 9465 transitions. Word has length 221 [2018-11-18 15:39:37,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:37,545 INFO L480 AbstractCegarLoop]: Abstraction has 8133 states and 9465 transitions. [2018-11-18 15:39:37,545 INFO L481 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-11-18 15:39:37,545 INFO L276 IsEmpty]: Start isEmpty. Operand 8133 states and 9465 transitions. [2018-11-18 15:39:37,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2018-11-18 15:39:37,551 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:37,551 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:37,551 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:37,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:37,551 INFO L82 PathProgramCache]: Analyzing trace with hash 578923834, now seen corresponding path program 1 times [2018-11-18 15:39:37,552 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:37,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:37,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:37,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:37,552 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:37,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:37,597 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-11-18 15:39:37,597 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:39:37,597 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:39:37,597 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 228 with the following transitions: [2018-11-18 15:39:37,598 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [562], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:39:37,600 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:39:37,600 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:39:37,637 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:39:37,637 INFO L272 AbstractInterpreter]: Visited 127 different actions 127 times. Never merged. Never widened. Performed 1053 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1053 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 58 variables. [2018-11-18 15:39:37,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:37,639 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:39:37,722 INFO L227 lantSequenceWeakener]: Weakened 135 states. On average, predicates are now at 66.56% of their original sizes. [2018-11-18 15:39:37,722 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:39:38,426 INFO L415 sIntCurrentIteration]: We unified 226 AI predicates to 226 [2018-11-18 15:39:38,426 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:39:38,426 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:39:38,426 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [51] imperfect sequences [3] total 52 [2018-11-18 15:39:38,426 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:38,426 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-11-18 15:39:38,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-11-18 15:39:38,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=495, Invalid=2055, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 15:39:38,427 INFO L87 Difference]: Start difference. First operand 8133 states and 9465 transitions. Second operand 51 states. [2018-11-18 15:39:44,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:44,610 INFO L93 Difference]: Finished difference Result 16082 states and 18782 transitions. [2018-11-18 15:39:44,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-18 15:39:44,610 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 227 [2018-11-18 15:39:44,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:44,624 INFO L225 Difference]: With dead ends: 16082 [2018-11-18 15:39:44,624 INFO L226 Difference]: Without dead ends: 8410 [2018-11-18 15:39:44,634 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1718 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1339, Invalid=5467, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 15:39:44,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8410 states. [2018-11-18 15:39:45,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8410 to 8385. [2018-11-18 15:39:45,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8385 states. [2018-11-18 15:39:45,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8385 states to 8385 states and 9750 transitions. [2018-11-18 15:39:45,094 INFO L78 Accepts]: Start accepts. Automaton has 8385 states and 9750 transitions. Word has length 227 [2018-11-18 15:39:45,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:45,094 INFO L480 AbstractCegarLoop]: Abstraction has 8385 states and 9750 transitions. [2018-11-18 15:39:45,094 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-11-18 15:39:45,095 INFO L276 IsEmpty]: Start isEmpty. Operand 8385 states and 9750 transitions. [2018-11-18 15:39:45,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2018-11-18 15:39:45,099 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:45,099 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:45,099 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:45,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:45,099 INFO L82 PathProgramCache]: Analyzing trace with hash -1479489337, now seen corresponding path program 1 times [2018-11-18 15:39:45,099 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:45,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:45,100 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:45,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:45,100 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:45,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:45,155 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 16 proven. 6 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-18 15:39:45,155 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:39:45,155 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:39:45,155 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 229 with the following transitions: [2018-11-18 15:39:45,156 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [562], [566], [572], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:39:45,158 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:39:45,158 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:39:45,206 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:39:45,206 INFO L272 AbstractInterpreter]: Visited 149 different actions 167 times. Merged at 11 different actions 11 times. Never widened. Performed 1486 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1486 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-18 15:39:45,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:45,209 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:39:45,318 INFO L227 lantSequenceWeakener]: Weakened 167 states. On average, predicates are now at 70.3% of their original sizes. [2018-11-18 15:39:45,318 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:39:46,345 INFO L415 sIntCurrentIteration]: We unified 227 AI predicates to 227 [2018-11-18 15:39:46,345 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:39:46,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:39:46,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [63] imperfect sequences [4] total 65 [2018-11-18 15:39:46,346 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:46,346 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-18 15:39:46,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-18 15:39:46,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=640, Invalid=3266, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 15:39:46,347 INFO L87 Difference]: Start difference. First operand 8385 states and 9750 transitions. Second operand 63 states. [2018-11-18 15:39:56,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:39:56,525 INFO L93 Difference]: Finished difference Result 16427 states and 19184 transitions. [2018-11-18 15:39:56,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-11-18 15:39:56,525 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 228 [2018-11-18 15:39:56,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:39:56,543 INFO L225 Difference]: With dead ends: 16427 [2018-11-18 15:39:56,543 INFO L226 Difference]: Without dead ends: 8755 [2018-11-18 15:39:56,556 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 270 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3248 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1745, Invalid=9385, Unknown=0, NotChecked=0, Total=11130 [2018-11-18 15:39:56,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8755 states. [2018-11-18 15:39:57,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8755 to 8666. [2018-11-18 15:39:57,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8666 states. [2018-11-18 15:39:57,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8666 states to 8666 states and 10061 transitions. [2018-11-18 15:39:57,116 INFO L78 Accepts]: Start accepts. Automaton has 8666 states and 10061 transitions. Word has length 228 [2018-11-18 15:39:57,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:39:57,116 INFO L480 AbstractCegarLoop]: Abstraction has 8666 states and 10061 transitions. [2018-11-18 15:39:57,116 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-18 15:39:57,116 INFO L276 IsEmpty]: Start isEmpty. Operand 8666 states and 10061 transitions. [2018-11-18 15:39:57,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2018-11-18 15:39:57,120 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:39:57,120 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:39:57,120 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:39:57,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:57,120 INFO L82 PathProgramCache]: Analyzing trace with hash 1810344003, now seen corresponding path program 1 times [2018-11-18 15:39:57,120 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:39:57,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:57,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:39:57,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:39:57,121 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:39:57,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:39:57,171 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 16 proven. 6 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-18 15:39:57,171 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:39:57,171 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:39:57,171 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 229 with the following transitions: [2018-11-18 15:39:57,172 INFO L202 CegarAbsIntRunner]: [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [73], [79], [81], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [559], [562], [566], [569], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:39:57,174 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:39:57,174 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:39:57,217 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:39:57,217 INFO L272 AbstractInterpreter]: Visited 149 different actions 167 times. Merged at 11 different actions 11 times. Never widened. Performed 1488 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1488 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-18 15:39:57,225 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:39:57,225 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:39:57,329 INFO L227 lantSequenceWeakener]: Weakened 167 states. On average, predicates are now at 70.3% of their original sizes. [2018-11-18 15:39:57,329 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:39:58,248 INFO L415 sIntCurrentIteration]: We unified 227 AI predicates to 227 [2018-11-18 15:39:58,248 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:39:58,248 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:39:58,249 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [63] imperfect sequences [4] total 65 [2018-11-18 15:39:58,249 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:39:58,249 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-18 15:39:58,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-18 15:39:58,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=678, Invalid=3228, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 15:39:58,250 INFO L87 Difference]: Start difference. First operand 8666 states and 10061 transitions. Second operand 63 states. [2018-11-18 15:40:15,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:15,272 INFO L93 Difference]: Finished difference Result 16912 states and 19750 transitions. [2018-11-18 15:40:15,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-18 15:40:15,273 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 228 [2018-11-18 15:40:15,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:15,292 INFO L225 Difference]: With dead ends: 16912 [2018-11-18 15:40:15,292 INFO L226 Difference]: Without dead ends: 9240 [2018-11-18 15:40:15,305 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 270 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3269 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1815, Invalid=9315, Unknown=0, NotChecked=0, Total=11130 [2018-11-18 15:40:15,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9240 states. [2018-11-18 15:40:15,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9240 to 9193. [2018-11-18 15:40:15,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9193 states. [2018-11-18 15:40:15,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9193 states to 9193 states and 10649 transitions. [2018-11-18 15:40:15,933 INFO L78 Accepts]: Start accepts. Automaton has 9193 states and 10649 transitions. Word has length 228 [2018-11-18 15:40:15,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:15,934 INFO L480 AbstractCegarLoop]: Abstraction has 9193 states and 10649 transitions. [2018-11-18 15:40:15,934 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-18 15:40:15,934 INFO L276 IsEmpty]: Start isEmpty. Operand 9193 states and 10649 transitions. [2018-11-18 15:40:15,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 230 [2018-11-18 15:40:15,938 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:15,938 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:15,938 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:15,938 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:15,938 INFO L82 PathProgramCache]: Analyzing trace with hash 119711641, now seen corresponding path program 1 times [2018-11-18 15:40:15,938 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:15,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:15,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:15,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:15,939 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:15,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:16,128 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 17 proven. 6 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-18 15:40:16,128 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:16,128 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:40:16,128 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 230 with the following transitions: [2018-11-18 15:40:16,128 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [559], [566], [572], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:40:16,134 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:40:16,134 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:40:16,284 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:40:16,285 INFO L272 AbstractInterpreter]: Visited 162 different actions 335 times. Merged at 29 different actions 56 times. Never widened. Performed 3599 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3599 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 8 fixpoints after 5 different actions. Largest state had 60 variables. [2018-11-18 15:40:16,286 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:16,287 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:40:16,287 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:16,287 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:40:16,295 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:16,296 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:40:16,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:16,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:40:16,480 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 61 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 15:40:16,480 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:40:16,625 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-18 15:40:16,642 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:40:16,642 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [4] total 6 [2018-11-18 15:40:16,642 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:16,642 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:40:16,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:40:16,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:40:16,643 INFO L87 Difference]: Start difference. First operand 9193 states and 10649 transitions. Second operand 3 states. [2018-11-18 15:40:17,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:17,501 INFO L93 Difference]: Finished difference Result 22952 states and 28208 transitions. [2018-11-18 15:40:17,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:40:17,501 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 229 [2018-11-18 15:40:17,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:17,532 INFO L225 Difference]: With dead ends: 22952 [2018-11-18 15:40:17,532 INFO L226 Difference]: Without dead ends: 15280 [2018-11-18 15:40:17,546 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 464 GetRequests, 458 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:40:17,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15280 states. [2018-11-18 15:40:18,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15280 to 15211. [2018-11-18 15:40:18,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15211 states. [2018-11-18 15:40:18,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15211 states to 15211 states and 18164 transitions. [2018-11-18 15:40:18,423 INFO L78 Accepts]: Start accepts. Automaton has 15211 states and 18164 transitions. Word has length 229 [2018-11-18 15:40:18,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:18,423 INFO L480 AbstractCegarLoop]: Abstraction has 15211 states and 18164 transitions. [2018-11-18 15:40:18,423 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:40:18,423 INFO L276 IsEmpty]: Start isEmpty. Operand 15211 states and 18164 transitions. [2018-11-18 15:40:18,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 232 [2018-11-18 15:40:18,431 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:18,431 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:18,431 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:18,431 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:18,432 INFO L82 PathProgramCache]: Analyzing trace with hash -86749512, now seen corresponding path program 1 times [2018-11-18 15:40:18,432 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:18,432 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:18,432 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:18,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:18,433 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:18,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:18,574 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 18 proven. 2 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-11-18 15:40:18,575 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:18,575 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:40:18,575 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 232 with the following transitions: [2018-11-18 15:40:18,575 INFO L202 CegarAbsIntRunner]: [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [73], [79], [81], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [559], [566], [569], [572], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:40:18,581 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:40:18,582 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:40:18,731 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:40:18,731 INFO L272 AbstractInterpreter]: Visited 162 different actions 312 times. Merged at 29 different actions 46 times. Never widened. Performed 3295 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3295 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 7 fixpoints after 6 different actions. Largest state had 60 variables. [2018-11-18 15:40:18,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:18,737 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:40:18,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:18,737 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:40:18,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:18,752 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:40:18,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:18,852 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:40:18,885 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 60 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 15:40:18,885 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:40:19,114 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-11-18 15:40:19,141 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:40:19,141 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [4] total 6 [2018-11-18 15:40:19,142 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:19,142 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:40:19,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:40:19,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:40:19,142 INFO L87 Difference]: Start difference. First operand 15211 states and 18164 transitions. Second operand 3 states. [2018-11-18 15:40:20,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:20,643 INFO L93 Difference]: Finished difference Result 39615 states and 50939 transitions. [2018-11-18 15:40:20,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:40:20,643 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 231 [2018-11-18 15:40:20,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:20,723 INFO L225 Difference]: With dead ends: 39615 [2018-11-18 15:40:20,723 INFO L226 Difference]: Without dead ends: 25940 [2018-11-18 15:40:20,765 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 466 GetRequests, 462 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:40:20,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25940 states. [2018-11-18 15:40:22,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25940 to 25820. [2018-11-18 15:40:22,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25820 states. [2018-11-18 15:40:22,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25820 states to 25820 states and 32047 transitions. [2018-11-18 15:40:22,428 INFO L78 Accepts]: Start accepts. Automaton has 25820 states and 32047 transitions. Word has length 231 [2018-11-18 15:40:22,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:22,428 INFO L480 AbstractCegarLoop]: Abstraction has 25820 states and 32047 transitions. [2018-11-18 15:40:22,428 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:40:22,428 INFO L276 IsEmpty]: Start isEmpty. Operand 25820 states and 32047 transitions. [2018-11-18 15:40:22,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 240 [2018-11-18 15:40:22,436 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:22,437 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:22,437 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:22,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:22,437 INFO L82 PathProgramCache]: Analyzing trace with hash -663943029, now seen corresponding path program 1 times [2018-11-18 15:40:22,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:22,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:22,437 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:22,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:22,438 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:22,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:22,503 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 35 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-11-18 15:40:22,503 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:40:22,503 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:40:22,503 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:22,504 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:40:22,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:40:22,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:40:22,504 INFO L87 Difference]: Start difference. First operand 25820 states and 32047 transitions. Second operand 3 states. [2018-11-18 15:40:24,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:24,662 INFO L93 Difference]: Finished difference Result 61247 states and 79010 transitions. [2018-11-18 15:40:24,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:40:24,662 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 239 [2018-11-18 15:40:24,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:24,755 INFO L225 Difference]: With dead ends: 61247 [2018-11-18 15:40:24,755 INFO L226 Difference]: Without dead ends: 37062 [2018-11-18 15:40:24,944 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:40:24,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37062 states. [2018-11-18 15:40:27,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37062 to 37047. [2018-11-18 15:40:27,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37047 states. [2018-11-18 15:40:27,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37047 states to 37047 states and 46721 transitions. [2018-11-18 15:40:27,153 INFO L78 Accepts]: Start accepts. Automaton has 37047 states and 46721 transitions. Word has length 239 [2018-11-18 15:40:27,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:27,153 INFO L480 AbstractCegarLoop]: Abstraction has 37047 states and 46721 transitions. [2018-11-18 15:40:27,153 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:40:27,154 INFO L276 IsEmpty]: Start isEmpty. Operand 37047 states and 46721 transitions. [2018-11-18 15:40:27,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2018-11-18 15:40:27,165 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:27,166 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:27,166 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:27,166 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:27,166 INFO L82 PathProgramCache]: Analyzing trace with hash 1752436253, now seen corresponding path program 1 times [2018-11-18 15:40:27,166 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:27,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:27,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:27,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:27,167 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:27,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:27,246 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 17 proven. 6 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-18 15:40:27,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:27,246 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:40:27,246 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 231 with the following transitions: [2018-11-18 15:40:27,247 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [559], [566], [572], [575], [579], [582], [592], [595], [607], [610], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:40:27,248 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:40:27,248 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:40:27,353 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:40:27,354 INFO L272 AbstractInterpreter]: Visited 164 different actions 316 times. Merged at 29 different actions 46 times. Never widened. Performed 3293 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3293 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 8 fixpoints after 7 different actions. Largest state had 60 variables. [2018-11-18 15:40:27,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:27,358 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:40:27,358 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:27,358 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:40:27,364 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:27,364 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:40:27,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:27,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:40:27,492 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:40:27,492 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:40:27,636 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 17 proven. 2 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-11-18 15:40:27,662 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:40:27,662 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-11-18 15:40:27,662 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:27,662 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:40:27,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:40:27,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:40:27,663 INFO L87 Difference]: Start difference. First operand 37047 states and 46721 transitions. Second operand 4 states. [2018-11-18 15:40:30,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:30,861 INFO L93 Difference]: Finished difference Result 70761 states and 95357 transitions. [2018-11-18 15:40:30,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:40:30,862 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 230 [2018-11-18 15:40:30,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:30,988 INFO L225 Difference]: With dead ends: 70761 [2018-11-18 15:40:30,989 INFO L226 Difference]: Without dead ends: 45043 [2018-11-18 15:40:31,054 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 468 GetRequests, 459 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:40:31,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45043 states. [2018-11-18 15:40:34,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45043 to 45016. [2018-11-18 15:40:34,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45016 states. [2018-11-18 15:40:34,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45016 states to 45016 states and 59776 transitions. [2018-11-18 15:40:34,143 INFO L78 Accepts]: Start accepts. Automaton has 45016 states and 59776 transitions. Word has length 230 [2018-11-18 15:40:34,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:34,143 INFO L480 AbstractCegarLoop]: Abstraction has 45016 states and 59776 transitions. [2018-11-18 15:40:34,143 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:40:34,143 INFO L276 IsEmpty]: Start isEmpty. Operand 45016 states and 59776 transitions. [2018-11-18 15:40:34,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 435 [2018-11-18 15:40:34,182 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:34,182 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:34,182 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:34,182 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:34,182 INFO L82 PathProgramCache]: Analyzing trace with hash -1659642113, now seen corresponding path program 1 times [2018-11-18 15:40:34,183 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:34,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:34,183 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:34,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:34,183 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:34,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:34,332 INFO L134 CoverageAnalysis]: Checked inductivity of 461 backedges. 43 proven. 26 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-11-18 15:40:34,332 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:34,332 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:40:34,332 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 435 with the following transitions: [2018-11-18 15:40:34,333 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [126], [128], [131], [135], [136], [137], [140], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [287], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [536], [540], [546], [553], [556], [562], [566], [569], [572], [575], [579], [582], [585], [592], [595], [601], [606], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [642], [644], [649], [657], [660], [665], [670], [674], [675], [678], [679], [680], [681], [682], [684], [685], [686], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [730], [731], [732], [733], [734], [735], [736], [737], [744], [745], [746], [747], [748] [2018-11-18 15:40:34,336 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:40:34,336 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:40:34,447 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:40:34,447 INFO L272 AbstractInterpreter]: Visited 174 different actions 360 times. Merged at 30 different actions 52 times. Never widened. Performed 3687 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3687 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 13 fixpoints after 9 different actions. Largest state had 60 variables. [2018-11-18 15:40:34,453 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:34,453 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:40:34,453 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:34,453 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:40:34,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:34,461 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:40:34,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:34,575 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:40:34,701 INFO L134 CoverageAnalysis]: Checked inductivity of 461 backedges. 260 proven. 0 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2018-11-18 15:40:34,701 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:40:35,147 INFO L134 CoverageAnalysis]: Checked inductivity of 461 backedges. 57 proven. 30 refuted. 0 times theorem prover too weak. 374 trivial. 0 not checked. [2018-11-18 15:40:35,163 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:40:35,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [8, 5] total 12 [2018-11-18 15:40:35,163 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:35,164 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:40:35,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:40:35,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-11-18 15:40:35,164 INFO L87 Difference]: Start difference. First operand 45016 states and 59776 transitions. Second operand 4 states. [2018-11-18 15:40:38,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:38,728 INFO L93 Difference]: Finished difference Result 82671 states and 113992 transitions. [2018-11-18 15:40:38,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:40:38,728 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 434 [2018-11-18 15:40:38,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:38,843 INFO L225 Difference]: With dead ends: 82671 [2018-11-18 15:40:38,843 INFO L226 Difference]: Without dead ends: 49098 [2018-11-18 15:40:38,918 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 880 GetRequests, 860 SyntacticMatches, 9 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-11-18 15:40:38,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49098 states. [2018-11-18 15:40:42,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49098 to 48619. [2018-11-18 15:40:42,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48619 states. [2018-11-18 15:40:42,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48619 states to 48619 states and 66275 transitions. [2018-11-18 15:40:42,504 INFO L78 Accepts]: Start accepts. Automaton has 48619 states and 66275 transitions. Word has length 434 [2018-11-18 15:40:42,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:42,505 INFO L480 AbstractCegarLoop]: Abstraction has 48619 states and 66275 transitions. [2018-11-18 15:40:42,505 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:40:42,505 INFO L276 IsEmpty]: Start isEmpty. Operand 48619 states and 66275 transitions. [2018-11-18 15:40:42,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 442 [2018-11-18 15:40:42,536 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:42,537 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:42,537 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:42,537 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:42,537 INFO L82 PathProgramCache]: Analyzing trace with hash 1715147790, now seen corresponding path program 1 times [2018-11-18 15:40:42,537 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:42,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:42,538 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:42,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:42,538 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:42,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:42,695 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 44 proven. 26 refuted. 0 times theorem prover too weak. 398 trivial. 0 not checked. [2018-11-18 15:40:42,696 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:42,696 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:40:42,696 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 442 with the following transitions: [2018-11-18 15:40:42,696 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [126], [128], [131], [135], [136], [137], [140], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [287], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [536], [540], [546], [553], [556], [562], [566], [569], [572], [579], [582], [585], [592], [595], [601], [606], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [642], [644], [649], [657], [660], [665], [670], [674], [675], [678], [679], [680], [681], [682], [684], [685], [686], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [730], [731], [732], [733], [734], [735], [736], [737], [744], [745], [746], [747], [748] [2018-11-18 15:40:42,699 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:40:42,699 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:40:43,220 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:40:43,220 INFO L272 AbstractInterpreter]: Visited 185 different actions 771 times. Merged at 50 different actions 153 times. Never widened. Performed 7346 root evaluator evaluations with a maximum evaluation depth of 3. Performed 7346 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 36 fixpoints after 16 different actions. Largest state had 60 variables. [2018-11-18 15:40:43,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:43,221 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:40:43,221 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:43,222 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:40:43,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:43,228 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:40:43,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:43,334 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:40:43,403 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 255 proven. 0 refuted. 0 times theorem prover too weak. 213 trivial. 0 not checked. [2018-11-18 15:40:43,403 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:40:43,598 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 49 proven. 12 refuted. 0 times theorem prover too weak. 407 trivial. 0 not checked. [2018-11-18 15:40:43,614 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:40:43,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8, 6] total 12 [2018-11-18 15:40:43,615 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:43,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:40:43,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:40:43,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-11-18 15:40:43,615 INFO L87 Difference]: Start difference. First operand 48619 states and 66275 transitions. Second operand 6 states. [2018-11-18 15:40:45,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:40:45,584 INFO L93 Difference]: Finished difference Result 76260 states and 101698 transitions. [2018-11-18 15:40:45,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:40:45,584 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 441 [2018-11-18 15:40:45,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:40:45,638 INFO L225 Difference]: With dead ends: 76260 [2018-11-18 15:40:45,638 INFO L226 Difference]: Without dead ends: 28037 [2018-11-18 15:40:45,722 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 894 GetRequests, 876 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:40:45,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28037 states. [2018-11-18 15:40:47,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28037 to 25739. [2018-11-18 15:40:47,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25739 states. [2018-11-18 15:40:47,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25739 states to 25739 states and 30435 transitions. [2018-11-18 15:40:47,524 INFO L78 Accepts]: Start accepts. Automaton has 25739 states and 30435 transitions. Word has length 441 [2018-11-18 15:40:47,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:40:47,525 INFO L480 AbstractCegarLoop]: Abstraction has 25739 states and 30435 transitions. [2018-11-18 15:40:47,525 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:40:47,525 INFO L276 IsEmpty]: Start isEmpty. Operand 25739 states and 30435 transitions. [2018-11-18 15:40:47,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 304 [2018-11-18 15:40:47,534 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:40:47,534 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:40:47,534 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:40:47,534 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:47,534 INFO L82 PathProgramCache]: Analyzing trace with hash 1704329150, now seen corresponding path program 1 times [2018-11-18 15:40:47,534 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:40:47,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:47,535 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:40:47,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:40:47,535 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:40:47,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:40:47,618 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 18 proven. 8 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-11-18 15:40:47,618 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:40:47,618 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:40:47,618 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 304 with the following transitions: [2018-11-18 15:40:47,619 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [140], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [287], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [562], [566], [569], [579], [582], [592], [595], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [680], [681], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:40:47,620 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:40:47,620 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:40:47,660 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-18 15:40:47,660 INFO L272 AbstractInterpreter]: Visited 159 different actions 174 times. Merged at 9 different actions 9 times. Never widened. Performed 1523 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1523 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-11-18 15:40:47,661 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:40:47,661 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-18 15:40:47,773 INFO L227 lantSequenceWeakener]: Weakened 182 states. On average, predicates are now at 69.84% of their original sizes. [2018-11-18 15:40:47,773 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-18 15:40:48,782 INFO L415 sIntCurrentIteration]: We unified 302 AI predicates to 302 [2018-11-18 15:40:48,782 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-18 15:40:48,782 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:40:48,783 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [66] imperfect sequences [4] total 68 [2018-11-18 15:40:48,783 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:40:48,783 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-11-18 15:40:48,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-11-18 15:40:48,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=590, Invalid=3700, Unknown=0, NotChecked=0, Total=4290 [2018-11-18 15:40:48,784 INFO L87 Difference]: Start difference. First operand 25739 states and 30435 transitions. Second operand 66 states. [2018-11-18 15:41:00,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:41:00,540 INFO L93 Difference]: Finished difference Result 42644 states and 50400 transitions. [2018-11-18 15:41:00,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 15:41:00,540 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 303 [2018-11-18 15:41:00,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:41:00,580 INFO L225 Difference]: With dead ends: 42644 [2018-11-18 15:41:00,580 INFO L226 Difference]: Without dead ends: 25886 [2018-11-18 15:41:00,603 INFO L604 BasicCegarLoop]: 2 DeclaredPredicates, 349 GetRequests, 238 SyntacticMatches, 0 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3803 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1612, Invalid=11044, Unknown=0, NotChecked=0, Total=12656 [2018-11-18 15:41:00,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25886 states. [2018-11-18 15:41:02,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25886 to 25813. [2018-11-18 15:41:02,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25813 states. [2018-11-18 15:41:02,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25813 states to 25813 states and 30518 transitions. [2018-11-18 15:41:02,069 INFO L78 Accepts]: Start accepts. Automaton has 25813 states and 30518 transitions. Word has length 303 [2018-11-18 15:41:02,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:41:02,070 INFO L480 AbstractCegarLoop]: Abstraction has 25813 states and 30518 transitions. [2018-11-18 15:41:02,070 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-11-18 15:41:02,070 INFO L276 IsEmpty]: Start isEmpty. Operand 25813 states and 30518 transitions. [2018-11-18 15:41:02,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2018-11-18 15:41:02,079 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:41:02,079 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:41:02,079 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:41:02,079 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:02,079 INFO L82 PathProgramCache]: Analyzing trace with hash -1819627996, now seen corresponding path program 1 times [2018-11-18 15:41:02,079 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:41:02,079 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:02,080 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:02,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:02,080 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:41:02,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:02,158 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 19 proven. 8 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-11-18 15:41:02,158 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:02,158 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:41:02,159 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 305 with the following transitions: [2018-11-18 15:41:02,159 INFO L202 CegarAbsIntRunner]: [2], [13], [19], [21], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [140], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [287], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [559], [566], [569], [579], [582], [592], [595], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [678], [679], [680], [681], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:41:02,160 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:41:02,160 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:41:02,341 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:41:02,341 INFO L272 AbstractInterpreter]: Visited 181 different actions 707 times. Merged at 46 different actions 133 times. Never widened. Performed 6624 root evaluator evaluations with a maximum evaluation depth of 3. Performed 6624 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 25 fixpoints after 11 different actions. Largest state had 60 variables. [2018-11-18 15:41:02,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:02,345 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:41:02,345 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:02,345 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:41:02,619 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:02,619 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:41:02,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:02,707 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:41:02,756 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 130 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-11-18 15:41:02,756 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:41:02,887 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 19 proven. 8 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-11-18 15:41:02,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:41:02,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-11-18 15:41:02,903 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:41:02,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:41:02,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:41:02,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:41:02,903 INFO L87 Difference]: Start difference. First operand 25813 states and 30518 transitions. Second operand 4 states. [2018-11-18 15:41:05,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:41:05,280 INFO L93 Difference]: Finished difference Result 56452 states and 68671 transitions. [2018-11-18 15:41:05,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:41:05,280 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 304 [2018-11-18 15:41:05,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:41:05,344 INFO L225 Difference]: With dead ends: 56452 [2018-11-18 15:41:05,345 INFO L226 Difference]: Without dead ends: 35174 [2018-11-18 15:41:05,389 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 616 GetRequests, 609 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:41:05,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35174 states. [2018-11-18 15:41:07,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35174 to 34930. [2018-11-18 15:41:07,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34930 states. [2018-11-18 15:41:07,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34930 states to 34930 states and 42351 transitions. [2018-11-18 15:41:07,765 INFO L78 Accepts]: Start accepts. Automaton has 34930 states and 42351 transitions. Word has length 304 [2018-11-18 15:41:07,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:41:07,766 INFO L480 AbstractCegarLoop]: Abstraction has 34930 states and 42351 transitions. [2018-11-18 15:41:07,766 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:41:07,766 INFO L276 IsEmpty]: Start isEmpty. Operand 34930 states and 42351 transitions. [2018-11-18 15:41:07,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 378 [2018-11-18 15:41:07,779 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:41:07,779 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:41:07,779 INFO L423 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:41:07,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:07,780 INFO L82 PathProgramCache]: Analyzing trace with hash -1544166477, now seen corresponding path program 1 times [2018-11-18 15:41:07,780 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:41:07,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:07,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:07,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:07,780 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:41:07,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:07,891 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 29 proven. 51 refuted. 0 times theorem prover too weak. 287 trivial. 0 not checked. [2018-11-18 15:41:07,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:07,891 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:41:07,892 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 378 with the following transitions: [2018-11-18 15:41:07,892 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [140], [143], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [316], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [559], [562], [566], [569], [575], [579], [582], [588], [592], [595], [598], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [676], [677], [678], [679], [680], [681], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:41:07,893 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:41:07,893 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:41:07,996 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:41:07,996 INFO L272 AbstractInterpreter]: Visited 180 different actions 440 times. Merged at 44 different actions 74 times. Never widened. Performed 3606 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3606 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 15 fixpoints after 11 different actions. Largest state had 60 variables. [2018-11-18 15:41:08,000 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:08,001 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:41:08,001 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:08,001 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:41:08,008 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:08,008 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:41:08,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:08,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:41:08,143 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 223 proven. 0 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-11-18 15:41:08,143 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:41:08,300 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 45 proven. 7 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-11-18 15:41:08,316 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:41:08,317 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5, 3] total 6 [2018-11-18 15:41:08,317 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:41:08,317 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:41:08,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:41:08,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:41:08,318 INFO L87 Difference]: Start difference. First operand 34930 states and 42351 transitions. Second operand 3 states. [2018-11-18 15:41:10,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:41:10,307 INFO L93 Difference]: Finished difference Result 62314 states and 74541 transitions. [2018-11-18 15:41:10,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:41:10,307 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 377 [2018-11-18 15:41:10,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:41:10,353 INFO L225 Difference]: With dead ends: 62314 [2018-11-18 15:41:10,353 INFO L226 Difference]: Without dead ends: 28696 [2018-11-18 15:41:10,411 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 759 GetRequests, 755 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:41:10,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28696 states. [2018-11-18 15:41:12,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28696 to 28236. [2018-11-18 15:41:12,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28236 states. [2018-11-18 15:41:12,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28236 states to 28236 states and 32510 transitions. [2018-11-18 15:41:12,227 INFO L78 Accepts]: Start accepts. Automaton has 28236 states and 32510 transitions. Word has length 377 [2018-11-18 15:41:12,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:41:12,227 INFO L480 AbstractCegarLoop]: Abstraction has 28236 states and 32510 transitions. [2018-11-18 15:41:12,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:41:12,227 INFO L276 IsEmpty]: Start isEmpty. Operand 28236 states and 32510 transitions. [2018-11-18 15:41:12,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 404 [2018-11-18 15:41:12,238 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:41:12,238 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:41:12,238 INFO L423 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:41:12,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:12,239 INFO L82 PathProgramCache]: Analyzing trace with hash 45061871, now seen corresponding path program 1 times [2018-11-18 15:41:12,239 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:41:12,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:12,239 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:12,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:12,239 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:41:12,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:12,323 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 70 proven. 6 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2018-11-18 15:41:12,323 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:12,323 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:41:12,323 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 404 with the following transitions: [2018-11-18 15:41:12,323 INFO L202 CegarAbsIntRunner]: [2], [4], [7], [13], [19], [21], [23], [25], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [140], [143], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [316], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [562], [566], [569], [572], [575], [579], [582], [585], [588], [592], [595], [598], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [676], [677], [678], [679], [680], [681], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:41:12,325 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:41:12,325 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:41:12,654 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:41:12,654 INFO L272 AbstractInterpreter]: Visited 193 different actions 1300 times. Merged at 62 different actions 199 times. Widened at 1 different actions 1 times. Performed 12356 root evaluator evaluations with a maximum evaluation depth of 3. Performed 12356 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 65 fixpoints after 20 different actions. Largest state had 60 variables. [2018-11-18 15:41:12,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:12,656 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:41:12,656 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:12,656 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:41:12,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:12,663 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:41:12,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:12,761 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:41:12,836 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 248 proven. 0 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2018-11-18 15:41:12,836 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:41:13,014 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 65 proven. 14 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2018-11-18 15:41:13,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:41:13,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-11-18 15:41:13,030 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:41:13,030 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:41:13,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:41:13,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:41:13,031 INFO L87 Difference]: Start difference. First operand 28236 states and 32510 transitions. Second operand 4 states. [2018-11-18 15:41:14,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:41:14,336 INFO L93 Difference]: Finished difference Result 41907 states and 47843 transitions. [2018-11-18 15:41:14,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:41:14,336 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 403 [2018-11-18 15:41:14,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:41:14,360 INFO L225 Difference]: With dead ends: 41907 [2018-11-18 15:41:14,360 INFO L226 Difference]: Without dead ends: 11862 [2018-11-18 15:41:14,398 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 812 GetRequests, 805 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:41:14,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11862 states. [2018-11-18 15:41:15,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11862 to 11393. [2018-11-18 15:41:15,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11393 states. [2018-11-18 15:41:15,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11393 states to 11393 states and 12437 transitions. [2018-11-18 15:41:15,127 INFO L78 Accepts]: Start accepts. Automaton has 11393 states and 12437 transitions. Word has length 403 [2018-11-18 15:41:15,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:41:15,128 INFO L480 AbstractCegarLoop]: Abstraction has 11393 states and 12437 transitions. [2018-11-18 15:41:15,128 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:41:15,128 INFO L276 IsEmpty]: Start isEmpty. Operand 11393 states and 12437 transitions. [2018-11-18 15:41:15,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 379 [2018-11-18 15:41:15,135 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:41:15,135 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:41:15,135 INFO L423 AbstractCegarLoop]: === Iteration 45 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:41:15,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:15,136 INFO L82 PathProgramCache]: Analyzing trace with hash 832600203, now seen corresponding path program 1 times [2018-11-18 15:41:15,136 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:41:15,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:15,136 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:15,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:15,136 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:41:15,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:15,324 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 30 proven. 51 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-11-18 15:41:15,324 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:15,324 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-18 15:41:15,325 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 379 with the following transitions: [2018-11-18 15:41:15,325 INFO L202 CegarAbsIntRunner]: [4], [7], [13], [19], [21], [23], [25], [29], [32], [34], [37], [43], [49], [51], [53], [55], [59], [62], [64], [67], [73], [79], [81], [83], [85], [89], [92], [94], [97], [103], [109], [111], [117], [118], [123], [137], [140], [143], [145], [147], [149], [151], [152], [157], [163], [169], [175], [181], [187], [193], [199], [205], [207], [208], [218], [220], [222], [223], [279], [282], [285], [289], [291], [293], [294], [295], [297], [302], [305], [310], [313], [316], [318], [321], [324], [326], [329], [332], [334], [336], [338], [339], [342], [366], [367], [372], [378], [384], [390], [396], [402], [408], [414], [420], [422], [423], [426], [431], [433], [435], [437], [438], [441], [447], [453], [459], [465], [469], [516], [517], [518], [522], [528], [531], [534], [540], [546], [553], [556], [559], [562], [566], [569], [575], [579], [582], [585], [592], [595], [598], [607], [610], [613], [615], [617], [619], [621], [622], [623], [632], [638], [640], [670], [674], [675], [676], [677], [678], [679], [680], [681], [682], [684], [685], [686], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [704], [705], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [746], [747], [748] [2018-11-18 15:41:15,326 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-18 15:41:15,326 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-18 15:41:15,554 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-18 15:41:15,554 INFO L272 AbstractInterpreter]: Visited 175 different actions 482 times. Merged at 29 different actions 76 times. Never widened. Performed 5847 root evaluator evaluations with a maximum evaluation depth of 3. Performed 5847 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 19 fixpoints after 8 different actions. Largest state had 60 variables. [2018-11-18 15:41:15,565 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:15,565 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-18 15:41:15,565 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:41:15,565 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:41:15,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:15,573 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-18 15:41:15,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:41:15,675 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:41:15,755 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 249 proven. 47 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2018-11-18 15:41:15,755 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-18 15:41:15,924 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 339 trivial. 0 not checked. [2018-11-18 15:41:15,949 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:41:15,949 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2018-11-18 15:41:15,949 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-18 15:41:15,949 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:41:15,949 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:41:15,949 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:41:15,950 INFO L87 Difference]: Start difference. First operand 11393 states and 12437 transitions. Second operand 5 states. [2018-11-18 15:41:16,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:41:16,721 INFO L93 Difference]: Finished difference Result 14594 states and 15922 transitions. [2018-11-18 15:41:16,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:41:16,722 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 378 [2018-11-18 15:41:16,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:41:16,729 INFO L225 Difference]: With dead ends: 14594 [2018-11-18 15:41:16,730 INFO L226 Difference]: Without dead ends: 4034 [2018-11-18 15:41:16,738 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 761 GetRequests, 749 SyntacticMatches, 5 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:41:16,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4034 states. [2018-11-18 15:41:17,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4034 to 3975. [2018-11-18 15:41:17,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3975 states. [2018-11-18 15:41:17,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3975 states to 3975 states and 4330 transitions. [2018-11-18 15:41:17,040 INFO L78 Accepts]: Start accepts. Automaton has 3975 states and 4330 transitions. Word has length 378 [2018-11-18 15:41:17,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:41:17,040 INFO L480 AbstractCegarLoop]: Abstraction has 3975 states and 4330 transitions. [2018-11-18 15:41:17,040 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:41:17,040 INFO L276 IsEmpty]: Start isEmpty. Operand 3975 states and 4330 transitions. [2018-11-18 15:41:17,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 456 [2018-11-18 15:41:17,044 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:41:17,044 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:41:17,044 INFO L423 AbstractCegarLoop]: === Iteration 46 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:41:17,045 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:41:17,045 INFO L82 PathProgramCache]: Analyzing trace with hash 1551912580, now seen corresponding path program 1 times [2018-11-18 15:41:17,045 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-18 15:41:17,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:17,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:41:17,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:41:17,046 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-18 15:41:17,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:41:17,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:41:17,198 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 15:41:17,344 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 03:41:17 BoogieIcfgContainer [2018-11-18 15:41:17,344 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 15:41:17,345 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:41:17,345 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:41:17,345 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:41:17,345 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:39:01" (3/4) ... [2018-11-18 15:41:17,347 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 15:41:17,497 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_2c7d5567-f197-4685-a499-e149e8cd0eec/bin-2019/utaipan/witness.graphml [2018-11-18 15:41:17,497 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:41:17,499 INFO L168 Benchmark]: Toolchain (without parser) took 137139.33 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.6 GB). Free memory was 959.8 MB in the beginning and 2.0 GB in the end (delta: -1.0 GB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. [2018-11-18 15:41:17,500 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:41:17,500 INFO L168 Benchmark]: CACSL2BoogieTranslator took 242.83 ms. Allocated memory is still 1.0 GB. Free memory was 959.8 MB in the beginning and 941.0 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-18 15:41:17,500 INFO L168 Benchmark]: Boogie Procedure Inliner took 53.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 151.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -205.7 MB). Peak memory consumption was 14.6 MB. Max. memory is 11.5 GB. [2018-11-18 15:41:17,501 INFO L168 Benchmark]: Boogie Preprocessor took 30.19 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:41:17,501 INFO L168 Benchmark]: RCFGBuilder took 531.26 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.3 MB). Peak memory consumption was 51.3 MB. Max. memory is 11.5 GB. [2018-11-18 15:41:17,501 INFO L168 Benchmark]: TraceAbstraction took 136125.37 ms. Allocated memory was 1.2 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: -961.7 MB). Peak memory consumption was 2.5 GB. Max. memory is 11.5 GB. [2018-11-18 15:41:17,501 INFO L168 Benchmark]: Witness Printer took 152.56 ms. Allocated memory is still 4.6 GB. Free memory was 2.1 GB in the beginning and 2.0 GB in the end (delta: 65.2 MB). Peak memory consumption was 65.2 MB. Max. memory is 11.5 GB. [2018-11-18 15:41:17,504 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 242.83 ms. Allocated memory is still 1.0 GB. Free memory was 959.8 MB in the beginning and 941.0 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 53.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 151.5 MB). Free memory was 941.0 MB in the beginning and 1.1 GB in the end (delta: -205.7 MB). Peak memory consumption was 14.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 30.19 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 531.26 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.3 MB). Peak memory consumption was 51.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 136125.37 ms. Allocated memory was 1.2 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: -961.7 MB). Peak memory consumption was 2.5 GB. Max. memory is 11.5 GB. * Witness Printer took 152.56 ms. Allocated memory is still 4.6 GB. Free memory was 2.1 GB in the beginning and 2.0 GB in the end (delta: 65.2 MB). Peak memory consumption was 65.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [\old(E_1)=21, \old(E_2)=5, \old(E_3)=25, \old(E_4)=11, \old(M_E)=17, \old(m_i)=7, \old(m_pc)=15, \old(m_st)=16, \old(T1_E)=3, \old(t1_i)=19, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=18, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=13, \old(T3_E)=23, \old(t3_i)=24, \old(t3_pc)=8, \old(t3_st)=14, \old(T4_E)=26, \old(t4_i)=20, \old(t4_pc)=22, \old(t4_st)=12, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L815] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] RET t4_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L815] init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L816] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L759] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] RET t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE, RET !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L762] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE, RET !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L762] activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE, RET !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L397] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L431] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] RET t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L445] transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] RET t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L473] transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L425] COND FALSE !(t1_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L439] COND FALSE !(t2_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L173] t3_pc = 1 [L174] RET t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L459] transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND FALSE !(t4_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L417] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE, RET !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] RET m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L417] master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE, RET !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L431] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE, RET !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] RET t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L445] transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L180] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] RET t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L180] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] RET t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L459] transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L214] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 27 procedures, 237 locations, 1 error locations. UNSAFE Result, 136.0s OverallTime, 46 OverallIterations, 6 TraceHistogramMax, 94.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 16192 SDtfs, 23704 SDslu, 46248 SDs, 0 SdLazy, 28620 SolverSat, 6263 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 20.3s Time, PredicateUnifierStatistics: 12 DeclaredPredicates, 8026 GetRequests, 7208 SyntacticMatches, 70 SemanticMatches, 748 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16351 ImplicationChecksByTransitivity, 11.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=48619occurred in iteration=39, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 2.4s AbstIntTime, 15 AbstIntIterations, 6 AbstIntStrong, 0.993785550844147 AbsIntWeakeningRatio, 0.5880281690140845 AbsIntAvgWeakeningVarsNumRemoved, 18.862676056338028 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 25.0s AutomataMinimizationTime, 45 MinimizatonAttempts, 6281 StatesRemovedByMinimization, 39 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 4.5s InterpolantComputationTime, 11836 NumberOfCodeBlocks, 11836 NumberOfCodeBlocksAsserted, 55 NumberOfCheckSat, 14345 ConstructedInterpolants, 0 QuantifiedInterpolants, 5265305 SizeOfPredicates, 11 NumberOfNonLiveVariables, 12758 ConjunctsInSsa, 48 ConjunctsInUnsatCore, 63 InterpolantComputations, 41 PerfectInterpolantSequences, 7930/8262 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...