./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-linux-3.16-rc1/205_9a_array_unsafes_linux-3.16-rc1.tar.xz-205_9a-drivers--net--ethernet--qlogic--qlge--qlge.ko-entry_point_false-unreach-call.cil.out.c --full-output --architecture 64bit


--------------------------------------------------------------------------------


Checking for ERROR reachability
Using default analysis
Version aa418289
Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_ff4caff4-f788-441d-aef2-47fbc52dd901/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_ff4caff4-f788-441d-aef2-47fbc52dd901/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_ff4caff4-f788-441d-aef2-47fbc52dd901/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_ff4caff4-f788-441d-aef2-47fbc52dd901/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-linux-3.16-rc1/205_9a_array_unsafes_linux-3.16-rc1.tar.xz-205_9a-drivers--net--ethernet--qlogic--qlge--qlge.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_ff4caff4-f788-441d-aef2-47fbc52dd901/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_ff4caff4-f788-441d-aef2-47fbc52dd901/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) )

 --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 6f26be61a4c80cdef40a191449117e5b2a95fe37
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................