./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/product-lines/email_spec27_product19_false-unreach-call_true-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_67fb1bb9-c1c5-4b58-bac3-a0f28aeb2c8e/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_67fb1bb9-c1c5-4b58-bac3-a0f28aeb2c8e/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_67fb1bb9-c1c5-4b58-bac3-a0f28aeb2c8e/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_67fb1bb9-c1c5-4b58-bac3-a0f28aeb2c8e/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/product-lines/email_spec27_product19_false-unreach-call_true-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_67fb1bb9-c1c5-4b58-bac3-a0f28aeb2c8e/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_67fb1bb9-c1c5-4b58-bac3-a0f28aeb2c8e/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4369547c44b7eb28808cd1c850f66fe8995f8d12 ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................