./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i -s /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a69112b8d023c6203418abb04301ebe890b3a5f5 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i -s /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a69112b8d023c6203418abb04301ebe890b3a5f5 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: TRUE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 02:57:33,612 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 02:57:33,613 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 02:57:33,621 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 02:57:33,622 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 02:57:33,622 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 02:57:33,623 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 02:57:33,624 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 02:57:33,625 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 02:57:33,626 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 02:57:33,627 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 02:57:33,627 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 02:57:33,628 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 02:57:33,628 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 02:57:33,629 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 02:57:33,630 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 02:57:33,630 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 02:57:33,631 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 02:57:33,633 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 02:57:33,634 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 02:57:33,635 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 02:57:33,635 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 02:57:33,637 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 02:57:33,637 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 02:57:33,638 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 02:57:33,638 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 02:57:33,639 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 02:57:33,640 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 02:57:33,640 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 02:57:33,641 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 02:57:33,641 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 02:57:33,642 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 02:57:33,642 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 02:57:33,642 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 02:57:33,643 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 02:57:33,643 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 02:57:33,643 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-23 02:57:33,654 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 02:57:33,654 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 02:57:33,655 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 02:57:33,655 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 02:57:33,655 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 02:57:33,655 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 02:57:33,655 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 02:57:33,655 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-23 02:57:33,656 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 02:57:33,656 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 02:57:33,656 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-23 02:57:33,656 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-23 02:57:33,656 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 02:57:33,657 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 02:57:33,657 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 02:57:33,657 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 02:57:33,657 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 02:57:33,657 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 02:57:33,658 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 02:57:33,659 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 02:57:33,659 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 02:57:33,659 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 02:57:33,659 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 02:57:33,659 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 02:57:33,659 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 02:57:33,659 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 02:57:33,660 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 02:57:33,660 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-23 02:57:33,660 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 02:57:33,660 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 02:57:33,660 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 02:57:33,660 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a69112b8d023c6203418abb04301ebe890b3a5f5 [2018-11-23 02:57:33,687 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 02:57:33,695 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 02:57:33,697 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 02:57:33,698 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 02:57:33,699 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 02:57:33,699 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 02:57:33,737 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/dd73e1960/d3dc7eefc2794d3bac0d688db7e368e0/FLAGa1a13d148 [2018-11-23 02:57:34,145 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 02:57:34,145 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 02:57:34,150 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/dd73e1960/d3dc7eefc2794d3bac0d688db7e368e0/FLAGa1a13d148 [2018-11-23 02:57:34,159 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/dd73e1960/d3dc7eefc2794d3bac0d688db7e368e0 [2018-11-23 02:57:34,161 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 02:57:34,162 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 02:57:34,162 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 02:57:34,162 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 02:57:34,165 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 02:57:34,165 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,167 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@64d4648b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34, skipping insertion in model container [2018-11-23 02:57:34,168 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,176 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 02:57:34,195 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 02:57:34,334 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 02:57:34,337 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 02:57:34,349 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 02:57:34,358 INFO L195 MainTranslator]: Completed translation [2018-11-23 02:57:34,358 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34 WrapperNode [2018-11-23 02:57:34,358 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 02:57:34,359 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 02:57:34,359 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 02:57:34,359 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 02:57:34,364 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,368 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,372 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 02:57:34,372 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 02:57:34,372 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 02:57:34,372 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 02:57:34,378 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,378 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,378 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,379 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,382 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,420 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,421 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... [2018-11-23 02:57:34,422 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 02:57:34,422 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 02:57:34,422 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 02:57:34,422 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 02:57:34,423 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 02:57:34,460 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 02:57:34,460 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 02:57:34,460 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 02:57:34,460 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 02:57:34,461 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 02:57:34,461 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 02:57:34,461 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 02:57:34,461 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 02:57:34,546 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 02:57:34,547 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-23 02:57:34,547 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:57:34 BoogieIcfgContainer [2018-11-23 02:57:34,547 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 02:57:34,548 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 02:57:34,548 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 02:57:34,549 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 02:57:34,550 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 02:57:34" (1/3) ... [2018-11-23 02:57:34,550 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7a515927 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:57:34, skipping insertion in model container [2018-11-23 02:57:34,550 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:34" (2/3) ... [2018-11-23 02:57:34,550 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7a515927 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:57:34, skipping insertion in model container [2018-11-23 02:57:34,551 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:57:34" (3/3) ... [2018-11-23 02:57:34,552 INFO L112 eAbstractionObserver]: Analyzing ICFG interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 02:57:34,557 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 02:57:34,561 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 02:57:34,570 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 02:57:34,589 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 02:57:34,589 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 02:57:34,589 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 02:57:34,589 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 02:57:34,589 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 02:57:34,589 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 02:57:34,590 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 02:57:34,590 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 02:57:34,599 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states. [2018-11-23 02:57:34,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-23 02:57:34,602 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:34,603 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:34,604 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:34,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:34,607 INFO L82 PathProgramCache]: Analyzing trace with hash -480905734, now seen corresponding path program 1 times [2018-11-23 02:57:34,608 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:34,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:34,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:34,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:34,645 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:34,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:34,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:34,734 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 02:57:34,734 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 02:57:34,734 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 02:57:34,737 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 02:57:34,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 02:57:34,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 02:57:34,750 INFO L87 Difference]: Start difference. First operand 18 states. Second operand 3 states. [2018-11-23 02:57:34,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:34,770 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2018-11-23 02:57:34,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 02:57:34,771 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-11-23 02:57:34,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:34,776 INFO L225 Difference]: With dead ends: 31 [2018-11-23 02:57:34,776 INFO L226 Difference]: Without dead ends: 13 [2018-11-23 02:57:34,778 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 02:57:34,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-11-23 02:57:34,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-11-23 02:57:34,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-11-23 02:57:34,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-11-23 02:57:34,804 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 11 [2018-11-23 02:57:34,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:34,805 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-11-23 02:57:34,805 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 02:57:34,805 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-11-23 02:57:34,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 02:57:34,806 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:34,806 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:34,806 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:34,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:34,806 INFO L82 PathProgramCache]: Analyzing trace with hash -436122843, now seen corresponding path program 1 times [2018-11-23 02:57:34,806 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:34,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:34,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:34,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:34,808 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:34,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:34,871 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:34,871 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:34,871 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:34,872 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-11-23 02:57:34,874 INFO L202 CegarAbsIntRunner]: [0], [4], [11], [13], [17], [20], [23], [25], [31], [32], [33], [35] [2018-11-23 02:57:34,897 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 02:57:34,897 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 02:57:34,988 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-11-23 02:57:34,989 INFO L272 AbstractInterpreter]: Visited 12 different actions 16 times. Merged at 1 different actions 2 times. Never widened. Performed 40 root evaluator evaluations with a maximum evaluation depth of 5. Performed 40 inverse root evaluator evaluations with a maximum inverse evaluation depth of 5. Found 1 fixpoints after 1 different actions. Largest state had 9 variables. [2018-11-23 02:57:34,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:34,997 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-11-23 02:57:34,997 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:34,997 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:35,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:35,004 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 02:57:35,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:35,020 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:35,047 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,047 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:35,078 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,094 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:35,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2018-11-23 02:57:35,094 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:35,095 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 02:57:35,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 02:57:35,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 02:57:35,095 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 5 states. [2018-11-23 02:57:35,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:35,113 INFO L93 Difference]: Finished difference Result 20 states and 20 transitions. [2018-11-23 02:57:35,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 02:57:35,115 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-11-23 02:57:35,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:35,115 INFO L225 Difference]: With dead ends: 20 [2018-11-23 02:57:35,115 INFO L226 Difference]: Without dead ends: 14 [2018-11-23 02:57:35,116 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 21 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 02:57:35,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-11-23 02:57:35,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-11-23 02:57:35,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-23 02:57:35,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2018-11-23 02:57:35,119 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 12 [2018-11-23 02:57:35,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:35,120 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2018-11-23 02:57:35,120 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 02:57:35,120 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2018-11-23 02:57:35,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-23 02:57:35,120 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:35,120 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:35,121 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:35,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:35,121 INFO L82 PathProgramCache]: Analyzing trace with hash 952146778, now seen corresponding path program 2 times [2018-11-23 02:57:35,121 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:35,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:35,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,122 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:35,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:35,205 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,205 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,205 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:35,206 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:35,206 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:35,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,206 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:35,213 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:35,213 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-23 02:57:35,221 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-23 02:57:35,222 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:35,222 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:35,249 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,250 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:35,282 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,296 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:35,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2018-11-23 02:57:35,296 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:35,297 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 02:57:35,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 02:57:35,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-11-23 02:57:35,297 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand 6 states. [2018-11-23 02:57:35,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:35,310 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-11-23 02:57:35,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 02:57:35,310 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 13 [2018-11-23 02:57:35,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:35,310 INFO L225 Difference]: With dead ends: 21 [2018-11-23 02:57:35,311 INFO L226 Difference]: Without dead ends: 15 [2018-11-23 02:57:35,311 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 22 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-11-23 02:57:35,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2018-11-23 02:57:35,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2018-11-23 02:57:35,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-23 02:57:35,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-11-23 02:57:35,314 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 13 [2018-11-23 02:57:35,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:35,314 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-11-23 02:57:35,314 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 02:57:35,314 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-11-23 02:57:35,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-23 02:57:35,314 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:35,315 INFO L402 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:35,315 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:35,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:35,315 INFO L82 PathProgramCache]: Analyzing trace with hash 1038832069, now seen corresponding path program 3 times [2018-11-23 02:57:35,315 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:35,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,316 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:35,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,316 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:35,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:35,393 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,393 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,394 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:35,394 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:35,394 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:35,394 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,394 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:35,405 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:57:35,405 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-23 02:57:35,418 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:57:35,418 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:35,419 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:35,446 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,446 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:35,508 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,523 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:35,523 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2018-11-23 02:57:35,524 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:35,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 02:57:35,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 02:57:35,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=67, Unknown=0, NotChecked=0, Total=110 [2018-11-23 02:57:35,524 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 7 states. [2018-11-23 02:57:35,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:35,552 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2018-11-23 02:57:35,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 02:57:35,552 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 14 [2018-11-23 02:57:35,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:35,553 INFO L225 Difference]: With dead ends: 22 [2018-11-23 02:57:35,553 INFO L226 Difference]: Without dead ends: 16 [2018-11-23 02:57:35,553 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=67, Unknown=0, NotChecked=0, Total=110 [2018-11-23 02:57:35,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-11-23 02:57:35,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-11-23 02:57:35,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 02:57:35,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-11-23 02:57:35,555 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 14 [2018-11-23 02:57:35,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:35,555 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-11-23 02:57:35,555 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 02:57:35,555 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-11-23 02:57:35,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 02:57:35,555 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:35,556 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:35,556 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:35,556 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:35,556 INFO L82 PathProgramCache]: Analyzing trace with hash -568891206, now seen corresponding path program 4 times [2018-11-23 02:57:35,556 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:35,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,557 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:35,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,557 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:35,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:35,623 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,623 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,623 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:35,623 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:35,624 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:35,624 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,624 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:35,634 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:35,634 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 02:57:35,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:35,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:35,681 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,681 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:35,759 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,783 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:35,783 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2018-11-23 02:57:35,783 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:35,783 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 02:57:35,783 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 02:57:35,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2018-11-23 02:57:35,784 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 8 states. [2018-11-23 02:57:35,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:35,807 INFO L93 Difference]: Finished difference Result 23 states and 23 transitions. [2018-11-23 02:57:35,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 02:57:35,808 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 15 [2018-11-23 02:57:35,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:35,808 INFO L225 Difference]: With dead ends: 23 [2018-11-23 02:57:35,808 INFO L226 Difference]: Without dead ends: 17 [2018-11-23 02:57:35,809 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 24 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2018-11-23 02:57:35,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2018-11-23 02:57:35,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2018-11-23 02:57:35,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-23 02:57:35,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 17 transitions. [2018-11-23 02:57:35,811 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 17 transitions. Word has length 15 [2018-11-23 02:57:35,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:35,811 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 17 transitions. [2018-11-23 02:57:35,812 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 02:57:35,812 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 17 transitions. [2018-11-23 02:57:35,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 02:57:35,812 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:35,812 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:35,812 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:35,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:35,813 INFO L82 PathProgramCache]: Analyzing trace with hash 1131294821, now seen corresponding path program 5 times [2018-11-23 02:57:35,813 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:35,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:35,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:35,814 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:35,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:35,891 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,891 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:35,891 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:35,891 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:35,891 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:35,892 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:35,898 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:35,898 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-23 02:57:35,913 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-11-23 02:57:35,913 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:35,914 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:35,931 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:35,931 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:36,039 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,053 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:36,054 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2018-11-23 02:57:36,054 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:36,054 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 02:57:36,054 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 02:57:36,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=135, Unknown=0, NotChecked=0, Total=210 [2018-11-23 02:57:36,054 INFO L87 Difference]: Start difference. First operand 17 states and 17 transitions. Second operand 9 states. [2018-11-23 02:57:36,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:36,085 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-11-23 02:57:36,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 02:57:36,085 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 16 [2018-11-23 02:57:36,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:36,086 INFO L225 Difference]: With dead ends: 24 [2018-11-23 02:57:36,086 INFO L226 Difference]: Without dead ends: 18 [2018-11-23 02:57:36,086 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 25 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=75, Invalid=135, Unknown=0, NotChecked=0, Total=210 [2018-11-23 02:57:36,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-11-23 02:57:36,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-11-23 02:57:36,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-23 02:57:36,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-11-23 02:57:36,088 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 16 [2018-11-23 02:57:36,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:36,089 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-11-23 02:57:36,089 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 02:57:36,089 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-11-23 02:57:36,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-23 02:57:36,089 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:36,090 INFO L402 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:36,090 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:36,090 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:36,090 INFO L82 PathProgramCache]: Analyzing trace with hash -1997513190, now seen corresponding path program 6 times [2018-11-23 02:57:36,090 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:36,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:36,091 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:36,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:36,091 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:36,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:36,173 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,174 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:36,174 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:36,174 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:36,174 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:36,174 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:36,174 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:36,183 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:57:36,183 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-23 02:57:36,190 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:57:36,190 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:36,192 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:36,217 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,218 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:36,339 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:36,354 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 17 [2018-11-23 02:57:36,354 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:36,355 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 02:57:36,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 02:57:36,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=178, Unknown=0, NotChecked=0, Total=272 [2018-11-23 02:57:36,355 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 10 states. [2018-11-23 02:57:36,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:36,381 INFO L93 Difference]: Finished difference Result 25 states and 25 transitions. [2018-11-23 02:57:36,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 02:57:36,381 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 17 [2018-11-23 02:57:36,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:36,382 INFO L225 Difference]: With dead ends: 25 [2018-11-23 02:57:36,382 INFO L226 Difference]: Without dead ends: 19 [2018-11-23 02:57:36,383 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 26 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=94, Invalid=178, Unknown=0, NotChecked=0, Total=272 [2018-11-23 02:57:36,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-11-23 02:57:36,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-11-23 02:57:36,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-23 02:57:36,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 19 transitions. [2018-11-23 02:57:36,385 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 19 transitions. Word has length 17 [2018-11-23 02:57:36,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:36,385 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 19 transitions. [2018-11-23 02:57:36,386 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 02:57:36,386 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 19 transitions. [2018-11-23 02:57:36,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-23 02:57:36,386 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:36,386 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:36,387 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:36,387 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:36,387 INFO L82 PathProgramCache]: Analyzing trace with hash -206313723, now seen corresponding path program 7 times [2018-11-23 02:57:36,387 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:36,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:36,388 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:36,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:36,389 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:36,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:36,474 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,474 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:36,474 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:36,474 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:36,474 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:36,475 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:36,475 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:36,488 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:36,488 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 02:57:36,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:36,497 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:36,548 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,548 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:36,709 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,723 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:36,723 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 19 [2018-11-23 02:57:36,723 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:36,724 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 02:57:36,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 02:57:36,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=227, Unknown=0, NotChecked=0, Total=342 [2018-11-23 02:57:36,724 INFO L87 Difference]: Start difference. First operand 19 states and 19 transitions. Second operand 11 states. [2018-11-23 02:57:36,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:36,761 INFO L93 Difference]: Finished difference Result 26 states and 26 transitions. [2018-11-23 02:57:36,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 02:57:36,762 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 18 [2018-11-23 02:57:36,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:36,762 INFO L225 Difference]: With dead ends: 26 [2018-11-23 02:57:36,762 INFO L226 Difference]: Without dead ends: 20 [2018-11-23 02:57:36,763 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 27 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=227, Unknown=0, NotChecked=0, Total=342 [2018-11-23 02:57:36,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-11-23 02:57:36,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-11-23 02:57:36,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 02:57:36,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 20 transitions. [2018-11-23 02:57:36,765 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 20 transitions. Word has length 18 [2018-11-23 02:57:36,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:36,765 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 20 transitions. [2018-11-23 02:57:36,766 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 02:57:36,766 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 20 transitions. [2018-11-23 02:57:36,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 02:57:36,766 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:36,766 INFO L402 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:36,766 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:36,767 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:36,767 INFO L82 PathProgramCache]: Analyzing trace with hash -513705094, now seen corresponding path program 8 times [2018-11-23 02:57:36,767 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:36,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:36,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:36,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:36,768 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:36,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:36,850 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,850 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:36,851 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:36,851 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:36,851 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:36,851 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:36,851 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:36,857 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:36,857 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-23 02:57:36,872 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-11-23 02:57:36,872 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:36,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:36,887 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:36,887 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:37,035 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,050 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:37,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 21 [2018-11-23 02:57:37,050 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:37,050 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 02:57:37,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 02:57:37,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=284, Unknown=0, NotChecked=0, Total=420 [2018-11-23 02:57:37,051 INFO L87 Difference]: Start difference. First operand 20 states and 20 transitions. Second operand 12 states. [2018-11-23 02:57:37,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:37,095 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-11-23 02:57:37,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 02:57:37,095 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 19 [2018-11-23 02:57:37,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:37,096 INFO L225 Difference]: With dead ends: 27 [2018-11-23 02:57:37,096 INFO L226 Difference]: Without dead ends: 21 [2018-11-23 02:57:37,096 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 28 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=136, Invalid=284, Unknown=0, NotChecked=0, Total=420 [2018-11-23 02:57:37,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2018-11-23 02:57:37,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2018-11-23 02:57:37,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 02:57:37,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-11-23 02:57:37,099 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 19 [2018-11-23 02:57:37,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:37,099 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-11-23 02:57:37,099 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 02:57:37,099 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-11-23 02:57:37,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-11-23 02:57:37,100 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:37,100 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:37,100 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:37,100 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:37,100 INFO L82 PathProgramCache]: Analyzing trace with hash -1452903003, now seen corresponding path program 9 times [2018-11-23 02:57:37,100 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:37,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:37,101 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:37,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:37,101 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:37,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:37,188 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,188 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:37,188 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:37,189 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:37,189 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:37,189 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:37,189 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:37,197 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:57:37,198 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-23 02:57:37,211 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:57:37,211 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:37,213 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:37,247 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,247 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:37,402 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,417 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:37,417 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 23 [2018-11-23 02:57:37,417 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:37,417 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 02:57:37,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 02:57:37,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=352, Unknown=0, NotChecked=0, Total=506 [2018-11-23 02:57:37,418 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 13 states. [2018-11-23 02:57:37,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:37,469 INFO L93 Difference]: Finished difference Result 28 states and 28 transitions. [2018-11-23 02:57:37,469 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 02:57:37,469 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 20 [2018-11-23 02:57:37,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:37,469 INFO L225 Difference]: With dead ends: 28 [2018-11-23 02:57:37,470 INFO L226 Difference]: Without dead ends: 22 [2018-11-23 02:57:37,470 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=154, Invalid=352, Unknown=0, NotChecked=0, Total=506 [2018-11-23 02:57:37,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-11-23 02:57:37,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-11-23 02:57:37,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-11-23 02:57:37,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-11-23 02:57:37,472 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 20 [2018-11-23 02:57:37,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:37,472 INFO L480 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-11-23 02:57:37,472 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 02:57:37,472 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-11-23 02:57:37,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-23 02:57:37,473 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:37,473 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:37,473 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:37,473 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:37,473 INFO L82 PathProgramCache]: Analyzing trace with hash -503267110, now seen corresponding path program 10 times [2018-11-23 02:57:37,473 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:37,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:37,474 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:37,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:37,474 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:37,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:37,568 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,568 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:37,568 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:37,568 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:37,568 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:37,568 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:37,568 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:37,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:37,578 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 02:57:37,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:37,584 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:37,600 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:37,775 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,790 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:37,790 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2018-11-23 02:57:37,790 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:37,791 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 02:57:37,791 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 02:57:37,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=430, Unknown=0, NotChecked=0, Total=600 [2018-11-23 02:57:37,791 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 14 states. [2018-11-23 02:57:37,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:37,843 INFO L93 Difference]: Finished difference Result 29 states and 29 transitions. [2018-11-23 02:57:37,844 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 02:57:37,844 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 21 [2018-11-23 02:57:37,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:37,844 INFO L225 Difference]: With dead ends: 29 [2018-11-23 02:57:37,844 INFO L226 Difference]: Without dead ends: 23 [2018-11-23 02:57:37,845 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 30 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=170, Invalid=430, Unknown=0, NotChecked=0, Total=600 [2018-11-23 02:57:37,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-11-23 02:57:37,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2018-11-23 02:57:37,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2018-11-23 02:57:37,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 23 transitions. [2018-11-23 02:57:37,848 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 23 transitions. Word has length 21 [2018-11-23 02:57:37,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:37,848 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 23 transitions. [2018-11-23 02:57:37,848 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 02:57:37,848 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 23 transitions. [2018-11-23 02:57:37,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 02:57:37,849 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:37,849 INFO L402 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:37,849 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:37,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:37,849 INFO L82 PathProgramCache]: Analyzing trace with hash -1129325499, now seen corresponding path program 11 times [2018-11-23 02:57:37,849 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:37,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:37,850 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:37,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:37,850 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:37,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:37,956 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,956 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:37,956 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:37,956 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:37,956 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:37,956 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:37,956 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:37,962 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:37,962 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-23 02:57:37,983 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-23 02:57:37,983 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:37,984 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:37,999 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:37,999 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:38,185 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:38,199 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:38,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 27 [2018-11-23 02:57:38,199 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:38,200 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 02:57:38,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 02:57:38,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=518, Unknown=0, NotChecked=0, Total=702 [2018-11-23 02:57:38,200 INFO L87 Difference]: Start difference. First operand 23 states and 23 transitions. Second operand 15 states. [2018-11-23 02:57:38,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:38,275 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-11-23 02:57:38,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 02:57:38,276 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 22 [2018-11-23 02:57:38,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:38,276 INFO L225 Difference]: With dead ends: 30 [2018-11-23 02:57:38,276 INFO L226 Difference]: Without dead ends: 24 [2018-11-23 02:57:38,277 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 31 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=184, Invalid=518, Unknown=0, NotChecked=0, Total=702 [2018-11-23 02:57:38,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-11-23 02:57:38,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-11-23 02:57:38,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 02:57:38,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-11-23 02:57:38,282 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 22 [2018-11-23 02:57:38,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:38,282 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-11-23 02:57:38,282 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 02:57:38,282 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-11-23 02:57:38,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-23 02:57:38,282 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:38,282 INFO L402 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:38,282 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:38,283 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:38,283 INFO L82 PathProgramCache]: Analyzing trace with hash 937700922, now seen corresponding path program 12 times [2018-11-23 02:57:38,283 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:38,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:38,283 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:38,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:38,283 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:38,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:38,420 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:38,420 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:38,420 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:38,420 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:38,420 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:38,421 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:38,421 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:38,434 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:57:38,435 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-23 02:57:38,443 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:57:38,443 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:38,445 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:38,463 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:38,463 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:38,678 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:38,693 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:38,693 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 29 [2018-11-23 02:57:38,693 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:38,693 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 02:57:38,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 02:57:38,693 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=196, Invalid=616, Unknown=0, NotChecked=0, Total=812 [2018-11-23 02:57:38,694 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 16 states. [2018-11-23 02:57:38,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:38,795 INFO L93 Difference]: Finished difference Result 31 states and 31 transitions. [2018-11-23 02:57:38,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 02:57:38,796 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 23 [2018-11-23 02:57:38,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:38,796 INFO L225 Difference]: With dead ends: 31 [2018-11-23 02:57:38,796 INFO L226 Difference]: Without dead ends: 25 [2018-11-23 02:57:38,797 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 32 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=196, Invalid=616, Unknown=0, NotChecked=0, Total=812 [2018-11-23 02:57:38,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-11-23 02:57:38,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2018-11-23 02:57:38,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-11-23 02:57:38,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 25 transitions. [2018-11-23 02:57:38,801 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 25 transitions. Word has length 23 [2018-11-23 02:57:38,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:38,801 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 25 transitions. [2018-11-23 02:57:38,801 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 02:57:38,801 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 25 transitions. [2018-11-23 02:57:38,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-23 02:57:38,802 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:38,802 INFO L402 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:38,802 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:38,802 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:38,802 INFO L82 PathProgramCache]: Analyzing trace with hash 591010533, now seen corresponding path program 13 times [2018-11-23 02:57:38,802 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:38,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:38,803 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:38,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:38,803 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:38,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:38,962 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:38,963 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:38,963 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:38,963 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:38,963 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:38,963 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:38,963 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:38,978 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:38,978 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-11-23 02:57:38,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:38,990 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:39,061 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:39,061 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:39,282 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:39,297 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:39,298 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 31 [2018-11-23 02:57:39,298 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:39,298 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 02:57:39,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 02:57:39,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=206, Invalid=724, Unknown=0, NotChecked=0, Total=930 [2018-11-23 02:57:39,299 INFO L87 Difference]: Start difference. First operand 25 states and 25 transitions. Second operand 17 states. [2018-11-23 02:57:39,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:39,377 INFO L93 Difference]: Finished difference Result 32 states and 32 transitions. [2018-11-23 02:57:39,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 02:57:39,378 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 24 [2018-11-23 02:57:39,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:39,378 INFO L225 Difference]: With dead ends: 32 [2018-11-23 02:57:39,378 INFO L226 Difference]: Without dead ends: 26 [2018-11-23 02:57:39,379 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 33 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 117 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=206, Invalid=724, Unknown=0, NotChecked=0, Total=930 [2018-11-23 02:57:39,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-11-23 02:57:39,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-11-23 02:57:39,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-23 02:57:39,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 26 transitions. [2018-11-23 02:57:39,381 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 26 transitions. Word has length 24 [2018-11-23 02:57:39,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:39,382 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 26 transitions. [2018-11-23 02:57:39,382 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 02:57:39,382 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2018-11-23 02:57:39,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 02:57:39,382 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:39,382 INFO L402 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:39,382 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:39,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:39,383 INFO L82 PathProgramCache]: Analyzing trace with hash -1566456934, now seen corresponding path program 14 times [2018-11-23 02:57:39,383 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:39,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:39,385 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:39,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:39,385 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:39,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:39,505 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:39,505 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:39,505 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:39,505 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:39,505 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:39,505 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:39,505 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:39,512 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:39,512 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-11-23 02:57:39,659 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-11-23 02:57:39,659 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:39,662 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:39,688 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:39,688 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:39,933 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:39,947 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:39,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 33 [2018-11-23 02:57:39,947 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:39,948 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 02:57:39,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 02:57:39,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=842, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 02:57:39,948 INFO L87 Difference]: Start difference. First operand 26 states and 26 transitions. Second operand 18 states. [2018-11-23 02:57:40,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:40,026 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-11-23 02:57:40,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 02:57:40,026 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 25 [2018-11-23 02:57:40,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:40,027 INFO L225 Difference]: With dead ends: 33 [2018-11-23 02:57:40,027 INFO L226 Difference]: Without dead ends: 27 [2018-11-23 02:57:40,027 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 34 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 135 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=214, Invalid=842, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 02:57:40,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-11-23 02:57:40,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2018-11-23 02:57:40,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-11-23 02:57:40,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-11-23 02:57:40,030 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 25 [2018-11-23 02:57:40,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:40,030 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-11-23 02:57:40,030 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 02:57:40,030 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-11-23 02:57:40,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-23 02:57:40,031 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:40,031 INFO L402 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:40,031 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:40,031 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:40,031 INFO L82 PathProgramCache]: Analyzing trace with hash 271528325, now seen corresponding path program 15 times [2018-11-23 02:57:40,031 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:40,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:40,032 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:40,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:40,032 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:40,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:40,175 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:40,175 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:40,175 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 02:57:40,175 INFO L184 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-11-23 02:57:40,175 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-11-23 02:57:40,176 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:40,176 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:40,183 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:57:40,183 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-11-23 02:57:40,190 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:57:40,190 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:40,191 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:40,214 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:40,214 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:40,509 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:40,523 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-11-23 02:57:40,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 35 [2018-11-23 02:57:40,524 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-11-23 02:57:40,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-23 02:57:40,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-23 02:57:40,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=220, Invalid=970, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 02:57:40,524 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 19 states. [2018-11-23 02:57:40,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:40,620 INFO L93 Difference]: Finished difference Result 34 states and 34 transitions. [2018-11-23 02:57:40,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 02:57:40,620 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 26 [2018-11-23 02:57:40,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:40,621 INFO L225 Difference]: With dead ends: 34 [2018-11-23 02:57:40,621 INFO L226 Difference]: Without dead ends: 28 [2018-11-23 02:57:40,621 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 35 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=220, Invalid=970, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 02:57:40,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-11-23 02:57:40,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-11-23 02:57:40,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-11-23 02:57:40,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 28 transitions. [2018-11-23 02:57:40,624 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 28 transitions. Word has length 26 [2018-11-23 02:57:40,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:40,624 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 28 transitions. [2018-11-23 02:57:40,625 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-23 02:57:40,625 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 28 transitions. [2018-11-23 02:57:40,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-23 02:57:40,625 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:40,625 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:40,625 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:40,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:40,626 INFO L82 PathProgramCache]: Analyzing trace with hash 1414496506, now seen corresponding path program 16 times [2018-11-23 02:57:40,626 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 02:57:40,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:40,627 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 02:57:40,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 02:57:40,627 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 02:57:40,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 02:57:40,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 02:57:40,651 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); [?] assume true; [?] RET #32#return; [?] CALL call #t~ret2 := main(); [?] ~x~0 := #t~nondet0;havoc #t~nondet0;~y~0 := #t~nondet1;havoc #t~nondet1;havoc ~xx~0;havoc ~yy~0;havoc ~zz~0;~z~0 := 0;~i~0 := 0; VAL [main_~i~0=0, main_~x~0=3, main_~y~0=2, main_~z~0=0] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=1, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=2, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=3, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=4, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=5, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=6, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=7, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=8, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=9, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=10, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=11, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=12, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=13, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=14, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=15, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=16, main_~x~0=3, main_~y~0=2] [?] assume !(~i~0 % 4294967296 < 16); VAL [main_~i~0=16, main_~x~0=3, main_~y~0=2] [?] ~xx~0 := ~x~0 % 65536;~yy~0 := ~y~0 % 65536;~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935);~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135);~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459);~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765);~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [main_~i~0=16, main_~x~0=3, main_~y~0=2] [?] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [|__VERIFIER_assert_#in~cond|=0] [?] ~cond := #in~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume 0 == ~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume !false; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] assume !(~i~0 % 4294967296 < 16); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5-L7] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] assume !(~i~0 % 4294967296 < 16); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5-L7] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] [L23] unsigned short x = __VERIFIER_nondet_ushort(); [L24] unsigned short y = __VERIFIER_nondet_ushort(); [L25] unsigned int xx; [L26] unsigned int yy; [L27] unsigned int zz; [L28] unsigned int z = 0; [L29] unsigned int i = 0; VAL [i=0, x=3, y=2, z=0] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=1, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=2, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=3, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=4, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=5, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=6, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=7, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=8, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=9, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=10, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=11, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=12, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=13, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=14, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=15, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=16, x=3, y=2] [L30] COND FALSE !(i < sizeof(x) * 8) VAL [i=16, x=3, y=2] [L34] xx = x [L35] yy = y [L36] xx = (xx | (xx << 8u)) & 16711935U [L37] xx = (xx | (xx << 4u)) & 252645135U [L38] xx = (xx | (xx << 2u)) & 858993459U [L39] xx = (xx | (xx << 1u)) & 1431655765U [L40] yy = (yy | (yy << 8u)) & 16711935U [L41] yy = (yy | (yy << 4u)) & 252645135U [L42] yy = (yy | (yy << 2u)) & 858993459U [L43] yy = (yy | (yy << 1u)) & 1431655765U [L45] zz = xx | (yy << 1U) VAL [i=16, x=3, y=2] [L47] CALL __VERIFIER_assert(z == zz) VAL [\old(cond)=0] [L5] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L6] __VERIFIER_error() VAL [\old(cond)=0, cond=0] ----- [2018-11-23 02:57:40,688 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 02:57:40 BoogieIcfgContainer [2018-11-23 02:57:40,688 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 02:57:40,689 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 02:57:40,689 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 02:57:40,689 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 02:57:40,689 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:57:34" (3/4) ... [2018-11-23 02:57:40,693 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-23 02:57:40,693 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 02:57:40,693 INFO L168 Benchmark]: Toolchain (without parser) took 6532.01 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 283.6 MB). Free memory was 959.1 MB in the beginning and 837.1 MB in the end (delta: 122.0 MB). Peak memory consumption was 405.7 MB. Max. memory is 11.5 GB. [2018-11-23 02:57:40,695 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 02:57:40,695 INFO L168 Benchmark]: CACSL2BoogieTranslator took 196.14 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 948.4 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-11-23 02:57:40,695 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.46 ms. Allocated memory is still 1.0 GB. Free memory was 948.4 MB in the beginning and 945.7 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 02:57:40,696 INFO L168 Benchmark]: Boogie Preprocessor took 49.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.9 MB). Free memory was 945.7 MB in the beginning and 1.2 GB in the end (delta: -212.5 MB). Peak memory consumption was 14.4 MB. Max. memory is 11.5 GB. [2018-11-23 02:57:40,696 INFO L168 Benchmark]: RCFGBuilder took 124.94 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 14.3 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. [2018-11-23 02:57:40,697 INFO L168 Benchmark]: TraceAbstraction took 6140.71 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 123.7 MB). Free memory was 1.1 GB in the beginning and 837.1 MB in the end (delta: 306.8 MB). Peak memory consumption was 430.6 MB. Max. memory is 11.5 GB. [2018-11-23 02:57:40,697 INFO L168 Benchmark]: Witness Printer took 4.20 ms. Allocated memory is still 1.3 GB. Free memory is still 837.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 02:57:40,700 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 196.14 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 948.4 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.46 ms. Allocated memory is still 1.0 GB. Free memory was 948.4 MB in the beginning and 945.7 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 49.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.9 MB). Free memory was 945.7 MB in the beginning and 1.2 GB in the end (delta: -212.5 MB). Peak memory consumption was 14.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 124.94 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 14.3 MB). Peak memory consumption was 14.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 6140.71 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 123.7 MB). Free memory was 1.1 GB in the beginning and 837.1 MB in the end (delta: 306.8 MB). Peak memory consumption was 430.6 MB. Max. memory is 11.5 GB. * Witness Printer took 4.20 ms. Allocated memory is still 1.3 GB. Free memory is still 837.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 6]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseOr at line 45, overapproximation of bitwiseAnd at line 36. Possible FailurePath: [L23] unsigned short x = __VERIFIER_nondet_ushort(); [L24] unsigned short y = __VERIFIER_nondet_ushort(); [L25] unsigned int xx; [L26] unsigned int yy; [L27] unsigned int zz; [L28] unsigned int z = 0; [L29] unsigned int i = 0; VAL [i=0, x=3, y=2, z=0] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=1, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=2, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=3, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=4, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=5, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=6, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=7, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=8, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=9, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=10, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=11, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=12, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=13, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=14, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=15, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=16, x=3, y=2] [L30] COND FALSE !(i < sizeof(x) * 8) VAL [i=16, x=3, y=2] [L34] xx = x [L35] yy = y [L36] xx = (xx | (xx << 8u)) & 16711935U [L37] xx = (xx | (xx << 4u)) & 252645135U [L38] xx = (xx | (xx << 2u)) & 858993459U [L39] xx = (xx | (xx << 1u)) & 1431655765U [L40] yy = (yy | (yy << 8u)) & 16711935U [L41] yy = (yy | (yy << 4u)) & 252645135U [L42] yy = (yy | (yy << 2u)) & 858993459U [L43] yy = (yy | (yy << 1u)) & 1431655765U [L45] zz = xx | (yy << 1U) VAL [i=16, x=3, y=2] [L47] CALL __VERIFIER_assert(z == zz) VAL [\old(cond)=0] [L5] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L6] __VERIFIER_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 18 locations, 1 error locations. UNSAFE Result, 6.1s OverallTime, 17 OverallIterations, 16 TraceHistogramMax, 0.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 182 SDtfs, 0 SDslu, 1032 SDs, 0 SdLazy, 1724 SolverSat, 120 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 723 GetRequests, 422 SyntacticMatches, 15 SemanticMatches, 286 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 804 ImplicationChecksByTransitivity, 3.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=28occurred in iteration=16, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.1s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 16 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 4.1s InterpolantComputationTime, 608 NumberOfCodeBlocks, 608 NumberOfCodeBlocksAsserted, 58 NumberOfCheckSat, 820 ConstructedInterpolants, 0 QuantifiedInterpolants, 64940 SizeOfPredicates, 15 NumberOfNonLiveVariables, 795 ConjunctsInSsa, 285 ConjunctsInUnsatCore, 46 InterpolantComputations, 1 PerfectInterpolantSequences, 0/2040 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-aa41828 [2018-11-23 02:57:42,234 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 02:57:42,236 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 02:57:42,244 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 02:57:42,245 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 02:57:42,245 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 02:57:42,246 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 02:57:42,247 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 02:57:42,248 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 02:57:42,249 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 02:57:42,249 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 02:57:42,250 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 02:57:42,250 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 02:57:42,251 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 02:57:42,252 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 02:57:42,252 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 02:57:42,253 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 02:57:42,254 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 02:57:42,255 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 02:57:42,256 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 02:57:42,257 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 02:57:42,258 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 02:57:42,259 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 02:57:42,259 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 02:57:42,259 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 02:57:42,260 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 02:57:42,261 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 02:57:42,261 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 02:57:42,262 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 02:57:42,262 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 02:57:42,263 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 02:57:42,263 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 02:57:42,263 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 02:57:42,263 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 02:57:42,264 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 02:57:42,264 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 02:57:42,265 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Bitvector.epf [2018-11-23 02:57:42,275 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 02:57:42,275 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 02:57:42,275 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 02:57:42,276 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 02:57:42,276 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 02:57:42,276 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 02:57:42,276 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 02:57:42,276 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 02:57:42,276 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 02:57:42,276 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 02:57:42,277 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 02:57:42,277 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 02:57:42,277 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 02:57:42,277 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 02:57:42,277 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 02:57:42,278 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 02:57:42,279 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 02:57:42,279 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 02:57:42,279 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 02:57:42,279 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 02:57:42,279 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 02:57:42,279 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 02:57:42,279 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 02:57:42,280 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 02:57:42,280 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-11-23 02:57:42,280 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 02:57:42,280 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 02:57:42,280 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 02:57:42,280 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a69112b8d023c6203418abb04301ebe890b3a5f5 [2018-11-23 02:57:42,309 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 02:57:42,318 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 02:57:42,321 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 02:57:42,322 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 02:57:42,322 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 02:57:42,323 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 02:57:42,359 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/363778f87/d3ef8f335dfc475bba0c1f201e3464e5/FLAGa3c86a7de [2018-11-23 02:57:42,689 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 02:57:42,690 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 02:57:42,694 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/363778f87/d3ef8f335dfc475bba0c1f201e3464e5/FLAGa3c86a7de [2018-11-23 02:57:43,121 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/data/363778f87/d3ef8f335dfc475bba0c1f201e3464e5 [2018-11-23 02:57:43,123 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 02:57:43,124 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 02:57:43,124 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 02:57:43,124 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 02:57:43,127 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 02:57:43,127 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,130 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5cd7030e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43, skipping insertion in model container [2018-11-23 02:57:43,130 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,136 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 02:57:43,152 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 02:57:43,274 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 02:57:43,278 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 02:57:43,293 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 02:57:43,302 INFO L195 MainTranslator]: Completed translation [2018-11-23 02:57:43,303 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43 WrapperNode [2018-11-23 02:57:43,303 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 02:57:43,303 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 02:57:43,304 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 02:57:43,304 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 02:57:43,309 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,313 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,318 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 02:57:43,318 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 02:57:43,318 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 02:57:43,318 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 02:57:43,323 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,323 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,324 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,324 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,328 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,330 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,331 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... [2018-11-23 02:57:43,332 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 02:57:43,333 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 02:57:43,333 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 02:57:43,333 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 02:57:43,334 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 02:57:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 02:57:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 02:57:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 02:57:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 02:57:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 02:57:43,419 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 02:57:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 02:57:43,419 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 02:57:43,542 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 02:57:43,542 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-23 02:57:43,542 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:57:43 BoogieIcfgContainer [2018-11-23 02:57:43,542 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 02:57:43,543 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 02:57:43,543 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 02:57:43,546 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 02:57:43,546 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 02:57:43" (1/3) ... [2018-11-23 02:57:43,547 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a6c84a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:57:43, skipping insertion in model container [2018-11-23 02:57:43,547 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:57:43" (2/3) ... [2018-11-23 02:57:43,547 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a6c84a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:57:43, skipping insertion in model container [2018-11-23 02:57:43,547 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:57:43" (3/3) ... [2018-11-23 02:57:43,549 INFO L112 eAbstractionObserver]: Analyzing ICFG interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 02:57:43,555 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 02:57:43,560 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 02:57:43,569 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 02:57:43,587 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 02:57:43,588 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 02:57:43,588 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 02:57:43,588 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 02:57:43,588 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 02:57:43,588 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 02:57:43,588 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 02:57:43,589 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 02:57:43,589 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 02:57:43,600 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states. [2018-11-23 02:57:43,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-23 02:57:43,603 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:43,604 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:43,605 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:43,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:43,608 INFO L82 PathProgramCache]: Analyzing trace with hash -480905734, now seen corresponding path program 1 times [2018-11-23 02:57:43,611 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 02:57:43,611 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 02:57:43,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:43,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:43,653 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:43,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:43,674 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 02:57:43,676 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 02:57:43,677 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 02:57:43,681 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 02:57:43,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 02:57:43,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 02:57:43,694 INFO L87 Difference]: Start difference. First operand 18 states. Second operand 3 states. [2018-11-23 02:57:43,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:43,734 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2018-11-23 02:57:43,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 02:57:43,736 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-11-23 02:57:43,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:43,744 INFO L225 Difference]: With dead ends: 31 [2018-11-23 02:57:43,744 INFO L226 Difference]: Without dead ends: 13 [2018-11-23 02:57:43,746 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 02:57:43,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-11-23 02:57:43,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-11-23 02:57:43,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-11-23 02:57:43,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-11-23 02:57:43,768 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 11 [2018-11-23 02:57:43,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:43,768 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-11-23 02:57:43,769 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 02:57:43,769 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-11-23 02:57:43,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 02:57:43,769 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:43,769 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:43,770 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:43,770 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:43,770 INFO L82 PathProgramCache]: Analyzing trace with hash -436122843, now seen corresponding path program 1 times [2018-11-23 02:57:43,770 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 02:57:43,770 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 02:57:43,794 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:43,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:43,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:43,832 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:43,832 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:43,859 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:43,860 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:43,860 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:43,866 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 02:57:43,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 02:57:43,879 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:43,882 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:43,883 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:43,906 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:43,924 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 02:57:43,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4] total 7 [2018-11-23 02:57:43,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 02:57:43,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 02:57:43,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 02:57:43,925 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 7 states. [2018-11-23 02:57:43,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:43,989 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2018-11-23 02:57:43,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 02:57:43,990 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 12 [2018-11-23 02:57:43,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:43,990 INFO L225 Difference]: With dead ends: 22 [2018-11-23 02:57:43,991 INFO L226 Difference]: Without dead ends: 16 [2018-11-23 02:57:43,991 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2018-11-23 02:57:43,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-11-23 02:57:43,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-11-23 02:57:43,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 02:57:43,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-11-23 02:57:43,995 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 12 [2018-11-23 02:57:43,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:43,996 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-11-23 02:57:43,996 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 02:57:43,996 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-11-23 02:57:43,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 02:57:43,997 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:43,997 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:43,997 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:43,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:43,998 INFO L82 PathProgramCache]: Analyzing trace with hash -568891206, now seen corresponding path program 2 times [2018-11-23 02:57:43,998 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 02:57:43,998 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 02:57:44,010 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 02:57:44,050 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 02:57:44,050 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:44,054 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:44,087 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:44,088 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:44,187 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:44,189 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:44,189 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:44,197 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 02:57:44,215 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 02:57:44,215 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:44,218 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:44,241 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:44,242 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:44,473 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:44,497 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 02:57:44,498 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7] total 16 [2018-11-23 02:57:44,498 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 02:57:44,498 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 02:57:44,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=156, Unknown=0, NotChecked=0, Total=240 [2018-11-23 02:57:44,499 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 16 states. [2018-11-23 02:57:44,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:44,814 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2018-11-23 02:57:44,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 02:57:44,814 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 15 [2018-11-23 02:57:44,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:44,815 INFO L225 Difference]: With dead ends: 28 [2018-11-23 02:57:44,815 INFO L226 Difference]: Without dead ends: 22 [2018-11-23 02:57:44,816 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=155, Invalid=265, Unknown=0, NotChecked=0, Total=420 [2018-11-23 02:57:44,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-11-23 02:57:44,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-11-23 02:57:44,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-11-23 02:57:44,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-11-23 02:57:44,820 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 15 [2018-11-23 02:57:44,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:44,820 INFO L480 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-11-23 02:57:44,821 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 02:57:44,821 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-11-23 02:57:44,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-23 02:57:44,821 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:44,821 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:44,822 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:44,822 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:44,822 INFO L82 PathProgramCache]: Analyzing trace with hash -503267110, now seen corresponding path program 3 times [2018-11-23 02:57:44,822 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 02:57:44,822 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 02:57:44,834 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:45,059 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-23 02:57:45,059 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:45,075 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:45,148 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:45,148 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:45,577 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (7)] Exception during sending of exit command (exit): Broken pipe [2018-11-23 02:57:45,583 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:57:45,583 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:57:45,592 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 02:57:45,637 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-23 02:57:45,637 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:45,641 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:45,663 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:45,663 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:57:45,680 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:45,696 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 02:57:45,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13] total 24 [2018-11-23 02:57:45,697 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 02:57:45,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 02:57:45,697 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=161, Invalid=391, Unknown=0, NotChecked=0, Total=552 [2018-11-23 02:57:45,697 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 24 states. [2018-11-23 02:57:46,142 WARN L180 SmtUtils]: Spent 218.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 35 [2018-11-23 02:57:46,414 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 35 [2018-11-23 02:57:46,611 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 35 [2018-11-23 02:57:46,801 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 35 [2018-11-23 02:57:47,262 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification that was a NOOP. DAG size: 54 [2018-11-23 02:57:47,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 02:57:47,576 INFO L93 Difference]: Finished difference Result 40 states and 51 transitions. [2018-11-23 02:57:47,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 02:57:47,576 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 21 [2018-11-23 02:57:47,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 02:57:47,577 INFO L225 Difference]: With dead ends: 40 [2018-11-23 02:57:47,577 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 02:57:47,578 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 58 SyntacticMatches, 2 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=370, Invalid=820, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 02:57:47,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 02:57:47,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2018-11-23 02:57:47,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-11-23 02:57:47,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 35 transitions. [2018-11-23 02:57:47,584 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 35 transitions. Word has length 21 [2018-11-23 02:57:47,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 02:57:47,585 INFO L480 AbstractCegarLoop]: Abstraction has 34 states and 35 transitions. [2018-11-23 02:57:47,585 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 02:57:47,585 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 35 transitions. [2018-11-23 02:57:47,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-23 02:57:47,585 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 02:57:47,585 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 02:57:47,585 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 02:57:47,586 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 02:57:47,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1414496506, now seen corresponding path program 4 times [2018-11-23 02:57:47,586 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 02:57:47,586 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 02:57:47,597 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:57:47,732 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:57:47,732 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:57:47,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:57:48,876 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:57:48,877 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:59:03,198 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification that was a NOOP. DAG size: 243 [2018-11-23 02:59:22,602 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 120 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:59:22,604 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 02:59:22,604 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 02:59:22,611 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 02:59:22,904 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 02:59:22,904 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 02:59:22,911 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 02:59:23,472 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 02:59:23,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 02:59:27,693 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 153 DAG size of output: 151 [2018-11-23 02:59:29,802 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 161 DAG size of output: 159 [2018-11-23 02:59:32,162 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 169 DAG size of output: 167 [2018-11-23 02:59:34,875 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 177 DAG size of output: 175 [2018-11-23 02:59:37,893 WARN L180 SmtUtils]: Spent 224.00 ms on a formula simplification. DAG size of input: 185 DAG size of output: 183 [2018-11-23 02:59:41,140 WARN L180 SmtUtils]: Spent 270.00 ms on a formula simplification. DAG size of input: 193 DAG size of output: 191 [2018-11-23 02:59:44,811 WARN L180 SmtUtils]: Spent 287.00 ms on a formula simplification. DAG size of input: 201 DAG size of output: 199 [2018-11-23 02:59:48,685 WARN L180 SmtUtils]: Spent 309.00 ms on a formula simplification. DAG size of input: 209 DAG size of output: 207 [2018-11-23 02:59:53,010 WARN L180 SmtUtils]: Spent 387.00 ms on a formula simplification. DAG size of input: 217 DAG size of output: 215 [2018-11-23 02:59:57,710 WARN L180 SmtUtils]: Spent 401.00 ms on a formula simplification. DAG size of input: 225 DAG size of output: 223 [2018-11-23 03:00:02,832 WARN L180 SmtUtils]: Spent 448.00 ms on a formula simplification. DAG size of input: 233 DAG size of output: 231 [2018-11-23 03:00:08,390 WARN L180 SmtUtils]: Spent 510.00 ms on a formula simplification. DAG size of input: 241 DAG size of output: 239 [2018-11-23 03:00:14,383 WARN L180 SmtUtils]: Spent 528.00 ms on a formula simplification. DAG size of input: 249 DAG size of output: 247 [2018-11-23 03:00:20,853 WARN L180 SmtUtils]: Spent 606.00 ms on a formula simplification. DAG size of input: 257 DAG size of output: 255 [2018-11-23 03:00:24,363 WARN L180 SmtUtils]: Spent 662.00 ms on a formula simplification. DAG size of input: 266 DAG size of output: 265 [2018-11-23 03:00:24,397 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 03:00:24,414 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 03:00:24,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 23, 23] total 58 [2018-11-23 03:00:24,415 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-23 03:00:24,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-23 03:00:24,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=2402, Unknown=1, NotChecked=0, Total=3306 [2018-11-23 03:00:24,416 INFO L87 Difference]: Start difference. First operand 34 states and 35 transitions. Second operand 58 states. [2018-11-23 03:00:31,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 03:00:31,108 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2018-11-23 03:00:31,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 03:00:31,108 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 27 [2018-11-23 03:00:31,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 03:00:31,108 INFO L225 Difference]: With dead ends: 38 [2018-11-23 03:00:31,108 INFO L226 Difference]: Without dead ends: 0 [2018-11-23 03:00:31,109 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 38 SyntacticMatches, 12 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 157.0s TimeCoverageRelationStatistics Valid=947, Invalid=2592, Unknown=1, NotChecked=0, Total=3540 [2018-11-23 03:00:31,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-11-23 03:00:31,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-11-23 03:00:31,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-11-23 03:00:31,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-11-23 03:00:31,110 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 27 [2018-11-23 03:00:31,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 03:00:31,110 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-11-23 03:00:31,110 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-23 03:00:31,110 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-11-23 03:00:31,110 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 03:00:31,113 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-11-23 03:00:32,973 WARN L180 SmtUtils]: Spent 1.77 s on a formula simplification. DAG size of input: 275 DAG size of output: 227 [2018-11-23 03:00:33,118 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 210 DAG size of output: 169 [2018-11-23 03:00:33,120 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-11-23 03:00:33,120 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-11-23 03:00:33,120 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-11-23 03:00:33,120 INFO L451 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-11-23 03:00:33,120 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-11-23 03:00:33,120 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-11-23 03:00:33,120 INFO L451 ceAbstractionStarter]: At program point mainENTRY(lines 21 48) the Hoare annotation is: true [2018-11-23 03:00:33,121 INFO L444 ceAbstractionStarter]: At program point L30-2(lines 30 33) the Hoare annotation is: (let ((.cse10 ((_ zero_extend 16) main_~x~0)) (.cse11 ((_ zero_extend 16) main_~y~0))) (let ((.cse7 (bvor (_ bv0 32) (bvor (bvshl (bvand .cse10 (_ bv1 32)) (_ bv0 32)) (bvshl (bvand .cse11 (_ bv1 32)) (_ bv1 32)))))) (let ((.cse4 (bvor .cse7 (bvor (bvshl (bvand .cse10 (_ bv2 32)) (_ bv1 32)) (bvshl (bvand .cse11 (_ bv2 32)) (_ bv2 32)))))) (let ((.cse6 (bvor (bvor .cse4 (bvor (bvshl (bvand .cse10 (_ bv4 32)) (_ bv2 32)) (bvshl (bvand .cse11 (_ bv4 32)) (_ bv3 32)))) (bvor (bvshl (bvand .cse10 (_ bv8 32)) (_ bv3 32)) (bvshl (bvand .cse11 (_ bv8 32)) (_ bv4 32)))))) (let ((.cse9 (bvor (bvor (bvor .cse6 (bvor (bvshl (bvand .cse10 (_ bv16 32)) (_ bv4 32)) (bvshl (bvand .cse11 (_ bv16 32)) (_ bv5 32)))) (bvor (bvshl (bvand .cse10 (_ bv32 32)) (_ bv5 32)) (bvshl (bvand .cse11 (_ bv32 32)) (_ bv6 32)))) (bvor (bvshl (bvand .cse10 (_ bv64 32)) (_ bv6 32)) (bvshl (bvand .cse11 (_ bv64 32)) (_ bv7 32)))))) (let ((.cse12 (bvor (bvor .cse9 (bvor (bvshl (bvand .cse10 (_ bv128 32)) (_ bv7 32)) (bvshl (bvand .cse11 (_ bv128 32)) (_ bv8 32)))) (bvor (bvshl (bvand .cse10 (_ bv256 32)) (_ bv8 32)) (bvshl (bvand .cse11 (_ bv256 32)) (_ bv9 32)))))) (let ((.cse0 (bvor .cse12 (bvor (bvshl (bvand .cse10 (_ bv512 32)) (_ bv9 32)) (bvshl (bvand .cse11 (_ bv512 32)) (_ bv10 32)))))) (let ((.cse3 (bvor .cse0 (bvor (bvshl (bvand .cse10 (_ bv1024 32)) (_ bv10 32)) (bvshl (bvand .cse11 (_ bv1024 32)) (_ bv11 32)))))) (let ((.cse8 (bvadd main_~i~0 (_ bv4294967295 32))) (.cse1 (bvor (bvor .cse3 (bvor (bvshl (bvand .cse10 (_ bv2048 32)) (_ bv11 32)) (bvshl (bvand .cse11 (_ bv2048 32)) (_ bv12 32)))) (bvor (bvshl (bvand .cse10 (_ bv4096 32)) (_ bv12 32)) (bvshl (bvand .cse11 (_ bv4096 32)) (_ bv13 32)))))) (let ((.cse2 (bvor .cse1 (bvor (bvshl (bvand .cse10 (_ bv8192 32)) (_ bv13 32)) (bvshl (bvand .cse11 (_ bv8192 32)) (_ bv14 32))))) (.cse5 (let ((.cse15 (bvshl (_ bv1 32) .cse8))) (bvor (bvshl (bvand .cse10 .cse15) .cse8) (bvshl (bvand .cse11 .cse15) main_~i~0))))) (or (and (= (bvadd main_~i~0 (_ bv4294967286 32)) (_ bv0 32)) (= main_~z~0 .cse0)) (and (= .cse1 main_~z~0) (= (bvadd main_~i~0 (_ bv4294967283 32)) (_ bv0 32))) (and (= main_~z~0 .cse2) (= (bvadd main_~i~0 (_ bv4294967282 32)) (_ bv0 32))) (and (= .cse3 main_~z~0) (= (bvadd main_~i~0 (_ bv4294967285 32)) (_ bv0 32))) (and (= main_~z~0 (_ bv0 32)) (= main_~i~0 (_ bv0 32))) (and (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32)) (= main_~z~0 (bvor .cse4 .cse5))) (and (= main_~z~0 (bvor .cse3 .cse5)) (= (_ bv12 32) main_~i~0)) (and (= main_~z~0 .cse6) (= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))) (and (= main_~z~0 .cse7) (= .cse8 (_ bv0 32))) (and (= main_~z~0 .cse9) (= (bvadd main_~i~0 (_ bv4294967289 32)) (_ bv0 32))) (and (= (bvor .cse2 .cse5) main_~z~0) (= (_ bv15 32) main_~i~0)) (and (= (bvor (bvor .cse2 (bvor (bvshl (bvand .cse10 (_ bv16384 32)) (_ bv14 32)) (bvshl (bvand .cse11 (_ bv16384 32)) (_ bv15 32)))) (bvor (bvshl (bvand .cse10 (_ bv32768 32)) (_ bv15 32)) (bvshl (bvand .cse11 (_ bv32768 32)) (_ bv16 32)))) main_~z~0) (= (bvadd main_~i~0 (_ bv4294967280 32)) (_ bv0 32))) (and (= (bvor .cse9 .cse5) main_~z~0) (= (_ bv8 32) main_~i~0)) (and (= (bvadd main_~i~0 (_ bv4294967291 32)) (_ bv0 32)) (= (bvor .cse6 .cse5) main_~z~0)) (and (= (bvadd main_~i~0 (_ bv4294967287 32)) (_ bv0 32)) (= main_~z~0 .cse12)) (and (= main_~z~0 .cse4) (= (_ bv2 32) main_~i~0)) (and (= main_~z~0 (bvor (bvor .cse6 (let ((.cse14 (bvadd main_~i~0 (_ bv4294967294 32)))) (let ((.cse13 (bvshl (_ bv1 32) .cse14))) (bvor (bvshl (bvand .cse10 .cse13) .cse14) (bvshl (bvand .cse11 .cse13) .cse8))))) .cse5)) (= (bvadd main_~i~0 (_ bv4294967290 32)) (_ bv0 32)))))))))))))) [2018-11-23 03:00:33,121 INFO L448 ceAbstractionStarter]: For program point L30-3(lines 30 33) no Hoare annotation was computed. [2018-11-23 03:00:33,121 INFO L448 ceAbstractionStarter]: For program point mainEXIT(lines 21 48) no Hoare annotation was computed. [2018-11-23 03:00:33,122 INFO L444 ceAbstractionStarter]: At program point L47(line 47) the Hoare annotation is: (and (= (let ((.cse0 ((_ zero_extend 16) main_~x~0)) (.cse1 ((_ zero_extend 16) main_~y~0))) (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (_ bv0 32) (bvor (bvshl (bvand .cse0 (_ bv1 32)) (_ bv0 32)) (bvshl (bvand .cse1 (_ bv1 32)) (_ bv1 32)))) (bvor (bvshl (bvand .cse0 (_ bv2 32)) (_ bv1 32)) (bvshl (bvand .cse1 (_ bv2 32)) (_ bv2 32)))) (bvor (bvshl (bvand .cse0 (_ bv4 32)) (_ bv2 32)) (bvshl (bvand .cse1 (_ bv4 32)) (_ bv3 32)))) (bvor (bvshl (bvand .cse0 (_ bv8 32)) (_ bv3 32)) (bvshl (bvand .cse1 (_ bv8 32)) (_ bv4 32)))) (bvor (bvshl (bvand .cse0 (_ bv16 32)) (_ bv4 32)) (bvshl (bvand .cse1 (_ bv16 32)) (_ bv5 32)))) (bvor (bvshl (bvand .cse0 (_ bv32 32)) (_ bv5 32)) (bvshl (bvand .cse1 (_ bv32 32)) (_ bv6 32)))) (bvor (bvshl (bvand .cse0 (_ bv64 32)) (_ bv6 32)) (bvshl (bvand .cse1 (_ bv64 32)) (_ bv7 32)))) (bvor (bvshl (bvand .cse0 (_ bv128 32)) (_ bv7 32)) (bvshl (bvand .cse1 (_ bv128 32)) (_ bv8 32)))) (bvor (bvshl (bvand .cse0 (_ bv256 32)) (_ bv8 32)) (bvshl (bvand .cse1 (_ bv256 32)) (_ bv9 32)))) (bvor (bvshl (bvand .cse0 (_ bv512 32)) (_ bv9 32)) (bvshl (bvand .cse1 (_ bv512 32)) (_ bv10 32)))) (bvor (bvshl (bvand .cse0 (_ bv1024 32)) (_ bv10 32)) (bvshl (bvand .cse1 (_ bv1024 32)) (_ bv11 32)))) (bvor (bvshl (bvand .cse0 (_ bv2048 32)) (_ bv11 32)) (bvshl (bvand .cse1 (_ bv2048 32)) (_ bv12 32)))) (bvor (bvshl (bvand .cse0 (_ bv4096 32)) (_ bv12 32)) (bvshl (bvand .cse1 (_ bv4096 32)) (_ bv13 32)))) (bvor (bvshl (bvand .cse0 (_ bv8192 32)) (_ bv13 32)) (bvshl (bvand .cse1 (_ bv8192 32)) (_ bv14 32)))) (bvor (bvshl (bvand .cse0 (_ bv16384 32)) (_ bv14 32)) (bvshl (bvand .cse1 (_ bv16384 32)) (_ bv15 32)))) (bvor (bvshl (bvand .cse0 (_ bv32768 32)) (_ bv15 32)) (bvshl (bvand .cse1 (_ bv32768 32)) (_ bv16 32))))) main_~z~0) (exists ((main_~y~0 (_ BitVec 16)) (main_~x~0 (_ BitVec 16))) (let ((.cse5 ((_ zero_extend 16) main_~x~0)) (.cse9 ((_ zero_extend 16) main_~y~0))) (and (= (bvor (bvand (_ bv1431655765 32) (let ((.cse2 (bvand (_ bv858993459 32) (let ((.cse3 (bvand (_ bv252645135 32) (let ((.cse4 (bvand (_ bv16711935 32) (bvor .cse5 (bvshl .cse5 (_ bv8 32)))))) (bvor .cse4 (bvshl .cse4 (_ bv4 32))))))) (bvor .cse3 (bvshl .cse3 (_ bv2 32))))))) (bvor .cse2 (bvshl .cse2 (_ bv1 32))))) (bvshl (bvand (_ bv1431655765 32) (let ((.cse6 (bvand (_ bv858993459 32) (let ((.cse7 (bvand (_ bv252645135 32) (let ((.cse8 (bvand (_ bv16711935 32) (bvor .cse9 (bvshl .cse9 (_ bv8 32)))))) (bvor .cse8 (bvshl .cse8 (_ bv4 32))))))) (bvor .cse7 (bvshl .cse7 (_ bv2 32))))))) (bvor .cse6 (bvshl .cse6 (_ bv1 32))))) (_ bv1 32))) main_~zz~0) (= (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (_ bv0 32) (bvor (bvshl (bvand .cse5 (_ bv1 32)) (_ bv0 32)) (bvshl (bvand .cse9 (_ bv1 32)) (_ bv1 32)))) (bvor (bvshl (bvand .cse5 (_ bv2 32)) (_ bv1 32)) (bvshl (bvand .cse9 (_ bv2 32)) (_ bv2 32)))) (bvor (bvshl (bvand .cse5 (_ bv4 32)) (_ bv2 32)) (bvshl (bvand .cse9 (_ bv4 32)) (_ bv3 32)))) (bvor (bvshl (bvand .cse5 (_ bv8 32)) (_ bv3 32)) (bvshl (bvand .cse9 (_ bv8 32)) (_ bv4 32)))) (bvor (bvshl (bvand .cse5 (_ bv16 32)) (_ bv4 32)) (bvshl (bvand .cse9 (_ bv16 32)) (_ bv5 32)))) (bvor (bvshl (bvand .cse5 (_ bv32 32)) (_ bv5 32)) (bvshl (bvand .cse9 (_ bv32 32)) (_ bv6 32)))) (bvor (bvshl (bvand .cse5 (_ bv64 32)) (_ bv6 32)) (bvshl (bvand .cse9 (_ bv64 32)) (_ bv7 32)))) (bvor (bvshl (bvand .cse5 (_ bv128 32)) (_ bv7 32)) (bvshl (bvand .cse9 (_ bv128 32)) (_ bv8 32)))) (bvor (bvshl (bvand .cse5 (_ bv256 32)) (_ bv8 32)) (bvshl (bvand .cse9 (_ bv256 32)) (_ bv9 32)))) (bvor (bvshl (bvand .cse5 (_ bv512 32)) (_ bv9 32)) (bvshl (bvand .cse9 (_ bv512 32)) (_ bv10 32)))) (bvor (bvshl (bvand .cse5 (_ bv1024 32)) (_ bv10 32)) (bvshl (bvand .cse9 (_ bv1024 32)) (_ bv11 32)))) (bvor (bvshl (bvand .cse5 (_ bv2048 32)) (_ bv11 32)) (bvshl (bvand .cse9 (_ bv2048 32)) (_ bv12 32)))) (bvor (bvshl (bvand .cse5 (_ bv4096 32)) (_ bv12 32)) (bvshl (bvand .cse9 (_ bv4096 32)) (_ bv13 32)))) (bvor (bvshl (bvand .cse5 (_ bv8192 32)) (_ bv13 32)) (bvshl (bvand .cse9 (_ bv8192 32)) (_ bv14 32)))) (bvor (bvshl (bvand .cse5 (_ bv16384 32)) (_ bv14 32)) (bvshl (bvand .cse9 (_ bv16384 32)) (_ bv15 32)))) (bvor (bvshl (bvand .cse5 (_ bv32768 32)) (_ bv15 32)) (bvshl (bvand .cse9 (_ bv32768 32)) (_ bv16 32)))) main_~z~0)))) (= (bvadd main_~i~0 (_ bv4294967280 32)) (_ bv0 32))) [2018-11-23 03:00:33,122 INFO L448 ceAbstractionStarter]: For program point mainFINAL(lines 21 48) no Hoare annotation was computed. [2018-11-23 03:00:33,122 INFO L451 ceAbstractionStarter]: At program point __VERIFIER_assertENTRY(lines 4 9) the Hoare annotation is: true [2018-11-23 03:00:33,122 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertEXIT(lines 4 9) no Hoare annotation was computed. [2018-11-23 03:00:33,122 INFO L448 ceAbstractionStarter]: For program point L6(line 6) no Hoare annotation was computed. [2018-11-23 03:00:33,122 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION(line 6) no Hoare annotation was computed. [2018-11-23 03:00:33,122 INFO L448 ceAbstractionStarter]: For program point L5(lines 5 7) no Hoare annotation was computed. [2018-11-23 03:00:33,122 INFO L448 ceAbstractionStarter]: For program point L5-2(lines 4 9) no Hoare annotation was computed. [2018-11-23 03:00:33,150 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 03:00:33 BoogieIcfgContainer [2018-11-23 03:00:33,150 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 03:00:33,151 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 03:00:33,151 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 03:00:33,151 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 03:00:33,151 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:57:43" (3/4) ... [2018-11-23 03:00:33,154 INFO L144 WitnessPrinter]: Generating witness for correct program [2018-11-23 03:00:33,160 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure ULTIMATE.init [2018-11-23 03:00:33,160 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure main [2018-11-23 03:00:33,161 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure __VERIFIER_assert [2018-11-23 03:00:33,164 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 7 nodes and edges [2018-11-23 03:00:33,164 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 2 nodes and edges [2018-11-23 03:00:33,164 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2018-11-23 03:00:33,210 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_d7dbe46e-f495-497b-84fe-0c3c47b6d417/bin-2019/utaipan/witness.graphml [2018-11-23 03:00:33,210 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 03:00:33,211 INFO L168 Benchmark]: Toolchain (without parser) took 170087.79 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 233.8 MB). Free memory was 948.7 MB in the beginning and 1.2 GB in the end (delta: -231.1 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 03:00:33,212 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:00:33,212 INFO L168 Benchmark]: CACSL2BoogieTranslator took 178.79 ms. Allocated memory is still 1.0 GB. Free memory was 948.7 MB in the beginning and 932.5 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-23 03:00:33,212 INFO L168 Benchmark]: Boogie Procedure Inliner took 14.27 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:00:33,213 INFO L168 Benchmark]: Boogie Preprocessor took 14.47 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:00:33,213 INFO L168 Benchmark]: RCFGBuilder took 209.81 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -187.1 MB). Peak memory consumption was 14.6 MB. Max. memory is 11.5 GB. [2018-11-23 03:00:33,213 INFO L168 Benchmark]: TraceAbstraction took 169607.39 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 84.9 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -60.1 MB). Peak memory consumption was 397.8 MB. Max. memory is 11.5 GB. [2018-11-23 03:00:33,213 INFO L168 Benchmark]: Witness Printer took 59.79 ms. Allocated memory is still 1.3 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 03:00:33,215 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 178.79 ms. Allocated memory is still 1.0 GB. Free memory was 948.7 MB in the beginning and 932.5 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 14.27 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 14.47 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 209.81 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -187.1 MB). Peak memory consumption was 14.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 169607.39 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 84.9 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -60.1 MB). Peak memory consumption was 397.8 MB. Max. memory is 11.5 GB. * Witness Printer took 59.79 ms. Allocated memory is still 1.3 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 6]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 30]: Loop Invariant Derived loop invariant: ((((((((((((((((~bvadd64(i, 4294967286bv32) == 0bv32 && z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32)))) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))) == z && ~bvadd64(i, 4294967283bv32) == 0bv32)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8192bv32), 13bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8192bv32), 14bv32))) && ~bvadd64(i, 4294967282bv32) == 0bv32)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))) == z && ~bvadd64(i, 4294967285bv32) == 0bv32)) || (z == 0bv32 && i == 0bv32)) || (~bvadd64(i, 4294967293bv32) == 0bv32 && z == ~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))))) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) && 12bv32 == i)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))) && ~bvadd64(i, 4294967292bv32) == 0bv32)) || (z == ~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))) && ~bvadd64(i, 4294967295bv32) == 0bv32)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))) && ~bvadd64(i, 4294967289bv32) == 0bv32)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8192bv32), 13bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8192bv32), 14bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) == z && 15bv32 == i)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8192bv32), 13bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8192bv32), 14bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16384bv32), 14bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16384bv32), 15bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32768bv32), 15bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32768bv32), 16bv32))) == z && ~bvadd64(i, 4294967280bv32) == 0bv32)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) == z && 8bv32 == i)) || (~bvadd64(i, 4294967291bv32) == 0bv32 && ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) == z)) || (~bvadd64(i, 4294967287bv32) == 0bv32 && z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))))) || (z == ~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))) && 2bv32 == i)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967294bv32))), ~bvadd64(i, 4294967294bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967294bv32))), ~bvadd64(i, 4294967295bv32)))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) && ~bvadd64(i, 4294967290bv32) == 0bv32) - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 18 locations, 1 error locations. SAFE Result, 169.5s OverallTime, 5 OverallIterations, 16 TraceHistogramMax, 9.0s AutomataDifference, 0.0s DeadEndRemovalTime, 2.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 55 SDtfs, 25 SDslu, 421 SDs, 0 SdLazy, 649 SolverSat, 110 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 321 GetRequests, 189 SyntacticMatches, 15 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 541 ImplicationChecksByTransitivity, 159.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=34occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 5 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 7 LocationsWithAnnotation, 12 PreInvPairs, 30 NumberOfFragments, 2806 HoareAnnotationTreeSize, 12 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.0s HoareSimplificationTime, 7 FomulaSimplificationsInter, 576 FormulaSimplificationTreeSizeReductionInter, 1.9s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 157.4s InterpolantComputationTime, 161 NumberOfCodeBlocks, 161 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 294 ConstructedInterpolants, 3 QuantifiedInterpolants, 537279 SizeOfPredicates, 24 NumberOfNonLiveVariables, 402 ConjunctsInSsa, 144 ConjunctsInUnsatCore, 17 InterpolantComputations, 1 PerfectInterpolantSequences, 120/808 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Received shutdown request...